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docs: log final re-verified real P&R signoff after SPI fix + reg file (EXP-0076)

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Confirms EXP-0075's fixes (SPI physical-layer bug, register file,
real pin constraints) don't regress timing: WNS +0.056ns (slightly
better than EXP-0074's +0.040ns), 0 failing endpoints, 5173 LUTs,
16 DSP48E1. User confirmed board plan: both JTAG and Master SPI boot
(Winbond W25Q32JVSSIQ config flash, verified in-stock on LCSC) will
be present on the custom PCB.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
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michele
2026-09-19 19:22:32 +02:00
co-authored by Claude Sonnet 5
parent ca17765fe3
commit fd6cc7a2fa
1 changed files with 33 additions and 0 deletions
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hardware/v2/logs/experiments.log
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@@ -4737,3 +4737,36 @@ up-to-date timing/resource signoff; write up the FPGA configuration
config flash, using the real dedicated pins found this session
(PROGRAM_B=P9, INIT_B=P7, DONE=P10, M0=P12/M1=P13/M2=P11, CCLK=E9,
D00_MOSI=K17, D01_DIN=K18, FCS_B=L13).
EXP-0076 -- final real P&R re-verification with pin constraints +
register file + SPI physical-layer fix (2026-09-19, same autonomous
continuation)
CONTEXT: EXP-0074's real P&R (WNS +0.040ns) predates EXP-0075's real
fixes (SPI MISO bit-corruption bug, register file, real pin
constraints for the neural-processor SPI + reserved config-flash
pins). Re-ran the full real in-context synth+impl to confirm none of
that regressed the timing signoff.
RESULT: route_design 100%, all timing constraints still met.
WNS = +0.056ns (TNS 0.000, 0/17341 failing setup endpoints) -- slightly
BETTER than EXP-0074's +0.040ns, not worse. WHS = +0.048ns (unchanged).
5173 LUTs (8.16%, +33 vs EXP-0074's 5140 -- the register file's own
small cost), 16 DSP48E1 (6.67%, unchanged). Real pin assignments
(sclk=A15/mosi=B16/miso=B17/cs_n=A16, config-flash pins reserved) are
now part of this signoff, not auto-placed.
DECISION: this is the current, final, trustworthy real timing/
resource signoff for the whole physically-interfaced N=2 system --
real DDR3, real pin constraints, real register-file host control
path, real (fixed) SPI physical layer. User confirmed board plan: both
JTAG (dev/debug) and Master SPI boot from an external config flash
(Winbond W25Q32JVSSIQ, verified in-stock on LCSC) will be present on
the custom PCB -- standard practice, no RTL work needed for this
(config boot is handled entirely by the FPGA's own dedicated
configuration logic, outside this project's own RTL).
next_action: none blocking -- remaining work is scaling past N=2,
building a real activation-fetch engine, and finalizing PCB-specific
constraints (SPI/reset pin LOCs) once the board layout itself is
underway. All disclosed, none of it changes today's real signoff.