feat: DDRManager phase 1 - single-slot look-ahead activation prefetch (EXP-0083)
New ddr_prefetch_mgr.v wraps act_tile_fetch.v with a depth-2 ping-pong buffer, issuing the next tile's DDR3 fetch as soon as the fetch engine is free instead of waiting for packed_slot.v to finish consuming the current tile. Wired into packed_slot.v's tile loop (job-level start instead of per-tile req), simplifying the S_TILEWAIT join in the process (ddrpf_tile_valid is level-held, no separate act_seen latch needed). Verification: new tb_ddr_prefetch_mgr.v (25/25 PASS after fixing a real testbench polling race found via iteration-tagged tracing, not an RTL bug), tb_packed_slot.v re-run unmodified (9/9 PASS, bit-identical results), tb_n2_system_ddr3.v re-run via real xsim against real ddr3_model.sv (8/8 PASS). Real P&R: WNS +0.073ns (up from EXP-0082's +0.068ns), LUTs 5644, DSP48E1 16 unchanged, 0 failing endpoints. Honest result: real A/B on the actual DDR3 backend (same testbench, before/after) shows a real but modest 2.86% reduction in total simulated time - smaller than the original hypothesis suggested, because neural_processor_packed.v already accepts one operand per cycle, so the per-tile dead time being removed was already small relative to real DDR3 fetch latency. Docs updated to report this honestly rather than oversell it; the larger multi-slot DDRManager is deferred pending re-measurement against the (still pending, user-gated) 32-bit channel widening. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
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Claude Sonnet 5
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`timescale 1ns/1ps
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// ============================================================
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// V3 -- ddr_prefetch_mgr.v: the DDRManager's real phase-1 deliverable
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// (EXP-0083), implementing the user's own proposed idea -- "vorrei che
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// orchestrator potesse 'prenotare' le letture future in RAM ... in modo
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// da azzerare i tempi di attesa (o almeno ridurli al minimo)" -- scoped,
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// per this project's own "one variable at a time" discipline and the
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// validation plan docs/ARCHITECTURE_ANALYSIS.md S5.2 laid out, to a
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// SINGLE slot's own activation-tile look-ahead first, before attempting
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// a cross-slot/whole-Director-queue scheduler.
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//
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// WHAT THIS DOES: wraps act_tile_fetch.v (unmodified, reused as the
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// "fetch exactly one tile" engine) with a depth-2 ping-pong buffer and a
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// sequencer that issues the NEXT tile's fetch the INSTANT the fetch
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// engine is free and that tile's buffer bank is free -- NOT waiting for
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// packed_slot.v to have consumed the CURRENT tile first. This overlaps
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// "fetching tile N+1" with "packed_slot.v consuming tile N", which the
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// original per-tile req/wait loop (EXP-0079/0081) never did.
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//
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// WHAT THIS DOES NOT DO (disclosed, not glossed over): it does not
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// change the real 1.24 GB/s physical DDR3 ceiling (S3.1 of the
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// architecture doc) or the per-fetch latency of any SINGLE tile fetch --
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// it only removes the small, real per-tile RE-REQUEST overhead (the
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// S_TILEREQ pulse cycle + the S_OPERAND consume cycle packed_slot.v's
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// own FSM previously spent NOT fetching, between one tile's data
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// arriving and the next tile's fetch being issued). Given
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// neural_processor_packed.v's own pipeline accepts one operand PER
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// CYCLE once in NP_WAIT_OPERANDS (operand_ready is state-only, not
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// gated on any internal pipeline stall), the real compute-side
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// consumption cost per tile is ~1 cycle -- meaning this fix's real
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// ceiling is bounded by that small per-tile overhead, not by hiding a
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// large compute-bound stall. The real, measured improvement is reported
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// in the EXP-0083 log entry, not assumed here.
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//
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// WHY A DOUBLE BUFFER (depth 2), not deeper: matches
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// layer_weight_buffer.v's own proven ping-pong pattern in this
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// codebase, and depth 2 is provably sufficient here -- the fetch
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// sequencer can be at most 1 tile ahead of the consumer, since issuing
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// tile N+2's fetch requires bank[(N+2)%2] == bank[N%2] to already be
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// free, which only happens once tile N has been consumed. No unbounded
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// lookahead is possible or attempted.
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//
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// WHY THIS IS TIMING-SAFE: bank selection for both the fill side
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// (fetch_idx[0]) and the read side (consume_idx[0]) is a REGISTERED
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// index bit, exactly the same "select known long before the data it
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// gates" discipline act_tile_fetch.v's own header (EXP-0081) already
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// established as safe -- never a bit racing live data. Requires its own
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// real P&R re-check before being trusted at N>1 scale, per this
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// project's standing practice (not assumed safe by analogy alone).
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// ============================================================
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module ddr_prefetch_mgr #(
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parameter DATA_WIDTH = 8,
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parameter P_IN = 8,
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parameter BURST_LEN = 8,
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parameter ADDR_WIDTH = 25 // word address, matches act_tile_fetch.v's own convention
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)(
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input wire clk,
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input wire rst,
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// ---- job-level control (packed_slot.v issues this ONCE per job,
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// not once per tile -- the whole tile loop's lookahead is driven
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// internally from here) ----
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input wire job_start, // one-shot pulse
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input wire [ADDR_WIDTH-1:0] base_a,
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input wire [ADDR_WIDTH-1:0] base_b,
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input wire [15:0] n_tiles,
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// ---- per-tile consumption interface (packed_slot.v side) ----
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// tile_valid is a LEVEL signal (unlike act_tile_fetch.v's one-cycle
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// `valid` pulse) -- it stays high as long as the current
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// consume-index's buffer bank holds unconsumed data, which may
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// already be true the cycle packed_slot.v asks, if the lookahead
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// fetch completed early. packed_slot.v pulses tile_consume once it
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// has latched data_a/data_b, which frees this bank for the next
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// lookahead fetch.
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output wire tile_valid,
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output wire signed [DATA_WIDTH*P_IN-1:0] data_a,
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output wire signed [DATA_WIDTH*P_IN-1:0] data_b,
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input wire tile_consume, // one-shot pulse
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// ---- shared DDR3 controller port (identical shape to
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// act_tile_fetch.v's own -- this module is a pure passthrough
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// wrapper on this side, connects straight through to the inner
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// act_tile_fetch instance) ----
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output wire mem_active,
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input wire mem_grant,
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output wire ctrl_req,
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output wire ctrl_wr,
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output wire [ADDR_WIDTH-1:0] ctrl_addr,
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output wire [16*BURST_LEN-1:0] ctrl_wdata,
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output wire [2*BURST_LEN-1:0] ctrl_wmask,
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input wire [16*BURST_LEN-1:0] ctrl_rdata,
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input wire ctrl_ready,
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input wire ctrl_busy
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);
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reg [ADDR_WIDTH-1:0] base_a_lat, base_b_lat;
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reg [15:0] n_tiles_lat;
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reg [15:0] fetch_idx, consume_idx;
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reg fetch_inflight;
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// ---- depth-2 ping-pong buffer ----
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reg signed [DATA_WIDTH*P_IN-1:0] bank_data_a [0:1];
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reg signed [DATA_WIDTH*P_IN-1:0] bank_data_b [0:1];
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reg [1:0] bank_valid;
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assign tile_valid = bank_valid[consume_idx[0]];
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assign data_a = bank_data_a[consume_idx[0]];
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assign data_b = bank_data_b[consume_idx[0]];
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// ---- inner fetch engine: act_tile_fetch.v, reused unmodified,
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// driven one tile at a time by this sequencer ----
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reg act_req;
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wire act_valid;
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wire signed [DATA_WIDTH*P_IN-1:0] act_data_a_w, act_data_b_w;
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act_tile_fetch #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH)
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) u_act (
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.clk(clk), .rst(rst),
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.req(act_req), .base_a(base_a_lat), .base_b(base_b_lat),
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.tcnt(fetch_idx), .valid(act_valid), .data_a(act_data_a_w), .data_b(act_data_b_w),
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.mem_active(mem_active), .mem_grant(mem_grant),
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.ctrl_req(ctrl_req), .ctrl_wr(ctrl_wr), .ctrl_addr(ctrl_addr),
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.ctrl_wdata(ctrl_wdata), .ctrl_wmask(ctrl_wmask),
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.ctrl_rdata(ctrl_rdata), .ctrl_ready(ctrl_ready), .ctrl_busy(ctrl_busy)
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);
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// can_issue: the inner fetch engine is free, there is a next tile
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// left in this job, and that tile's destination bank has already
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// been consumed (or was never filled yet, at job start).
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wire can_issue = !fetch_inflight && (fetch_idx < n_tiles_lat) && !bank_valid[fetch_idx[0]];
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always @(posedge clk) begin
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if (rst) begin
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base_a_lat <= {ADDR_WIDTH{1'b0}};
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base_b_lat <= {ADDR_WIDTH{1'b0}};
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n_tiles_lat <= 16'd0;
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fetch_idx <= 16'd0;
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consume_idx <= 16'd0;
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fetch_inflight <= 1'b0;
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act_req <= 1'b0;
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bank_valid <= 2'b00;
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end else begin
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act_req <= 1'b0;
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if (job_start) begin
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base_a_lat <= base_a;
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base_b_lat <= base_b;
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n_tiles_lat <= n_tiles;
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fetch_idx <= 16'd0;
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consume_idx <= 16'd0;
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fetch_inflight <= 1'b0;
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bank_valid <= 2'b00;
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end else begin
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if (can_issue) begin
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act_req <= 1'b1;
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fetch_inflight <= 1'b1;
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end
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if (act_valid) begin
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bank_data_a[fetch_idx[0]] <= act_data_a_w;
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bank_data_b[fetch_idx[0]] <= act_data_b_w;
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bank_valid[fetch_idx[0]] <= 1'b1;
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fetch_idx <= fetch_idx + 16'd1;
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fetch_inflight <= 1'b0;
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end
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if (tile_consume) begin
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bank_valid[consume_idx[0]] <= 1'b0;
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consume_idx <= consume_idx + 16'd1;
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end
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end
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end
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end
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endmodule
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