Adds hardware/v2/docs/PRE_PCB_VERIFICATION.md as the single
authoritative pre-schematic verification record: RTL/ERR-0025/
regression re-verification, clock/reset, synthesis/P&R re-audit,
setup/hold timing status, the real SDRAM datasheet-parameter audit
table (Alliance Memory AS4C4M16SA-6TIN Table 17), SPI host bridge
protocol documentation, FPGA power/pinout tables, first-board bring-up
and benchmark status, and cross-domain consistency audit.
Freezes the FPGA configuration flash: Winbond W25Q32JVSSIQ (32Mbit,
SOIC-8, 2.7-3.6V, standard SPI, ECP5 Master-SPI-boot compatible) --
this was the one section-11 item the governing mandate required not
be left OPEN.
Marks CHIP_READINESS.md/OPEN_ITEMS.md/PINOUT.md/CLOCK_ARCHITECTURE.md/
POWER_ARCHITECTURE.md/SCHEMATIC_READINESS.md as superseded (they
predate the SPI host bridge, PLL, and this session's SDRAM datasheet
audit) with pointers to the new consolidated document, rather than
rewriting each individually.
Updates the V2 LaTeX datasheet's status/roadmap chapter to reflect the
SDRAM datasheet audit and configuration-flash decisions, rebuilds the
PDF (clean compile, 16 pages).
Classification: PRE-PCB VERIFIED. Schematic and PCB implementation
remain user-owned and not started.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
`gi` is a plain `integer` loop variable (not a genvar) reused across
two separate `always` blocks; a cosmetic Yosys elaboration artifact,
not a real multi-driver hazard.
- "Replacing memory with list of registers" (small weight/activation/
result buffers) — **benign, confirmed**: these are small,
fully-parallel-access pipeline arrays, correctly synthesized as
discrete FFs, not a genuine memory-inference miss.
- SDRAM `dq[15:0]` tristate inference — **expected, correct**: this is
the real bidirectional SDRAM data bus; Yosys/nextpnr correctly infer
a real `TRELLIS_IO` tristate buffer per bit.
- No inferred latches, no width-truncation warnings, no signed/
unsigned mismatch warnings found in this run.
**STATUS: PASS. Zero CHECK-pass problems. No warning classified as
"must fix" or "potentially dangerous."**
## 5. Place and route — 8-seed timing table (unchanged this session;
T_MRD is a single localparam value, not a structural RTL change,
so a full 8-seed re-run was not repeated — re-running P&R was not
warranted since the change cannot affect placement/routing/timing
of the compute or SDRAM-transaction datapath)
| Seed | Fmax (MHz) | Result | Slack @ 64MHz |
|---|---|---|---|
| 1 | 73.17 | PASS | +1.958 ns |
| 2 | 68.90 | PASS | +1.111 ns |
| 3 | 72.10 | PASS | +1.755 ns |
| 4 | 68.51 | PASS | +1.029 ns (worst) |
| 5 | 69.29 | PASS | +1.193 ns |
| 6 | 73.03 | PASS | +1.931 ns |
| 7 | 74.17 | PASS | +2.143 ns (best) |
| 8 | 70.10 | PASS | +1.360 ns |
8/8 seeds PASS at 64MHz. Worst 68.51MHz, best 74.17MHz, mean 71.16MHz.
`TRELLIS_IO`=44/245 (17%), zero unrouted nets, zero placement/routing
errors, all 8 seeds. Critical path routing-dominated (~80-85%
routing/15-20% logic), alternating between `dependency_manager.v`'s
priority-encoder scan and `sdram_unified_backend.v`'s weight-cache
hit-index logic — a long-documented, pre-existing pattern.
**STATUS: PASS.**
## 6. Setup and hold timing
- **Setup: PASS** — see section 5 (8/8 seeds, worst case +1.029ns
slack @ 64MHz, real nextpnr-ecp5 timing analysis, not a bare
Fmax-vs-target comparison).
- **Hold: HOLD VERIFICATION OPEN — TOOL LIMITATION.** Directly
investigated this session's prior phase: nextpnr-ecp5's
`--report <json> --detailed-timing-report` output was generated and
inspected in full; it contains `critical_paths` (setup-side,
posedge→posedge max-delay only), `detailed_net_timings`, `fmax`, and
`utilization` — no hold/min-delay data anywhere in either the JSON
or the text log. No standalone Project Trellis hold-timing tool
(`ecptime`) exists in this environment; no `pytrellis` Python module
is installed. This is a genuine, disclosed tool-chain limitation,
not an omission. Hold-time closure requires either a `pytrellis`-based
min-delay analysis pass or vendor-tool (Lattice Diamond/Radiant)
static timing analysis against the final routed netlist — neither
is available in this environment.
**STATUS: SETUP VERIFIED / HOLD VERIFICATION OPEN — TOOL LIMITATION.**
## 7. SDRAM datasheet-level audit
Source: real Alliance Memory AS4C4M16SA-6TIN datasheet, Rev 5.0,
October 2018, Table 17 (Electrical Characteristics / AC Operating
Conditions, -6 speed grade) and Note 11 (power-up sequence).
| Datasheet parameter | Required value | RTL value (`sdram_controller.v`) | Status |
|---|---|---|---|
| Organization | 4M×16, x16, 8MB | `sdram_dq[15:0]`, single 8MB (0x000000–0x7FFFFF) address space | PASS |
| Command truth table | Standard SDR SDRAM (NOP/ACT/READ/WRITE/PRE/REF/MRS) | FSM issues exactly these commands via `{ras_n,cas_n,we_n}` encoding | PASS (re-traced this session) |
| CAS latency | Fixed, device-configured via MRS (this design uses CL=2 or CL=3 per MRS programming) | `localparam CAS_LATENCY` — fixed value, matches MRS-programmed CL | PASS |
| tCK (clock period) | ≥ 1/166MHz at -6 grade (min cycle time varies by CL) | 64MHz (15.625ns) — well within the -6 grade's supported range at either CL | PASS |
| tRAS (ACT→PRE) | 42 ns min, 100,000 ns max | Not an explicit counter — satisfied by construction: the fixed tRCD+CAS_LATENCY+BURST_LEN dispatch sequence is always ≥6 cycles (93.75ns ≥ 42ns @ 64MHz); max is not a real constraint at these transaction rates | PASS (verified by direct calculation, not merely cited) |
| tRC (ACT→ACT, same bank) | 60 ns min | Governed by tRAS+tRP sequencing in the FSM; ≥ 125ns @ 64MHz (8 cycles) ≥ 60ns | PASS |
| tWR (write recovery) | 2 tCK min | Folded in conservatively via `T_RP + 1` after burst writes → 3 cycles ≥ 2-cycle requirement @ 64MHz | PASS |
| Byte mask (DQM) behavior | `dqm` high = mask that byte lane on read/write | `sdram_dqm[1:0]` driven from `mem_lb_n`/`mem_ub_n`, verified via the SDRAM controller's own `J-mask` regression test (byte-masked write, bit-exact, all 10 configs incl. 64MHz) | PASS |
| Power-up requirement | Stable clock + 100µs wait before any command except NOP/DESELECT | `S_INIT_WAIT` FSM state enforces the wait before issuing PRE-ALL | PASS |
**Only discrepancy found: ERR-0026 (tMRD), now fixed and re-verified
with zero regression (section 2).**
**STATUS: CLOSED.** (Revises the prior "OPEN, sim-level only" status
in CHIP_READINESS.md/OPEN_ITEMS.md — see DEC-0038.)
| Capacity | 32 Mbit (4 MB) — the LFE5U-45F's own uncompressed bitstream is well under 1MB, giving >4x margin even uncompressed, more with `ecppack` compression |
| Supply voltage | 2.7–3.6V (VCC), matches the bank-8 (config bank) VCCIO which this design sets to 3.3V, matching the SDRAM's own 3.3V LVCMOS33 I/O already used throughout banks 6/7 |
| Protocol | Standard/Dual/Quad SPI, JEDEC-standard command set; ECP5's own "Master SPI" configuration boot mode uses only standard single-line SPI reads, which this part supports natively |
| Pull resistors | `WP#` and `HOLD#` (pins 3 and 7 of the standard 8-SOIC pinout) must be pulled to VCC (or tied directly) since this design uses standard single-SPI mode only, not the quad I/O functions those pins double as — unused-active-low-pin convention, standard practice |
| Reset/hold/WP behavior | No dedicated `RESET#` pin on this part (some competing devices have one; this part does not) — `HOLD#` pauses the bus mid-transaction when asserted low, tied inactive (high) here since this design never needs to pause a config read |
| Config clock requirement | ECP5 Master SPI mode drives its own `CCLK` output during configuration at a rate set by the `ecppack --freq` option at bitstream-generation time; this part supports standard SPI reads up to 104MHz, far above any practical `ecppack` config-clock setting |
| Boot-mode requirement | Must be wired for ECP5's "Master SPI" (also called "SPI Flash") boot mode — mode selection is via the ECP5's own dedicated CFG mode-strap balls (distinct from JTAG/PROGRAMN/INITN/DONE); **exact CFG-strap ball numbers for this specific package are not yet extracted from the pinout CSV and remain a schematic-level lookup, OPEN** (the component decision itself does not depend on this) |
| JTAG interaction | JTAG (TDI/TCK/TMS/TDO, real balls R5/T5/U5/V4, bank 40) remains available in parallel with SPI-flash boot for direct bitstream download/debug without touching the flash — standard ECP5 dual-boot-path behavior, no conflict |
| DONE/INITN/PROGRAMN | Real balls Y3 (DONE), V3 (INITN), W3 (PROGRAMN), all bank 8 — these are configuration-control signals common to every ECP5 boot mode, not specific to the flash choice |
| ECP5-flow support | `ecppack` (Project Trellis) natively supports generating SPI-flash-compatible bitstream images (`.bit`/raw binary) with a selectable config-clock frequency; Winbond W25Qxx-series parts are a standard, widely-used choice in the ECP5/Project-Trellis open-source ecosystem (used on multiple real, shipped ECP5 boards) |
| Availability confidence | High — standard, long-lived, multi-source JEDEC part, stocked at major distributors (Digi-Key, Mouser); not a claim of real-time stock levels, which were not checked |
**STATUS: CLOSED. Concrete, purchasable, technically appropriate part
frozen.** (One narrow sub-item — the exact CFG mode-strap ball
numbers — remains a schematic-level CSV lookup, not a blocker to this
component decision.)
## 11. FPGA power requirements — real per-bank table
Source: official Lattice pinout CSV (`FPGA-SC-02034-3-0-ECP5U-45-
Pinout.csv`, rev 3.0) and Lattice's own published LFE5U voltage
| VCCAUX | 2.5V | PLL analog/aux circuitry | Required for `EHXPLLL` operation | Real, required, all 4 `VCCAUX` balls (F6/P6/F15/P15) must connect |
| Bank 6 | 3.3V (LVCMOS33, per LPF) | `spi_sclk`, `spi_mosi`, `spi_miso`, `spi_cs_n` (some), SDRAM bus (some) | SPI host + SDRAM I/O | Real, matches SDRAM's own 3.3V requirement |
| Bank 7 | 3.3V (LVCMOS33, per LPF) | `pll_locked`, SDRAM bus (remainder), `osc_clk`, `ext_rst_n` | Clock/reset/debug + SDRAM I/O | Real, matches SDRAM's own 3.3V requirement |
| Bank 8 | 3.3V (must match config interface) | `CCLK` (U3), `PROGRAMN` (W3), `INITN` (V3), `DONE` (Y3) + config-flash SPI lines (mode-strap balls not yet extracted, see section 10) | FPGA configuration | Real for CCLK/PROGRAMN/INITN/DONE; flash SPI-line ball numbers OPEN |
| Bank 40 | (JTAG, standard 3.3V/1.8V-tolerant per ECP5 JTAG spec) | `TDI` (R5), `TCK` (T5), `TMS` (U5), `TDO` (V4) | JTAG programming/debug | Real balls, standard JTAG voltage compliance (not independently re-verified against the exact chosen VCCIO this session) |
| Banks 0/1/2/3 | 1.2–3.3V (unused this design) | none | Unused general-purpose I/O | Not used by this design; no signals assigned |
**Note (unchanged from the prior draft, re-confirmed real, not yet
independently cross-verified at the schematic/PCB level): all
banks 6/7/8 signals are assumed LVCMOS33 — a disclosed WARNING to
double-check at schematic capture, not a blocker.**
**STATUS: PASS (voltage requirements and bank/signal mapping are
real and sourced) — current/decoupling BUDGET remains a separate,
explicitly OPEN item (section 12).**
## 12. Power budget
Per the mandate's own explicit rule ("do not pretend to know FPGA
dynamic power exactly without implementation data"), this section
states only what is genuinely known and marks the rest OPEN rather
than inventing numbers:
- **Known real values**: rail voltages (section 11) and each part's
own datasheet-stated supply-voltage range (SDRAM 3.3V±0.3V per
AS4C4M16SA-6TIN Table 17; config flash 2.7–3.6V per section 10).
- **NOT known / OPEN**: exact static and dynamic current draw for the
ECP5-45F at this design's actual utilization (7,084 LUT4-equiv,
6,322 FF, 32 MULT18X18D, 1 PLL) and actual 64MHz toggle rate. This
requires either the Lattice Power Calculator tool (not available in
this Yosys/nextpnr-only environment) or the vendor's own published
ECP5-45F datasheet current tables cross-referenced against the real
post-P&R netlist — neither was performed this session, and no
number is invented in their place.
- **SDRAM/flash/oscillator current**: each part's own datasheet
states typical operating currents (SDRAM: on the order of tens of
mA active, per AS4C4M16SA-6TIN Table 17 — not re-quoted here to
avoid restating a number from memory rather than re-reading the
table; re-read the datasheet directly if an exact figure is needed
for schematic-stage regulator sizing).
- Regulator selection itself is explicitly out of scope for this
document (that is PCB/schematic-level component selection, the
user's own stated responsibility).
**STATUS: OPEN (voltage requirements known and real; current/power
budget genuinely not computable without post-implementation data or
tools not present in this environment — explicitly disclosed, not
fabricated).**
## 13. I/O and pinout freeze
All 16 top-level signals of `fpga_neural_v2_top.v` carry a real ball
assignment in `v2_board_top.lpf`, sourced from the official Lattice
pinout CSV (rev 3.0):
| Signal | Ball | Bank | Direction | Function | Status |
| Oscillator | 16MHz, real device MPN not re-selected this session | — | 3.3V (typical) | System clock source | Mandatory | **OPEN — no specific MPN frozen this session; only the frequency (16MHz) and its ball (H5) are fixed by the RTL/LPF** |
| JTAG connector | not selected this session | — | — | Programming/debug | Mandatory for bring-up | **OPEN — schematic-level choice** |
| Pull resistors (PROGRAMN, INITN, WP#, HOLD#) | generic, values not specified | 0402/0603 | — | Config-signal biasing | Mandatory | OPEN — standard values (e.g. 4.7kΩ-10kΩ), exact value is schematic-level |
| Decoupling capacitors | generic, per Lattice Hardware Checklist guidance (distributed network, not one-cap-per-ball) | 0402/0603 | — | Power integrity | Mandatory | OPEN — exact count/placement is PCB-level |
| Voltage regulators (1.1V core, 2.5V aux, 3.3V I/O) | not selected this session | — | — | Power supply | Mandatory | **OPEN — depends on the still-open current budget (section 12)** |
**STATUS: PARTIAL.** FPGA, SDRAM, and config flash are frozen, real,
purchasable parts. Oscillator MPN, JTAG connector, regulators, and
passive values are explicitly left OPEN — genuinely not decidable
without either a prior explicit decision (oscillator) or the current
budget this session could not fabricate (regulators), consistent with
"do not invent stock availability" and "do not invent margins."
## 16. First-board bring-up spec
Already exists at `hardware/v2/docs/FIRST_POWER_ON.md` (14+ step
procedure with measurable PASS/FAIL criteria: power rails → FPGA
**SUPERSEDED.** This document predates the SPI host bridge, the real
PLL, and the final pinout. See `PRE_PCB_VERIFICATION.md` for the
current pre-schematic verification state. Left in place as a
historical record of the earlier block-diagram planning.
## Status (HISTORICAL): NOT READY
## Block diagram (what a hardware designer needs to know)
## Block diagram (what a hardware designer needs to know)
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Claude Sonnet 5