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docs: PRE-PCB VERIFICATION FREEZE report + config flash freeze

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Adds hardware/v2/docs/PRE_PCB_VERIFICATION.md as the single
authoritative pre-schematic verification record: RTL/ERR-0025/
regression re-verification, clock/reset, synthesis/P&R re-audit,
setup/hold timing status, the real SDRAM datasheet-parameter audit
table (Alliance Memory AS4C4M16SA-6TIN Table 17), SPI host bridge
protocol documentation, FPGA power/pinout tables, first-board bring-up
and benchmark status, and cross-domain consistency audit.

Freezes the FPGA configuration flash: Winbond W25Q32JVSSIQ (32Mbit,
SOIC-8, 2.7-3.6V, standard SPI, ECP5 Master-SPI-boot compatible) --
this was the one section-11 item the governing mandate required not
be left OPEN.

Marks CHIP_READINESS.md/OPEN_ITEMS.md/PINOUT.md/CLOCK_ARCHITECTURE.md/
POWER_ARCHITECTURE.md/SCHEMATIC_READINESS.md as superseded (they
predate the SPI host bridge, PLL, and this session's SDRAM datasheet
audit) with pointers to the new consolidated document, rather than
rewriting each individually.

Updates the V2 LaTeX datasheet's status/roadmap chapter to reflect the
SDRAM datasheet audit and configuration-flash decisions, rebuilds the
PDF (clean compile, 16 pages).

Classification: PRE-PCB VERIFIED. Schematic and PCB implementation
remain user-owned and not started.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-06 18:32:40 +02:00
co-authored by Claude Sonnet 5
parent 8890b0abc2
commit eb0b0f9170
10 changed files with 650 additions and 13 deletions
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hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.log
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hardware/v2/docs/DatasheetLatex/FPGA-Neural-V2-Datasheet-EN.pdf
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hardware/v2/docs/DatasheetLatex/chapters/08-status-roadmap.tex
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@@ -17,11 +17,11 @@ Synthesis (final top, real Yosys run) & \OK\ (0 CHECK-pass problems) \\
\rowa Place\&route (8 real seeds) & \OK\ (8/8 fit, routed, zero errors) \\
Timing closure @ 64\,MHz & \OK\ (8/8 seeds PASS, worst 68.51\,MHz) \\
\rowa Final pinout (44/44 top-level signals) & \OK\ (real balls, P\&R-confirmed) \\
Hold-time analysis & OPEN (not reported by this toolchain's summary) \\
Hold-time analysis & OPEN (tool limitation, see PRE\_PCB\_VERIFICATION.md \S6) \\
\rowa Power: rail voltages & OK (real datasheet values) \\
Power: regulator selection / current budget & OPEN \\
\rowa SDRAM datasheet-parameter cross-check & OPEN (sim-level only) \\
Configuration flash selection & OPEN \\
\rowa SDRAM datasheet-parameter cross-check & \OK\ (real AS4C4M16SA-6TIN Table 17 audit; found and fixed ERR-0026, tMRD unit mismatch) \\
Configuration flash selection & \OK\ (Winbond \code{W25Q32JVSSIQ}, SOIC-8, frozen) \\
\rowa Real KiCad schematic + ERC & NOT STARTED \\
PCB layout & NOT STARTED \\
\rowa BOM (sourced, purchasable parts) & NOT STARTED \\
@@ -49,8 +49,6 @@ complete in this revision.
connectors).
\item Real power current-budget estimate against the actual
synthesized netlist.
\item Real SDRAM-datasheet-parameter cross-check of controller timing
constants.
\item First physical board fabrication and the 15-step bring-up
procedure already documented in \code{FIRST\_POWER\_ON.md}.
\item A real embedded-target (ESP32-class) software baseline, once