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feat: real DDR3 memory path verified against MIG's own ddr3_model.sv (EXP-0068)

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New hardware/v3/rtl/mig_native_adapter.v: adapts this project's
established req/wr/addr/wdata/wmask->rdata/ready/busy contract to the
real MIG 7-series native app interface (app_addr/app_cmd/app_en,
app_wdf_data/app_wdf_mask/app_wdf_wren/app_wdf_end, app_rd_data/
app_rd_data_valid/app_rd_data_end), derived from this project's own
real generated mig_7series_0.v port widths, not assumed. Runs in the
ui_clk domain (MIG's own generated clock becomes this project's
system clock going forward).

Verified against MIG's own real, vendor-shipped DDR3 behavioral model
(ddr3_model.sv) via real Xilinx xsim/xvlog/xelab (UNISIM primitives
in MIG's PHY require this over Verilator): 12/12 write-then-read-back
transactions bit-exact, 0 errors, real JEDEC command sequence observed
(Activate/Write/Read/Precharge). Confirms the app_cmd encoding and
burst/beat sequencing on first real test.

Also adds hardware/v3/rtl/sdram_arbiter_n.v (generalized N-way
arbiter, generalizing EXP-0066's 2-way version for N>2 scaling and a
future host-access requester) -- its own isolated test currently
HANGS, root cause not yet found, do not trust this module yet
(disclosed, not hidden).

Full writeup in hardware/v2/logs/experiments.log EXP-0068.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
michele
2026-09-17 08:43:22 +02:00
co-authored by Claude Sonnet 5
parent 0589620b58
commit e25e4a1506
5 changed files with 847 additions and 0 deletions
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hardware/v2/logs/experiments.log
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@@ -4162,3 +4162,102 @@ attempted, watch specifically for placement congestion effects (the
EXP-0060 8-core-array class of degradation) since that is the one EXP-0060 8-core-array class of degradation) since that is the one
variable not yet tested at higher N with the REAL Director+arbiter variable not yet tested at higher N with the REAL Director+arbiter
system, only with a zero-interconnect array. system, only with a zero-interconnect array.
EXP-0068 -- MILESTONE: first real DDR3 memory path, mig_native_
adapter.v verified against MIG's own real DDR3 behavioral model
(2026-09-17, autonomous continuation while user offline)
CONTEXT: user corrected this session's own long-standing SDR SDRAM
placeholder assumption -- XC7A100T was chosen specifically for DDR3,
this is a from-scratch custom board (bare chip, user's own PCB), not
a dev-board purchase. User then interactively ran the real Vivado MIG
7-series wizard (with this session's real-time guidance, including a
genuine self-correction on Clock Period -- the tool's own "maintain
default or higher" warning overrode this session's earlier "push to
the fastest allowed period" advice) to generate a REAL DDR3 IP core:
mig_7series_0, part xc7a100tcsg324-1 (corrected from an initially
wrong -3 speed grade, also caught this session), memory part
MT41J128M16JT-125:K (chosen over the originally-suggested MT41K
variant specifically because it's the one confirmed in stock on LCSC
-- real component sourcing, not just simulation convenience), Data
Width 16, PHY:Controller ratio 2:1, Design Clock Frequency 3225ps
(310.08MHz, auto-adjusted by the tool for the real -1 speed grade).
Real IP generation + its own out-of-context synthesis both completed
with 0 errors (3782 LUT48/63400, 5.97%).
User then requested autonomous continuation: build the real DDR3
integration, get real (not placeholder) timing, and re-audit the SPI
opcode set for V3 correctness/completeness.
METHOD: read the REAL generated mig_7series_0.v top wrapper's own
port list (not assumed) to get the actual native "app" UI interface
(PG063-standard: app_addr[27:0]/app_cmd[2:0]/app_en, app_wdf_data
[63:0]/app_wdf_mask[7:0]/app_wdf_wren/app_wdf_end, app_rd_data[63:0]/
app_rd_data_valid/app_rd_data_end, app_rdy/app_wdf_rdy, ui_clk/
ui_clk_sync_rst/init_calib_complete) -- confirmed the 64-bit app data
width matches this project's own real config (16-bit DDR3 x BURST_LEN
8 / nCK_PER_CLK 2 = 64), meaning one app_addr/app_cmd issuance moves a
full BURST_LEN=8 (128-bit) chunk as two 64-bit beats -- the SAME unit
this project's own ctrl_addr has used everywhere since STEP16, so no
address-scaling needed at this boundary.
New hardware/v3/rtl/mig_native_adapter.v: adapts this project's
established req/wr/addr/wdata/wmask->rdata/ready/busy contract to the
real MIG native app interface, running entirely in the ui_clk domain
(the standard way MIG designs are built -- ui_clk becomes this
project's system clock going forward, not a separate CDC boundary).
Sequential, not pipelined (correctness first): command issued and
accepted before any write-data beat; each of the two write-data beats
held until its own app_wdf_rdy.
app_cmd encoding (000=Write, 001=Read) is the stable, well-known MIG
convention -- but per this project's own "measure, don't assume"
standard, NOT taken on faith: verified against MIG's own real,
vendor-shipped ddr3_model.sv (found the exact real files needed by
reading this project's own generated example_design/sim tree --
mig_7series_0_mig_sim.v, which unlike the public mig_7series_0.v
wrapper exposes SIM_BYPASS_INIT_CAL="FAST" and unlike mig_7series_0_
mig.v defaults to it, avoiding an impractically slow full-calibration
sim; wiredly.v for the real WireDelay zero-delay DQ/DQS pass-through
this project's own vendor testbench uses). New hardware/v3/sim/
tb_mig_native_adapter.v mirrors example_design/sim/sim_tb_top.v's own
proven clock/reset generation exactly (CLKIN_PERIOD=3225ps, matching
this project's real config) rather than re-deriving it.
Compiled via real Xilinx xsim/xvlog/xelab (not Verilator -- MIG's PHY
uses real UNISIM primitives Verilator cannot simulate), 69 real RTL
files, -L unisims_ver/unimacro_ver/secureip, +glbl. Found and fixed
one real bug during elaboration (xelab itself caught it, not visual
inspection): app_addr declared 25 bits in the testbench but indexed
[27:0] (28 bits) at both instantiation sites -- fixed to a genuine
28-bit declaration.
RESULT: real DDR3 calibration completed (FAST sim mode) at ~usual
MIG sim timescale; 12/12 write-then-read-back transactions bit-exact
against the real ddr3_model.sv, 0 errors, real JEDEC command sequence
observed in the model's own log (Activate/Write/Read/Precharge,
correct bank/row/col progression) -- confirms the app_cmd encoding,
burst/beat sequencing, and address-unit assumptions were all correct
on the first real test, not by luck: they were independently
cross-checked against the real generated ui_top/mem_intfc RTL
parameter widths before this run, and this run is the actual
empirical confirmation.
DECISION: mig_native_adapter.v is genuinely verified against real
DDR3 timing, not a placeholder. This is the first real memory-
technology-correct path this project has had -- everything before
this (EXP-0057 onward) used the declared SDR SDRAM stand-in.
next_action: (1) re-audit spi_host_bridge.v against V3's actual
architecture (neural_director_packed.v's job_in_* port lacks the
dependency-tracking fields -- required/producer_ids -- that spi_host_
bridge.v's own WRITE_JOB opcode was built for, and V3 has NO host
raw-memory-access path at all yet, the WRITE_MEM/READ_MEM equivalent
-- both real, disclosed gaps, not yet closed); (2) generalize the
N=2 arbiter to N-way (in progress: hardware/v3/rtl/sdram_arbiter_n.v,
its own isolated test hardware/v3/sim/tb_sdram_arbiter_n.v currently
hangs, root cause not yet found -- do not trust this module until
that is resolved); (3) swap mig_native_adapter.v into packed_slot.v's
memory path, replacing the SDR SDRAM placeholder, and re-verify the
N=2 system against real DDR3; (4) real (not out-of-context) P&R with
the actual generated MIG XDC constraints for genuine timing signoff.
hardware/v3/rtl/mig_native_adapter.v
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`timescale 1ns/1ps
// ============================================================
// V3 -- adapter between this project's own established memory-
// controller contract (req/wr/addr/wdata/wmask -> rdata/ready/busy,
// BURST_LEN=8 16-bit words = 128 bits/transaction, the SAME shape
// sdram_controller.v has presented everywhere in this project since
// STEP16) and the REAL Xilinx MIG 7-series native "app" user
// interface (PG063), generated for this project's actual DDR3 target
// (mig_7series_0, XC7A100T, MT41J128M16JT-125:K, PHY:Controller
// ratio 2:1).
//
// Runs entirely in the ui_clk domain -- MIG's own generated clock is
// this design's new system clock (the standard way MIG-based designs
// are built; matches every real MIG reference design, not a
// deviation this project is inventing). rst must already be
// synchronized to ui_clk by the caller.
//
// ADDRESSING (real, derived from THIS project's actual generated MIG
// config, not assumed): Data Width=16, Phy:Controller ratio 2:1 =>
// nCK_PER_CLK=2 => app data width = 16*8/2 = 64 bits, matching the
// real generated mig_7series_0.v port widths exactly (app_wdf_data
// [63:0], app_rd_data[63:0]). One app_addr/app_cmd issuance moves a
// FULL BURST_LEN=8 (128-bit) DDR3 burst, delivered as TWO 64-bit
// beats on the app data bus -- so app_addr increments in the SAME
// unit as this project's own existing ctrl_addr (one BURST_LEN=8
// chunk per increment), no address scaling needed at this boundary.
//
// Sequencing is deliberately fully sequential, not pipelined
// (correctness first): the command is issued and accepted (app_en/
// app_rdy) BEFORE any write-data beat is asserted, and each of the
// two write-data beats (real MIG allows the address and write-data
// channels to accept independently/concurrently -- not used here) is
// held until its own app_wdf_rdy fires.
//
// app_cmd encoding (000=Write, 001=Read) is the standard, stable MIG
// convention -- NOT taken on faith alone: hardware/v3/sim/
// tb_mig_native_adapter.v verifies this adapter against MIG's own
// real, vendor-provided ddr3_model.sv (write, real DDR3 behavioral
// model, real read-back, bit-exact compare), so a wrong assumption
// here would show up as a real, observed data mismatch, not silently
// trusted.
// ============================================================
module mig_native_adapter #(
parameter BURST_LEN = 8,
parameter ADDR_WIDTH = 25 // matches this project's own word-address convention
)(
input wire clk, // = ui_clk
input wire rst, // pre-synchronized to ui_clk
// ---- this project's own established memory-controller contract ----
input wire req,
input wire wr,
input wire [ADDR_WIDTH-1:0] addr,
input wire [16*BURST_LEN-1:0] wdata,
input wire [2*BURST_LEN-1:0] wmask,
output reg [16*BURST_LEN-1:0] rdata,
output reg ready,
output wire busy,
// ---- MIG native "app" interface (real generated port widths) ----
output reg [27:0] app_addr,
output reg [2:0] app_cmd,
output reg app_en,
input wire app_rdy,
output reg [63:0] app_wdf_data,
output reg app_wdf_end,
output reg [7:0] app_wdf_mask,
output reg app_wdf_wren,
input wire app_wdf_rdy,
input wire [63:0] app_rd_data,
input wire app_rd_data_end,
input wire app_rd_data_valid
);
localparam CMD_WRITE = 3'b000;
localparam CMD_READ = 3'b001;
localparam S_IDLE = 3'd0,
S_CMD_WAIT = 3'd1,
S_WDF0 = 3'd2,
S_WDF1 = 3'd3,
S_RD_WAIT = 3'd4,
S_DONE = 3'd5;
reg [2:0] state;
reg wr_lat;
reg [16*BURST_LEN-1:0] wdata_lat;
reg [2*BURST_LEN-1:0] wmask_lat;
assign busy = (state != S_IDLE);
always @(posedge clk) begin
if (rst) begin
state <= S_IDLE;
app_en <= 1'b0;
app_wdf_wren <= 1'b0;
app_wdf_end <= 1'b0;
ready <= 1'b0;
rdata <= {(16*BURST_LEN){1'b0}};
app_addr <= 28'h0;
app_cmd <= CMD_READ;
app_wdf_data <= 64'h0;
app_wdf_mask <= 8'h0;
end else begin
ready <= 1'b0;
case (state)
S_IDLE: begin
if (req) begin
wr_lat <= wr;
wdata_lat <= wdata;
wmask_lat <= wmask;
app_addr <= {{(28-ADDR_WIDTH){1'b0}}, addr};
app_cmd <= wr ? CMD_WRITE : CMD_READ;
app_en <= 1'b1;
state <= S_CMD_WAIT;
end
end
S_CMD_WAIT: begin
if (app_rdy) begin
app_en <= 1'b0;
if (wr_lat) begin
app_wdf_data <= wdata_lat[63:0];
app_wdf_mask <= wmask_lat[7:0];
app_wdf_end <= 1'b0;
app_wdf_wren <= 1'b1;
state <= S_WDF0;
end else begin
state <= S_RD_WAIT;
end
end
end
S_WDF0: begin
if (app_wdf_rdy) begin
app_wdf_data <= wdata_lat[127:64];
app_wdf_mask <= wmask_lat[15:8];
app_wdf_end <= 1'b1;
app_wdf_wren <= 1'b1;
state <= S_WDF1;
end
end
S_WDF1: begin
if (app_wdf_rdy) begin
app_wdf_wren <= 1'b0;
app_wdf_end <= 1'b0;
state <= S_DONE;
end
end
S_RD_WAIT: begin
if (app_rd_data_valid) begin
if (!app_rd_data_end) begin
rdata[63:0] <= app_rd_data;
end else begin
rdata[127:64] <= app_rd_data;
state <= S_DONE;
end
end
end
S_DONE: begin
ready <= 1'b1;
state <= S_IDLE;
end
default: state <= S_IDLE;
endcase
end
end
endmodule
hardware/v3/rtl/sdram_arbiter_n.v
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`timescale 1ns/1ps
// ============================================================
// V3 -- generalized N-way arbiter for a shared memory controller
// port (SDRAM placeholder today, DDR3/mig_native_adapter.v tomorrow
// -- this arbiter sits on the req/wr/addr/wdata/wmask->rdata/ready/
// busy side, identical on either backend).
//
// Generalizes sdram_slot_arbiter2.v (EXP-0066) to NUM_REQ requesters
// instead of a hardcoded 2, for (a) scaling the compute system past
// N=2 packed slots, and (b) adding a HOST raw-memory-access requester
// (the still-missing SPI WRITE_MEM/READ_MEM equivalent for V3,
// flagged when re-auditing spi_host_bridge.v's own opcode set against
// this project's actual V3 architecture).
//
// Preserves EXACTLY the combinational-first-grant mechanism EXP-0066
// found necessary the hard way: layer_prefetch_ctrl.v (and any other
// requester built the same way, e.g. a future host-access engine)
// issues its own ctrl_req as a genuine ONE-SHOT pulse with no retry,
// so a requester must see ITS OWN grant asserted the SAME cycle its
// own `active` first goes high, or that first request is silently
// lost forever (a real, previously-hit bug, not a hypothetical one --
// see EXP-0066's own writeup). `locked`/`grant_reg` below only LATCH
// a decision already available combinationally, purely to keep it
// sticky once made (no mid-fetch grant switching), never to delay
// the first grant.
//
// Priority: lowest-indexed active requester wins on first grant (same
// policy as sdram_slot_arbiter2.v -- a documented, simple, first-
// come-by-index scheme, not fairness-optimized; matches this
// project's own "correctness first" precedent of choosing the
// simplest policy that is provably correct before optimizing).
// ============================================================
module sdram_arbiter_n #(
parameter NUM_REQ = 3,
parameter ADDR_WIDTH = 25,
parameter BURST_LEN = 8
)(
input wire clk,
input wire rst,
input wire [NUM_REQ-1:0] req_active,
output wire [NUM_REQ-1:0] req_grant,
input wire [NUM_REQ-1:0] req_req,
input wire [NUM_REQ-1:0] req_wr,
input wire [NUM_REQ*ADDR_WIDTH-1:0] req_addr,
input wire [NUM_REQ*16*BURST_LEN-1:0] req_wdata,
input wire [NUM_REQ*2*BURST_LEN-1:0] req_wmask,
output wire [NUM_REQ*16*BURST_LEN-1:0] req_rdata,
output wire [NUM_REQ-1:0] req_ready,
output wire [NUM_REQ-1:0] req_busy,
output wire ctrl_req,
output wire ctrl_wr,
output wire [ADDR_WIDTH-1:0] ctrl_addr,
output wire [16*BURST_LEN-1:0] ctrl_wdata,
output wire [2*BURST_LEN-1:0] ctrl_wmask,
input wire [16*BURST_LEN-1:0] ctrl_rdata,
input wire ctrl_ready,
input wire ctrl_busy
);
localparam SELW = (NUM_REQ <= 1) ? 1 : $clog2(NUM_REQ);
wire any_active = |req_active;
// combinational lowest-index-active picker -- available with zero
// cycle latency relative to req_active first asserting (see header).
reg [SELW-1:0] pick_idx;
integer pi;
always @(*) begin
pick_idx = {SELW{1'b0}};
for (pi = NUM_REQ-1; pi >= 0; pi = pi - 1)
if (req_active[pi]) pick_idx = pi[SELW-1:0];
end
reg locked;
reg [SELW-1:0] grant_idx_r;
wire [SELW-1:0] grant_idx_now = locked ? grant_idx_r : pick_idx;
always @(posedge clk) begin
if (rst) begin
locked <= 1'b0;
grant_idx_r <= {SELW{1'b0}};
end else begin
if (!locked) begin
if (any_active) begin
locked <= 1'b1;
grant_idx_r <= grant_idx_now;
end
end else begin
if (!req_active[grant_idx_r]) locked <= 1'b0;
end
end
end
wire [NUM_REQ-1:0] sel;
genvar gs;
generate
for (gs = 0; gs < NUM_REQ; gs = gs + 1) begin : GEN_SEL
assign sel[gs] = any_active && (grant_idx_now == gs[SELW-1:0]);
end
endgenerate
assign req_grant = sel;
// mux request-side signals from the granted requester -> shared ctrl
reg m_req, m_wr;
reg [ADDR_WIDTH-1:0] m_addr;
reg [16*BURST_LEN-1:0] m_wdata;
reg [2*BURST_LEN-1:0] m_wmask;
integer mi;
always @(*) begin
m_req = 1'b0;
m_wr = 1'b0;
m_addr = {ADDR_WIDTH{1'b0}};
m_wdata = {(16*BURST_LEN){1'b0}};
m_wmask = {(2*BURST_LEN){1'b0}};
for (mi = 0; mi < NUM_REQ; mi = mi + 1) begin
if (sel[mi]) begin
m_req = req_req[mi];
m_wr = req_wr[mi];
m_addr = req_addr[mi*ADDR_WIDTH +: ADDR_WIDTH];
m_wdata = req_wdata[mi*16*BURST_LEN +: 16*BURST_LEN];
m_wmask = req_wmask[mi*2*BURST_LEN +: 2*BURST_LEN];
end
end
end
assign ctrl_req = m_req;
assign ctrl_wr = m_wr;
assign ctrl_addr = m_addr;
assign ctrl_wdata = m_wdata;
assign ctrl_wmask = m_wmask;
// demux response back to whichever requester is currently granted
genvar gd;
generate
for (gd = 0; gd < NUM_REQ; gd = gd + 1) begin : GEN_DEMUX
assign req_rdata[gd*16*BURST_LEN +: 16*BURST_LEN] = ctrl_rdata;
assign req_ready[gd] = sel[gd] ? ctrl_ready : 1'b0;
assign req_busy[gd] = sel[gd] ? ctrl_busy : 1'b1;
end
endgenerate
endmodule
hardware/v3/sim/tb_mig_native_adapter.v
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`timescale 1ps/100fs
// ============================================================
// First real verification of mig_native_adapter.v against the REAL,
// vendor-provided DDR3 behavioral model (ddr3_model.sv, shipped with
// this project's own generated mig_7series_0 IP) -- not a stand-in,
// the actual JEDEC-timed model MIG itself ships for exactly this
// purpose. Confirms the app_cmd encoding, burst/beat sequencing, and
// address unit assumed by mig_native_adapter.v's own header comment
// are correct by real write-then-read-back comparison, not by
// documentation archaeology alone.
//
// Instantiates mig_7series_0_mig (the inner module, NOT the public
// mig_7series_0.v wrapper) directly, with SIM_BYPASS_INIT_CAL="FAST"
// overridden -- mig_7series_0.v's own wrapper hardcodes "OFF" (full
// real calibration, impractically slow for simulation) and does not
// expose this parameter; mig_7series_0_mig.v does. All other
// parameters are left at their defaults, which already ARE this
// project's real generated configuration (DQ_WIDTH=16, MEM_DENSITY=
// 2Gb, MEM_SPEEDGRADE=125, MEM_ADDR_ORDER=BANK_ROW_COLUMN, etc.) --
// not generic MIG defaults.
//
// Clock/reset generation and DDR3 pin wiring (WireDelay pass-through,
// zero propagation delay) mirror this project's own vendor-shipped
// example_design/sim/sim_tb_top.v exactly, per its own real, proven
// pattern -- not re-derived from scratch.
// ============================================================
module tb;
localparam CLKIN_PERIOD = 3225; // ps, matches this project's real MIG config
localparam REFCLK_FREQ = 200.0; // MHz
localparam real REFCLK_PERIOD = (1000000.0/(2*REFCLK_FREQ));
localparam RESET_PERIOD = 200000; // ps
localparam ADDR_WIDTH = 25; // this project's own word-address convention (BURST_LEN=8)
localparam BURST_LEN = 8;
reg sys_rst_n;
wire sys_rst = sys_rst_n; // Active Low, matches mig_7series_0_mig's own default polarity
reg sys_clk_i = 1'b0;
always #(CLKIN_PERIOD/2.0) sys_clk_i = ~sys_clk_i;
reg clk_ref_i = 1'b0;
always #REFCLK_PERIOD clk_ref_i = ~clk_ref_i;
initial begin
sys_rst_n = 1'b0;
#RESET_PERIOD sys_rst_n = 1'b1;
end
// ---- real DDR3 pins ----
wire ddr3_reset_n;
wire [15:0] ddr3_dq_fpga;
wire [1:0] ddr3_dqs_p_fpga, ddr3_dqs_n_fpga;
wire [13:0] ddr3_addr_fpga;
wire [2:0] ddr3_ba_fpga;
wire ddr3_ras_n_fpga, ddr3_cas_n_fpga, ddr3_we_n_fpga;
wire [0:0] ddr3_cke_fpga, ddr3_ck_p_fpga, ddr3_ck_n_fpga, ddr3_cs_n_fpga;
wire [1:0] ddr3_dm_fpga;
wire [0:0] ddr3_odt_fpga;
wire [15:0] ddr3_dq_sdram;
reg [13:0] ddr3_addr_sdram;
reg [2:0] ddr3_ba_sdram;
reg ddr3_ras_n_sdram, ddr3_cas_n_sdram, ddr3_we_n_sdram;
wire [0:0] ddr3_cs_n_sdram;
wire [0:0] ddr3_odt_sdram;
reg [0:0] ddr3_cke_sdram;
wire [1:0] ddr3_dm_sdram;
wire [1:0] ddr3_dqs_p_sdram, ddr3_dqs_n_sdram;
reg [0:0] ddr3_ck_p_sdram, ddr3_ck_n_sdram;
reg [0:0] ddr3_cs_n_sdram_tmp;
reg [1:0] ddr3_dm_sdram_tmp;
reg [0:0] ddr3_odt_sdram_tmp;
always @(*) begin
ddr3_ck_p_sdram <= ddr3_ck_p_fpga;
ddr3_ck_n_sdram <= ddr3_ck_n_fpga;
ddr3_addr_sdram <= ddr3_addr_fpga;
ddr3_ba_sdram <= ddr3_ba_fpga;
ddr3_ras_n_sdram <= ddr3_ras_n_fpga;
ddr3_cas_n_sdram <= ddr3_cas_n_fpga;
ddr3_we_n_sdram <= ddr3_we_n_fpga;
ddr3_cke_sdram <= ddr3_cke_fpga;
end
always @(*) ddr3_cs_n_sdram_tmp <= ddr3_cs_n_fpga;
assign ddr3_cs_n_sdram = ddr3_cs_n_sdram_tmp;
always @(*) ddr3_dm_sdram_tmp <= ddr3_dm_fpga;
assign ddr3_dm_sdram = ddr3_dm_sdram_tmp;
always @(*) ddr3_odt_sdram_tmp <= ddr3_odt_fpga;
assign ddr3_odt_sdram = ddr3_odt_sdram_tmp;
genvar dqwd;
generate
for (dqwd = 0; dqwd < 16; dqwd = dqwd + 1) begin : dq_delay
WireDelay #(.Delay_g(0.00), .Delay_rd(0.00), .ERR_INSERT("OFF")) u_delay_dq (
.A(ddr3_dq_fpga[dqwd]), .B(ddr3_dq_sdram[dqwd]),
.reset(sys_rst_n), .phy_init_done(init_calib_complete)
);
end
endgenerate
genvar dqswd;
generate
for (dqswd = 0; dqswd < 2; dqswd = dqswd + 1) begin : dqs_delay
WireDelay #(.Delay_g(0.00), .Delay_rd(0.00), .ERR_INSERT("OFF")) u_delay_dqs_p (
.A(ddr3_dqs_p_fpga[dqswd]), .B(ddr3_dqs_p_sdram[dqswd]),
.reset(sys_rst_n), .phy_init_done(init_calib_complete)
);
WireDelay #(.Delay_g(0.00), .Delay_rd(0.00), .ERR_INSERT("OFF")) u_delay_dqs_n (
.A(ddr3_dqs_n_fpga[dqswd]), .B(ddr3_dqs_n_sdram[dqswd]),
.reset(sys_rst_n), .phy_init_done(init_calib_complete)
);
end
endgenerate
// ---- real DDR3 behavioral model (single component, DQ_WIDTH=16
// matches MEMORY_WIDTH=16 exactly, no splitting needed) ----
ddr3_model u_ddr3 (
.rst_n(ddr3_reset_n), .ck(ddr3_ck_p_sdram), .ck_n(ddr3_ck_n_sdram),
.cke(ddr3_cke_sdram[0]), .cs_n(ddr3_cs_n_sdram[0]),
.ras_n(ddr3_ras_n_sdram), .cas_n(ddr3_cas_n_sdram), .we_n(ddr3_we_n_sdram),
.dm_tdqs(ddr3_dm_sdram), .ba(ddr3_ba_sdram), .addr(ddr3_addr_sdram),
.dq(ddr3_dq_sdram), .dqs(ddr3_dqs_p_sdram), .dqs_n(ddr3_dqs_n_sdram),
.tdqs_n(), .odt(ddr3_odt_sdram[0])
);
// ---- real MIG controller (inner module, SIM_BYPASS_INIT_CAL
// overridden for a real but fast simulation calibration) ----
wire [27:0] app_addr;
wire [2:0] app_cmd;
wire app_en, app_rdy;
wire [63:0] app_wdf_data;
wire app_wdf_end;
wire [7:0] app_wdf_mask;
wire app_wdf_wren, app_wdf_rdy;
wire [63:0] app_rd_data;
wire app_rd_data_end, app_rd_data_valid;
wire ui_clk, ui_clk_sync_rst, init_calib_complete;
mig_7series_0_mig #(
.SIM_BYPASS_INIT_CAL("FAST")
) u_mig (
.ddr3_dq(ddr3_dq_fpga), .ddr3_dqs_n(ddr3_dqs_n_fpga), .ddr3_dqs_p(ddr3_dqs_p_fpga),
.ddr3_addr(ddr3_addr_fpga), .ddr3_ba(ddr3_ba_fpga),
.ddr3_ras_n(ddr3_ras_n_fpga), .ddr3_cas_n(ddr3_cas_n_fpga), .ddr3_we_n(ddr3_we_n_fpga),
.ddr3_reset_n(ddr3_reset_n),
.ddr3_ck_p(ddr3_ck_p_fpga), .ddr3_ck_n(ddr3_ck_n_fpga),
.ddr3_cke(ddr3_cke_fpga), .ddr3_cs_n(ddr3_cs_n_fpga),
.ddr3_dm(ddr3_dm_fpga), .ddr3_odt(ddr3_odt_fpga),
.sys_clk_i(sys_clk_i), .clk_ref_i(clk_ref_i),
.app_addr(app_addr), .app_cmd(app_cmd), .app_en(app_en),
.app_wdf_data(app_wdf_data), .app_wdf_end(app_wdf_end),
.app_wdf_mask(app_wdf_mask), .app_wdf_wren(app_wdf_wren),
.app_rd_data(app_rd_data), .app_rd_data_end(app_rd_data_end),
.app_rd_data_valid(app_rd_data_valid), .app_rdy(app_rdy), .app_wdf_rdy(app_wdf_rdy),
.app_sr_req(1'b0), .app_ref_req(1'b0), .app_zq_req(1'b0),
.app_sr_active(), .app_ref_ack(), .app_zq_ack(),
.ui_clk(ui_clk), .ui_clk_sync_rst(ui_clk_sync_rst),
.init_calib_complete(init_calib_complete),
.device_temp(),
.sys_rst(sys_rst)
);
// ---- adapter under test ----
reg req, wr;
reg [ADDR_WIDTH-1:0] addr;
reg [16*BURST_LEN-1:0] wdata;
reg [2*BURST_LEN-1:0] wmask;
wire [16*BURST_LEN-1:0] rdata;
wire ready, busy;
mig_native_adapter #(.BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH)) u_adapter (
.clk(ui_clk), .rst(ui_clk_sync_rst),
.req(req), .wr(wr), .addr(addr), .wdata(wdata), .wmask(wmask),
.rdata(rdata), .ready(ready), .busy(busy),
.app_addr(app_addr), .app_cmd(app_cmd), .app_en(app_en), .app_rdy(app_rdy),
.app_wdf_data(app_wdf_data), .app_wdf_end(app_wdf_end), .app_wdf_mask(app_wdf_mask),
.app_wdf_wren(app_wdf_wren), .app_wdf_rdy(app_wdf_rdy),
.app_rd_data(app_rd_data), .app_rd_data_end(app_rd_data_end), .app_rd_data_valid(app_rd_data_valid)
);
task automatic do_txn(
input t_wr,
input [ADDR_WIDTH-1:0] t_addr,
input [16*BURST_LEN-1:0] t_wdata,
output [16*BURST_LEN-1:0] t_rdata
);
begin
@(posedge ui_clk);
while (busy) @(posedge ui_clk);
req = 1'b1; wr = t_wr; addr = t_addr; wdata = t_wdata; wmask = {(2*BURST_LEN){1'b0}};
@(posedge ui_clk);
req = 1'b0;
while (!ready) @(posedge ui_clk);
t_rdata = rdata;
end
endtask
integer errors, tests;
reg [16*BURST_LEN-1:0] got, wpat;
integer k, i;
task automatic check_addr(input [ADDR_WIDTH-1:0] a, input [15:0] pattern);
begin
for (k = 0; k < BURST_LEN; k = k + 1)
wpat[k*16 +: 16] = pattern + k[15:0];
do_txn(1'b1, a, wpat, got);
do_txn(1'b0, a, {(16*BURST_LEN){1'b0}}, got);
tests = tests + 1;
if (got !== wpat) begin
$display("FAIL addr=%0d: got=%h expected=%h", a, got, wpat);
errors = errors + 1;
end else begin
$display("PASS addr=%0d: bit-exact %h", a, got);
end
end
endtask
initial begin
errors = 0; tests = 0;
req = 0; wr = 0; addr = 0; wdata = 0; wmask = 0;
$display("=== waiting for real DDR3 init_calib_complete (FAST sim calibration) ===");
wait (init_calib_complete);
$display("=== calibration done at time %0t, starting real write/read-back test ===", $time);
repeat (10) @(posedge ui_clk);
check_addr(25'd0, 16'hA5A5);
check_addr(25'd8, 16'h1000);
check_addr(25'd16, 16'h2000);
check_addr(25'd1024,16'h3000);
for (i = 0; i < 8; i = i + 1)
check_addr((25'd2048 + i*8), 16'h4000 + i);
$display("=== %0d/%0d tests, %0d errors ===", tests-errors, tests, errors);
if (errors == 0) $display("ALL TESTS PASSED (tb_mig_native_adapter, real ddr3_model.sv)");
else $display("SOME TESTS FAILED");
$finish;
end
initial begin
#200000000.0; // 200us watchdog
if (!init_calib_complete) $display("FAIL: calibration never completed within watchdog");
else $display("(watchdog fired after calibration already completed -- not a failure by itself)");
$finish;
end
endmodule
hardware/v3/sim/tb_sdram_arbiter_n.v
+180
View File
@@ -0,0 +1,180 @@
`timescale 1ns/1ps
// ============================================================
// Isolated correctness test for sdram_arbiter_n.v (NUM_REQ=3, the
// immediate real use case: 2 packed slots + 1 host raw-access
// requester). Each requester stub mirrors layer_prefetch_ctrl.v's
// own real, risky pattern that caused EXP-0066's real bug: a ONE-SHOT
// ctrl_req pulse issued the instant its own `active` first goes high,
// no retry -- this test exists specifically to re-confirm the
// combinational-first-grant fix generalizes correctly to N=3, not
// just N=2.
// ============================================================
module tb;
localparam BURST_LEN = 8;
localparam ROW_BITS = 13;
localparam COL_BITS = 10;
localparam BANK_BITS = 2;
localparam ADDR_WIDTH = BANK_BITS + ROW_BITS + COL_BITS;
localparam CLK_FREQ_MHZ = 64;
localparam CLK_PERIOD_NS = 1000.0/CLK_FREQ_MHZ;
localparam NUM_REQ = 3;
reg clk = 0;
always #(CLK_PERIOD_NS/2.0) clk = ~clk;
reg rst;
wire ctrl_req, ctrl_wr;
wire [ADDR_WIDTH-1:0] ctrl_addr;
wire [16*BURST_LEN-1:0] ctrl_wdata, ctrl_rdata;
wire [2*BURST_LEN-1:0] ctrl_wmask;
wire ctrl_ready, ctrl_busy;
wire cke, cs_n, ras_n, cas_n, we_n;
wire [BANK_BITS-1:0] ba;
wire [ROW_BITS-1:0] a;
wire [15:0] dq;
wire [1:0] dqm;
sdram_controller #(
.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(BURST_LEN),
.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
) u_ctrl (
.clk(clk), .rst(rst),
.req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr), .wdata(ctrl_wdata), .wmask(ctrl_wmask),
.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy),
.sdram_cke(cke), .sdram_cs_n(cs_n), .sdram_ras_n(ras_n), .sdram_cas_n(cas_n), .sdram_we_n(we_n),
.sdram_ba(ba), .sdram_a(a), .sdram_dq(dq), .sdram_dqm(dqm)
);
sdram_model #(
.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
) u_mem (
.clk(clk), .cke(cke), .cs_n(cs_n), .ras_n(ras_n), .cas_n(cas_n), .we_n(we_n),
.ba(ba), .a(a), .dq(dq), .dqm(dqm)
);
reg [NUM_REQ-1:0] req_active, req_req, req_wr;
wire [NUM_REQ-1:0] req_grant, req_ready, req_busy;
reg [NUM_REQ*ADDR_WIDTH-1:0] req_addr;
reg [NUM_REQ*16*BURST_LEN-1:0] req_wdata;
reg [NUM_REQ*2*BURST_LEN-1:0] req_wmask;
wire [NUM_REQ*16*BURST_LEN-1:0] req_rdata;
sdram_arbiter_n #(
.NUM_REQ(NUM_REQ), .ADDR_WIDTH(ADDR_WIDTH), .BURST_LEN(BURST_LEN)
) u_arb (
.clk(clk), .rst(rst),
.req_active(req_active), .req_grant(req_grant),
.req_req(req_req), .req_wr(req_wr), .req_addr(req_addr),
.req_wdata(req_wdata), .req_wmask(req_wmask),
.req_rdata(req_rdata), .req_ready(req_ready), .req_busy(req_busy),
.ctrl_req(ctrl_req), .ctrl_wr(ctrl_wr), .ctrl_addr(ctrl_addr),
.ctrl_wdata(ctrl_wdata), .ctrl_wmask(ctrl_wmask),
.ctrl_rdata(ctrl_rdata), .ctrl_ready(ctrl_ready), .ctrl_busy(ctrl_busy)
);
integer errors, tests;
// one-shot-pulse requester task: mirrors layer_prefetch_ctrl.v's
// own real risk pattern -- raise active, issue req THE SAME cycle
// active first asserts (no waiting for grant confirmation first),
// no retry if lost.
task automatic one_shot_txn(
input integer slot, input t_wr, input [ADDR_WIDTH-1:0] t_addr,
input [16*BURST_LEN-1:0] t_wdata, output [16*BURST_LEN-1:0] t_rdata
);
begin
@(posedge clk);
req_active[slot] = 1'b1;
req_req[slot] = 1'b1;
req_wr[slot] = t_wr;
req_addr[slot*ADDR_WIDTH +: ADDR_WIDTH] = t_addr;
req_wdata[slot*16*BURST_LEN +: 16*BURST_LEN] = t_wdata;
req_wmask[slot*2*BURST_LEN +: 2*BURST_LEN] = {(2*BURST_LEN){1'b0}};
@(posedge clk);
req_req[slot] = 1'b0;
while (!req_ready[slot]) @(posedge clk);
t_rdata = req_rdata[slot*16*BURST_LEN +: 16*BURST_LEN];
req_active[slot] = 1'b0;
end
endtask
reg [16*BURST_LEN-1:0] got, wpat;
integer k;
task automatic check_slot(input integer slot, input [ADDR_WIDTH-1:0] a, input [15:0] pattern);
integer i;
begin
for (i = 0; i < BURST_LEN; i = i + 1)
wpat[i*16 +: 16] = pattern + i[15:0];
one_shot_txn(slot, 1'b1, a, wpat, got);
one_shot_txn(slot, 1'b0, a, {(16*BURST_LEN){1'b0}}, got);
tests = tests + 1;
if (got !== wpat) begin
$display("FAIL slot=%0d addr=%0d: got=%h expected=%h", slot, a, got, wpat);
errors = errors + 1;
end else begin
$display("PASS slot=%0d addr=%0d: bit-exact", slot, a);
end
end
endtask
integer i;
initial begin
errors = 0; tests = 0;
rst = 1; req_active = 0; req_req = 0; req_wr = 0; req_addr = 0; req_wdata = 0; req_wmask = 0;
repeat(5) @(posedge clk);
rst = 0;
@(posedge clk);
$display("=== TEST 1: sequential single-requester transactions, all 3 slots ===");
check_slot(0, 25'd0, 16'hA000);
check_slot(1, 25'd8, 16'hB000);
check_slot(2, 25'd16, 16'hC000);
$display("=== TEST 2: simultaneous multi-requester activation (the real EXP-0066 risk case) ===");
begin : test2
reg [16*BURST_LEN-1:0] g0, g1, g2, w0, w1, w2;
integer kk;
for (kk = 0; kk < BURST_LEN; kk = kk + 1) begin
w0[kk*16 +: 16] = 16'hD000 + kk[15:0];
w1[kk*16 +: 16] = 16'hE000 + kk[15:0];
w2[kk*16 +: 16] = 16'hF000 + kk[15:0];
end
// all three assert `active`+`req` on the SAME cycle --
// exactly the scenario a registered/late grant loses.
@(posedge clk);
req_active = 3'b111; req_req = 3'b111;
req_wr[0] = 1'b1; req_wr[1] = 1'b1; req_wr[2] = 1'b1;
req_addr[0*ADDR_WIDTH +: ADDR_WIDTH] = 25'd100;
req_addr[1*ADDR_WIDTH +: ADDR_WIDTH] = 25'd108;
req_addr[2*ADDR_WIDTH +: ADDR_WIDTH] = 25'd116;
req_wdata[0*16*BURST_LEN +: 16*BURST_LEN] = w0;
req_wdata[1*16*BURST_LEN +: 16*BURST_LEN] = w1;
req_wdata[2*16*BURST_LEN +: 16*BURST_LEN] = w2;
@(posedge clk);
req_req = 3'b000;
// slot 0 (lowest index) must win first; 1 and 2 must NOT
// silently lose their request -- wait for each in turn.
while (!req_ready[0]) @(posedge clk);
req_active[0] = 1'b0;
while (!req_ready[1]) @(posedge clk);
req_active[1] = 1'b0;
while (!req_ready[2]) @(posedge clk);
req_active[2] = 1'b0;
tests = tests + 1;
$display("PASS TEST2: all 3 simultaneous requests completed (none silently lost)");
// now read back all three and confirm bit-exact, real
// proof none of the writes were corrupted/misrouted.
check_slot(0, 25'd100, 16'hD000);
check_slot(1, 25'd108, 16'hE000);
check_slot(2, 25'd116, 16'hF000);
end
$display("=== %0d/%0d tests, %0d errors ===", tests-errors, tests, errors);
if (errors == 0) $display("ALL TESTS PASSED (tb_sdram_arbiter_n)");
$finish;
end
endmodule