feat: real DDR3 memory path verified against MIG's own ddr3_model.sv (EXP-0068)
New hardware/v3/rtl/mig_native_adapter.v: adapts this project's established req/wr/addr/wdata/wmask->rdata/ready/busy contract to the real MIG 7-series native app interface (app_addr/app_cmd/app_en, app_wdf_data/app_wdf_mask/app_wdf_wren/app_wdf_end, app_rd_data/ app_rd_data_valid/app_rd_data_end), derived from this project's own real generated mig_7series_0.v port widths, not assumed. Runs in the ui_clk domain (MIG's own generated clock becomes this project's system clock going forward). Verified against MIG's own real, vendor-shipped DDR3 behavioral model (ddr3_model.sv) via real Xilinx xsim/xvlog/xelab (UNISIM primitives in MIG's PHY require this over Verilator): 12/12 write-then-read-back transactions bit-exact, 0 errors, real JEDEC command sequence observed (Activate/Write/Read/Precharge). Confirms the app_cmd encoding and burst/beat sequencing on first real test. Also adds hardware/v3/rtl/sdram_arbiter_n.v (generalized N-way arbiter, generalizing EXP-0066's 2-way version for N>2 scaling and a future host-access requester) -- its own isolated test currently HANGS, root cause not yet found, do not trust this module yet (disclosed, not hidden). Full writeup in hardware/v2/logs/experiments.log EXP-0068. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
Claude Sonnet 5
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`timescale 1ps/100fs
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// ============================================================
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// First real verification of mig_native_adapter.v against the REAL,
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// vendor-provided DDR3 behavioral model (ddr3_model.sv, shipped with
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// this project's own generated mig_7series_0 IP) -- not a stand-in,
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// the actual JEDEC-timed model MIG itself ships for exactly this
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// purpose. Confirms the app_cmd encoding, burst/beat sequencing, and
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// address unit assumed by mig_native_adapter.v's own header comment
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// are correct by real write-then-read-back comparison, not by
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// documentation archaeology alone.
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//
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// Instantiates mig_7series_0_mig (the inner module, NOT the public
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// mig_7series_0.v wrapper) directly, with SIM_BYPASS_INIT_CAL="FAST"
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// overridden -- mig_7series_0.v's own wrapper hardcodes "OFF" (full
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// real calibration, impractically slow for simulation) and does not
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// expose this parameter; mig_7series_0_mig.v does. All other
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// parameters are left at their defaults, which already ARE this
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// project's real generated configuration (DQ_WIDTH=16, MEM_DENSITY=
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// 2Gb, MEM_SPEEDGRADE=125, MEM_ADDR_ORDER=BANK_ROW_COLUMN, etc.) --
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// not generic MIG defaults.
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//
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// Clock/reset generation and DDR3 pin wiring (WireDelay pass-through,
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// zero propagation delay) mirror this project's own vendor-shipped
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// example_design/sim/sim_tb_top.v exactly, per its own real, proven
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// pattern -- not re-derived from scratch.
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// ============================================================
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module tb;
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localparam CLKIN_PERIOD = 3225; // ps, matches this project's real MIG config
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localparam REFCLK_FREQ = 200.0; // MHz
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localparam real REFCLK_PERIOD = (1000000.0/(2*REFCLK_FREQ));
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localparam RESET_PERIOD = 200000; // ps
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localparam ADDR_WIDTH = 25; // this project's own word-address convention (BURST_LEN=8)
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localparam BURST_LEN = 8;
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reg sys_rst_n;
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wire sys_rst = sys_rst_n; // Active Low, matches mig_7series_0_mig's own default polarity
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reg sys_clk_i = 1'b0;
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always #(CLKIN_PERIOD/2.0) sys_clk_i = ~sys_clk_i;
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reg clk_ref_i = 1'b0;
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always #REFCLK_PERIOD clk_ref_i = ~clk_ref_i;
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initial begin
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sys_rst_n = 1'b0;
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#RESET_PERIOD sys_rst_n = 1'b1;
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end
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// ---- real DDR3 pins ----
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wire ddr3_reset_n;
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wire [15:0] ddr3_dq_fpga;
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wire [1:0] ddr3_dqs_p_fpga, ddr3_dqs_n_fpga;
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wire [13:0] ddr3_addr_fpga;
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wire [2:0] ddr3_ba_fpga;
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wire ddr3_ras_n_fpga, ddr3_cas_n_fpga, ddr3_we_n_fpga;
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wire [0:0] ddr3_cke_fpga, ddr3_ck_p_fpga, ddr3_ck_n_fpga, ddr3_cs_n_fpga;
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wire [1:0] ddr3_dm_fpga;
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wire [0:0] ddr3_odt_fpga;
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wire [15:0] ddr3_dq_sdram;
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reg [13:0] ddr3_addr_sdram;
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reg [2:0] ddr3_ba_sdram;
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reg ddr3_ras_n_sdram, ddr3_cas_n_sdram, ddr3_we_n_sdram;
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wire [0:0] ddr3_cs_n_sdram;
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wire [0:0] ddr3_odt_sdram;
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reg [0:0] ddr3_cke_sdram;
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wire [1:0] ddr3_dm_sdram;
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wire [1:0] ddr3_dqs_p_sdram, ddr3_dqs_n_sdram;
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reg [0:0] ddr3_ck_p_sdram, ddr3_ck_n_sdram;
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reg [0:0] ddr3_cs_n_sdram_tmp;
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reg [1:0] ddr3_dm_sdram_tmp;
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reg [0:0] ddr3_odt_sdram_tmp;
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always @(*) begin
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ddr3_ck_p_sdram <= ddr3_ck_p_fpga;
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ddr3_ck_n_sdram <= ddr3_ck_n_fpga;
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ddr3_addr_sdram <= ddr3_addr_fpga;
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ddr3_ba_sdram <= ddr3_ba_fpga;
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ddr3_ras_n_sdram <= ddr3_ras_n_fpga;
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ddr3_cas_n_sdram <= ddr3_cas_n_fpga;
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ddr3_we_n_sdram <= ddr3_we_n_fpga;
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ddr3_cke_sdram <= ddr3_cke_fpga;
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end
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always @(*) ddr3_cs_n_sdram_tmp <= ddr3_cs_n_fpga;
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assign ddr3_cs_n_sdram = ddr3_cs_n_sdram_tmp;
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always @(*) ddr3_dm_sdram_tmp <= ddr3_dm_fpga;
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assign ddr3_dm_sdram = ddr3_dm_sdram_tmp;
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always @(*) ddr3_odt_sdram_tmp <= ddr3_odt_fpga;
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assign ddr3_odt_sdram = ddr3_odt_sdram_tmp;
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genvar dqwd;
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generate
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for (dqwd = 0; dqwd < 16; dqwd = dqwd + 1) begin : dq_delay
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WireDelay #(.Delay_g(0.00), .Delay_rd(0.00), .ERR_INSERT("OFF")) u_delay_dq (
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.A(ddr3_dq_fpga[dqwd]), .B(ddr3_dq_sdram[dqwd]),
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.reset(sys_rst_n), .phy_init_done(init_calib_complete)
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);
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end
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endgenerate
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genvar dqswd;
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generate
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for (dqswd = 0; dqswd < 2; dqswd = dqswd + 1) begin : dqs_delay
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WireDelay #(.Delay_g(0.00), .Delay_rd(0.00), .ERR_INSERT("OFF")) u_delay_dqs_p (
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.A(ddr3_dqs_p_fpga[dqswd]), .B(ddr3_dqs_p_sdram[dqswd]),
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.reset(sys_rst_n), .phy_init_done(init_calib_complete)
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);
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WireDelay #(.Delay_g(0.00), .Delay_rd(0.00), .ERR_INSERT("OFF")) u_delay_dqs_n (
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.A(ddr3_dqs_n_fpga[dqswd]), .B(ddr3_dqs_n_sdram[dqswd]),
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.reset(sys_rst_n), .phy_init_done(init_calib_complete)
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);
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end
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endgenerate
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// ---- real DDR3 behavioral model (single component, DQ_WIDTH=16
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// matches MEMORY_WIDTH=16 exactly, no splitting needed) ----
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ddr3_model u_ddr3 (
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.rst_n(ddr3_reset_n), .ck(ddr3_ck_p_sdram), .ck_n(ddr3_ck_n_sdram),
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.cke(ddr3_cke_sdram[0]), .cs_n(ddr3_cs_n_sdram[0]),
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.ras_n(ddr3_ras_n_sdram), .cas_n(ddr3_cas_n_sdram), .we_n(ddr3_we_n_sdram),
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.dm_tdqs(ddr3_dm_sdram), .ba(ddr3_ba_sdram), .addr(ddr3_addr_sdram),
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.dq(ddr3_dq_sdram), .dqs(ddr3_dqs_p_sdram), .dqs_n(ddr3_dqs_n_sdram),
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.tdqs_n(), .odt(ddr3_odt_sdram[0])
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);
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// ---- real MIG controller (inner module, SIM_BYPASS_INIT_CAL
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// overridden for a real but fast simulation calibration) ----
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wire [27:0] app_addr;
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wire [2:0] app_cmd;
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wire app_en, app_rdy;
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wire [63:0] app_wdf_data;
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wire app_wdf_end;
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wire [7:0] app_wdf_mask;
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wire app_wdf_wren, app_wdf_rdy;
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wire [63:0] app_rd_data;
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wire app_rd_data_end, app_rd_data_valid;
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wire ui_clk, ui_clk_sync_rst, init_calib_complete;
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mig_7series_0_mig #(
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.SIM_BYPASS_INIT_CAL("FAST")
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) u_mig (
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.ddr3_dq(ddr3_dq_fpga), .ddr3_dqs_n(ddr3_dqs_n_fpga), .ddr3_dqs_p(ddr3_dqs_p_fpga),
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.ddr3_addr(ddr3_addr_fpga), .ddr3_ba(ddr3_ba_fpga),
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.ddr3_ras_n(ddr3_ras_n_fpga), .ddr3_cas_n(ddr3_cas_n_fpga), .ddr3_we_n(ddr3_we_n_fpga),
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.ddr3_reset_n(ddr3_reset_n),
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.ddr3_ck_p(ddr3_ck_p_fpga), .ddr3_ck_n(ddr3_ck_n_fpga),
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.ddr3_cke(ddr3_cke_fpga), .ddr3_cs_n(ddr3_cs_n_fpga),
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.ddr3_dm(ddr3_dm_fpga), .ddr3_odt(ddr3_odt_fpga),
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.sys_clk_i(sys_clk_i), .clk_ref_i(clk_ref_i),
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.app_addr(app_addr), .app_cmd(app_cmd), .app_en(app_en),
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.app_wdf_data(app_wdf_data), .app_wdf_end(app_wdf_end),
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.app_wdf_mask(app_wdf_mask), .app_wdf_wren(app_wdf_wren),
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.app_rd_data(app_rd_data), .app_rd_data_end(app_rd_data_end),
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.app_rd_data_valid(app_rd_data_valid), .app_rdy(app_rdy), .app_wdf_rdy(app_wdf_rdy),
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.app_sr_req(1'b0), .app_ref_req(1'b0), .app_zq_req(1'b0),
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.app_sr_active(), .app_ref_ack(), .app_zq_ack(),
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.ui_clk(ui_clk), .ui_clk_sync_rst(ui_clk_sync_rst),
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.init_calib_complete(init_calib_complete),
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.device_temp(),
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.sys_rst(sys_rst)
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);
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// ---- adapter under test ----
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reg req, wr;
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reg [ADDR_WIDTH-1:0] addr;
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reg [16*BURST_LEN-1:0] wdata;
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reg [2*BURST_LEN-1:0] wmask;
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wire [16*BURST_LEN-1:0] rdata;
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wire ready, busy;
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mig_native_adapter #(.BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH)) u_adapter (
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.clk(ui_clk), .rst(ui_clk_sync_rst),
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.req(req), .wr(wr), .addr(addr), .wdata(wdata), .wmask(wmask),
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.rdata(rdata), .ready(ready), .busy(busy),
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.app_addr(app_addr), .app_cmd(app_cmd), .app_en(app_en), .app_rdy(app_rdy),
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.app_wdf_data(app_wdf_data), .app_wdf_end(app_wdf_end), .app_wdf_mask(app_wdf_mask),
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.app_wdf_wren(app_wdf_wren), .app_wdf_rdy(app_wdf_rdy),
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.app_rd_data(app_rd_data), .app_rd_data_end(app_rd_data_end), .app_rd_data_valid(app_rd_data_valid)
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);
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task automatic do_txn(
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input t_wr,
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input [ADDR_WIDTH-1:0] t_addr,
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input [16*BURST_LEN-1:0] t_wdata,
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output [16*BURST_LEN-1:0] t_rdata
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);
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begin
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@(posedge ui_clk);
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while (busy) @(posedge ui_clk);
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req = 1'b1; wr = t_wr; addr = t_addr; wdata = t_wdata; wmask = {(2*BURST_LEN){1'b0}};
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@(posedge ui_clk);
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req = 1'b0;
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while (!ready) @(posedge ui_clk);
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t_rdata = rdata;
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end
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endtask
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integer errors, tests;
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reg [16*BURST_LEN-1:0] got, wpat;
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integer k, i;
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task automatic check_addr(input [ADDR_WIDTH-1:0] a, input [15:0] pattern);
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begin
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for (k = 0; k < BURST_LEN; k = k + 1)
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wpat[k*16 +: 16] = pattern + k[15:0];
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do_txn(1'b1, a, wpat, got);
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do_txn(1'b0, a, {(16*BURST_LEN){1'b0}}, got);
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tests = tests + 1;
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if (got !== wpat) begin
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$display("FAIL addr=%0d: got=%h expected=%h", a, got, wpat);
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errors = errors + 1;
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end else begin
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$display("PASS addr=%0d: bit-exact %h", a, got);
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end
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end
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endtask
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initial begin
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errors = 0; tests = 0;
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req = 0; wr = 0; addr = 0; wdata = 0; wmask = 0;
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$display("=== waiting for real DDR3 init_calib_complete (FAST sim calibration) ===");
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wait (init_calib_complete);
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$display("=== calibration done at time %0t, starting real write/read-back test ===", $time);
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repeat (10) @(posedge ui_clk);
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check_addr(25'd0, 16'hA5A5);
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check_addr(25'd8, 16'h1000);
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check_addr(25'd16, 16'h2000);
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check_addr(25'd1024,16'h3000);
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for (i = 0; i < 8; i = i + 1)
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check_addr((25'd2048 + i*8), 16'h4000 + i);
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$display("=== %0d/%0d tests, %0d errors ===", tests-errors, tests, errors);
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if (errors == 0) $display("ALL TESTS PASSED (tb_mig_native_adapter, real ddr3_model.sv)");
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else $display("SOME TESTS FAILED");
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$finish;
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end
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initial begin
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#200000000.0; // 200us watchdog
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if (!init_calib_complete) $display("FAIL: calibration never completed within watchdog");
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else $display("(watchdog fired after calibration already completed -- not a failure by itself)");
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$finish;
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end
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endmodule
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@@ -0,0 +1,180 @@
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`timescale 1ns/1ps
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// ============================================================
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// Isolated correctness test for sdram_arbiter_n.v (NUM_REQ=3, the
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// immediate real use case: 2 packed slots + 1 host raw-access
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// requester). Each requester stub mirrors layer_prefetch_ctrl.v's
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// own real, risky pattern that caused EXP-0066's real bug: a ONE-SHOT
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// ctrl_req pulse issued the instant its own `active` first goes high,
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// no retry -- this test exists specifically to re-confirm the
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// combinational-first-grant fix generalizes correctly to N=3, not
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// just N=2.
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// ============================================================
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module tb;
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localparam BURST_LEN = 8;
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localparam ROW_BITS = 13;
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localparam COL_BITS = 10;
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localparam BANK_BITS = 2;
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localparam ADDR_WIDTH = BANK_BITS + ROW_BITS + COL_BITS;
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localparam CLK_FREQ_MHZ = 64;
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localparam CLK_PERIOD_NS = 1000.0/CLK_FREQ_MHZ;
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localparam NUM_REQ = 3;
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reg clk = 0;
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always #(CLK_PERIOD_NS/2.0) clk = ~clk;
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reg rst;
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wire ctrl_req, ctrl_wr;
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wire [ADDR_WIDTH-1:0] ctrl_addr;
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wire [16*BURST_LEN-1:0] ctrl_wdata, ctrl_rdata;
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wire [2*BURST_LEN-1:0] ctrl_wmask;
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wire ctrl_ready, ctrl_busy;
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wire cke, cs_n, ras_n, cas_n, we_n;
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wire [BANK_BITS-1:0] ba;
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wire [ROW_BITS-1:0] a;
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wire [15:0] dq;
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wire [1:0] dqm;
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sdram_controller #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .BURST_LEN(BURST_LEN),
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.ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) u_ctrl (
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.clk(clk), .rst(rst),
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.req(ctrl_req), .wr(ctrl_wr), .addr(ctrl_addr), .wdata(ctrl_wdata), .wmask(ctrl_wmask),
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.rdata(ctrl_rdata), .ready(ctrl_ready), .busy(ctrl_busy),
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.sdram_cke(cke), .sdram_cs_n(cs_n), .sdram_ras_n(ras_n), .sdram_cas_n(cas_n), .sdram_we_n(we_n),
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.sdram_ba(ba), .sdram_a(a), .sdram_dq(dq), .sdram_dqm(dqm)
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);
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sdram_model #(
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.CLK_FREQ_MHZ(CLK_FREQ_MHZ), .ROW_BITS(ROW_BITS), .COL_BITS(COL_BITS), .BANK_BITS(BANK_BITS)
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) u_mem (
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.clk(clk), .cke(cke), .cs_n(cs_n), .ras_n(ras_n), .cas_n(cas_n), .we_n(we_n),
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.ba(ba), .a(a), .dq(dq), .dqm(dqm)
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);
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reg [NUM_REQ-1:0] req_active, req_req, req_wr;
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wire [NUM_REQ-1:0] req_grant, req_ready, req_busy;
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reg [NUM_REQ*ADDR_WIDTH-1:0] req_addr;
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reg [NUM_REQ*16*BURST_LEN-1:0] req_wdata;
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reg [NUM_REQ*2*BURST_LEN-1:0] req_wmask;
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wire [NUM_REQ*16*BURST_LEN-1:0] req_rdata;
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sdram_arbiter_n #(
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.NUM_REQ(NUM_REQ), .ADDR_WIDTH(ADDR_WIDTH), .BURST_LEN(BURST_LEN)
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) u_arb (
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.clk(clk), .rst(rst),
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.req_active(req_active), .req_grant(req_grant),
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.req_req(req_req), .req_wr(req_wr), .req_addr(req_addr),
|
||||
.req_wdata(req_wdata), .req_wmask(req_wmask),
|
||||
.req_rdata(req_rdata), .req_ready(req_ready), .req_busy(req_busy),
|
||||
.ctrl_req(ctrl_req), .ctrl_wr(ctrl_wr), .ctrl_addr(ctrl_addr),
|
||||
.ctrl_wdata(ctrl_wdata), .ctrl_wmask(ctrl_wmask),
|
||||
.ctrl_rdata(ctrl_rdata), .ctrl_ready(ctrl_ready), .ctrl_busy(ctrl_busy)
|
||||
);
|
||||
|
||||
integer errors, tests;
|
||||
|
||||
// one-shot-pulse requester task: mirrors layer_prefetch_ctrl.v's
|
||||
// own real risk pattern -- raise active, issue req THE SAME cycle
|
||||
// active first asserts (no waiting for grant confirmation first),
|
||||
// no retry if lost.
|
||||
task automatic one_shot_txn(
|
||||
input integer slot, input t_wr, input [ADDR_WIDTH-1:0] t_addr,
|
||||
input [16*BURST_LEN-1:0] t_wdata, output [16*BURST_LEN-1:0] t_rdata
|
||||
);
|
||||
begin
|
||||
@(posedge clk);
|
||||
req_active[slot] = 1'b1;
|
||||
req_req[slot] = 1'b1;
|
||||
req_wr[slot] = t_wr;
|
||||
req_addr[slot*ADDR_WIDTH +: ADDR_WIDTH] = t_addr;
|
||||
req_wdata[slot*16*BURST_LEN +: 16*BURST_LEN] = t_wdata;
|
||||
req_wmask[slot*2*BURST_LEN +: 2*BURST_LEN] = {(2*BURST_LEN){1'b0}};
|
||||
@(posedge clk);
|
||||
req_req[slot] = 1'b0;
|
||||
while (!req_ready[slot]) @(posedge clk);
|
||||
t_rdata = req_rdata[slot*16*BURST_LEN +: 16*BURST_LEN];
|
||||
req_active[slot] = 1'b0;
|
||||
end
|
||||
endtask
|
||||
|
||||
reg [16*BURST_LEN-1:0] got, wpat;
|
||||
integer k;
|
||||
|
||||
task automatic check_slot(input integer slot, input [ADDR_WIDTH-1:0] a, input [15:0] pattern);
|
||||
integer i;
|
||||
begin
|
||||
for (i = 0; i < BURST_LEN; i = i + 1)
|
||||
wpat[i*16 +: 16] = pattern + i[15:0];
|
||||
one_shot_txn(slot, 1'b1, a, wpat, got);
|
||||
one_shot_txn(slot, 1'b0, a, {(16*BURST_LEN){1'b0}}, got);
|
||||
tests = tests + 1;
|
||||
if (got !== wpat) begin
|
||||
$display("FAIL slot=%0d addr=%0d: got=%h expected=%h", slot, a, got, wpat);
|
||||
errors = errors + 1;
|
||||
end else begin
|
||||
$display("PASS slot=%0d addr=%0d: bit-exact", slot, a);
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
integer i;
|
||||
initial begin
|
||||
errors = 0; tests = 0;
|
||||
rst = 1; req_active = 0; req_req = 0; req_wr = 0; req_addr = 0; req_wdata = 0; req_wmask = 0;
|
||||
repeat(5) @(posedge clk);
|
||||
rst = 0;
|
||||
@(posedge clk);
|
||||
|
||||
$display("=== TEST 1: sequential single-requester transactions, all 3 slots ===");
|
||||
check_slot(0, 25'd0, 16'hA000);
|
||||
check_slot(1, 25'd8, 16'hB000);
|
||||
check_slot(2, 25'd16, 16'hC000);
|
||||
|
||||
$display("=== TEST 2: simultaneous multi-requester activation (the real EXP-0066 risk case) ===");
|
||||
begin : test2
|
||||
reg [16*BURST_LEN-1:0] g0, g1, g2, w0, w1, w2;
|
||||
integer kk;
|
||||
for (kk = 0; kk < BURST_LEN; kk = kk + 1) begin
|
||||
w0[kk*16 +: 16] = 16'hD000 + kk[15:0];
|
||||
w1[kk*16 +: 16] = 16'hE000 + kk[15:0];
|
||||
w2[kk*16 +: 16] = 16'hF000 + kk[15:0];
|
||||
end
|
||||
// all three assert `active`+`req` on the SAME cycle --
|
||||
// exactly the scenario a registered/late grant loses.
|
||||
@(posedge clk);
|
||||
req_active = 3'b111; req_req = 3'b111;
|
||||
req_wr[0] = 1'b1; req_wr[1] = 1'b1; req_wr[2] = 1'b1;
|
||||
req_addr[0*ADDR_WIDTH +: ADDR_WIDTH] = 25'd100;
|
||||
req_addr[1*ADDR_WIDTH +: ADDR_WIDTH] = 25'd108;
|
||||
req_addr[2*ADDR_WIDTH +: ADDR_WIDTH] = 25'd116;
|
||||
req_wdata[0*16*BURST_LEN +: 16*BURST_LEN] = w0;
|
||||
req_wdata[1*16*BURST_LEN +: 16*BURST_LEN] = w1;
|
||||
req_wdata[2*16*BURST_LEN +: 16*BURST_LEN] = w2;
|
||||
@(posedge clk);
|
||||
req_req = 3'b000;
|
||||
|
||||
// slot 0 (lowest index) must win first; 1 and 2 must NOT
|
||||
// silently lose their request -- wait for each in turn.
|
||||
while (!req_ready[0]) @(posedge clk);
|
||||
req_active[0] = 1'b0;
|
||||
while (!req_ready[1]) @(posedge clk);
|
||||
req_active[1] = 1'b0;
|
||||
while (!req_ready[2]) @(posedge clk);
|
||||
req_active[2] = 1'b0;
|
||||
|
||||
tests = tests + 1;
|
||||
$display("PASS TEST2: all 3 simultaneous requests completed (none silently lost)");
|
||||
|
||||
// now read back all three and confirm bit-exact, real
|
||||
// proof none of the writes were corrupted/misrouted.
|
||||
check_slot(0, 25'd100, 16'hD000);
|
||||
check_slot(1, 25'd108, 16'hE000);
|
||||
check_slot(2, 25'd116, 16'hF000);
|
||||
end
|
||||
|
||||
$display("=== %0d/%0d tests, %0d errors ===", tests-errors, tests, errors);
|
||||
if (errors == 0) $display("ALL TESTS PASSED (tb_sdram_arbiter_n)");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
Reference in New Issue
Block a user