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docs: update LaTeX docs for N16 real timing closure + honest ESP32-S3 projection (EXP-0097)

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architecture.tex: document the real MAC-pipeline fix (Stage 1a/1b
split) and its real result on both N8 (WNS 0.000ns -> +0.108ns) and
N16 (now closed, WNS=+0.269ns) -- N16 is a real, verified candidate
for a future board revision, N8 remains the configuration in current
physical fabrication.

tests_timing.tex: extended P&R history table, real N8/N16 signoff
tables (post-fix), the new N16 critical path (Director queue logic,
still route-dominated) and the negative result of a second directive
attempt (confirms current result is the best found). Added a new,
clearly-labeled PROJECTION (not a measurement) for N16 vs ESP32-S3 --
30-68x range, built from real measured scaling factors (same core
count as the original ECP5 comparison, real clock ratio, real 2x INT8
packing factor) -- more grounded than the old, superseded ~55-85x
figure, with the same DDR3-bandwidth-bound honest caveat carried
forward.

datasheet.tex: N8/N16 side-by-side timing/utilization/performance
tables, open items and revision history updated to reflect physical
fabrication status and the N16 candidate decision.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
michele
2026-09-22 00:59:46 +02:00
co-authored by Claude Sonnet 5
parent 2ab2ff7769
commit cc6cfe168e
3 changed files with 263 additions and 109 deletions
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docs/latex/datasheet.tex
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@@ -106,12 +106,17 @@ shared-weight-broadcast systolic architecture), reducing redundant
DDR3 weight traffic without the complexity of a literal PE-to-PE
systolic pipeline.
N8 is the current, definitive, real deployment configuration of the
FPGA-Neural family: it is the largest core count in the family that
closes real static timing on the target part with a real, verified
margin. Smaller (N=2, N=4) and larger (N=16) configurations of the
same RTL exist and are documented (see \S\ref{sec:variants}), but N8
is the one recommended for real board fabrication.
N8 is the configuration currently in real physical board fabrication.
A real MAC-datapath pipeline fix (developed on the
\texttt{n16-timing-closure} branch, isolated from the board already in
production) has since ALSO closed real static timing for \textbf{N16}
with a comfortable real margin (WNS=+0.269\,ns) and improved N8's own
margin further (WNS=+0.108\,ns, up from the original exact-zero
0.000\,ns) -- both configurations are now real, functionally verified,
timing-closed options (see \S\ref{sec:variants}). N8 remains the
configuration in current physical production; N16 is a real, verified
candidate for a future board revision, pending the user's own hardware
decision.
\clearpage
@@ -132,14 +137,14 @@ for reference.
\toprule
\textbf{Variant} & \textbf{PEs} & \textbf{DSP48E1} & \textbf{Real WNS} & \textbf{Status} & \textbf{Top-level file} \\
\midrule
N2 & 2 & 16 & +0.100\,ns & \textbf{Closed, deployable fallback} & \texttt{n2\_system\_ddr3\_top.v} \\
N4 & 4 & 32 & $-0.005$\,ns & Nearly closed (2 failing endpoints) & \emph{(generic override only)} \\
N2 & 2 & 16 & +0.100\,ns & Closed, deployable fallback & \texttt{n2\_system\_ddr3\_top.v} \\
N4 & 4 & 32 & $-0.005$\,ns & Nearly closed (2 failing endpoints), pre-fix & \emph{(generic override only)} \\
\rowcolor{dslight}
N8 & 8 & 64 & \textbf{0.000\,ns} & \textbf{RECOMMENDED --- closed} & \texttt{n8\_system\_ddr3\_top.v} \\
N16 & 16 & 128 & $-0.338$\,ns & Functional, timing not closed & \texttt{n16\_system\_ddr3\_top.v} \\
N8 & 8 & 64 & \textbf{+0.108\,ns} & \textbf{IN PHYSICAL PRODUCTION --- closed} & \texttt{n8\_system\_ddr3\_top.v} \\
N16 & 16 & 128 & \textbf{+0.269\,ns} & \textbf{Closed, real candidate for next revision} & \texttt{n16\_system\_ddr3\_top.v} \\
\bottomrule
\end{tabular}
\caption{Real family configurations. All share identical DDR3/SPI/flash physical connections and identical host protocol.}
\caption{Real family configurations, post MAC-pipeline fix (\texttt{n16-timing-closure} branch) for N8/N16. All share identical DDR3/SPI/flash physical connections and identical host protocol.}
\end{table}
%======================================================================
@@ -322,46 +327,51 @@ CFGBVS & P8 & & & \\
\clearpage
\section{Timing Characteristics}
Real, in-context Vivado place-and-route on XC7A100T-CSG324-2, N8
configuration (\texttt{n8\_system\_ddr3\_top.v}), directive stack
Real, in-context Vivado place-and-route on XC7A100T-CSG324-2, both
with the real MAC-pipeline fix (\texttt{n16-timing-closure} branch),
directive stack
\texttt{Explore}/\texttt{ExtraNetDelay\_high}/\texttt{AggressiveExplore}:
\begin{table}[h]
\centering
\renewcommand{\arraystretch}{1.2}
\begin{tabular}{lll}
\begin{tabular}{llll}
\toprule
\textbf{Parameter} & \textbf{Value} & \textbf{Condition} \\
\textbf{Parameter} & \textbf{N8 (in production)} & \textbf{N16 (verified)} & \textbf{Condition} \\
\midrule
Setup slack (WNS) & \textbf{0.000\,ns} & \texttt{clk\_pll\_i}, 155.039\,MHz, 0 of 63212 failing \\
Hold slack (WHS) & +0.017\,ns & 0 of 63209 failing \\
Compute-domain clock period & 6.450\,ns & 155.039\,MHz \\
DDR3 CAS latency (real, measured) & CL=5 (16.125\,ns) & matches MIG configuration \\
Same-row read-to-read & 12.9\,ns & real JEDEC trace \\
Row-switch (Activate$\to$Read) penalty & +25--130\% & vs.\ same-row access, real measured \\
Setup slack (WNS) & +0.108\,ns & +0.269\,ns & \texttt{clk\_pll\_i}, 155.039\,MHz, 0 failing \\
Hold slack (WHS) & +0.036\,ns & +0.026\,ns & 0 failing \\
Compute-domain clock period & 6.450\,ns & 6.450\,ns & 155.039\,MHz \\
DDR3 CAS latency (real, measured) & \multicolumn{2}{c}{CL=5 (16.125\,ns)} & matches MIG configuration \\
Same-row read-to-read & \multicolumn{2}{c}{12.9\,ns} & real JEDEC trace \\
Row-switch penalty & \multicolumn{2}{c}{+25--130\%} & vs.\ same-row access, real measured \\
\bottomrule
\end{tabular}
\end{table}
\noindent\textbf{Margin notice:} the real WNS is exactly zero --- closed,
but with no spare slack. Any RTL modification to this configuration
requires a fresh real place-and-route run (same directive stack) before
the design may be considered timing-clean again.
\noindent\textbf{Margin notice:} both real margins are positive and
closed. N8's own pre-fix signoff (\texttt{n8\_system\_ddr3\_top.v}
without the MAC-pipeline fix, the version currently in physical
fabrication) closed at an exact-zero WNS=0.000\,ns, no spare slack ---
the improved +0.108\,ns figure above applies once the pipeline fix
(\S\ref{sec:variants}) is adopted. Any RTL modification requires a
fresh real place-and-route run (same directive stack) before the
design may be considered timing-clean again.
%======================================================================
\section{Resource Utilization (XC7A100T-CSG324-2, N8)}
\section{Resource Utilization (XC7A100T-CSG324-2)}
\begin{table}[h]
\centering
\renewcommand{\arraystretch}{1.2}
\begin{tabular}{lrrr}
\begin{tabular}{lrrrr}
\toprule
\textbf{Resource} & \textbf{Used} & \textbf{Available} & \textbf{Utilization} \\
\textbf{Resource} & \textbf{N8 Used} & \textbf{N16 Used} & \textbf{Available} & \textbf{N8 / N16 Util.} \\
\midrule
Slice LUTs & 12535 & 63400 & 19.77\% \\
Slice Registers & 19902 & 126800 & 15.70\% \\
DSP48E1 & 64 & 240 & 26.7\% \\
Block RAM & 0 & 135 & 0\% \\
Slice LUTs & 12536 & 19903 & 63400 & 19.77\% / 31.39\% \\
Slice Registers & 19910 & 35409 & 126800 & 15.70\% / 27.93\% \\
DSP48E1 & 64 & 128 & 240 & 26.7\% / 53.33\% \\
Block RAM & 0 & 0 & 135 & 0\% / 0\% \\
\bottomrule
\end{tabular}
\end{table}
@@ -371,28 +381,29 @@ Block RAM & 0 & 135 & 0\% \\
\begin{table}[h]
\centering
\begin{tabular}{ll}
\begin{tabular}{lll}
\toprule
\textbf{Parameter} & \textbf{Value} \\
\textbf{Parameter} & \textbf{N8} & \textbf{N16} \\
\midrule
MAC operations per DSP48E1 per cycle & 2 (packed INT8, lane A + lane B) \\
DSP48E1 per processing element & 8 \\
MAC/cycle per PE & 16 \\
Real parallel PEs & 8 \\
Aggregate MAC/cycle & 128 \\
\textbf{Aggregate peak throughput} (calculated, 155.039\,MHz) & \textbf{$\sim$19.84\,GMAC/s} \\
Real DDR3 physical bandwidth ceiling & $\sim$2.48\,GB/s (shared across all 8 PEs) \\
MAC operations per DSP48E1 per cycle & \multicolumn{2}{c}{2 (packed INT8, lane A + lane B)} \\
DSP48E1 per processing element & \multicolumn{2}{c}{8} \\
MAC/cycle per PE & \multicolumn{2}{c}{16} \\
Real parallel PEs & 8 & 16 \\
Aggregate MAC/cycle & 128 & 256 \\
\textbf{Aggregate peak throughput} (calc., 155.039\,MHz) & \textbf{$\sim$19.84\,GMAC/s} & \textbf{$\sim$39.69\,GMAC/s} \\
Real DDR3 bandwidth ceiling (shared) & \multicolumn{2}{c}{$\sim$2.48\,GB/s} \\
\bottomrule
\end{tabular}
\end{table}
\noindent The peak MAC figure is a real calculation from measured
\noindent The peak MAC figures are a real calculation from measured
building blocks (DSP count $\times$ packing factor $\times$ measured
Fmax) --- not itself an independently benchmarked sustained-throughput
number. Sustained throughput on a real workload is bounded by the real
DDR3 bandwidth ceiling above, shared across all active PEs; a direct
measurement of sustained aggregate throughput at N8 has not yet been
performed (see \S\ref{sec:openitems}).
Fmax) --- not themselves independently benchmarked sustained-throughput
numbers. Sustained throughput on a real workload is bounded by the real
DDR3 bandwidth ceiling above, shared across all active PEs (more
tightly at N16, twice the PEs on the same physical channel); a direct
measurement of sustained aggregate throughput has not yet been
performed at either N (see \S\ref{sec:openitems}).
%======================================================================
\section{Host Communication Protocol}
@@ -470,8 +481,8 @@ Host MCU & ESP32-S3-WROOM-1-N16R8 & In stock, LCSC C2913202 \\
\label{sec:openitems}
\begin{itemize}
\item Physical board has not yet been fabricated; no real
electrical/thermal measurement exists yet.
\item Physical board fabrication is underway (N8 configuration,
unmodified); no real electrical/thermal measurement exists yet.
\item \texttt{sys\_clk} oscillator requires a custom-programmed order
(no off-the-shelf SKU at 310.077\,MHz).
\item Power-tree regulators (VCCINT, VCCAUX, VTT, per-bank VCCO) not
@@ -481,10 +492,14 @@ Host MCU & ESP32-S3-WROOM-1-N16R8 & In stock, LCSC C2913202 \\
\item ESP32-side firmware (JTAG bit-banging, SPI host driver,
result-readback address translation) not yet written --- software
work outside this document's scope.
\item Real, direct sustained-throughput benchmark at N8 (vs.\ a
real ESP32-S3 baseline) not yet performed --- see the project's
Tests \& Timing chapter for the honest historical comparison
context.
\item Real, direct sustained-throughput benchmark (vs.\ a real
ESP32-S3 baseline) not yet performed at either N8 or N16 --- see
the project's Tests \& Timing chapter for the honest historical
comparison context and a real, clearly-labeled projection for N16.
\item Whether to adopt N16 (real, functionally verified, timing-
closed on the \texttt{n16-timing-closure} branch) for a future
board revision is a real, open hardware decision, not an RTL
blocker.
\end{itemize}
%======================================================================
@@ -497,6 +512,11 @@ Host MCU & ESP32-S3-WROOM-1-N16R8 & In stock, LCSC C2913202 \\
\textbf{Rev.} & \textbf{Date} & \textbf{Description} \\
\midrule
1.0 & 2026-09-21 & Initial preliminary datasheet, N8 configuration \\
1.1 & 2026-09-22 & N8 re-verified with a real MAC-pipeline fix
(WNS improved 0.000\,ns $\to$ +0.108\,ns); N16 now also real,
functionally verified, and timing-closed (WNS=+0.269\,ns) on a
separate development branch, documented as a real candidate for a
future board revision \\
\bottomrule
\end{tabular}
\end{table}