exp: dual-bank SDRAM sim shows W/AR split gives only ~9% cycle gain, not thrashing removal (EXP-0051)
Forked nms_neural_multiprocessor_sdram_unified.v + its D-Stress testbench into a dual-bank variant (two independent sdram_unified_backend.v instances, one for weight-fetch, one for activation+result) to test the Fase-3 memory-bound hypothesis ahead of Phase 2. Simulation-only: the real board (v2_board_top.lpf) still wires exactly one physical chip, per STEP19's governing single-SDRAM mandate. Result is honest but not the hoped-for one: splitting by traffic class only cuts D-Stress cycles ~8-10% (N=4: 49927->45724, N=8: 49909->44980), because the AR (activation+result) path was already lightly loaded (~12% busy) even alone. The real ceiling is the weight-fetch channel itself, which stays ~77-78% busy even with its own dedicated bank and zero cross-traffic. Full writeup in experiments.log EXP-0051, including the refined next-step options this suggests instead of a straight 2-bank board revision. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01YHENedK76onD2Vtc2CMjej
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Claude Sonnet 5
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`timescale 1ns/1ps
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// ================================================================
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// Neural Memory System (NMS) -- EXPERIMENTAL two-physical-SDRAM-bank
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// variant, forked from nms_neural_multiprocessor_sdram_unified.v
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// (STEP19) to test one specific hypothesis before committing to
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// Phase 2/3 of the N=8-timing/85F-retarget/SDRAM-bank-sweep brief:
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// is this system's real bottleneck external-memory BANDWIDTH (one
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// shared physical SDRAM chip serialising ALL weight+activation+
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// result traffic through one sdram_controller.v instance), or
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// something else? See hardware/v2/logs/decisions.log (search
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// "memory-bound") and errors.log ERR-0030/ERR-0031 for the
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// measurement (tb_nms_dstress_sdram_unified.v: SDRAM controller port
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// busy ~81.6% of all cycles at BOTH N_SLOTS=4 and N_SLOTS=8) this
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// variant exists to stress-test.
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//
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// NOT a proposal to change the real V2 board (hardware/v2/constraints/
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// v2_board_top.lpf wires exactly ONE physical AS4C4M16SA-6TIN chip --
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// unchanged, untouched). This module is SIMULATION-side exploration
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// only: it duplicates sdram_unified_backend.v (byte-for-byte reused,
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// zero modification) into TWO independent instances --
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// u_sdram_backend_w : services ONLY the W (weight-fetch) port,
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// ar_req permanently tied low
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// u_sdram_backend_ar : services ONLY the AR (activation-fill +
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// result-writeback) port, w_req permanently
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// tied low
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// -- each with its OWN sdram_controller.v instance and its OWN set of
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// physical SDRAM pins, i.e. what a real two-physical-chip board
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// revision would look like. Tying ar_req/w_req permanently to 0 on
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// the respective instance is safe by inspection of sdram_unified_
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// backend.v's own state machine: with ar_req/ar_req_pending always 0,
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// S_AR_RD_WAIT/S_AR_WR_WAIT are simply never entered (and symmetrically
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// for w_req/S_W_WAIT) -- no dead-state risk, no latch ever set from a
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// permanently-0 input.
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//
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// u_dataflow_core, u_arbiter (AR, N_SLOTS+1 ports), and u_arbiter_wide
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// (W, N_SLOTS ports) are ALL byte-for-byte unchanged from the single-
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// bank wrapper -- only the final memory-side fanout changes.
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// ================================================================
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module nms_neural_multiprocessor_sdram_dualbank #(
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parameter DATA_WIDTH = 8,
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parameter P_IN = 8,
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parameter ACC_WIDTH = 32,
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parameter ADDR_WIDTH = 26,
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parameter N_SLOTS = 2,
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parameter N_NODES = 16,
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parameter MAX_DEPS = 4,
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parameter QUEUE_DEPTH = 8,
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parameter MAX_TILES = 16,
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parameter PREFETCH_DISTANCE = 8,
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parameter CLK_FREQ_MHZ = 80
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)(
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input wire clk,
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input wire rst,
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input wire reg_valid,
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output wire reg_ready,
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input wire [$clog2(N_NODES)-1:0] reg_node_id,
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input wire [$clog2(MAX_DEPS+1)-1:0] reg_required,
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input wire [MAX_DEPS*$clog2(N_NODES)-1:0] reg_producer_ids,
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input wire [ADDR_WIDTH-1:0] reg_x_base,
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input wire [ADDR_WIDTH-1:0] reg_w_base,
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input wire [15:0] reg_n_tiles,
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input wire [ADDR_WIDTH-1:0] reg_result_addr,
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output wire data_ready,
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// ---- Bank W: weight-fetch-only physical SDRAM chip ----
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output wire sdram_w_cke,
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output wire sdram_w_cs_n,
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output wire sdram_w_ras_n,
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output wire sdram_w_cas_n,
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output wire sdram_w_we_n,
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output wire [1:0] sdram_w_ba,
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output wire [12:0] sdram_w_a,
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inout wire [15:0] sdram_w_dq,
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output wire [1:0] sdram_w_dqm,
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// ---- Bank AR: activation-fill + result-writeback-only physical
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// SDRAM chip ----
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output wire sdram_ar_cke,
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output wire sdram_ar_cs_n,
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output wire sdram_ar_ras_n,
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output wire sdram_ar_cas_n,
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output wire sdram_ar_we_n,
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output wire [1:0] sdram_ar_ba,
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output wire [12:0] sdram_ar_a,
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inout wire [15:0] sdram_ar_dq,
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output wire [1:0] sdram_ar_dqm
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);
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wire [N_SLOTS:0] slot_mem_req, slot_mem_wr;
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wire [ADDR_WIDTH*(N_SLOTS+1)-1:0] slot_mem_addr;
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wire [16*(N_SLOTS+1)-1:0] slot_mem_wdata, slot_mem_rdata;
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wire [N_SLOTS:0] slot_mem_lb_n, slot_mem_ub_n;
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wire [N_SLOTS:0] slot_mem_ready;
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wire [N_SLOTS-1:0] wide_slot_mem_req;
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wire [ADDR_WIDTH*N_SLOTS-1:0] wide_slot_mem_addr;
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wire [64*N_SLOTS-1:0] wide_slot_mem_rdata;
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wire [N_SLOTS-1:0] wide_slot_mem_ready;
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nms_dataflow_core_sdram #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH), .ADDR_WIDTH(ADDR_WIDTH),
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.N_SLOTS(N_SLOTS), .N_NODES(N_NODES), .MAX_DEPS(MAX_DEPS), .QUEUE_DEPTH(QUEUE_DEPTH),
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.MAX_TILES(MAX_TILES), .PREFETCH_DISTANCE(PREFETCH_DISTANCE)
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) u_dataflow_core (
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.clk(clk), .rst(rst),
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.reg_valid(reg_valid), .reg_ready(reg_ready), .reg_node_id(reg_node_id),
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.reg_required(reg_required), .reg_producer_ids(reg_producer_ids),
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.reg_x_base(reg_x_base), .reg_w_base(reg_w_base), .reg_n_tiles(reg_n_tiles),
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.reg_result_addr(reg_result_addr),
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.data_ready(data_ready),
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.slot_mem_req(slot_mem_req), .slot_mem_wr(slot_mem_wr), .slot_mem_addr(slot_mem_addr),
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.slot_mem_wdata(slot_mem_wdata), .slot_mem_lb_n(slot_mem_lb_n), .slot_mem_ub_n(slot_mem_ub_n),
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.slot_mem_rdata(slot_mem_rdata), .slot_mem_ready(slot_mem_ready),
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.wide_slot_mem_req(wide_slot_mem_req), .wide_slot_mem_addr(wide_slot_mem_addr),
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.wide_slot_mem_rdata(wide_slot_mem_rdata), .wide_slot_mem_ready(wide_slot_mem_ready)
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);
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// ---- AR: activation-fill (shared, 1 port) + per-slot result
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// writeback (N_SLOTS ports), arbitrated exactly as before ----
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wire arb_m_req, arb_m_wr;
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wire [ADDR_WIDTH-1:0] arb_m_addr;
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wire [15:0] arb_m_wdata;
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wire arb_m_lb_n, arb_m_ub_n;
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wire [15:0] arb_m_rdata;
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wire arb_m_ready;
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slot_mem_arbiter #(
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.ADDR_WIDTH(ADDR_WIDTH), .N_PORTS(N_SLOTS+1)
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) u_arbiter (
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.clk(clk), .rst(rst),
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.s_req(slot_mem_req), .s_wr(slot_mem_wr), .s_addr(slot_mem_addr),
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.s_wdata(slot_mem_wdata), .s_lb_n(slot_mem_lb_n), .s_ub_n(slot_mem_ub_n),
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.s_rdata(slot_mem_rdata), .s_ready(slot_mem_ready),
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.m_req(arb_m_req), .m_wr(arb_m_wr), .m_addr(arb_m_addr), .m_wdata(arb_m_wdata),
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.m_lb_n(arb_m_lb_n), .m_ub_n(arb_m_ub_n),
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.m_rdata(arb_m_rdata), .m_ready(arb_m_ready)
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);
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// ---- W: weight fetch (N_SLOTS ports), arbitrated exactly as
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// before -- weight fetch never writes, same tie-off convention
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// as STEP16-19 ----
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wire [N_SLOTS-1:0] wide_s_wr = {N_SLOTS{1'b0}};
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wire [64*N_SLOTS-1:0] wide_s_wdata = {(64*N_SLOTS){1'b0}};
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wire [N_SLOTS-1:0] wide_s_lb_n = {N_SLOTS{1'b0}};
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wire [N_SLOTS-1:0] wide_s_ub_n = {N_SLOTS{1'b0}};
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wire wide_arb_m_req, wide_arb_m_wr;
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wire [ADDR_WIDTH-1:0] wide_arb_m_addr;
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wire [63:0] wide_arb_m_wdata;
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wire wide_arb_m_lb_n, wide_arb_m_ub_n;
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wire [63:0] wide_arb_m_rdata;
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wire wide_arb_m_ready;
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slot_mem_arbiter_wide #(
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.ADDR_WIDTH(ADDR_WIDTH), .N_PORTS(N_SLOTS), .DATA_WIDTH(64)
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) u_arbiter_wide (
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.clk(clk), .rst(rst),
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.s_req(wide_slot_mem_req), .s_wr(wide_s_wr), .s_addr(wide_slot_mem_addr),
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.s_wdata(wide_s_wdata), .s_lb_n(wide_s_lb_n), .s_ub_n(wide_s_ub_n),
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.s_rdata(wide_slot_mem_rdata), .s_ready(wide_slot_mem_ready),
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.m_req(wide_arb_m_req), .m_wr(wide_arb_m_wr), .m_addr(wide_arb_m_addr), .m_wdata(wide_arb_m_wdata),
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.m_lb_n(wide_arb_m_lb_n), .m_ub_n(wide_arb_m_ub_n),
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.m_rdata(wide_arb_m_rdata), .m_ready(wide_arb_m_ready)
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);
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// ---- Bank W: dedicated physical SDRAM backend, W port only, AR
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// port permanently idle (tied off -- never issues an AR-side
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// physical transaction, see header note on why this is safe) ----
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sdram_unified_backend #(
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.ADDR_WIDTH(ADDR_WIDTH), .CLK_FREQ_MHZ(CLK_FREQ_MHZ)
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) u_sdram_backend_w (
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.clk(clk), .rst(rst),
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.w_req(wide_arb_m_req), .w_addr(wide_arb_m_addr),
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.w_rdata(wide_arb_m_rdata), .w_ready(wide_arb_m_ready),
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.ar_req(1'b0), .ar_wr(1'b0), .ar_addr({ADDR_WIDTH{1'b0}}),
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.ar_wdata(16'h0), .ar_lb_n(1'b1), .ar_ub_n(1'b1),
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.ar_rdata(), .ar_ready(),
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.sdram_cke(sdram_w_cke), .sdram_cs_n(sdram_w_cs_n), .sdram_ras_n(sdram_w_ras_n),
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.sdram_cas_n(sdram_w_cas_n), .sdram_we_n(sdram_w_we_n),
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.sdram_ba(sdram_w_ba), .sdram_a(sdram_w_a), .sdram_dq(sdram_w_dq), .sdram_dqm(sdram_w_dqm)
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);
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// ---- Bank AR: dedicated physical SDRAM backend, AR port only, W
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// port permanently idle ----
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sdram_unified_backend #(
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.ADDR_WIDTH(ADDR_WIDTH), .CLK_FREQ_MHZ(CLK_FREQ_MHZ)
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) u_sdram_backend_ar (
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.clk(clk), .rst(rst),
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.w_req(1'b0), .w_addr({ADDR_WIDTH{1'b0}}),
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.w_rdata(), .w_ready(),
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.ar_req(arb_m_req), .ar_wr(arb_m_wr), .ar_addr(arb_m_addr), .ar_wdata(arb_m_wdata),
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.ar_lb_n(arb_m_lb_n), .ar_ub_n(arb_m_ub_n),
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.ar_rdata(arb_m_rdata), .ar_ready(arb_m_ready),
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.sdram_cke(sdram_ar_cke), .sdram_cs_n(sdram_ar_cs_n), .sdram_ras_n(sdram_ar_ras_n),
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.sdram_cas_n(sdram_ar_cas_n), .sdram_we_n(sdram_ar_we_n),
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.sdram_ba(sdram_ar_ba), .sdram_a(sdram_ar_a), .sdram_dq(sdram_ar_dq), .sdram_dqm(sdram_ar_dqm)
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);
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endmodule
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