feat: config-flash passthrough bridge via STARTUPE2, real board-exclusive flash access (EXP-0077)
Implements the user's board architecture: config flash wired exclusively to the FPGA, host (ESP32) reaches it only through the FPGA. flash_spi_master.v is a plain byte-wide SPI master using STARTUPE2 to reclaim CCLK after configuration (the real, Xilinx- documented "indirect SPI flash programming" technique, UG470 p94-96). New opcode 0x40 FLASH_XFER in spi_host_bridge_v3.v relays bytes byte-for-byte between host and the physical flash bus -- the host decides the exact SPI NOR command sequence (verified against the real W25Q32JV datasheet), this RTL knows nothing about flash semantics. Found and fixed two real bugs during verification: a byte-assembly off-by-one in flash_spi_master.v, and a genuine protocol-latency bug in the FLASH_XFER opcode's response timing (needed 2 trailing margin bytes, not 1 -- the internal flash transfer doesn't start until the triggering byte finishes, so 1 byte of margin isn't enough). 39/39 tests pass end to end (host SPI -> bridge -> flash_spi_master -> behavioral flash model). Wired into n2_system_ddr3_top.v with real pin constraints (flash_mosi =K17/flash_miso=K18/flash_cs_n=L13, the same pins reserved-but-unused in EXP-0075) and BITSTREAM.CONFIG.PERSIST=FALSE made explicit. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
Claude Sonnet 5
@@ -44,10 +44,31 @@ module tb_spi_host_bridge_v3;
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reg init_calib_complete_model = 0;
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reg dir_error_model = 0;
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// ---- config-flash passthrough path: real flash_spi_master.v +
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// the same behavioral W25Q32JV-like model used standalone in
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// tb_flash_spi_master.v (EXP-0077), wired end to end through
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// spi_host_bridge_v3.v's own new FLASH_XFER opcode ----
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wire flash_xfer_active, flash_byte_req, flash_byte_done;
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wire [7:0] flash_byte_wdata, flash_byte_rdata;
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wire flash_cs_n, flash_mosi, flash_miso;
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flash_spi_master u_flash (
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.clk(clk), .rst(rst),
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.xfer_active(flash_xfer_active), .byte_req(flash_byte_req),
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.byte_wdata(flash_byte_wdata), .byte_rdata(flash_byte_rdata), .byte_done(flash_byte_done), .busy(),
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.flash_cs_n(flash_cs_n), .flash_mosi(flash_mosi), .flash_miso(flash_miso)
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);
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flash_model_w25q32 u_flash_model (
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.flash_cs_n(flash_cs_n), .flash_mosi(flash_mosi), .flash_miso(flash_miso),
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.flash_sclk(u_flash.cclk_r)
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);
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spi_host_bridge_v3 #(
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.JOB_ADDR_WIDTH(JOB_ADDR_WIDTH), .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH), .N_SLOTS(2)
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) dut (
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.clk(clk), .rst(rst),
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.flash_xfer_active(flash_xfer_active), .flash_byte_req(flash_byte_req),
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.flash_byte_wdata(flash_byte_wdata), .flash_byte_rdata(flash_byte_rdata), .flash_byte_done(flash_byte_done),
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.sclk(sclk), .mosi(mosi), .miso(miso), .cs_n(cs_n),
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.init_calib_complete(init_calib_complete_model), .dir_error(dir_error_model),
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.job_in_valid(job_in_valid), .job_in_ready(job_in_ready_model),
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@@ -315,9 +336,122 @@ module tb_spi_host_bridge_v3;
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spi_byte(8'h00, rxb); check(rxb == 8'h79, "M: READ_MEM LSB byte == 0x79 (bit0=1, catches the ROUT-exit bug)");
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cs_n = 1; #40;
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// ================= Test N: FLASH_XFER passthrough end to end
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// -- real flash_spi_master.v + a real Winbond-command-set
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// behavioral flash model behind it. Write Enable + Page
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// Program + Read Data, entirely through spi_host_bridge_v3.v's
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// own opcode 0x40, proving the WHOLE relay chain (host SPI ->
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// this bridge -> flash_spi_master.v -> physical flash bus) is
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// bit-exact, not just each half in isolation. ===============
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cs_n = 0; #20;
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spi_byte(8'h40, rxb); // opcode FLASH_XFER
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spi_byte(8'h06, rxb); // relay: Write Enable
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cs_n = 1; #40;
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cs_n = 0; #20;
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spi_byte(8'h40, rxb);
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spi_byte(8'h02, rxb); // relay: Page Program
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spi_byte(8'h30, rxb); // relay: addr=0x30
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spi_byte(8'h5A, rxb); // relay: data=0x5A
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spi_byte(8'h00, rxb); // trailing margin byte 1 of 2 -- see header's own real latency note
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spi_byte(8'h00, rxb); // trailing margin byte 2 of 2
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cs_n = 1; #40;
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cs_n = 0; #20;
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spi_byte(8'h40, rxb);
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spi_byte(8'h03, rxb); // relay: Read Data
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spi_byte(8'h30, rxb); // relay: addr=0x30
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spi_byte(8'h00, rxb); // relay: dummy clock for the data byte
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spi_byte(8'h00, rxb); // trailing margin byte 1 of 2
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spi_byte(8'h00, rxb); // trailing margin byte 2 of 2 -- response is safely stable here
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check(rxb == 8'h5A, "N: FLASH_XFER end-to-end round trip through the real flash model, bit-exact");
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cs_n = 1; #40;
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$display("=== tb_spi_host_bridge_v3: %0d/%0d PASS ===", tests-errors, tests);
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if (errors != 0) $display("*** %0d FAILURES ***", errors);
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$finish;
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end
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endmodule
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// STARTUPE2 simulation-only stub -- see tb_flash_spi_master.v's own
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// header for why real UNISIM verification is a disclosed follow-up,
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// not done here (this test verifies the protocol/relay logic, which
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// is independent of STARTUPE2's own real behavior).
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module STARTUPE2 #(
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parameter PROG_USR = "FALSE",
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parameter real SIM_CCLK_FREQ = 0.0
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)(
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output wire CFGCLK, output wire CFGMCLK, output wire EOS, output wire PREQ,
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input wire CLK, input wire GSR, input wire GTS, input wire KEYCLEARB, input wire PACK,
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input wire USRCCLKO, input wire USRCCLKTS,
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input wire USRDONEO, input wire USRDONETS
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);
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endmodule
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// Same behavioral W25Q32JV-like flash model as tb_flash_spi_master.v
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// (EXP-0077) -- kept independent (not shared via `include) since each
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// testbench owns its own self-contained model, matching this
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// project's existing convention (e.g. sdram_model.v is the one real
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// exception, shared because it stands in for real vendor-supplied
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// silicon behavior, not a test-specific convenience model).
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module flash_model_w25q32 (
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input wire flash_cs_n,
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input wire flash_mosi,
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output reg flash_miso,
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input wire flash_sclk
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);
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reg [7:0] flash_mem [0:255];
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reg [7:0] flash_cmd;
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reg [7:0] flash_addr;
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reg flash_wel;
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reg [7:0] model_shift;
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reg [2:0] model_bitcnt;
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reg [2:0] model_bytecnt;
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reg [7:0] model_rdata_byte;
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initial begin flash_wel = 0; model_bytecnt = 0; model_bitcnt = 0; flash_miso = 0; end
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always @(posedge flash_sclk) begin
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if (!flash_cs_n) begin
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model_shift <= {model_shift[6:0], flash_mosi};
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if (model_bitcnt == 3'd7) begin
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model_bitcnt <= 3'd0;
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case (model_bytecnt)
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3'd0: begin
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flash_cmd <= {model_shift[6:0], flash_mosi};
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if ({model_shift[6:0], flash_mosi} == 8'h06) flash_wel <= 1'b1;
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model_bytecnt <= model_bytecnt + 1'b1;
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end
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3'd1: begin
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if (flash_cmd == 8'h02 || flash_cmd == 8'h03) begin
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flash_addr <= {model_shift[6:0], flash_mosi};
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model_bytecnt <= model_bytecnt + 1'b1;
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end
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end
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3'd2: begin
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if (flash_cmd == 8'h02) flash_mem[flash_addr] <= {model_shift[6:0], flash_mosi};
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model_bytecnt <= model_bytecnt + 1'b1;
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end
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default: ;
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endcase
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end else begin
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model_bitcnt <= model_bitcnt + 1'b1;
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end
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end
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end
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always @(*) begin
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if (flash_cmd == 8'h05) model_rdata_byte = {6'b0, flash_wel, 1'b0};
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else if (flash_cmd == 8'h03) model_rdata_byte = flash_mem[flash_addr];
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else model_rdata_byte = 8'h00;
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end
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always @(negedge flash_sclk) begin
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if (!flash_cs_n && model_bytecnt >= (flash_cmd==8'h05 ? 3'd1 : 3'd2))
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flash_miso <= model_rdata_byte[3'd7 - model_bitcnt];
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end
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always @(posedge flash_cs_n) begin
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model_bytecnt <= 3'd0;
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model_bitcnt <= 3'd0;
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end
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endmodule
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