micheleandClaude Sonnet 5
a4c080da83
Implements the user's board architecture: config flash wired exclusively to the FPGA, host (ESP32) reaches it only through the FPGA. flash_spi_master.v is a plain byte-wide SPI master using STARTUPE2 to reclaim CCLK after configuration (the real, Xilinx- documented "indirect SPI flash programming" technique, UG470 p94-96). New opcode 0x40 FLASH_XFER in spi_host_bridge_v3.v relays bytes byte-for-byte between host and the physical flash bus -- the host decides the exact SPI NOR command sequence (verified against the real W25Q32JV datasheet), this RTL knows nothing about flash semantics. Found and fixed two real bugs during verification: a byte-assembly off-by-one in flash_spi_master.v, and a genuine protocol-latency bug in the FLASH_XFER opcode's response timing (needed 2 trailing margin bytes, not 1 -- the internal flash transfer doesn't start until the triggering byte finishes, so 1 byte of margin isn't enough). 39/39 tests pass end to end (host SPI -> bridge -> flash_spi_master -> behavioral flash model). Wired into n2_system_ddr3_top.v with real pin constraints (flash_mosi =K17/flash_miso=K18/flash_cs_n=L13, the same pins reserved-but-unused in EXP-0075) and BITSTREAM.CONFIG.PERSIST=FALSE made explicit. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
458 lines
21 KiB
Verilog
458 lines
21 KiB
Verilog
`timescale 1ns/1ps
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// ================================================================
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// Isolated unit regression for spi_host_bridge_v3.v (V3 SPI opcode
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// re-audit, this session). Mirrors hardware/v2/sim/tb_spi_host_
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// bridge.v's own proven BFM/latency-model structure exactly, adapted
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// for the new job_in_*/mem_* port shapes (16-byte WRITE_JOB, no
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// required/producer_ids fields; 4-byte WRITE_MEM/READ_MEM address).
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//
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// Emulates: (1) neural_director_packed.v's job_in_ready contract (a
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// level, deliberately delayed for a few cycles on the first job to
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// prove job_in_valid is HELD, not pulsed blind); (2) host_mem_
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// bridge.v's mem_ready contract (one clean req/ready handshake, fixed
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// latency, backed by a simple model array standing in for real DDR3
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// content -- host_mem_bridge.v itself is already independently
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// verified in EXP-0071, so this test only needs to prove
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// spi_host_bridge_v3.v drives ITS OWN side of that same word-
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// granularity contract correctly).
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// ================================================================
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module tb_spi_host_bridge_v3;
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localparam JOB_ADDR_WIDTH = 26;
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localparam MEM_ADDR_WIDTH = 25;
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reg clk = 0, rst = 1;
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always #5 clk = ~clk; // 100MHz sim clock
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reg sclk = 0, mosi = 0, cs_n = 1;
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wire miso;
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reg job_in_ready_model = 0;
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wire job_in_valid;
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wire [JOB_ADDR_WIDTH-1:0] job_in_x_base, job_in_w_base, job_in_result_addr;
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wire [15:0] job_in_n_tiles, job_in_node_id;
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wire mem_req, mem_wr, mem_lb_n, mem_ub_n;
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wire [MEM_ADDR_WIDTH-1:0] mem_addr;
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wire [15:0] mem_wdata;
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reg [15:0] mem_rdata_model;
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reg mem_ready_model = 0;
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wire soft_rst_pulse;
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reg init_calib_complete_model = 0;
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reg dir_error_model = 0;
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// ---- config-flash passthrough path: real flash_spi_master.v +
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// the same behavioral W25Q32JV-like model used standalone in
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// tb_flash_spi_master.v (EXP-0077), wired end to end through
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// spi_host_bridge_v3.v's own new FLASH_XFER opcode ----
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wire flash_xfer_active, flash_byte_req, flash_byte_done;
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wire [7:0] flash_byte_wdata, flash_byte_rdata;
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wire flash_cs_n, flash_mosi, flash_miso;
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flash_spi_master u_flash (
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.clk(clk), .rst(rst),
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.xfer_active(flash_xfer_active), .byte_req(flash_byte_req),
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.byte_wdata(flash_byte_wdata), .byte_rdata(flash_byte_rdata), .byte_done(flash_byte_done), .busy(),
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.flash_cs_n(flash_cs_n), .flash_mosi(flash_mosi), .flash_miso(flash_miso)
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);
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flash_model_w25q32 u_flash_model (
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.flash_cs_n(flash_cs_n), .flash_mosi(flash_mosi), .flash_miso(flash_miso),
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.flash_sclk(u_flash.cclk_r)
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);
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spi_host_bridge_v3 #(
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.JOB_ADDR_WIDTH(JOB_ADDR_WIDTH), .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH), .N_SLOTS(2)
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) dut (
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.clk(clk), .rst(rst),
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.flash_xfer_active(flash_xfer_active), .flash_byte_req(flash_byte_req),
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.flash_byte_wdata(flash_byte_wdata), .flash_byte_rdata(flash_byte_rdata), .flash_byte_done(flash_byte_done),
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.sclk(sclk), .mosi(mosi), .miso(miso), .cs_n(cs_n),
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.init_calib_complete(init_calib_complete_model), .dir_error(dir_error_model),
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.job_in_valid(job_in_valid), .job_in_ready(job_in_ready_model),
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.job_in_x_base(job_in_x_base), .job_in_w_base(job_in_w_base),
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.job_in_n_tiles(job_in_n_tiles), .job_in_result_addr(job_in_result_addr),
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.job_in_node_id(job_in_node_id),
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.mem_req(mem_req), .mem_wr(mem_wr), .mem_addr(mem_addr),
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.mem_wdata(mem_wdata), .mem_lb_n(mem_lb_n), .mem_ub_n(mem_ub_n),
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.mem_rdata(mem_rdata_model), .mem_ready(mem_ready_model),
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.soft_rst_pulse(soft_rst_pulse)
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);
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// ---- simple backing memory model: fixed 6-cycle mem_ready latency ----
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reg [15:0] mem_model [0:1023];
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integer mem_latency_cnt;
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reg mem_pending;
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always @(posedge clk) begin
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if (rst) begin
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mem_ready_model <= 1'b0; mem_pending <= 1'b0; mem_latency_cnt <= 0;
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end else begin
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mem_ready_model <= 1'b0;
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if (mem_req && !mem_pending) begin
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mem_pending <= 1'b1;
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mem_latency_cnt <= 6;
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end else if (mem_pending) begin
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if (mem_latency_cnt == 0) begin
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mem_pending <= 1'b0;
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mem_ready_model <= 1'b1;
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if (mem_wr) mem_model[mem_addr[9:0]] <= mem_wdata;
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else mem_rdata_model <= mem_model[mem_addr[9:0]];
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end else begin
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mem_latency_cnt <= mem_latency_cnt - 1;
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end
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end
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end
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end
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// ---- SPI master BFM: mode 0, MSB-first (same timing as tb_spi_host_bridge.v) ----
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task spi_byte(input [7:0] tx, output [7:0] rx);
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integer i;
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begin
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rx = 8'h00;
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for (i = 7; i >= 0; i = i - 1) begin
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mosi = tx[i];
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#200; sclk = 1; #50; rx = {rx[6:0], miso}; #50; sclk = 0; #200;
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end
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end
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endtask
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integer errors = 0, tests = 0;
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task check(input cond, input [255:0] name);
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begin
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tests = tests + 1;
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if (!cond) begin errors = errors + 1; $display("FAIL: %0s", name); end
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else $display("PASS: %0s", name);
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end
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endtask
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reg [7:0] rxb;
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initial begin
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rst = 1; cs_n = 1; sclk = 0; mosi = 0;
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repeat (10) @(posedge clk);
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rst = 0;
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repeat (5) @(posedge clk);
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// ================= Test A: WRITE_JOB (16 bytes), delayed job_in_ready =====
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job_in_ready_model = 0;
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cs_n = 0; #20;
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spi_byte(8'h10, rxb); // opcode WRITE_JOB
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spi_byte(8'h00, rxb); // node_id[15:8]
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spi_byte(8'h05, rxb); // node_id[7:0] -> node_id=5
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spi_byte(8'h00, rxb); // x_base[25:24]
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spi_byte(8'h00, rxb); // x_base[23:16]
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spi_byte(8'h10, rxb); // x_base[15:8]
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spi_byte(8'h00, rxb); // x_base[7:0] -> x_base=0x001000
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spi_byte(8'h00, rxb); // w_base[25:24]
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spi_byte(8'h00, rxb); // w_base[23:16]
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spi_byte(8'h20, rxb); // w_base[15:8]
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spi_byte(8'h00, rxb); // w_base[7:0] -> w_base=0x002000
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spi_byte(8'h00, rxb); // n_tiles[15:8]
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spi_byte(8'h04, rxb); // n_tiles[7:0] -> n_tiles=4
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spi_byte(8'h00, rxb); // result_addr[25:24]
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spi_byte(8'h00, rxb); // result_addr[23:16]
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spi_byte(8'h30, rxb); // result_addr[15:8]
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spi_byte(8'h00, rxb); // result_addr[7:0] -> result_addr=0x003000
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repeat (8) @(posedge clk);
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check(job_in_valid == 1'b1, "A: job_in_valid asserted after 16th payload byte");
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check(job_in_node_id == 16'h0005, "A: job_in_node_id");
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check(job_in_x_base == 26'h001000, "A: job_in_x_base");
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check(job_in_w_base == 26'h002000, "A: job_in_w_base");
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check(job_in_n_tiles == 16'h0004, "A: job_in_n_tiles");
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check(job_in_result_addr == 26'h003000, "A: job_in_result_addr");
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repeat (3) begin
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@(posedge clk);
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check(job_in_valid == 1'b1, "A: job_in_valid still held while job_in_ready=0");
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end
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job_in_ready_model = 1;
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@(posedge clk);
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#1;
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check(job_in_valid == 1'b0, "A: job_in_valid drops the cycle after job_in_ready seen");
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job_in_ready_model = 0;
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cs_n = 1; #40;
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// ================= Test B: STATUS after accepted job ========
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cs_n = 0; #20;
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spi_byte(8'h20, rxb); // opcode STATUS
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spi_byte(8'h00, rxb); // clocks out status byte
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check(rxb[2] == 1'b1, "B: STATUS last_job_accepted=1");
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check(rxb[0] == 1'b0, "B: STATUS job_busy=0 (already accepted)");
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cs_n = 1; #40;
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// ================= Test C: WRITE_MEM, single word (4-byte addr) =====
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cs_n = 0; #20;
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spi_byte(8'h01, rxb); // opcode WRITE_MEM
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spi_byte(8'h00, rxb); spi_byte(8'h00, rxb); spi_byte(8'h00, rxb); spi_byte(8'h55, rxb); // addr=0x000055
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spi_byte(8'h00, rxb); spi_byte(8'h01, rxb); // len_words=1
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spi_byte(8'h12, rxb); spi_byte(8'h34, rxb); // data=0x1234
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#200;
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cs_n = 1; #40;
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check(mem_model[16'h0055] == 16'h1234, "C: WRITE_MEM wrote 0x1234 @ 0x000055");
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// ================= Test D: READ_MEM, single word =============
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cs_n = 0; #20;
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spi_byte(8'h02, rxb); // opcode READ_MEM
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spi_byte(8'h00, rxb); spi_byte(8'h00, rxb); spi_byte(8'h00, rxb); spi_byte(8'h55, rxb); // addr=0x000055
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spi_byte(8'h00, rxb); spi_byte(8'h01, rxb); // len_words=1
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#200;
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spi_byte(8'h00, rxb);
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check(rxb == 8'h12, "D: READ_MEM MSB byte == 0x12");
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spi_byte(8'h00, rxb);
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check(rxb == 8'h34, "D: READ_MEM LSB byte == 0x34");
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cs_n = 1; #40;
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// ================= Test E: multi-word WRITE_MEM/READ_MEM, exercising
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// the 25-bit MEM_ADDR_WIDTH's own top bit (addr near 2^24) =========
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cs_n = 0; #20;
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spi_byte(8'h01, rxb); // opcode WRITE_MEM
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spi_byte(8'h01, rxb); spi_byte(8'h00, rxb); spi_byte(8'h00, rxb); spi_byte(8'h00, rxb); // addr=0x1000000 (bit24=1)
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spi_byte(8'h00, rxb); spi_byte(8'h02, rxb); // len_words=2
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spi_byte(8'hAA, rxb); spi_byte(8'hBB, rxb); // word0=0xAABB
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spi_byte(8'hCC, rxb); spi_byte(8'hDD, rxb); // word1=0xCCDD
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#400;
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cs_n = 1; #40;
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check(mem_model[(25'h1000000) & 10'h3FF] == 16'hAABB, "E: WRITE_MEM word0 @ addr bit24 set");
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check(mem_model[((25'h1000000)+1) & 10'h3FF] == 16'hCCDD, "E: WRITE_MEM word1 @ addr bit24 set");
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// ================= Test G: REG_READ, DEVICE_ID (0x00) ========
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cs_n = 0; #20;
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spi_byte(8'h31, rxb); // opcode REG_READ
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spi_byte(8'h00, rxb); // reg_addr=0x00 DEVICE_ID
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spi_byte(8'h00, rxb); check(rxb == 8'h4E, "G: DEVICE_ID byte0 == 'N'");
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spi_byte(8'h00, rxb); check(rxb == 8'h50, "G: DEVICE_ID byte1 == 'P'");
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spi_byte(8'h00, rxb); check(rxb == 8'h56, "G: DEVICE_ID byte2 == 'V'");
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spi_byte(8'h00, rxb); check(rxb == 8'h01, "G: DEVICE_ID byte3 == version 1");
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cs_n = 1; #40;
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// ================= Test H: REG_READ, N_SLOTS (0x03) ==========
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cs_n = 0; #20;
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spi_byte(8'h31, rxb);
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spi_byte(8'h03, rxb);
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spi_byte(8'h00, rxb); check(rxb == 8'h00, "H: N_SLOTS byte0 == 0");
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spi_byte(8'h00, rxb); check(rxb == 8'h00, "H: N_SLOTS byte1 == 0");
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spi_byte(8'h00, rxb); check(rxb == 8'h00, "H: N_SLOTS byte2 == 0");
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spi_byte(8'h00, rxb); check(rxb == 8'h02, "H: N_SLOTS byte3 == 2 (matches N_SLOTS param)");
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cs_n = 1; #40;
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// ================= Test I: REG_READ, STATUS (0x02), with
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// init_calib_complete and dir_error both driven high by the
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// model, confirming they land in the right bits ============
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init_calib_complete_model = 1'b1;
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dir_error_model = 1'b1;
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cs_n = 0; #20;
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spi_byte(8'h31, rxb);
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spi_byte(8'h02, rxb);
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spi_byte(8'h00, rxb); check(rxb == 8'h00, "I: STATUS byte0 == 0 (bits[31:8] reserved)");
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spi_byte(8'h00, rxb); check(rxb == 8'h00, "I: STATUS byte1 == 0");
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spi_byte(8'h00, rxb); check(rxb == 8'h00, "I: STATUS byte2 == 0");
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spi_byte(8'h00, rxb); check(rxb[3] == 1'b1, "I: STATUS bit3 == init_calib_complete");
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check(rxb[4] == 1'b1, "I: STATUS bit4 == dir_error");
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cs_n = 1; #40;
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init_calib_complete_model = 1'b0;
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dir_error_model = 1'b0;
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// ================= Test J: REG_READ, unknown address =========
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cs_n = 0; #20;
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spi_byte(8'h31, rxb);
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spi_byte(8'hEE, rxb); // unmapped register
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spi_byte(8'h00, rxb); check(rxb == 8'hFF, "J: unmapped reg byte0 == 0xFF");
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spi_byte(8'h00, rxb); check(rxb == 8'hFF, "J: unmapped reg byte1 == 0xFF");
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spi_byte(8'h00, rxb); check(rxb == 8'hFF, "J: unmapped reg byte2 == 0xFF");
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spi_byte(8'h00, rxb); check(rxb == 8'hFF, "J: unmapped reg byte3 == 0xFF (distinct from a real 0)");
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cs_n = 1; #40;
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// ================= Test K: REG_WRITE to CONTROL (0x01) bit0
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// pulses soft_rst_pulse, same physical effect as RESET.
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// UNLIKE the RESET opcode (which pulses only after CS rises),
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// REG_WRITE applies immediately when its last data byte
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// lands -- no backend handshake to wait on (see this module's
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// own header). The watchdog must therefore run CONCURRENTLY
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// with the last data byte's own spi_byte() call (a `fork`,
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// same technique as tb_sdram_arbiter_n.v's own one-shot-pulse
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// watchers), not after CS has already risen -- a first draft
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// of this test watched only after CS rose and missed the
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// pulse entirely (a testbench-timing bug, not an RTL one,
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// confirmed via a DUT-internal trace before writing this). ==
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cs_n = 0; #20;
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spi_byte(8'h30, rxb); // opcode REG_WRITE
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spi_byte(8'h01, rxb); // reg_addr=0x01 CONTROL
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spi_byte(8'h00, rxb); spi_byte(8'h00, rxb); spi_byte(8'h00, rxb); // value bytes 31:8 = 0
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begin : wait_reg_soft_rst
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reg seen;
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seen = 1'b0;
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fork
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spi_byte(8'h01, rxb); // value byte 7:0 = 1 (bit0 set) -- triggers the pulse
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begin : watcher
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integer wi;
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for (wi = 0; wi < 410; wi = wi + 1) begin // covers spi_byte's own ~400-clk duration plus margin
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@(posedge clk);
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if (soft_rst_pulse) seen = 1'b1;
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end
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end
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join
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check(seen, "K: REG_WRITE CONTROL bit0 pulses soft_rst_pulse");
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end
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cs_n = 1; #40;
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// ================= Test L: RESET opcode ======================
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cs_n = 0; #20;
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spi_byte(8'h0F, rxb); // opcode RESET
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cs_n = 1;
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begin : wait_soft_rst
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integer wi; reg seen;
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seen = 1'b0;
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for (wi = 0; wi < 10; wi = wi + 1) begin
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@(posedge clk);
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if (soft_rst_pulse) seen = 1'b1;
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end
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check(seen, "L: soft_rst_pulse asserted after CS rises (within CDC latency)");
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end
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// ================= Test M: READ_MEM regression for the ROUT-
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// exit bit_count==0 corruption (found via REG_READ this
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// session, see spi_host_bridge_v3.v's own header note) --
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// Test C/D's word 0x1234 has LSB byte 0x34 (bit0=0), which
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// coincidentally matched the corrupted substitute's bit7=0
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// and masked the bug. Use 0x5679 instead: LSB byte 0x79 =
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// 0111_1001, bit0=1, which the (now-fixed) bug would have
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// flipped to 0 (reading back 0x78 instead of 0x79). =========
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cs_n = 0; #20;
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spi_byte(8'h01, rxb);
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spi_byte(8'h00, rxb); spi_byte(8'h00, rxb); spi_byte(8'h00, rxb); spi_byte(8'h60, rxb); // addr=0x60
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spi_byte(8'h00, rxb); spi_byte(8'h01, rxb); // len_words=1
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spi_byte(8'h56, rxb); spi_byte(8'h79, rxb); // data=0x5679
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#200;
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cs_n = 1; #40;
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cs_n = 0; #20;
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spi_byte(8'h02, rxb);
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spi_byte(8'h00, rxb); spi_byte(8'h00, rxb); spi_byte(8'h00, rxb); spi_byte(8'h60, rxb);
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spi_byte(8'h00, rxb); spi_byte(8'h01, rxb);
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#200;
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spi_byte(8'h00, rxb); check(rxb == 8'h56, "M: READ_MEM MSB byte == 0x56");
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spi_byte(8'h00, rxb); check(rxb == 8'h79, "M: READ_MEM LSB byte == 0x79 (bit0=1, catches the ROUT-exit bug)");
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|
cs_n = 1; #40;
|
|
|
|
// ================= Test N: FLASH_XFER passthrough end to end
|
|
// -- real flash_spi_master.v + a real Winbond-command-set
|
|
// behavioral flash model behind it. Write Enable + Page
|
|
// Program + Read Data, entirely through spi_host_bridge_v3.v's
|
|
// own opcode 0x40, proving the WHOLE relay chain (host SPI ->
|
|
// this bridge -> flash_spi_master.v -> physical flash bus) is
|
|
// bit-exact, not just each half in isolation. ===============
|
|
cs_n = 0; #20;
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|
spi_byte(8'h40, rxb); // opcode FLASH_XFER
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|
spi_byte(8'h06, rxb); // relay: Write Enable
|
|
cs_n = 1; #40;
|
|
|
|
cs_n = 0; #20;
|
|
spi_byte(8'h40, rxb);
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|
spi_byte(8'h02, rxb); // relay: Page Program
|
|
spi_byte(8'h30, rxb); // relay: addr=0x30
|
|
spi_byte(8'h5A, rxb); // relay: data=0x5A
|
|
spi_byte(8'h00, rxb); // trailing margin byte 1 of 2 -- see header's own real latency note
|
|
spi_byte(8'h00, rxb); // trailing margin byte 2 of 2
|
|
cs_n = 1; #40;
|
|
|
|
cs_n = 0; #20;
|
|
spi_byte(8'h40, rxb);
|
|
spi_byte(8'h03, rxb); // relay: Read Data
|
|
spi_byte(8'h30, rxb); // relay: addr=0x30
|
|
spi_byte(8'h00, rxb); // relay: dummy clock for the data byte
|
|
spi_byte(8'h00, rxb); // trailing margin byte 1 of 2
|
|
spi_byte(8'h00, rxb); // trailing margin byte 2 of 2 -- response is safely stable here
|
|
check(rxb == 8'h5A, "N: FLASH_XFER end-to-end round trip through the real flash model, bit-exact");
|
|
cs_n = 1; #40;
|
|
|
|
$display("=== tb_spi_host_bridge_v3: %0d/%0d PASS ===", tests-errors, tests);
|
|
if (errors != 0) $display("*** %0d FAILURES ***", errors);
|
|
$finish;
|
|
end
|
|
|
|
endmodule
|
|
|
|
// STARTUPE2 simulation-only stub -- see tb_flash_spi_master.v's own
|
|
// header for why real UNISIM verification is a disclosed follow-up,
|
|
// not done here (this test verifies the protocol/relay logic, which
|
|
// is independent of STARTUPE2's own real behavior).
|
|
module STARTUPE2 #(
|
|
parameter PROG_USR = "FALSE",
|
|
parameter real SIM_CCLK_FREQ = 0.0
|
|
)(
|
|
output wire CFGCLK, output wire CFGMCLK, output wire EOS, output wire PREQ,
|
|
input wire CLK, input wire GSR, input wire GTS, input wire KEYCLEARB, input wire PACK,
|
|
input wire USRCCLKO, input wire USRCCLKTS,
|
|
input wire USRDONEO, input wire USRDONETS
|
|
);
|
|
endmodule
|
|
|
|
// Same behavioral W25Q32JV-like flash model as tb_flash_spi_master.v
|
|
// (EXP-0077) -- kept independent (not shared via `include) since each
|
|
// testbench owns its own self-contained model, matching this
|
|
// project's existing convention (e.g. sdram_model.v is the one real
|
|
// exception, shared because it stands in for real vendor-supplied
|
|
// silicon behavior, not a test-specific convenience model).
|
|
module flash_model_w25q32 (
|
|
input wire flash_cs_n,
|
|
input wire flash_mosi,
|
|
output reg flash_miso,
|
|
input wire flash_sclk
|
|
);
|
|
reg [7:0] flash_mem [0:255];
|
|
reg [7:0] flash_cmd;
|
|
reg [7:0] flash_addr;
|
|
reg flash_wel;
|
|
reg [7:0] model_shift;
|
|
reg [2:0] model_bitcnt;
|
|
reg [2:0] model_bytecnt;
|
|
reg [7:0] model_rdata_byte;
|
|
|
|
initial begin flash_wel = 0; model_bytecnt = 0; model_bitcnt = 0; flash_miso = 0; end
|
|
|
|
always @(posedge flash_sclk) begin
|
|
if (!flash_cs_n) begin
|
|
model_shift <= {model_shift[6:0], flash_mosi};
|
|
if (model_bitcnt == 3'd7) begin
|
|
model_bitcnt <= 3'd0;
|
|
case (model_bytecnt)
|
|
3'd0: begin
|
|
flash_cmd <= {model_shift[6:0], flash_mosi};
|
|
if ({model_shift[6:0], flash_mosi} == 8'h06) flash_wel <= 1'b1;
|
|
model_bytecnt <= model_bytecnt + 1'b1;
|
|
end
|
|
3'd1: begin
|
|
if (flash_cmd == 8'h02 || flash_cmd == 8'h03) begin
|
|
flash_addr <= {model_shift[6:0], flash_mosi};
|
|
model_bytecnt <= model_bytecnt + 1'b1;
|
|
end
|
|
end
|
|
3'd2: begin
|
|
if (flash_cmd == 8'h02) flash_mem[flash_addr] <= {model_shift[6:0], flash_mosi};
|
|
model_bytecnt <= model_bytecnt + 1'b1;
|
|
end
|
|
default: ;
|
|
endcase
|
|
end else begin
|
|
model_bitcnt <= model_bitcnt + 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
always @(*) begin
|
|
if (flash_cmd == 8'h05) model_rdata_byte = {6'b0, flash_wel, 1'b0};
|
|
else if (flash_cmd == 8'h03) model_rdata_byte = flash_mem[flash_addr];
|
|
else model_rdata_byte = 8'h00;
|
|
end
|
|
always @(negedge flash_sclk) begin
|
|
if (!flash_cs_n && model_bytecnt >= (flash_cmd==8'h05 ? 3'd1 : 3'd2))
|
|
flash_miso <= model_rdata_byte[3'd7 - model_bitcnt];
|
|
end
|
|
always @(posedge flash_cs_n) begin
|
|
model_bytecnt <= 3'd0;
|
|
model_bitcnt <= 3'd0;
|
|
end
|
|
endmodule
|