test: add Phase 2 parameter sweep for neuron_parallel, update roadmap
Roadmap Phase 2 asks to validate N_INPUTS/N_NEURONS/PARALLEL combinations, including non-exact-multiple configurations. Added sim/parameter_sweep_tb.v with 5 configs (two exact-multiple sanity checks, two non-exact-multiple, one degenerate PARALLEL>N_INPUTS), using a cycle-count watchdog instead of a blocking wait so a hanging config is reported rather than hanging the simulation. Findings (RTL unchanged, core datapath left untouched): - GROUPS = N_INPUTS / PARALLEL truncates: when N_INPUTS is not an exact multiple of PARALLEL, the remainder inputs are silently never summed (confirmed 30/8 -> 6 dropped, 20/16 -> 4 dropped). - PARALLEL > N_INPUTS gives GROUPS=0, and the controller's group_index == GROUPS-1 terminal condition is never met: the neuron hangs forever (confirmed via watchdog timeout). Documented both as findings under Phase 2 in docs/FPGA-NeuralNetwork-Engine.md for follow-up in Phase 3/7. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01WQV3vS9TXaGDJ5cRfnfidt
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Claude Sonnet 5
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`timescale 1ns/1ps
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// ================================================================
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// PHASE 2 - PARAMETER SWEEP
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//
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// Roadmap requirement (docs/FPGA-NeuralNetwork-Engine.md, Phase 2):
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// validate multiple combinations of N_INPUTS / N_NEURONS / PARALLEL,
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// including configurations where N_INPUTS is NOT an exact multiple
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// of PARALLEL.
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//
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// neuron_parallel.v computes:
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// localparam GROUPS = N_INPUTS / PARALLEL;
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// which is an INTEGER division. When N_INPUTS is not an exact
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// multiple of PARALLEL, the remainder inputs are silently never
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// read by the accumulator (GEN_TREE only ever selects the first
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// GROUPS*PARALLEL inputs). This bench characterizes that behavior
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// instead of assuming it does not exist, and uses a cycle-count
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// watchdog (never a blocking `wait`) so a config that never
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// asserts `done` is reported instead of hanging the simulation.
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// ================================================================
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module tb;
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reg clk;
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reg rst;
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initial begin
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clk = 0;
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forever #5 clk = ~clk;
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end
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integer errors;
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integer findings;
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// ============================================================
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// CONFIG A - baseline, exact multiple (sanity check)
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// N_INPUTS=32 PARALLEL=8 -> GROUPS=4
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// ============================================================
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localparam A_DATA_WIDTH = 8;
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localparam A_N_INPUTS = 32;
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localparam A_PARALLEL = 8;
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localparam A_ACC_WIDTH = 32;
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reg start_a;
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reg signed [A_DATA_WIDTH*A_N_INPUTS-1:0] x_bus_a;
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reg signed [A_DATA_WIDTH*A_N_INPUTS-1:0] w_bus_a;
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reg signed [A_DATA_WIDTH-1:0] bias_a;
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wire signed [A_DATA_WIDTH-1:0] y_a;
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wire busy_a, done_a;
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neuron_parallel #(
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.DATA_WIDTH(A_DATA_WIDTH),
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.N_INPUTS(A_N_INPUTS),
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.PARALLEL(A_PARALLEL),
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.ACC_WIDTH(A_ACC_WIDTH)
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) u_a (
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.clk(clk), .rst(rst), .start(start_a),
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.x_bus(x_bus_a), .w_bus(w_bus_a), .bias(bias_a),
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.y(y_a), .busy(busy_a), .done(done_a)
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);
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// ============================================================
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// CONFIG B - non-exact multiple
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// N_INPUTS=30 PARALLEL=8 -> GROUPS=3 (24 inputs actually summed)
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// ============================================================
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localparam B_DATA_WIDTH = 8;
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localparam B_N_INPUTS = 30;
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localparam B_PARALLEL = 8;
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localparam B_ACC_WIDTH = 32;
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reg start_b;
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reg signed [B_DATA_WIDTH*B_N_INPUTS-1:0] x_bus_b;
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reg signed [B_DATA_WIDTH*B_N_INPUTS-1:0] w_bus_b;
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reg signed [B_DATA_WIDTH-1:0] bias_b;
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wire signed [B_DATA_WIDTH-1:0] y_b;
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wire busy_b, done_b;
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neuron_parallel #(
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.DATA_WIDTH(B_DATA_WIDTH),
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.N_INPUTS(B_N_INPUTS),
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.PARALLEL(B_PARALLEL),
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.ACC_WIDTH(B_ACC_WIDTH)
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) u_b (
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.clk(clk), .rst(rst), .start(start_b),
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.x_bus(x_bus_b), .w_bus(w_bus_b), .bias(bias_b),
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.y(y_b), .busy(busy_b), .done(done_b)
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);
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// ============================================================
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// CONFIG C - non-exact multiple, different PARALLEL
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// N_INPUTS=20 PARALLEL=16 -> GROUPS=1 (16 inputs actually summed)
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// ============================================================
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localparam C_DATA_WIDTH = 8;
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localparam C_N_INPUTS = 20;
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localparam C_PARALLEL = 16;
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localparam C_ACC_WIDTH = 32;
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reg start_c;
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reg signed [C_DATA_WIDTH*C_N_INPUTS-1:0] x_bus_c;
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reg signed [C_DATA_WIDTH*C_N_INPUTS-1:0] w_bus_c;
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reg signed [C_DATA_WIDTH-1:0] bias_c;
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wire signed [C_DATA_WIDTH-1:0] y_c;
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wire busy_c, done_c;
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neuron_parallel #(
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.DATA_WIDTH(C_DATA_WIDTH),
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.N_INPUTS(C_N_INPUTS),
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.PARALLEL(C_PARALLEL),
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.ACC_WIDTH(C_ACC_WIDTH)
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) u_c (
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.clk(clk), .rst(rst), .start(start_c),
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.x_bus(x_bus_c), .w_bus(w_bus_c), .bias(bias_c),
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.y(y_c), .busy(busy_c), .done(done_c)
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);
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// ============================================================
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// CONFIG D - exact multiple, wide parallelism (sanity check)
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// N_INPUTS=64 PARALLEL=32 -> GROUPS=2
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// ============================================================
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localparam D_DATA_WIDTH = 8;
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localparam D_N_INPUTS = 64;
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localparam D_PARALLEL = 32;
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localparam D_ACC_WIDTH = 32;
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reg start_d;
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reg signed [D_DATA_WIDTH*D_N_INPUTS-1:0] x_bus_d;
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reg signed [D_DATA_WIDTH*D_N_INPUTS-1:0] w_bus_d;
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reg signed [D_DATA_WIDTH-1:0] bias_d;
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wire signed [D_DATA_WIDTH-1:0] y_d;
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wire busy_d, done_d;
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neuron_parallel #(
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.DATA_WIDTH(D_DATA_WIDTH),
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.N_INPUTS(D_N_INPUTS),
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.PARALLEL(D_PARALLEL),
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.ACC_WIDTH(D_ACC_WIDTH)
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) u_d (
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.clk(clk), .rst(rst), .start(start_d),
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.x_bus(x_bus_d), .w_bus(w_bus_d), .bias(bias_d),
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.y(y_d), .busy(busy_d), .done(done_d)
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);
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// ============================================================
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// CONFIG E - degenerate: PARALLEL > N_INPUTS
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// N_INPUTS=4 PARALLEL=8 -> GROUPS=0
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// Watchdog-guarded: expected to NOT complete (documents the
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// constraint "PARALLEL must not exceed N_INPUTS").
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// ============================================================
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localparam E_DATA_WIDTH = 8;
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localparam E_N_INPUTS = 4;
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localparam E_PARALLEL = 8;
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localparam E_ACC_WIDTH = 32;
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reg start_e;
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reg signed [E_DATA_WIDTH*E_N_INPUTS-1:0] x_bus_e;
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reg signed [E_DATA_WIDTH*E_N_INPUTS-1:0] w_bus_e;
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reg signed [E_DATA_WIDTH-1:0] bias_e;
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wire signed [E_DATA_WIDTH-1:0] y_e;
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wire busy_e, done_e;
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neuron_parallel #(
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.DATA_WIDTH(E_DATA_WIDTH),
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.N_INPUTS(E_N_INPUTS),
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.PARALLEL(E_PARALLEL),
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.ACC_WIDTH(E_ACC_WIDTH)
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) u_e (
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.clk(clk), .rst(rst), .start(start_e),
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.x_bus(x_bus_e), .w_bus(w_bus_e), .bias(bias_e),
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.y(y_e), .busy(busy_e), .done(done_e)
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);
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// ============================================================
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// MAIN
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// ============================================================
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integer max_cycles;
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integer count;
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reg timed_out;
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initial begin
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$dumpfile("sim/parameter_sweep.vcd");
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$dumpvars(0, tb);
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rst = 1;
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errors = 0;
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findings = 0;
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max_cycles = 500;
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start_a = 0; x_bus_a = 0; w_bus_a = 0; bias_a = 0;
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start_b = 0; x_bus_b = 0; w_bus_b = 0; bias_b = 0;
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start_c = 0; x_bus_c = 0; w_bus_c = 0; bias_c = 0;
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start_d = 0; x_bus_d = 0; w_bus_d = 0; bias_d = 0;
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start_e = 0; x_bus_e = 0; w_bus_e = 0; bias_e = 0;
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repeat (2) @(posedge clk);
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rst = 0;
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$display("");
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$display("========================================");
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$display("PHASE 2 - PARAMETER SWEEP");
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$display("========================================");
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// --------------------------------------------------------
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// CONFIG A: all x=1, all w=1, bias=0
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// full sum = 32, exact multiple -> expect 32
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// --------------------------------------------------------
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for (count = 0; count < A_N_INPUTS; count = count + 1) begin
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x_bus_a[count*A_DATA_WIDTH +: A_DATA_WIDTH] = 8'sd1;
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w_bus_a[count*A_DATA_WIDTH +: A_DATA_WIDTH] = 8'sd1;
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end
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bias_a = 0;
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@(posedge clk); start_a <= 1'b1;
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@(posedge clk); start_a <= 1'b0;
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timed_out = 1'b0;
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count = 0;
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while (!done_a && !timed_out) begin
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@(posedge clk);
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count = count + 1;
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if (count > max_cycles) timed_out = 1'b1;
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end
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@(posedge clk);
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$display("");
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$display("CONFIG A: N_INPUTS=%0d PARALLEL=%0d (exact, GROUPS=%0d)",
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A_N_INPUTS, A_PARALLEL, A_N_INPUTS/A_PARALLEL);
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if (timed_out) begin
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$display(" RESULT: TIMEOUT (did not assert done within %0d cycles)", max_cycles);
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errors = errors + 1;
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end else begin
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$display(" y = %0d expected = 32", y_a);
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if (y_a !== 8'sd32) begin
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$display(" FAIL");
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errors = errors + 1;
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end else begin
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$display(" PASS");
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end
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end
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// --------------------------------------------------------
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// CONFIG B: all x=1, all w=1, bias=0
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// N_INPUTS=30, PARALLEL=8 -> GROUPS=3 -> only first 24
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// inputs are actually summed by the current RTL.
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// full-sum expectation would be 30; RTL-truncated
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// expectation is 24. We check against the RTL-truncated
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// value and flag the mismatch vs. the full sum as a
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// documented finding (not a failure of this bench).
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// --------------------------------------------------------
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for (count = 0; count < B_N_INPUTS; count = count + 1) begin
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x_bus_b[count*B_DATA_WIDTH +: B_DATA_WIDTH] = 8'sd1;
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w_bus_b[count*B_DATA_WIDTH +: B_DATA_WIDTH] = 8'sd1;
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end
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bias_b = 0;
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@(posedge clk); start_b <= 1'b1;
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@(posedge clk); start_b <= 1'b0;
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timed_out = 1'b0;
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count = 0;
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while (!done_b && !timed_out) begin
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@(posedge clk);
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count = count + 1;
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if (count > max_cycles) timed_out = 1'b1;
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end
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@(posedge clk);
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$display("");
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$display("CONFIG B: N_INPUTS=%0d PARALLEL=%0d (NON-exact, GROUPS=%0d, %0d inputs actually read)",
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B_N_INPUTS, B_PARALLEL, B_N_INPUTS/B_PARALLEL,
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(B_N_INPUTS/B_PARALLEL)*B_PARALLEL);
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if (timed_out) begin
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$display(" RESULT: TIMEOUT (did not assert done within %0d cycles)", max_cycles);
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errors = errors + 1;
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end else begin
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$display(" y = %0d RTL-truncated expected = 24 full-sum (NOT met) = 30", y_b);
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if (y_b !== 8'sd24) begin
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$display(" FAIL (unexpected value for current RTL behavior)");
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errors = errors + 1;
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end else begin
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$display(" PASS (matches current RTL truncation behavior)");
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end
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if (y_b !== B_N_INPUTS[7:0]) begin
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$display(" FINDING: last %0d input(s) are silently ignored (GROUPS = N_INPUTS/PARALLEL truncates)",
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B_N_INPUTS - (B_N_INPUTS/B_PARALLEL)*B_PARALLEL);
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findings = findings + 1;
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end
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end
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// --------------------------------------------------------
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// CONFIG C: same characterization, different sizes
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// N_INPUTS=20, PARALLEL=16 -> GROUPS=1 -> only first 16 read
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// --------------------------------------------------------
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for (count = 0; count < C_N_INPUTS; count = count + 1) begin
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x_bus_c[count*C_DATA_WIDTH +: C_DATA_WIDTH] = 8'sd1;
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w_bus_c[count*C_DATA_WIDTH +: C_DATA_WIDTH] = 8'sd1;
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end
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bias_c = 0;
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@(posedge clk); start_c <= 1'b1;
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@(posedge clk); start_c <= 1'b0;
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timed_out = 1'b0;
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count = 0;
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while (!done_c && !timed_out) begin
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@(posedge clk);
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count = count + 1;
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if (count > max_cycles) timed_out = 1'b1;
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end
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@(posedge clk);
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$display("");
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$display("CONFIG C: N_INPUTS=%0d PARALLEL=%0d (NON-exact, GROUPS=%0d, %0d inputs actually read)",
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C_N_INPUTS, C_PARALLEL, C_N_INPUTS/C_PARALLEL,
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(C_N_INPUTS/C_PARALLEL)*C_PARALLEL);
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if (timed_out) begin
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$display(" RESULT: TIMEOUT (did not assert done within %0d cycles)", max_cycles);
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errors = errors + 1;
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end else begin
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$display(" y = %0d RTL-truncated expected = 16 full-sum (NOT met) = 20", y_c);
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if (y_c !== 8'sd16) begin
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$display(" FAIL (unexpected value for current RTL behavior)");
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errors = errors + 1;
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end else begin
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$display(" PASS (matches current RTL truncation behavior)");
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end
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if (y_c !== C_N_INPUTS[7:0]) begin
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$display(" FINDING: last %0d input(s) are silently ignored (GROUPS = N_INPUTS/PARALLEL truncates)",
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C_N_INPUTS - (C_N_INPUTS/C_PARALLEL)*C_PARALLEL);
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findings = findings + 1;
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end
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end
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// --------------------------------------------------------
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// CONFIG D: all x=1, all w=1, bias=0
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// full sum = 64, exact multiple -> expect 64
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// --------------------------------------------------------
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for (count = 0; count < D_N_INPUTS; count = count + 1) begin
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x_bus_d[count*D_DATA_WIDTH +: D_DATA_WIDTH] = 8'sd1;
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w_bus_d[count*D_DATA_WIDTH +: D_DATA_WIDTH] = 8'sd1;
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end
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bias_d = 0;
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@(posedge clk); start_d <= 1'b1;
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@(posedge clk); start_d <= 1'b0;
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timed_out = 1'b0;
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count = 0;
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while (!done_d && !timed_out) begin
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@(posedge clk);
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count = count + 1;
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if (count > max_cycles) timed_out = 1'b1;
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end
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@(posedge clk);
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$display("");
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$display("CONFIG D: N_INPUTS=%0d PARALLEL=%0d (exact, GROUPS=%0d)",
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D_N_INPUTS, D_PARALLEL, D_N_INPUTS/D_PARALLEL);
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if (timed_out) begin
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$display(" RESULT: TIMEOUT (did not assert done within %0d cycles)", max_cycles);
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errors = errors + 1;
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end else begin
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$display(" y = %0d expected = 64", y_d);
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if (y_d !== 8'sd64) begin
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$display(" FAIL");
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errors = errors + 1;
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end else begin
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$display(" PASS");
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end
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end
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// --------------------------------------------------------
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// CONFIG E: degenerate PARALLEL > N_INPUTS -> GROUPS=0
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// We EXPECT this to time out. If it ever completes, that
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// is itself worth flagging (behavior changed).
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// --------------------------------------------------------
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for (count = 0; count < E_N_INPUTS; count = count + 1) begin
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x_bus_e[count*E_DATA_WIDTH +: E_DATA_WIDTH] = 8'sd1;
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w_bus_e[count*E_DATA_WIDTH +: E_DATA_WIDTH] = 8'sd1;
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end
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bias_e = 0;
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@(posedge clk); start_e <= 1'b1;
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@(posedge clk); start_e <= 1'b0;
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timed_out = 1'b0;
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count = 0;
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while (!done_e && !timed_out) begin
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@(posedge clk);
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count = count + 1;
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if (count > max_cycles) timed_out = 1'b1;
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end
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@(posedge clk);
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$display("");
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$display("CONFIG E: N_INPUTS=%0d PARALLEL=%0d (DEGENERATE, GROUPS=%0d)",
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E_N_INPUTS, E_PARALLEL, E_N_INPUTS/E_PARALLEL);
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if (timed_out) begin
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$display(" RESULT: TIMEOUT as expected (done never asserted within %0d cycles)", max_cycles);
|
||||
$display(" FINDING: PARALLEL > N_INPUTS (GROUPS=0) hangs neuron_parallel forever -- design constraint, not currently guarded in RTL");
|
||||
findings = findings + 1;
|
||||
end else begin
|
||||
$display(" RESULT: completed with y=%0d (unexpected -- previously assumed to hang)", y_e);
|
||||
errors = errors + 1;
|
||||
end
|
||||
|
||||
$display("");
|
||||
$display("========================================");
|
||||
$display("PARAMETER SWEEP SUMMARY");
|
||||
$display(" errors = %0d", errors);
|
||||
$display(" findings = %0d (documented limitations, not bench failures)", findings);
|
||||
if (errors == 0)
|
||||
$display("PARAMETER SWEEP: PASSED (all configs behaved as characterized)");
|
||||
else
|
||||
$display("PARAMETER SWEEP: FAILED");
|
||||
$display("========================================");
|
||||
$display("");
|
||||
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user