diff --git a/WORKLOG.md b/WORKLOG.md
index c9a2b39..61f9687 100644
--- a/WORKLOG.md
+++ b/WORKLOG.md
@@ -47,3 +47,26 @@
 - 2026-09-02T00:43 — [FASE 6] — Compilato ed eseguito `sim/layer_tb.v`: `iverilog -g2012 -o <tmp> rtl/*.v sim/layer_tb.v` + `vvp`. Risultato: TUTTI GLI 8 NEURONI PASSANO (32,96,0,127,5,0,22,21), busy=0, done=1 a fine test.
 - 2026-09-02T00:44 — [FASE 6] — Rigenerati gli artefatti tracciati in git `sim/neuron_sim` (da neuron_parallel_tb.v) e `sim/layer_sim` (da layer_tb.v) con i relativi `.vcd`, per coerenza con la convenzione del repo di committare i binari di simulazione insieme alle sorgenti.
 - 2026-09-02T00:45 — [FASE 7] — Nessuna modifica a rtl/ in questa fase: root cause dei due fallimenti era esclusivamente nei testbench (riferimento a un parametro FRAC_BITS rimosso da tempo dall'RTL), non nel core di calcolo. Sessione di debug neuron_memory + fix dei due test residui considerata chiusa.
+
+## Fase: Roadmap Fase 2 — Parameter Sweep (2026-09-02)
+
+- 2026-09-02T01:00 — [FASE 8] — Utente: "passiamo a fase 1 (o successiva)". Chiarito (dopo scambio) che il riferimento è al roadmap ufficiale in docs/FPGA-NeuralNetwork-Engine.md (sezione 15, "Development Roadmap"), da seguire come percorso vincolante. Letta la roadmap: Fase 1 (Parametric Layer) risulta già completamente spuntata; Fase 2 (Parameter Sweep) non ancora affrontata: "Validate multiple combinations of N_INPUTS/N_NEURONS/PARALLEL, including configurations where the number of inputs is not an exact multiple of the parallelism."
+- 2026-09-02T01:02 — [FASE 8] — Letto rtl/mac8.v per intero: PARALLEL deve essere potenza di 2 (adder tree binario con $clog2(PARALLEL) livelli). Nessun vincolo esplicito che N_INPUTS sia multiplo di PARALLEL.
+- 2026-09-02T01:03 — [FASE 8] — Ri-analizzato rtl/neuron_parallel.v: `localparam GROUPS = N_INPUTS / PARALLEL;` è divisione INTERA. Ipotesi: se N_INPUTS non è multiplo esatto di PARALLEL, gli input residui (N_INPUTS - GROUPS*PARALLEL) non vengono mai letti dall'accumulatore (nessun errore/warning a compile o runtime). Ipotesi aggiuntiva: se PARALLEL > N_INPUTS, GROUPS=0 e la condizione di terminazione del controller (`group_index == GROUPS-1`) non è mai soddisfatta -> hang permanente (busy=1, done mai asserito).
+- 2026-09-02T01:10 — [FASE 8] — Creato sim/parameter_sweep_tb.v: 5 istanze di neuron_parallel con configurazioni diverse (CONFIG A..E), watchdog a ciclo (max 500 cicli, nessun `wait` bloccante) per evitare hang reale della simulazione anche nel caso patologico:
+  - A: N_INPUTS=32 PARALLEL=8 (esatto, sanity check, atteso y=32)
+  - B: N_INPUTS=30 PARALLEL=8 (non esatto, GROUPS=3, atteso y=24 per troncamento RTL vs somma piena=30)
+  - C: N_INPUTS=20 PARALLEL=16 (non esatto, GROUPS=1, atteso y=16 per troncamento RTL vs somma piena=20)
+  - D: N_INPUTS=64 PARALLEL=32 (esatto, sanity check, atteso y=64)
+  - E: N_INPUTS=4 PARALLEL=8 (degenere, GROUPS=0, atteso TIMEOUT/hang)
+- 2026-09-02T01:12 — [FASE 8] — Compilato: `iverilog -g2012 -o <tmp> rtl/*.v sim/parameter_sweep_tb.v`. Nessun errore (anche il part-select fuori range in CONFIG E, dovuto a x_bus/w_bus da 32 bit letti come blocchi da 64 bit dentro neuron_parallel, non causa errore di elaborazione in Icarus).
+- 2026-09-02T01:13 — [FASE 8] — Eseguito `vvp`. RISULTATI (tutti confermano le ipotesi):
+  - CONFIG A: PASS, y=32.
+  - CONFIG B: y=24 (non 30) -> confermato troncamento silenzioso, 6 input su 30 ignorati.
+  - CONFIG C: y=16 (non 20) -> confermato troncamento silenzioso, 4 input su 20 ignorati.
+  - CONFIG D: PASS, y=64.
+  - CONFIG E: TIMEOUT confermato -> done mai asserito entro 500 cicli, hang reale per PARALLEL > N_INPUTS (GROUPS=0).
+  - Sweep complessivo: errors=0 (nessun comportamento imprevisto rispetto alle ipotesi), findings=3 (troncamento non-multiplo x2, hang degenerato x1).
+- 2026-09-02T01:15 — [FASE 8] — Rigenerato artefatto tracciato sim/parameter_sweep_sim + sim/parameter_sweep.vcd per coerenza con la convenzione del repo.
+- 2026-09-02T01:16 — [FASE 8] — Nessuna modifica a rtl/neuron_parallel.v in questa fase (core di calcolo non toccato, come da policy di progetto). I due limiti trovati (troncamento su non-multiplo, hang su PARALLEL>N_INPUTS) sono documentati come "Findings" nella Fase 2 della roadmap (docs/FPGA-NeuralNetwork-Engine.md) e proposti come azione futura per Fase 3/7, non risolti ora.
+- 2026-09-02T01:18 — [FASE 8] — Aggiornato docs/FPGA-NeuralNetwork-Engine.md, sezione "## Phase 2 — Parameter Sweep": aggiunta checklist di completamento e sezione "Findings" con i due limiti documentati sopra.
diff --git a/docs/FPGA-NeuralNetwork-Engine.md b/docs/FPGA-NeuralNetwork-Engine.md
index 75f3121..68aaa96 100644
--- a/docs/FPGA-NeuralNetwork-Engine.md
+++ b/docs/FPGA-NeuralNetwork-Engine.md
@@ -595,6 +595,31 @@ PARALLEL
 
 including configurations where the number of inputs is not an exact multiple of the parallelism.
 
+- [x] Exact-multiple sanity configs (32×8, 64×32)
+- [x] Non-exact-multiple configs (30×8, 20×16)
+- [x] Degenerate config, PARALLEL > N_INPUTS (4×8)
+- [x] Sweep testbench: `sim/parameter_sweep_tb.v`
+
+**Findings (current RTL behavior, not yet fixed):**
+
+- `neuron_parallel.v` computes `GROUPS = N_INPUTS / PARALLEL` with
+  integer division. When `N_INPUTS` is **not** an exact multiple of
+  `PARALLEL`, only the first `GROUPS * PARALLEL` inputs are ever read
+  by the accumulator — the remainder is silently dropped (no error,
+  no warning). Confirmed for 30×8 → only 24 of 30 inputs summed, and
+  20×16 → only 16 of 20 inputs summed.
+- If `PARALLEL > N_INPUTS`, `GROUPS = 0` and the controller's
+  `group_index == GROUPS-1` terminal condition is never satisfied:
+  the neuron enters `busy` and never asserts `done` (confirmed hang,
+  500-cycle watchdog in the sweep bench). This is a design
+  constraint (`PARALLEL` must not exceed `N_INPUTS`, and should
+  divide it exactly) that is not currently guarded in RTL.
+- Action: either enforce `N_INPUTS % PARALLEL == 0` and
+  `PARALLEL <= N_INPUTS` at the caller/config level, or extend
+  `neuron_parallel.v` to handle a partial final group. Not addressed
+  in this phase — core datapath left untouched per current project
+  policy; tracked here for Phase 3/7.
+
 ## Phase 3 — Memory Architecture
 
 Define:
diff --git a/sim/parameter_sweep.vcd b/sim/parameter_sweep.vcd
new file mode 100644
index 0000000..b28cb2a
--- /dev/null
+++ b/sim/parameter_sweep.vcd
@@ -0,0 +1,18892 @@
+$date
+	Wed Sep  2 14:24:09 2026
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module tb $end
+$var wire 8 ! y_e [7:0] $end
+$var wire 8 " y_d [7:0] $end
+$var wire 8 # y_c [7:0] $end
+$var wire 8 $ y_b [7:0] $end
+$var wire 8 % y_a [7:0] $end
+$var wire 1 & done_e $end
+$var wire 1 ' done_d $end
+$var wire 1 ( done_c $end
+$var wire 1 ) done_b $end
+$var wire 1 * done_a $end
+$var wire 1 + busy_e $end
+$var wire 1 , busy_d $end
+$var wire 1 - busy_c $end
+$var wire 1 . busy_b $end
+$var wire 1 / busy_a $end
+$var parameter 32 0 A_ACC_WIDTH $end
+$var parameter 32 1 A_DATA_WIDTH $end
+$var parameter 32 2 A_N_INPUTS $end
+$var parameter 32 3 A_PARALLEL $end
+$var parameter 32 4 B_ACC_WIDTH $end
+$var parameter 32 5 B_DATA_WIDTH $end
+$var parameter 32 6 B_N_INPUTS $end
+$var parameter 32 7 B_PARALLEL $end
+$var parameter 32 8 C_ACC_WIDTH $end
+$var parameter 32 9 C_DATA_WIDTH $end
+$var parameter 32 : C_N_INPUTS $end
+$var parameter 32 ; C_PARALLEL $end
+$var parameter 32 < D_ACC_WIDTH $end
+$var parameter 32 = D_DATA_WIDTH $end
+$var parameter 32 > D_N_INPUTS $end
+$var parameter 32 ? D_PARALLEL $end
+$var parameter 32 @ E_ACC_WIDTH $end
+$var parameter 32 A E_DATA_WIDTH $end
+$var parameter 32 B E_N_INPUTS $end
+$var parameter 32 C E_PARALLEL $end
+$var reg 8 D bias_a [7:0] $end
+$var reg 8 E bias_b [7:0] $end
+$var reg 8 F bias_c [7:0] $end
+$var reg 8 G bias_d [7:0] $end
+$var reg 8 H bias_e [7:0] $end
+$var reg 1 I clk $end
+$var reg 1 J rst $end
+$var reg 1 K start_a $end
+$var reg 1 L start_b $end
+$var reg 1 M start_c $end
+$var reg 1 N start_d $end
+$var reg 1 O start_e $end
+$var reg 1 P timed_out $end
+$var reg 256 Q w_bus_a [255:0] $end
+$var reg 240 R w_bus_b [239:0] $end
+$var reg 160 S w_bus_c [159:0] $end
+$var reg 512 T w_bus_d [511:0] $end
+$var reg 32 U w_bus_e [31:0] $end
+$var reg 256 V x_bus_a [255:0] $end
+$var reg 240 W x_bus_b [239:0] $end
+$var reg 160 X x_bus_c [159:0] $end
+$var reg 512 Y x_bus_d [511:0] $end
+$var reg 32 Z x_bus_e [31:0] $end
+$var integer 32 [ count [31:0] $end
+$var integer 32 \ errors [31:0] $end
+$var integer 32 ] findings [31:0] $end
+$var integer 32 ^ max_cycles [31:0] $end
+$scope module u_a $end
+$var wire 8 _ bias [7:0] $end
+$var wire 1 I clk $end
+$var wire 1 J rst $end
+$var wire 1 K start $end
+$var wire 256 ` w_bus [255:0] $end
+$var wire 256 a x_bus [255:0] $end
+$var wire 64 b x_group [63:0] $end
+$var wire 64 c w_group [63:0] $end
+$var wire 32 d final_acc [31:0] $end
+$var wire 32 e bias_ext [31:0] $end
+$var wire 32 f acc_next [31:0] $end
+$var parameter 32 g ACC_WIDTH $end
+$var parameter 32 h DATA_WIDTH $end
+$var parameter 32 i GROUPS $end
+$var parameter 32 j GROUP_INDEX_WIDTH $end
+$var parameter 32 k N_INPUTS $end
+$var parameter 32 l PARALLEL $end
+$var reg 32 m acc [31:0] $end
+$var reg 1 / busy $end
+$var reg 1 * done $end
+$var reg 2 n group_index [1:0] $end
+$var reg 8 o y [7:0] $end
+$scope module u_mac8 $end
+$var wire 32 p acc_in [31:0] $end
+$var wire 64 q w_bus [63:0] $end
+$var wire 64 r x_bus [63:0] $end
+$var wire 32 s acc_out [31:0] $end
+$var parameter 32 t ACC_WIDTH $end
+$var parameter 32 u DATA_WIDTH $end
+$var parameter 32 v PARALLEL $end
+$var parameter 32 w TREE_LEVELS $end
+$scope begin GEN_MAC[0] $end
+$var parameter 2 x i $end
+$scope module u_mac $end
+$var wire 32 y acc_in [31:0] $end
+$var wire 8 z w [7:0] $end
+$var wire 8 { x [7:0] $end
+$var wire 32 | product_ext [31:0] $end
+$var wire 16 } product [15:0] $end
+$var wire 32 ~ acc_out [31:0] $end
+$var parameter 32 !" ACC_WIDTH $end
+$var parameter 32 "" DATA_WIDTH $end
+$var parameter 64 #" PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[1] $end
+$var parameter 2 $" i $end
+$scope module u_mac $end
+$var wire 32 %" acc_in [31:0] $end
+$var wire 8 &" w [7:0] $end
+$var wire 8 '" x [7:0] $end
+$var wire 32 (" product_ext [31:0] $end
+$var wire 16 )" product [15:0] $end
+$var wire 32 *" acc_out [31:0] $end
+$var parameter 32 +" ACC_WIDTH $end
+$var parameter 32 ," DATA_WIDTH $end
+$var parameter 64 -" PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[2] $end
+$var parameter 3 ." i $end
+$scope module u_mac $end
+$var wire 32 /" acc_in [31:0] $end
+$var wire 8 0" w [7:0] $end
+$var wire 8 1" x [7:0] $end
+$var wire 32 2" product_ext [31:0] $end
+$var wire 16 3" product [15:0] $end
+$var wire 32 4" acc_out [31:0] $end
+$var parameter 32 5" ACC_WIDTH $end
+$var parameter 32 6" DATA_WIDTH $end
+$var parameter 64 7" PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[3] $end
+$var parameter 3 8" i $end
+$scope module u_mac $end
+$var wire 32 9" acc_in [31:0] $end
+$var wire 8 :" w [7:0] $end
+$var wire 8 ;" x [7:0] $end
+$var wire 32 <" product_ext [31:0] $end
+$var wire 16 =" product [15:0] $end
+$var wire 32 >" acc_out [31:0] $end
+$var parameter 32 ?" ACC_WIDTH $end
+$var parameter 32 @" DATA_WIDTH $end
+$var parameter 64 A" PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[4] $end
+$var parameter 4 B" i $end
+$scope module u_mac $end
+$var wire 32 C" acc_in [31:0] $end
+$var wire 8 D" w [7:0] $end
+$var wire 8 E" x [7:0] $end
+$var wire 32 F" product_ext [31:0] $end
+$var wire 16 G" product [15:0] $end
+$var wire 32 H" acc_out [31:0] $end
+$var parameter 32 I" ACC_WIDTH $end
+$var parameter 32 J" DATA_WIDTH $end
+$var parameter 64 K" PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[5] $end
+$var parameter 4 L" i $end
+$scope module u_mac $end
+$var wire 32 M" acc_in [31:0] $end
+$var wire 8 N" w [7:0] $end
+$var wire 8 O" x [7:0] $end
+$var wire 32 P" product_ext [31:0] $end
+$var wire 16 Q" product [15:0] $end
+$var wire 32 R" acc_out [31:0] $end
+$var parameter 32 S" ACC_WIDTH $end
+$var parameter 32 T" DATA_WIDTH $end
+$var parameter 64 U" PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[6] $end
+$var parameter 4 V" i $end
+$scope module u_mac $end
+$var wire 32 W" acc_in [31:0] $end
+$var wire 8 X" w [7:0] $end
+$var wire 8 Y" x [7:0] $end
+$var wire 32 Z" product_ext [31:0] $end
+$var wire 16 [" product [15:0] $end
+$var wire 32 \" acc_out [31:0] $end
+$var parameter 32 ]" ACC_WIDTH $end
+$var parameter 32 ^" DATA_WIDTH $end
+$var parameter 64 _" PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[7] $end
+$var parameter 4 `" i $end
+$scope module u_mac $end
+$var wire 32 a" acc_in [31:0] $end
+$var wire 8 b" w [7:0] $end
+$var wire 8 c" x [7:0] $end
+$var wire 32 d" product_ext [31:0] $end
+$var wire 16 e" product [15:0] $end
+$var wire 32 f" acc_out [31:0] $end
+$var parameter 32 g" ACC_WIDTH $end
+$var parameter 32 h" DATA_WIDTH $end
+$var parameter 64 i" PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[0] $end
+$var parameter 2 j" i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[1] $end
+$var parameter 2 k" i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[2] $end
+$var parameter 3 l" i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[3] $end
+$var parameter 3 m" i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[4] $end
+$var parameter 4 n" i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[5] $end
+$var parameter 4 o" i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[6] $end
+$var parameter 4 p" i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[7] $end
+$var parameter 4 q" i $end
+$upscope $end
+$scope begin GEN_TREE_LEVEL[0] $end
+$var parameter 2 r" level $end
+$scope begin GEN_TREE_NODE[0] $end
+$var parameter 2 s" node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[1] $end
+$var parameter 2 t" node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[2] $end
+$var parameter 3 u" node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[3] $end
+$var parameter 3 v" node $end
+$upscope $end
+$upscope $end
+$scope begin GEN_TREE_LEVEL[1] $end
+$var parameter 2 w" level $end
+$scope begin GEN_TREE_NODE[0] $end
+$var parameter 2 x" node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[1] $end
+$var parameter 2 y" node $end
+$upscope $end
+$upscope $end
+$scope begin GEN_TREE_LEVEL[2] $end
+$var parameter 3 z" level $end
+$scope begin GEN_TREE_NODE[0] $end
+$var parameter 2 {" node $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope module u_b $end
+$var wire 8 |" bias [7:0] $end
+$var wire 1 I clk $end
+$var wire 1 J rst $end
+$var wire 1 L start $end
+$var wire 240 }" w_bus [239:0] $end
+$var wire 240 ~" x_bus [239:0] $end
+$var wire 64 !# x_group [63:0] $end
+$var wire 64 "# w_group [63:0] $end
+$var wire 32 ## final_acc [31:0] $end
+$var wire 32 $# bias_ext [31:0] $end
+$var wire 32 %# acc_next [31:0] $end
+$var parameter 32 &# ACC_WIDTH $end
+$var parameter 32 '# DATA_WIDTH $end
+$var parameter 32 (# GROUPS $end
+$var parameter 32 )# GROUP_INDEX_WIDTH $end
+$var parameter 32 *# N_INPUTS $end
+$var parameter 32 +# PARALLEL $end
+$var reg 32 ,# acc [31:0] $end
+$var reg 1 . busy $end
+$var reg 1 ) done $end
+$var reg 2 -# group_index [1:0] $end
+$var reg 8 .# y [7:0] $end
+$scope module u_mac8 $end
+$var wire 32 /# acc_in [31:0] $end
+$var wire 64 0# w_bus [63:0] $end
+$var wire 64 1# x_bus [63:0] $end
+$var wire 32 2# acc_out [31:0] $end
+$var parameter 32 3# ACC_WIDTH $end
+$var parameter 32 4# DATA_WIDTH $end
+$var parameter 32 5# PARALLEL $end
+$var parameter 32 6# TREE_LEVELS $end
+$scope begin GEN_MAC[0] $end
+$var parameter 2 7# i $end
+$scope module u_mac $end
+$var wire 32 8# acc_in [31:0] $end
+$var wire 8 9# w [7:0] $end
+$var wire 8 :# x [7:0] $end
+$var wire 32 ;# product_ext [31:0] $end
+$var wire 16 <# product [15:0] $end
+$var wire 32 =# acc_out [31:0] $end
+$var parameter 32 ># ACC_WIDTH $end
+$var parameter 32 ?# DATA_WIDTH $end
+$var parameter 64 @# PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[1] $end
+$var parameter 2 A# i $end
+$scope module u_mac $end
+$var wire 32 B# acc_in [31:0] $end
+$var wire 8 C# w [7:0] $end
+$var wire 8 D# x [7:0] $end
+$var wire 32 E# product_ext [31:0] $end
+$var wire 16 F# product [15:0] $end
+$var wire 32 G# acc_out [31:0] $end
+$var parameter 32 H# ACC_WIDTH $end
+$var parameter 32 I# DATA_WIDTH $end
+$var parameter 64 J# PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[2] $end
+$var parameter 3 K# i $end
+$scope module u_mac $end
+$var wire 32 L# acc_in [31:0] $end
+$var wire 8 M# w [7:0] $end
+$var wire 8 N# x [7:0] $end
+$var wire 32 O# product_ext [31:0] $end
+$var wire 16 P# product [15:0] $end
+$var wire 32 Q# acc_out [31:0] $end
+$var parameter 32 R# ACC_WIDTH $end
+$var parameter 32 S# DATA_WIDTH $end
+$var parameter 64 T# PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[3] $end
+$var parameter 3 U# i $end
+$scope module u_mac $end
+$var wire 32 V# acc_in [31:0] $end
+$var wire 8 W# w [7:0] $end
+$var wire 8 X# x [7:0] $end
+$var wire 32 Y# product_ext [31:0] $end
+$var wire 16 Z# product [15:0] $end
+$var wire 32 [# acc_out [31:0] $end
+$var parameter 32 \# ACC_WIDTH $end
+$var parameter 32 ]# DATA_WIDTH $end
+$var parameter 64 ^# PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[4] $end
+$var parameter 4 _# i $end
+$scope module u_mac $end
+$var wire 32 `# acc_in [31:0] $end
+$var wire 8 a# w [7:0] $end
+$var wire 8 b# x [7:0] $end
+$var wire 32 c# product_ext [31:0] $end
+$var wire 16 d# product [15:0] $end
+$var wire 32 e# acc_out [31:0] $end
+$var parameter 32 f# ACC_WIDTH $end
+$var parameter 32 g# DATA_WIDTH $end
+$var parameter 64 h# PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[5] $end
+$var parameter 4 i# i $end
+$scope module u_mac $end
+$var wire 32 j# acc_in [31:0] $end
+$var wire 8 k# w [7:0] $end
+$var wire 8 l# x [7:0] $end
+$var wire 32 m# product_ext [31:0] $end
+$var wire 16 n# product [15:0] $end
+$var wire 32 o# acc_out [31:0] $end
+$var parameter 32 p# ACC_WIDTH $end
+$var parameter 32 q# DATA_WIDTH $end
+$var parameter 64 r# PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[6] $end
+$var parameter 4 s# i $end
+$scope module u_mac $end
+$var wire 32 t# acc_in [31:0] $end
+$var wire 8 u# w [7:0] $end
+$var wire 8 v# x [7:0] $end
+$var wire 32 w# product_ext [31:0] $end
+$var wire 16 x# product [15:0] $end
+$var wire 32 y# acc_out [31:0] $end
+$var parameter 32 z# ACC_WIDTH $end
+$var parameter 32 {# DATA_WIDTH $end
+$var parameter 64 |# PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[7] $end
+$var parameter 4 }# i $end
+$scope module u_mac $end
+$var wire 32 ~# acc_in [31:0] $end
+$var wire 8 !$ w [7:0] $end
+$var wire 8 "$ x [7:0] $end
+$var wire 32 #$ product_ext [31:0] $end
+$var wire 16 $$ product [15:0] $end
+$var wire 32 %$ acc_out [31:0] $end
+$var parameter 32 &$ ACC_WIDTH $end
+$var parameter 32 '$ DATA_WIDTH $end
+$var parameter 64 ($ PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[0] $end
+$var parameter 2 )$ i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[1] $end
+$var parameter 2 *$ i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[2] $end
+$var parameter 3 +$ i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[3] $end
+$var parameter 3 ,$ i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[4] $end
+$var parameter 4 -$ i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[5] $end
+$var parameter 4 .$ i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[6] $end
+$var parameter 4 /$ i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[7] $end
+$var parameter 4 0$ i $end
+$upscope $end
+$scope begin GEN_TREE_LEVEL[0] $end
+$var parameter 2 1$ level $end
+$scope begin GEN_TREE_NODE[0] $end
+$var parameter 2 2$ node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[1] $end
+$var parameter 2 3$ node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[2] $end
+$var parameter 3 4$ node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[3] $end
+$var parameter 3 5$ node $end
+$upscope $end
+$upscope $end
+$scope begin GEN_TREE_LEVEL[1] $end
+$var parameter 2 6$ level $end
+$scope begin GEN_TREE_NODE[0] $end
+$var parameter 2 7$ node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[1] $end
+$var parameter 2 8$ node $end
+$upscope $end
+$upscope $end
+$scope begin GEN_TREE_LEVEL[2] $end
+$var parameter 3 9$ level $end
+$scope begin GEN_TREE_NODE[0] $end
+$var parameter 2 :$ node $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope module u_c $end
+$var wire 8 ;$ bias [7:0] $end
+$var wire 1 I clk $end
+$var wire 1 J rst $end
+$var wire 1 M start $end
+$var wire 160 <$ w_bus [159:0] $end
+$var wire 160 =$ x_bus [159:0] $end
+$var wire 128 >$ x_group [127:0] $end
+$var wire 128 ?$ w_group [127:0] $end
+$var wire 32 @$ final_acc [31:0] $end
+$var wire 32 A$ bias_ext [31:0] $end
+$var wire 32 B$ acc_next [31:0] $end
+$var parameter 32 C$ ACC_WIDTH $end
+$var parameter 32 D$ DATA_WIDTH $end
+$var parameter 32 E$ GROUPS $end
+$var parameter 32 F$ GROUP_INDEX_WIDTH $end
+$var parameter 32 G$ N_INPUTS $end
+$var parameter 32 H$ PARALLEL $end
+$var reg 32 I$ acc [31:0] $end
+$var reg 1 - busy $end
+$var reg 1 ( done $end
+$var reg 1 J$ group_index $end
+$var reg 8 K$ y [7:0] $end
+$scope module u_mac8 $end
+$var wire 32 L$ acc_in [31:0] $end
+$var wire 128 M$ w_bus [127:0] $end
+$var wire 128 N$ x_bus [127:0] $end
+$var wire 32 O$ acc_out [31:0] $end
+$var parameter 32 P$ ACC_WIDTH $end
+$var parameter 32 Q$ DATA_WIDTH $end
+$var parameter 32 R$ PARALLEL $end
+$var parameter 32 S$ TREE_LEVELS $end
+$scope begin GEN_MAC[0] $end
+$var parameter 2 T$ i $end
+$scope module u_mac $end
+$var wire 32 U$ acc_in [31:0] $end
+$var wire 8 V$ w [7:0] $end
+$var wire 8 W$ x [7:0] $end
+$var wire 32 X$ product_ext [31:0] $end
+$var wire 16 Y$ product [15:0] $end
+$var wire 32 Z$ acc_out [31:0] $end
+$var parameter 32 [$ ACC_WIDTH $end
+$var parameter 32 \$ DATA_WIDTH $end
+$var parameter 64 ]$ PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[1] $end
+$var parameter 2 ^$ i $end
+$scope module u_mac $end
+$var wire 32 _$ acc_in [31:0] $end
+$var wire 8 `$ w [7:0] $end
+$var wire 8 a$ x [7:0] $end
+$var wire 32 b$ product_ext [31:0] $end
+$var wire 16 c$ product [15:0] $end
+$var wire 32 d$ acc_out [31:0] $end
+$var parameter 32 e$ ACC_WIDTH $end
+$var parameter 32 f$ DATA_WIDTH $end
+$var parameter 64 g$ PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[2] $end
+$var parameter 3 h$ i $end
+$scope module u_mac $end
+$var wire 32 i$ acc_in [31:0] $end
+$var wire 8 j$ w [7:0] $end
+$var wire 8 k$ x [7:0] $end
+$var wire 32 l$ product_ext [31:0] $end
+$var wire 16 m$ product [15:0] $end
+$var wire 32 n$ acc_out [31:0] $end
+$var parameter 32 o$ ACC_WIDTH $end
+$var parameter 32 p$ DATA_WIDTH $end
+$var parameter 64 q$ PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[3] $end
+$var parameter 3 r$ i $end
+$scope module u_mac $end
+$var wire 32 s$ acc_in [31:0] $end
+$var wire 8 t$ w [7:0] $end
+$var wire 8 u$ x [7:0] $end
+$var wire 32 v$ product_ext [31:0] $end
+$var wire 16 w$ product [15:0] $end
+$var wire 32 x$ acc_out [31:0] $end
+$var parameter 32 y$ ACC_WIDTH $end
+$var parameter 32 z$ DATA_WIDTH $end
+$var parameter 64 {$ PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[4] $end
+$var parameter 4 |$ i $end
+$scope module u_mac $end
+$var wire 32 }$ acc_in [31:0] $end
+$var wire 8 ~$ w [7:0] $end
+$var wire 8 !% x [7:0] $end
+$var wire 32 "% product_ext [31:0] $end
+$var wire 16 #% product [15:0] $end
+$var wire 32 $% acc_out [31:0] $end
+$var parameter 32 %% ACC_WIDTH $end
+$var parameter 32 &% DATA_WIDTH $end
+$var parameter 64 '% PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[5] $end
+$var parameter 4 (% i $end
+$scope module u_mac $end
+$var wire 32 )% acc_in [31:0] $end
+$var wire 8 *% w [7:0] $end
+$var wire 8 +% x [7:0] $end
+$var wire 32 ,% product_ext [31:0] $end
+$var wire 16 -% product [15:0] $end
+$var wire 32 .% acc_out [31:0] $end
+$var parameter 32 /% ACC_WIDTH $end
+$var parameter 32 0% DATA_WIDTH $end
+$var parameter 64 1% PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[6] $end
+$var parameter 4 2% i $end
+$scope module u_mac $end
+$var wire 32 3% acc_in [31:0] $end
+$var wire 8 4% w [7:0] $end
+$var wire 8 5% x [7:0] $end
+$var wire 32 6% product_ext [31:0] $end
+$var wire 16 7% product [15:0] $end
+$var wire 32 8% acc_out [31:0] $end
+$var parameter 32 9% ACC_WIDTH $end
+$var parameter 32 :% DATA_WIDTH $end
+$var parameter 64 ;% PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[7] $end
+$var parameter 4 <% i $end
+$scope module u_mac $end
+$var wire 32 =% acc_in [31:0] $end
+$var wire 8 >% w [7:0] $end
+$var wire 8 ?% x [7:0] $end
+$var wire 32 @% product_ext [31:0] $end
+$var wire 16 A% product [15:0] $end
+$var wire 32 B% acc_out [31:0] $end
+$var parameter 32 C% ACC_WIDTH $end
+$var parameter 32 D% DATA_WIDTH $end
+$var parameter 64 E% PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[8] $end
+$var parameter 5 F% i $end
+$scope module u_mac $end
+$var wire 32 G% acc_in [31:0] $end
+$var wire 8 H% w [7:0] $end
+$var wire 8 I% x [7:0] $end
+$var wire 32 J% product_ext [31:0] $end
+$var wire 16 K% product [15:0] $end
+$var wire 32 L% acc_out [31:0] $end
+$var parameter 32 M% ACC_WIDTH $end
+$var parameter 32 N% DATA_WIDTH $end
+$var parameter 64 O% PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[9] $end
+$var parameter 5 P% i $end
+$scope module u_mac $end
+$var wire 32 Q% acc_in [31:0] $end
+$var wire 8 R% w [7:0] $end
+$var wire 8 S% x [7:0] $end
+$var wire 32 T% product_ext [31:0] $end
+$var wire 16 U% product [15:0] $end
+$var wire 32 V% acc_out [31:0] $end
+$var parameter 32 W% ACC_WIDTH $end
+$var parameter 32 X% DATA_WIDTH $end
+$var parameter 64 Y% PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[10] $end
+$var parameter 5 Z% i $end
+$scope module u_mac $end
+$var wire 32 [% acc_in [31:0] $end
+$var wire 8 \% w [7:0] $end
+$var wire 8 ]% x [7:0] $end
+$var wire 32 ^% product_ext [31:0] $end
+$var wire 16 _% product [15:0] $end
+$var wire 32 `% acc_out [31:0] $end
+$var parameter 32 a% ACC_WIDTH $end
+$var parameter 32 b% DATA_WIDTH $end
+$var parameter 64 c% PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[11] $end
+$var parameter 5 d% i $end
+$scope module u_mac $end
+$var wire 32 e% acc_in [31:0] $end
+$var wire 8 f% w [7:0] $end
+$var wire 8 g% x [7:0] $end
+$var wire 32 h% product_ext [31:0] $end
+$var wire 16 i% product [15:0] $end
+$var wire 32 j% acc_out [31:0] $end
+$var parameter 32 k% ACC_WIDTH $end
+$var parameter 32 l% DATA_WIDTH $end
+$var parameter 64 m% PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[12] $end
+$var parameter 5 n% i $end
+$scope module u_mac $end
+$var wire 32 o% acc_in [31:0] $end
+$var wire 8 p% w [7:0] $end
+$var wire 8 q% x [7:0] $end
+$var wire 32 r% product_ext [31:0] $end
+$var wire 16 s% product [15:0] $end
+$var wire 32 t% acc_out [31:0] $end
+$var parameter 32 u% ACC_WIDTH $end
+$var parameter 32 v% DATA_WIDTH $end
+$var parameter 64 w% PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[13] $end
+$var parameter 5 x% i $end
+$scope module u_mac $end
+$var wire 32 y% acc_in [31:0] $end
+$var wire 8 z% w [7:0] $end
+$var wire 8 {% x [7:0] $end
+$var wire 32 |% product_ext [31:0] $end
+$var wire 16 }% product [15:0] $end
+$var wire 32 ~% acc_out [31:0] $end
+$var parameter 32 !& ACC_WIDTH $end
+$var parameter 32 "& DATA_WIDTH $end
+$var parameter 64 #& PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[14] $end
+$var parameter 5 $& i $end
+$scope module u_mac $end
+$var wire 32 %& acc_in [31:0] $end
+$var wire 8 && w [7:0] $end
+$var wire 8 '& x [7:0] $end
+$var wire 32 (& product_ext [31:0] $end
+$var wire 16 )& product [15:0] $end
+$var wire 32 *& acc_out [31:0] $end
+$var parameter 32 +& ACC_WIDTH $end
+$var parameter 32 ,& DATA_WIDTH $end
+$var parameter 64 -& PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[15] $end
+$var parameter 5 .& i $end
+$scope module u_mac $end
+$var wire 32 /& acc_in [31:0] $end
+$var wire 8 0& w [7:0] $end
+$var wire 8 1& x [7:0] $end
+$var wire 32 2& product_ext [31:0] $end
+$var wire 16 3& product [15:0] $end
+$var wire 32 4& acc_out [31:0] $end
+$var parameter 32 5& ACC_WIDTH $end
+$var parameter 32 6& DATA_WIDTH $end
+$var parameter 64 7& PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[0] $end
+$var parameter 2 8& i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[1] $end
+$var parameter 2 9& i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[2] $end
+$var parameter 3 :& i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[3] $end
+$var parameter 3 ;& i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[4] $end
+$var parameter 4 <& i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[5] $end
+$var parameter 4 =& i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[6] $end
+$var parameter 4 >& i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[7] $end
+$var parameter 4 ?& i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[8] $end
+$var parameter 5 @& i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[9] $end
+$var parameter 5 A& i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[10] $end
+$var parameter 5 B& i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[11] $end
+$var parameter 5 C& i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[12] $end
+$var parameter 5 D& i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[13] $end
+$var parameter 5 E& i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[14] $end
+$var parameter 5 F& i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[15] $end
+$var parameter 5 G& i $end
+$upscope $end
+$scope begin GEN_TREE_LEVEL[0] $end
+$var parameter 2 H& level $end
+$scope begin GEN_TREE_NODE[0] $end
+$var parameter 2 I& node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[1] $end
+$var parameter 2 J& node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[2] $end
+$var parameter 3 K& node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[3] $end
+$var parameter 3 L& node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[4] $end
+$var parameter 4 M& node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[5] $end
+$var parameter 4 N& node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[6] $end
+$var parameter 4 O& node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[7] $end
+$var parameter 4 P& node $end
+$upscope $end
+$upscope $end
+$scope begin GEN_TREE_LEVEL[1] $end
+$var parameter 2 Q& level $end
+$scope begin GEN_TREE_NODE[0] $end
+$var parameter 2 R& node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[1] $end
+$var parameter 2 S& node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[2] $end
+$var parameter 3 T& node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[3] $end
+$var parameter 3 U& node $end
+$upscope $end
+$upscope $end
+$scope begin GEN_TREE_LEVEL[2] $end
+$var parameter 3 V& level $end
+$scope begin GEN_TREE_NODE[0] $end
+$var parameter 2 W& node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[1] $end
+$var parameter 2 X& node $end
+$upscope $end
+$upscope $end
+$scope begin GEN_TREE_LEVEL[3] $end
+$var parameter 3 Y& level $end
+$scope begin GEN_TREE_NODE[0] $end
+$var parameter 2 Z& node $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope module u_d $end
+$var wire 8 [& bias [7:0] $end
+$var wire 1 I clk $end
+$var wire 1 J rst $end
+$var wire 1 N start $end
+$var wire 512 \& w_bus [511:0] $end
+$var wire 512 ]& x_bus [511:0] $end
+$var wire 256 ^& x_group [255:0] $end
+$var wire 256 _& w_group [255:0] $end
+$var wire 32 `& final_acc [31:0] $end
+$var wire 32 a& bias_ext [31:0] $end
+$var wire 32 b& acc_next [31:0] $end
+$var parameter 32 c& ACC_WIDTH $end
+$var parameter 32 d& DATA_WIDTH $end
+$var parameter 32 e& GROUPS $end
+$var parameter 32 f& GROUP_INDEX_WIDTH $end
+$var parameter 32 g& N_INPUTS $end
+$var parameter 32 h& PARALLEL $end
+$var reg 32 i& acc [31:0] $end
+$var reg 1 , busy $end
+$var reg 1 ' done $end
+$var reg 1 j& group_index $end
+$var reg 8 k& y [7:0] $end
+$scope module u_mac8 $end
+$var wire 32 l& acc_in [31:0] $end
+$var wire 256 m& w_bus [255:0] $end
+$var wire 256 n& x_bus [255:0] $end
+$var wire 32 o& acc_out [31:0] $end
+$var parameter 32 p& ACC_WIDTH $end
+$var parameter 32 q& DATA_WIDTH $end
+$var parameter 32 r& PARALLEL $end
+$var parameter 32 s& TREE_LEVELS $end
+$scope begin GEN_MAC[0] $end
+$var parameter 2 t& i $end
+$scope module u_mac $end
+$var wire 32 u& acc_in [31:0] $end
+$var wire 8 v& w [7:0] $end
+$var wire 8 w& x [7:0] $end
+$var wire 32 x& product_ext [31:0] $end
+$var wire 16 y& product [15:0] $end
+$var wire 32 z& acc_out [31:0] $end
+$var parameter 32 {& ACC_WIDTH $end
+$var parameter 32 |& DATA_WIDTH $end
+$var parameter 64 }& PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[1] $end
+$var parameter 2 ~& i $end
+$scope module u_mac $end
+$var wire 32 !' acc_in [31:0] $end
+$var wire 8 "' w [7:0] $end
+$var wire 8 #' x [7:0] $end
+$var wire 32 $' product_ext [31:0] $end
+$var wire 16 %' product [15:0] $end
+$var wire 32 &' acc_out [31:0] $end
+$var parameter 32 '' ACC_WIDTH $end
+$var parameter 32 (' DATA_WIDTH $end
+$var parameter 64 )' PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[2] $end
+$var parameter 3 *' i $end
+$scope module u_mac $end
+$var wire 32 +' acc_in [31:0] $end
+$var wire 8 ,' w [7:0] $end
+$var wire 8 -' x [7:0] $end
+$var wire 32 .' product_ext [31:0] $end
+$var wire 16 /' product [15:0] $end
+$var wire 32 0' acc_out [31:0] $end
+$var parameter 32 1' ACC_WIDTH $end
+$var parameter 32 2' DATA_WIDTH $end
+$var parameter 64 3' PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[3] $end
+$var parameter 3 4' i $end
+$scope module u_mac $end
+$var wire 32 5' acc_in [31:0] $end
+$var wire 8 6' w [7:0] $end
+$var wire 8 7' x [7:0] $end
+$var wire 32 8' product_ext [31:0] $end
+$var wire 16 9' product [15:0] $end
+$var wire 32 :' acc_out [31:0] $end
+$var parameter 32 ;' ACC_WIDTH $end
+$var parameter 32 <' DATA_WIDTH $end
+$var parameter 64 =' PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[4] $end
+$var parameter 4 >' i $end
+$scope module u_mac $end
+$var wire 32 ?' acc_in [31:0] $end
+$var wire 8 @' w [7:0] $end
+$var wire 8 A' x [7:0] $end
+$var wire 32 B' product_ext [31:0] $end
+$var wire 16 C' product [15:0] $end
+$var wire 32 D' acc_out [31:0] $end
+$var parameter 32 E' ACC_WIDTH $end
+$var parameter 32 F' DATA_WIDTH $end
+$var parameter 64 G' PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[5] $end
+$var parameter 4 H' i $end
+$scope module u_mac $end
+$var wire 32 I' acc_in [31:0] $end
+$var wire 8 J' w [7:0] $end
+$var wire 8 K' x [7:0] $end
+$var wire 32 L' product_ext [31:0] $end
+$var wire 16 M' product [15:0] $end
+$var wire 32 N' acc_out [31:0] $end
+$var parameter 32 O' ACC_WIDTH $end
+$var parameter 32 P' DATA_WIDTH $end
+$var parameter 64 Q' PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[6] $end
+$var parameter 4 R' i $end
+$scope module u_mac $end
+$var wire 32 S' acc_in [31:0] $end
+$var wire 8 T' w [7:0] $end
+$var wire 8 U' x [7:0] $end
+$var wire 32 V' product_ext [31:0] $end
+$var wire 16 W' product [15:0] $end
+$var wire 32 X' acc_out [31:0] $end
+$var parameter 32 Y' ACC_WIDTH $end
+$var parameter 32 Z' DATA_WIDTH $end
+$var parameter 64 [' PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[7] $end
+$var parameter 4 \' i $end
+$scope module u_mac $end
+$var wire 32 ]' acc_in [31:0] $end
+$var wire 8 ^' w [7:0] $end
+$var wire 8 _' x [7:0] $end
+$var wire 32 `' product_ext [31:0] $end
+$var wire 16 a' product [15:0] $end
+$var wire 32 b' acc_out [31:0] $end
+$var parameter 32 c' ACC_WIDTH $end
+$var parameter 32 d' DATA_WIDTH $end
+$var parameter 64 e' PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[8] $end
+$var parameter 5 f' i $end
+$scope module u_mac $end
+$var wire 32 g' acc_in [31:0] $end
+$var wire 8 h' w [7:0] $end
+$var wire 8 i' x [7:0] $end
+$var wire 32 j' product_ext [31:0] $end
+$var wire 16 k' product [15:0] $end
+$var wire 32 l' acc_out [31:0] $end
+$var parameter 32 m' ACC_WIDTH $end
+$var parameter 32 n' DATA_WIDTH $end
+$var parameter 64 o' PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[9] $end
+$var parameter 5 p' i $end
+$scope module u_mac $end
+$var wire 32 q' acc_in [31:0] $end
+$var wire 8 r' w [7:0] $end
+$var wire 8 s' x [7:0] $end
+$var wire 32 t' product_ext [31:0] $end
+$var wire 16 u' product [15:0] $end
+$var wire 32 v' acc_out [31:0] $end
+$var parameter 32 w' ACC_WIDTH $end
+$var parameter 32 x' DATA_WIDTH $end
+$var parameter 64 y' PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[10] $end
+$var parameter 5 z' i $end
+$scope module u_mac $end
+$var wire 32 {' acc_in [31:0] $end
+$var wire 8 |' w [7:0] $end
+$var wire 8 }' x [7:0] $end
+$var wire 32 ~' product_ext [31:0] $end
+$var wire 16 !( product [15:0] $end
+$var wire 32 "( acc_out [31:0] $end
+$var parameter 32 #( ACC_WIDTH $end
+$var parameter 32 $( DATA_WIDTH $end
+$var parameter 64 %( PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[11] $end
+$var parameter 5 &( i $end
+$scope module u_mac $end
+$var wire 32 '( acc_in [31:0] $end
+$var wire 8 (( w [7:0] $end
+$var wire 8 )( x [7:0] $end
+$var wire 32 *( product_ext [31:0] $end
+$var wire 16 +( product [15:0] $end
+$var wire 32 ,( acc_out [31:0] $end
+$var parameter 32 -( ACC_WIDTH $end
+$var parameter 32 .( DATA_WIDTH $end
+$var parameter 64 /( PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[12] $end
+$var parameter 5 0( i $end
+$scope module u_mac $end
+$var wire 32 1( acc_in [31:0] $end
+$var wire 8 2( w [7:0] $end
+$var wire 8 3( x [7:0] $end
+$var wire 32 4( product_ext [31:0] $end
+$var wire 16 5( product [15:0] $end
+$var wire 32 6( acc_out [31:0] $end
+$var parameter 32 7( ACC_WIDTH $end
+$var parameter 32 8( DATA_WIDTH $end
+$var parameter 64 9( PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[13] $end
+$var parameter 5 :( i $end
+$scope module u_mac $end
+$var wire 32 ;( acc_in [31:0] $end
+$var wire 8 <( w [7:0] $end
+$var wire 8 =( x [7:0] $end
+$var wire 32 >( product_ext [31:0] $end
+$var wire 16 ?( product [15:0] $end
+$var wire 32 @( acc_out [31:0] $end
+$var parameter 32 A( ACC_WIDTH $end
+$var parameter 32 B( DATA_WIDTH $end
+$var parameter 64 C( PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[14] $end
+$var parameter 5 D( i $end
+$scope module u_mac $end
+$var wire 32 E( acc_in [31:0] $end
+$var wire 8 F( w [7:0] $end
+$var wire 8 G( x [7:0] $end
+$var wire 32 H( product_ext [31:0] $end
+$var wire 16 I( product [15:0] $end
+$var wire 32 J( acc_out [31:0] $end
+$var parameter 32 K( ACC_WIDTH $end
+$var parameter 32 L( DATA_WIDTH $end
+$var parameter 64 M( PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[15] $end
+$var parameter 5 N( i $end
+$scope module u_mac $end
+$var wire 32 O( acc_in [31:0] $end
+$var wire 8 P( w [7:0] $end
+$var wire 8 Q( x [7:0] $end
+$var wire 32 R( product_ext [31:0] $end
+$var wire 16 S( product [15:0] $end
+$var wire 32 T( acc_out [31:0] $end
+$var parameter 32 U( ACC_WIDTH $end
+$var parameter 32 V( DATA_WIDTH $end
+$var parameter 64 W( PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[16] $end
+$var parameter 6 X( i $end
+$scope module u_mac $end
+$var wire 32 Y( acc_in [31:0] $end
+$var wire 8 Z( w [7:0] $end
+$var wire 8 [( x [7:0] $end
+$var wire 32 \( product_ext [31:0] $end
+$var wire 16 ]( product [15:0] $end
+$var wire 32 ^( acc_out [31:0] $end
+$var parameter 32 _( ACC_WIDTH $end
+$var parameter 32 `( DATA_WIDTH $end
+$var parameter 64 a( PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[17] $end
+$var parameter 6 b( i $end
+$scope module u_mac $end
+$var wire 32 c( acc_in [31:0] $end
+$var wire 8 d( w [7:0] $end
+$var wire 8 e( x [7:0] $end
+$var wire 32 f( product_ext [31:0] $end
+$var wire 16 g( product [15:0] $end
+$var wire 32 h( acc_out [31:0] $end
+$var parameter 32 i( ACC_WIDTH $end
+$var parameter 32 j( DATA_WIDTH $end
+$var parameter 64 k( PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[18] $end
+$var parameter 6 l( i $end
+$scope module u_mac $end
+$var wire 32 m( acc_in [31:0] $end
+$var wire 8 n( w [7:0] $end
+$var wire 8 o( x [7:0] $end
+$var wire 32 p( product_ext [31:0] $end
+$var wire 16 q( product [15:0] $end
+$var wire 32 r( acc_out [31:0] $end
+$var parameter 32 s( ACC_WIDTH $end
+$var parameter 32 t( DATA_WIDTH $end
+$var parameter 64 u( PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[19] $end
+$var parameter 6 v( i $end
+$scope module u_mac $end
+$var wire 32 w( acc_in [31:0] $end
+$var wire 8 x( w [7:0] $end
+$var wire 8 y( x [7:0] $end
+$var wire 32 z( product_ext [31:0] $end
+$var wire 16 {( product [15:0] $end
+$var wire 32 |( acc_out [31:0] $end
+$var parameter 32 }( ACC_WIDTH $end
+$var parameter 32 ~( DATA_WIDTH $end
+$var parameter 64 !) PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[20] $end
+$var parameter 6 ") i $end
+$scope module u_mac $end
+$var wire 32 #) acc_in [31:0] $end
+$var wire 8 $) w [7:0] $end
+$var wire 8 %) x [7:0] $end
+$var wire 32 &) product_ext [31:0] $end
+$var wire 16 ') product [15:0] $end
+$var wire 32 () acc_out [31:0] $end
+$var parameter 32 )) ACC_WIDTH $end
+$var parameter 32 *) DATA_WIDTH $end
+$var parameter 64 +) PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[21] $end
+$var parameter 6 ,) i $end
+$scope module u_mac $end
+$var wire 32 -) acc_in [31:0] $end
+$var wire 8 .) w [7:0] $end
+$var wire 8 /) x [7:0] $end
+$var wire 32 0) product_ext [31:0] $end
+$var wire 16 1) product [15:0] $end
+$var wire 32 2) acc_out [31:0] $end
+$var parameter 32 3) ACC_WIDTH $end
+$var parameter 32 4) DATA_WIDTH $end
+$var parameter 64 5) PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[22] $end
+$var parameter 6 6) i $end
+$scope module u_mac $end
+$var wire 32 7) acc_in [31:0] $end
+$var wire 8 8) w [7:0] $end
+$var wire 8 9) x [7:0] $end
+$var wire 32 :) product_ext [31:0] $end
+$var wire 16 ;) product [15:0] $end
+$var wire 32 <) acc_out [31:0] $end
+$var parameter 32 =) ACC_WIDTH $end
+$var parameter 32 >) DATA_WIDTH $end
+$var parameter 64 ?) PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[23] $end
+$var parameter 6 @) i $end
+$scope module u_mac $end
+$var wire 32 A) acc_in [31:0] $end
+$var wire 8 B) w [7:0] $end
+$var wire 8 C) x [7:0] $end
+$var wire 32 D) product_ext [31:0] $end
+$var wire 16 E) product [15:0] $end
+$var wire 32 F) acc_out [31:0] $end
+$var parameter 32 G) ACC_WIDTH $end
+$var parameter 32 H) DATA_WIDTH $end
+$var parameter 64 I) PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[24] $end
+$var parameter 6 J) i $end
+$scope module u_mac $end
+$var wire 32 K) acc_in [31:0] $end
+$var wire 8 L) w [7:0] $end
+$var wire 8 M) x [7:0] $end
+$var wire 32 N) product_ext [31:0] $end
+$var wire 16 O) product [15:0] $end
+$var wire 32 P) acc_out [31:0] $end
+$var parameter 32 Q) ACC_WIDTH $end
+$var parameter 32 R) DATA_WIDTH $end
+$var parameter 64 S) PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[25] $end
+$var parameter 6 T) i $end
+$scope module u_mac $end
+$var wire 32 U) acc_in [31:0] $end
+$var wire 8 V) w [7:0] $end
+$var wire 8 W) x [7:0] $end
+$var wire 32 X) product_ext [31:0] $end
+$var wire 16 Y) product [15:0] $end
+$var wire 32 Z) acc_out [31:0] $end
+$var parameter 32 [) ACC_WIDTH $end
+$var parameter 32 \) DATA_WIDTH $end
+$var parameter 64 ]) PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[26] $end
+$var parameter 6 ^) i $end
+$scope module u_mac $end
+$var wire 32 _) acc_in [31:0] $end
+$var wire 8 `) w [7:0] $end
+$var wire 8 a) x [7:0] $end
+$var wire 32 b) product_ext [31:0] $end
+$var wire 16 c) product [15:0] $end
+$var wire 32 d) acc_out [31:0] $end
+$var parameter 32 e) ACC_WIDTH $end
+$var parameter 32 f) DATA_WIDTH $end
+$var parameter 64 g) PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[27] $end
+$var parameter 6 h) i $end
+$scope module u_mac $end
+$var wire 32 i) acc_in [31:0] $end
+$var wire 8 j) w [7:0] $end
+$var wire 8 k) x [7:0] $end
+$var wire 32 l) product_ext [31:0] $end
+$var wire 16 m) product [15:0] $end
+$var wire 32 n) acc_out [31:0] $end
+$var parameter 32 o) ACC_WIDTH $end
+$var parameter 32 p) DATA_WIDTH $end
+$var parameter 64 q) PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[28] $end
+$var parameter 6 r) i $end
+$scope module u_mac $end
+$var wire 32 s) acc_in [31:0] $end
+$var wire 8 t) w [7:0] $end
+$var wire 8 u) x [7:0] $end
+$var wire 32 v) product_ext [31:0] $end
+$var wire 16 w) product [15:0] $end
+$var wire 32 x) acc_out [31:0] $end
+$var parameter 32 y) ACC_WIDTH $end
+$var parameter 32 z) DATA_WIDTH $end
+$var parameter 64 {) PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[29] $end
+$var parameter 6 |) i $end
+$scope module u_mac $end
+$var wire 32 }) acc_in [31:0] $end
+$var wire 8 ~) w [7:0] $end
+$var wire 8 !* x [7:0] $end
+$var wire 32 "* product_ext [31:0] $end
+$var wire 16 #* product [15:0] $end
+$var wire 32 $* acc_out [31:0] $end
+$var parameter 32 %* ACC_WIDTH $end
+$var parameter 32 &* DATA_WIDTH $end
+$var parameter 64 '* PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[30] $end
+$var parameter 6 (* i $end
+$scope module u_mac $end
+$var wire 32 )* acc_in [31:0] $end
+$var wire 8 ** w [7:0] $end
+$var wire 8 +* x [7:0] $end
+$var wire 32 ,* product_ext [31:0] $end
+$var wire 16 -* product [15:0] $end
+$var wire 32 .* acc_out [31:0] $end
+$var parameter 32 /* ACC_WIDTH $end
+$var parameter 32 0* DATA_WIDTH $end
+$var parameter 64 1* PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[31] $end
+$var parameter 6 2* i $end
+$scope module u_mac $end
+$var wire 32 3* acc_in [31:0] $end
+$var wire 8 4* w [7:0] $end
+$var wire 8 5* x [7:0] $end
+$var wire 32 6* product_ext [31:0] $end
+$var wire 16 7* product [15:0] $end
+$var wire 32 8* acc_out [31:0] $end
+$var parameter 32 9* ACC_WIDTH $end
+$var parameter 32 :* DATA_WIDTH $end
+$var parameter 64 ;* PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[0] $end
+$var parameter 2 <* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[1] $end
+$var parameter 2 =* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[2] $end
+$var parameter 3 >* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[3] $end
+$var parameter 3 ?* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[4] $end
+$var parameter 4 @* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[5] $end
+$var parameter 4 A* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[6] $end
+$var parameter 4 B* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[7] $end
+$var parameter 4 C* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[8] $end
+$var parameter 5 D* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[9] $end
+$var parameter 5 E* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[10] $end
+$var parameter 5 F* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[11] $end
+$var parameter 5 G* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[12] $end
+$var parameter 5 H* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[13] $end
+$var parameter 5 I* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[14] $end
+$var parameter 5 J* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[15] $end
+$var parameter 5 K* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[16] $end
+$var parameter 6 L* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[17] $end
+$var parameter 6 M* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[18] $end
+$var parameter 6 N* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[19] $end
+$var parameter 6 O* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[20] $end
+$var parameter 6 P* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[21] $end
+$var parameter 6 Q* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[22] $end
+$var parameter 6 R* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[23] $end
+$var parameter 6 S* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[24] $end
+$var parameter 6 T* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[25] $end
+$var parameter 6 U* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[26] $end
+$var parameter 6 V* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[27] $end
+$var parameter 6 W* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[28] $end
+$var parameter 6 X* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[29] $end
+$var parameter 6 Y* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[30] $end
+$var parameter 6 Z* i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[31] $end
+$var parameter 6 [* i $end
+$upscope $end
+$scope begin GEN_TREE_LEVEL[0] $end
+$var parameter 2 \* level $end
+$scope begin GEN_TREE_NODE[0] $end
+$var parameter 2 ]* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[1] $end
+$var parameter 2 ^* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[2] $end
+$var parameter 3 _* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[3] $end
+$var parameter 3 `* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[4] $end
+$var parameter 4 a* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[5] $end
+$var parameter 4 b* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[6] $end
+$var parameter 4 c* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[7] $end
+$var parameter 4 d* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[8] $end
+$var parameter 5 e* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[9] $end
+$var parameter 5 f* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[10] $end
+$var parameter 5 g* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[11] $end
+$var parameter 5 h* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[12] $end
+$var parameter 5 i* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[13] $end
+$var parameter 5 j* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[14] $end
+$var parameter 5 k* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[15] $end
+$var parameter 5 l* node $end
+$upscope $end
+$upscope $end
+$scope begin GEN_TREE_LEVEL[1] $end
+$var parameter 2 m* level $end
+$scope begin GEN_TREE_NODE[0] $end
+$var parameter 2 n* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[1] $end
+$var parameter 2 o* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[2] $end
+$var parameter 3 p* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[3] $end
+$var parameter 3 q* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[4] $end
+$var parameter 4 r* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[5] $end
+$var parameter 4 s* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[6] $end
+$var parameter 4 t* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[7] $end
+$var parameter 4 u* node $end
+$upscope $end
+$upscope $end
+$scope begin GEN_TREE_LEVEL[2] $end
+$var parameter 3 v* level $end
+$scope begin GEN_TREE_NODE[0] $end
+$var parameter 2 w* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[1] $end
+$var parameter 2 x* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[2] $end
+$var parameter 3 y* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[3] $end
+$var parameter 3 z* node $end
+$upscope $end
+$upscope $end
+$scope begin GEN_TREE_LEVEL[3] $end
+$var parameter 3 {* level $end
+$scope begin GEN_TREE_NODE[0] $end
+$var parameter 2 |* node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[1] $end
+$var parameter 2 }* node $end
+$upscope $end
+$upscope $end
+$scope begin GEN_TREE_LEVEL[4] $end
+$var parameter 4 ~* level $end
+$scope begin GEN_TREE_NODE[0] $end
+$var parameter 2 !+ node $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope module u_e $end
+$var wire 8 "+ bias [7:0] $end
+$var wire 1 I clk $end
+$var wire 1 J rst $end
+$var wire 1 O start $end
+$var wire 32 #+ w_bus [31:0] $end
+$var wire 32 $+ x_bus [31:0] $end
+$var wire 64 %+ x_group [63:0] $end
+$var wire 64 &+ w_group [63:0] $end
+$var wire 32 '+ final_acc [31:0] $end
+$var wire 32 (+ bias_ext [31:0] $end
+$var wire 32 )+ acc_next [31:0] $end
+$var parameter 32 *+ ACC_WIDTH $end
+$var parameter 32 ++ DATA_WIDTH $end
+$var parameter 32 ,+ GROUPS $end
+$var parameter 32 -+ GROUP_INDEX_WIDTH $end
+$var parameter 32 .+ N_INPUTS $end
+$var parameter 32 /+ PARALLEL $end
+$var reg 32 0+ acc [31:0] $end
+$var reg 1 + busy $end
+$var reg 1 & done $end
+$var reg 1 1+ group_index $end
+$var reg 8 2+ y [7:0] $end
+$scope module u_mac8 $end
+$var wire 32 3+ acc_in [31:0] $end
+$var wire 64 4+ w_bus [63:0] $end
+$var wire 64 5+ x_bus [63:0] $end
+$var wire 32 6+ acc_out [31:0] $end
+$var parameter 32 7+ ACC_WIDTH $end
+$var parameter 32 8+ DATA_WIDTH $end
+$var parameter 32 9+ PARALLEL $end
+$var parameter 32 :+ TREE_LEVELS $end
+$scope begin GEN_MAC[0] $end
+$var parameter 2 ;+ i $end
+$scope module u_mac $end
+$var wire 32 <+ acc_in [31:0] $end
+$var wire 8 =+ w [7:0] $end
+$var wire 8 >+ x [7:0] $end
+$var wire 32 ?+ product_ext [31:0] $end
+$var wire 16 @+ product [15:0] $end
+$var wire 32 A+ acc_out [31:0] $end
+$var parameter 32 B+ ACC_WIDTH $end
+$var parameter 32 C+ DATA_WIDTH $end
+$var parameter 64 D+ PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[1] $end
+$var parameter 2 E+ i $end
+$scope module u_mac $end
+$var wire 32 F+ acc_in [31:0] $end
+$var wire 8 G+ w [7:0] $end
+$var wire 8 H+ x [7:0] $end
+$var wire 32 I+ product_ext [31:0] $end
+$var wire 16 J+ product [15:0] $end
+$var wire 32 K+ acc_out [31:0] $end
+$var parameter 32 L+ ACC_WIDTH $end
+$var parameter 32 M+ DATA_WIDTH $end
+$var parameter 64 N+ PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[2] $end
+$var parameter 3 O+ i $end
+$scope module u_mac $end
+$var wire 32 P+ acc_in [31:0] $end
+$var wire 8 Q+ w [7:0] $end
+$var wire 8 R+ x [7:0] $end
+$var wire 32 S+ product_ext [31:0] $end
+$var wire 16 T+ product [15:0] $end
+$var wire 32 U+ acc_out [31:0] $end
+$var parameter 32 V+ ACC_WIDTH $end
+$var parameter 32 W+ DATA_WIDTH $end
+$var parameter 64 X+ PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[3] $end
+$var parameter 3 Y+ i $end
+$scope module u_mac $end
+$var wire 32 Z+ acc_in [31:0] $end
+$var wire 8 [+ w [7:0] $end
+$var wire 8 \+ x [7:0] $end
+$var wire 32 ]+ product_ext [31:0] $end
+$var wire 16 ^+ product [15:0] $end
+$var wire 32 _+ acc_out [31:0] $end
+$var parameter 32 `+ ACC_WIDTH $end
+$var parameter 32 a+ DATA_WIDTH $end
+$var parameter 64 b+ PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[4] $end
+$var parameter 4 c+ i $end
+$scope module u_mac $end
+$var wire 32 d+ acc_in [31:0] $end
+$var wire 8 e+ w [7:0] $end
+$var wire 8 f+ x [7:0] $end
+$var wire 32 g+ product_ext [31:0] $end
+$var wire 16 h+ product [15:0] $end
+$var wire 32 i+ acc_out [31:0] $end
+$var parameter 32 j+ ACC_WIDTH $end
+$var parameter 32 k+ DATA_WIDTH $end
+$var parameter 64 l+ PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[5] $end
+$var parameter 4 m+ i $end
+$scope module u_mac $end
+$var wire 32 n+ acc_in [31:0] $end
+$var wire 8 o+ w [7:0] $end
+$var wire 8 p+ x [7:0] $end
+$var wire 32 q+ product_ext [31:0] $end
+$var wire 16 r+ product [15:0] $end
+$var wire 32 s+ acc_out [31:0] $end
+$var parameter 32 t+ ACC_WIDTH $end
+$var parameter 32 u+ DATA_WIDTH $end
+$var parameter 64 v+ PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[6] $end
+$var parameter 4 w+ i $end
+$scope module u_mac $end
+$var wire 32 x+ acc_in [31:0] $end
+$var wire 8 y+ w [7:0] $end
+$var wire 8 z+ x [7:0] $end
+$var wire 32 {+ product_ext [31:0] $end
+$var wire 16 |+ product [15:0] $end
+$var wire 32 }+ acc_out [31:0] $end
+$var parameter 32 ~+ ACC_WIDTH $end
+$var parameter 32 !, DATA_WIDTH $end
+$var parameter 64 ", PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_MAC[7] $end
+$var parameter 4 #, i $end
+$scope module u_mac $end
+$var wire 32 $, acc_in [31:0] $end
+$var wire 8 %, w [7:0] $end
+$var wire 8 &, x [7:0] $end
+$var wire 32 ', product_ext [31:0] $end
+$var wire 16 (, product [15:0] $end
+$var wire 32 ), acc_out [31:0] $end
+$var parameter 32 *, ACC_WIDTH $end
+$var parameter 32 +, DATA_WIDTH $end
+$var parameter 64 ,, PROD_WIDTH $end
+$upscope $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[0] $end
+$var parameter 2 -, i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[1] $end
+$var parameter 2 ., i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[2] $end
+$var parameter 3 /, i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[3] $end
+$var parameter 3 0, i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[4] $end
+$var parameter 4 1, i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[5] $end
+$var parameter 4 2, i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[6] $end
+$var parameter 4 3, i $end
+$upscope $end
+$scope begin GEN_TREE_INPUT[7] $end
+$var parameter 4 4, i $end
+$upscope $end
+$scope begin GEN_TREE_LEVEL[0] $end
+$var parameter 2 5, level $end
+$scope begin GEN_TREE_NODE[0] $end
+$var parameter 2 6, node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[1] $end
+$var parameter 2 7, node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[2] $end
+$var parameter 3 8, node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[3] $end
+$var parameter 3 9, node $end
+$upscope $end
+$upscope $end
+$scope begin GEN_TREE_LEVEL[1] $end
+$var parameter 2 :, level $end
+$scope begin GEN_TREE_NODE[0] $end
+$var parameter 2 ;, node $end
+$upscope $end
+$scope begin GEN_TREE_NODE[1] $end
+$var parameter 2 <, node $end
+$upscope $end
+$upscope $end
+$scope begin GEN_TREE_LEVEL[2] $end
+$var parameter 3 =, level $end
+$scope begin GEN_TREE_NODE[0] $end
+$var parameter 2 >, node $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$comment Show the parameter values. $end
+$dumpall
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+$end
+#0
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diff --git a/sim/parameter_sweep_sim b/sim/parameter_sweep_sim
new file mode 100755
index 0000000..fd6895a
--- /dev/null
+++ b/sim/parameter_sweep_sim
@@ -0,0 +1,11411 @@
+#! /opt/homebrew/Cellar/icarus-verilog/13.0/bin/vvp
+:ivl_version "13.0 (stable)" "(v13_0)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 12;
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/system.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_sys.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_textio.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2005_math.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/va_math.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2009.vpi";
+S_0x102d24e90 .scope package, "$unit" "$unit" 2 1;
+ .timescale 0 0;
+S_0x102d16e70 .scope module, "layer" "layer" 3 1;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "start";
+    .port_info 3 /INPUT 1024 "x_bus";
+    .port_info 4 /INPUT 8192 "weights_bus";
+    .port_info 5 /INPUT 128 "bias_bus";
+    .port_info 6 /OUTPUT 128 "y_bus";
+    .port_info 7 /OUTPUT 1 "busy";
+    .port_info 8 /OUTPUT 1 "done";
+P_0xc4f294000 .param/l "ACC_WIDTH" 0 3 6, +C4<00000000000000000000000000101000>;
+P_0xc4f294040 .param/l "DATA_WIDTH" 0 3 2, +C4<00000000000000000000000000010000>;
+P_0xc4f294080 .param/l "N_INPUTS" 0 3 3, +C4<00000000000000000000000001000000>;
+P_0xc4f2940c0 .param/l "N_NEURONS" 0 3 4, +C4<00000000000000000000000000001000>;
+P_0xc4f294100 .param/l "PARALLEL" 0 3 5, +C4<00000000000000000000000000001000>;
+o0xc4e855350 .functor BUFZ 128, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f3157c0_0 .net/s "bias_bus", 127 0, o0xc4e855350;  0 drivers
+v0xc4f315860_0 .net "busy", 0 0, L_0xc4f39c640;  1 drivers
+o0xc4e845fc0 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f315900_0 .net "clk", 0 0, o0xc4e845fc0;  0 drivers
+v0xc4f3159a0_0 .net "done", 0 0, L_0xc4f39c6e0;  1 drivers
+v0xc4f315a40_0 .net "neuron_busy", 7 0, L_0xc4f3a0a00;  1 drivers
+v0xc4f315ae0_0 .net "neuron_done", 7 0, L_0xc4f3a0aa0;  1 drivers
+o0xc4e846080 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f315b80_0 .net "rst", 0 0, o0xc4e846080;  0 drivers
+o0xc4e8460b0 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f315c20_0 .net "start", 0 0, o0xc4e8460b0;  0 drivers
+o0xc4e855440 .functor BUFZ 8192, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f315cc0_0 .net/s "weights_bus", 8191 0, o0xc4e855440;  0 drivers
+o0xc4e846110 .functor BUFZ 1024, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f315d60_0 .net/s "x_bus", 1023 0, o0xc4e846110;  0 drivers
+v0xc4f315e00_0 .net/s "y_bus", 127 0, L_0xc4f3a0960;  1 drivers
+L_0xc4f2a85a0 .part o0xc4e855440, 0, 1024;
+L_0xc4f2a8640 .part o0xc4e855350, 0, 16;
+L_0xc4f2a97c0 .part o0xc4e855440, 1024, 1024;
+L_0xc4f2a9860 .part o0xc4e855350, 16, 16;
+L_0xc4f2aa9e0 .part o0xc4e855440, 2048, 1024;
+L_0xc4f2aaa80 .part o0xc4e855350, 32, 16;
+L_0xc4f2abc00 .part o0xc4e855440, 3072, 1024;
+L_0xc4f2abca0 .part o0xc4e855350, 48, 16;
+L_0xc4f394e60 .part o0xc4e855440, 4096, 1024;
+L_0xc4f394f00 .part o0xc4e855350, 64, 16;
+L_0xc4f396080 .part o0xc4e855440, 5120, 1024;
+L_0xc4f396120 .part o0xc4e855350, 80, 16;
+L_0xc4f3972a0 .part o0xc4e855440, 6144, 1024;
+L_0xc4f397340 .part o0xc4e855350, 96, 16;
+L_0xc4f39c500 .part o0xc4e855440, 7168, 1024;
+L_0xc4f39c5a0 .part o0xc4e855350, 112, 16;
+LS_0xc4f3a0960_0_0 .concat8 [ 16 16 16 16], v0xc4f2cd9a0_0, v0xc4f2da260_0, v0xc4f2e2b20_0, v0xc4f2eb3e0_0;
+LS_0xc4f3a0960_0_4 .concat8 [ 16 16 16 16], v0xc4f2f3ca0_0, v0xc4f3045a0_0, v0xc4f308e60_0, v0xc4f315720_0;
+L_0xc4f3a0960 .concat8 [ 64 64 0 0], LS_0xc4f3a0960_0_0, LS_0xc4f3a0960_0_4;
+LS_0xc4f3a0a00_0_0 .concat8 [ 1 1 1 1], v0xc4f2cd2c0_0, v0xc4f2d9b80_0, v0xc4f2e2440_0, v0xc4f2ead00_0;
+LS_0xc4f3a0a00_0_4 .concat8 [ 1 1 1 1], v0xc4f2f35c0_0, v0xc4f2ffe80_0, v0xc4f308780_0, v0xc4f315040_0;
+L_0xc4f3a0a00 .concat8 [ 4 4 0 0], LS_0xc4f3a0a00_0_0, LS_0xc4f3a0a00_0_4;
+LS_0xc4f3a0aa0_0_0 .concat8 [ 1 1 1 1], v0xc4f2cd400_0, v0xc4f2d9cc0_0, v0xc4f2e2580_0, v0xc4f2eae40_0;
+LS_0xc4f3a0aa0_0_4 .concat8 [ 1 1 1 1], v0xc4f2f3700_0, v0xc4f304000_0, v0xc4f3088c0_0, v0xc4f315180_0;
+L_0xc4f3a0aa0 .concat8 [ 4 4 0 0], LS_0xc4f3a0aa0_0_0, LS_0xc4f3a0aa0_0_4;
+L_0xc4f39c640 .reduce/or L_0xc4f3a0a00;
+L_0xc4f39c6e0 .reduce/and L_0xc4f3a0aa0;
+S_0x102d151b0 .scope generate, "GEN_NEURON[0]" "GEN_NEURON[0]" 3 34, 3 34 0, S_0x102d16e70;
+ .timescale 0 0;
+P_0xc4f287680 .param/l "n" 1 3 34, +C4<00>;
+S_0x102d14700 .scope module, "u_neuron" "neuron_parallel" 3 41, 4 1 0, S_0x102d151b0;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "start";
+    .port_info 3 /INPUT 1024 "x_bus";
+    .port_info 4 /INPUT 1024 "w_bus";
+    .port_info 5 /INPUT 16 "bias";
+    .port_info 6 /OUTPUT 16 "y";
+    .port_info 7 /OUTPUT 1 "busy";
+    .port_info 8 /OUTPUT 1 "done";
+P_0x102d14880 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000101000>;
+P_0x102d148c0 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>;
+P_0x102d14900 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000001000>;
+P_0x102d14940 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000011>;
+P_0x102d14980 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000001000000>;
+P_0x102d149c0 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>;
+v0xc4f2cc780_0 .net *"_ivl_0", 31 0, L_0xc4f386c60;  1 drivers
+v0xc4f2cc820_0 .net *"_ivl_11", 31 0, L_0xc4eed94a0;  1 drivers
+v0xc4f2cc8c0_0 .net *"_ivl_14", 31 0, L_0xc4f386d00;  1 drivers
+L_0xc4e8780e8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2cc960_0 .net *"_ivl_17", 28 0, L_0xc4e8780e8;  1 drivers
+L_0xc4e878130 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2cca00_0 .net/2u *"_ivl_18", 31 0, L_0xc4e878130;  1 drivers
+v0xc4f2ccaa0_0 .net *"_ivl_21", 31 0, L_0xc4eed95e0;  1 drivers
+L_0xc4e878178 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2ccb40_0 .net/2u *"_ivl_22", 31 0, L_0xc4e878178;  1 drivers
+v0xc4f2ccbe0_0 .net *"_ivl_25", 31 0, L_0xc4eed9680;  1 drivers
+v0xc4f2ccc80_0 .net *"_ivl_29", 0 0, L_0xc4f2a8500;  1 drivers
+L_0xc4e878010 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2ccd20_0 .net *"_ivl_3", 28 0, L_0xc4e878010;  1 drivers
+v0xc4f2ccdc0_0 .net *"_ivl_31", 23 0, L_0xc4eeda1c0;  1 drivers
+L_0xc4e878058 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2cce60_0 .net/2u *"_ivl_4", 31 0, L_0xc4e878058;  1 drivers
+v0xc4f2ccf00_0 .net *"_ivl_7", 31 0, L_0xc4eed9540;  1 drivers
+L_0xc4e8780a0 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2ccfa0_0 .net/2u *"_ivl_8", 31 0, L_0xc4e8780a0;  1 drivers
+v0xc4f2cd040_0 .var/s "acc", 39 0;
+v0xc4f2cd0e0_0 .net/s "acc_next", 39 0, L_0xc4f388640;  1 drivers
+v0xc4f2cd180_0 .net/s "bias", 15 0, L_0xc4f2a8640;  1 drivers
+v0xc4f2cd220_0 .net/s "bias_ext", 39 0, L_0xc4f3886e0;  1 drivers
+v0xc4f2cd2c0_0 .var "busy", 0 0;
+v0xc4f2cd360_0 .net "clk", 0 0, o0xc4e845fc0;  alias, 0 drivers
+v0xc4f2cd400_0 .var "done", 0 0;
+v0xc4f2cd4a0_0 .net/s "final_acc", 39 0, L_0xc4f388780;  1 drivers
+v0xc4f2cd540_0 .var "group_index", 2 0;
+v0xc4f2cd5e0_0 .net "rst", 0 0, o0xc4e846080;  alias, 0 drivers
+v0xc4f2cd680_0 .net "start", 0 0, o0xc4e8460b0;  alias, 0 drivers
+v0xc4f2cd720_0 .net/s "w_bus", 1023 0, L_0xc4f2a85a0;  1 drivers
+v0xc4f2cd7c0_0 .net/s "w_group", 127 0, L_0xc4f293de0;  1 drivers
+v0xc4f2cd860_0 .net/s "x_bus", 1023 0, o0xc4e846110;  alias, 0 drivers
+v0xc4f2cd900_0 .net/s "x_group", 127 0, L_0xc4f293d40;  1 drivers
+v0xc4f2cd9a0_0 .var/s "y", 15 0;
+E_0xc4eec7600 .event posedge, v0xc4f2cd360_0;
+L_0xc4f386c60 .concat [ 3 29 0 0], v0xc4f2cd540_0, L_0xc4e878010;
+L_0xc4eed9540 .arith/mult 32, L_0xc4f386c60, L_0xc4e878058;
+L_0xc4eed94a0 .arith/mult 32, L_0xc4eed9540, L_0xc4e8780a0;
+L_0xc4f293d40 .part/v o0xc4e846110, L_0xc4eed94a0, 128;
+L_0xc4f386d00 .concat [ 3 29 0 0], v0xc4f2cd540_0, L_0xc4e8780e8;
+L_0xc4eed95e0 .arith/mult 32, L_0xc4f386d00, L_0xc4e878130;
+L_0xc4eed9680 .arith/mult 32, L_0xc4eed95e0, L_0xc4e878178;
+L_0xc4f293de0 .part/v L_0xc4f2a85a0, L_0xc4eed9680, 128;
+L_0xc4f2a8500 .part L_0xc4f2a8640, 15, 1;
+L_0xc4eeda1c0 .repeat 24, 24, L_0xc4f2a8500;
+L_0xc4f3886e0 .concat [ 16 24 0 0], L_0xc4f2a8640, L_0xc4eeda1c0;
+L_0xc4f388780 .arith/sum 40, L_0xc4f388640, L_0xc4f3886e0;
+S_0x102d13870 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0x102d14700;
+ .timescale 0 0;
+    .port_info 0 /INPUT 128 "x_bus";
+    .port_info 1 /INPUT 128 "w_bus";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4ef0c000 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000101000>;
+P_0xc4ef0c040 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>;
+P_0xc4ef0c080 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>;
+P_0xc4ef0c0c0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>;
+v0xc4f2cc3c0_0 .net/s "acc_in", 39 0, v0xc4f2cd040_0;  1 drivers
+v0xc4f2cc460_0 .net/s "acc_out", 39 0, L_0xc4f388640;  alias, 1 drivers
+v0xc4f2cc500 .array "products", 7 0;
+v0xc4f2cc500_0 .net/s v0xc4f2cc500 0, 39 0, L_0xc4f386f80; 1 drivers
+v0xc4f2cc500_1 .net/s v0xc4f2cc500 1, 39 0, L_0xc4f387200; 1 drivers
+v0xc4f2cc500_2 .net/s v0xc4f2cc500 2, 39 0, L_0xc4f387480; 1 drivers
+v0xc4f2cc500_3 .net/s v0xc4f2cc500 3, 39 0, L_0xc4f387700; 1 drivers
+v0xc4f2cc500_4 .net/s v0xc4f2cc500 4, 39 0, L_0xc4f387980; 1 drivers
+v0xc4f2cc500_5 .net/s v0xc4f2cc500 5, 39 0, L_0xc4f387c00; 1 drivers
+v0xc4f2cc500_6 .net/s v0xc4f2cc500 6, 39 0, L_0xc4f387e80; 1 drivers
+v0xc4f2cc500_7 .net/s v0xc4f2cc500 7, 39 0, L_0xc4f388140; 1 drivers
+v0xc4f2cc5a0 .array "tree", 31 0;
+v0xc4f2cc5a0_0 .net/s v0xc4f2cc5a0 0, 39 0, L_0xc4f064310; 1 drivers
+v0xc4f2cc5a0_1 .net/s v0xc4f2cc5a0 1, 39 0, L_0xc4f064380; 1 drivers
+v0xc4f2cc5a0_2 .net/s v0xc4f2cc5a0 2, 39 0, L_0xc4f0643f0; 1 drivers
+v0xc4f2cc5a0_3 .net/s v0xc4f2cc5a0 3, 39 0, L_0xc4f064460; 1 drivers
+v0xc4f2cc5a0_4 .net/s v0xc4f2cc5a0 4, 39 0, L_0xc4f0644d0; 1 drivers
+v0xc4f2cc5a0_5 .net/s v0xc4f2cc5a0 5, 39 0, L_0xc4f064540; 1 drivers
+v0xc4f2cc5a0_6 .net/s v0xc4f2cc5a0 6, 39 0, L_0xc4f0645b0; 1 drivers
+v0xc4f2cc5a0_7 .net/s v0xc4f2cc5a0 7, 39 0, L_0xc4f064620; 1 drivers
+v0xc4f2cc5a0_8 .net/s v0xc4f2cc5a0 8, 39 0, L_0xc4f3881e0; 1 drivers
+v0xc4f2cc5a0_9 .net/s v0xc4f2cc5a0 9, 39 0, L_0xc4f388280; 1 drivers
+v0xc4f2cc5a0_10 .net/s v0xc4f2cc5a0 10, 39 0, L_0xc4f388320; 1 drivers
+v0xc4f2cc5a0_11 .net/s v0xc4f2cc5a0 11, 39 0, L_0xc4f3883c0; 1 drivers
+o0xc4e8457b0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2cc5a0_12 .net/s v0xc4f2cc5a0 12, 39 0, o0xc4e8457b0; 0 drivers
+o0xc4e8457e0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2cc5a0_13 .net/s v0xc4f2cc5a0 13, 39 0, o0xc4e8457e0; 0 drivers
+o0xc4e845810 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2cc5a0_14 .net/s v0xc4f2cc5a0 14, 39 0, o0xc4e845810; 0 drivers
+o0xc4e845840 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2cc5a0_15 .net/s v0xc4f2cc5a0 15, 39 0, o0xc4e845840; 0 drivers
+v0xc4f2cc5a0_16 .net/s v0xc4f2cc5a0 16, 39 0, L_0xc4f388460; 1 drivers
+v0xc4f2cc5a0_17 .net/s v0xc4f2cc5a0 17, 39 0, L_0xc4f388500; 1 drivers
+o0xc4e8458d0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2cc5a0_18 .net/s v0xc4f2cc5a0 18, 39 0, o0xc4e8458d0; 0 drivers
+o0xc4e845900 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2cc5a0_19 .net/s v0xc4f2cc5a0 19, 39 0, o0xc4e845900; 0 drivers
+o0xc4e845930 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2cc5a0_20 .net/s v0xc4f2cc5a0 20, 39 0, o0xc4e845930; 0 drivers
+o0xc4e845960 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2cc5a0_21 .net/s v0xc4f2cc5a0 21, 39 0, o0xc4e845960; 0 drivers
+o0xc4e845990 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2cc5a0_22 .net/s v0xc4f2cc5a0 22, 39 0, o0xc4e845990; 0 drivers
+o0xc4e8459c0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2cc5a0_23 .net/s v0xc4f2cc5a0 23, 39 0, o0xc4e8459c0; 0 drivers
+v0xc4f2cc5a0_24 .net/s v0xc4f2cc5a0 24, 39 0, L_0xc4f3885a0; 1 drivers
+o0xc4e845a20 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2cc5a0_25 .net/s v0xc4f2cc5a0 25, 39 0, o0xc4e845a20; 0 drivers
+o0xc4e845a50 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2cc5a0_26 .net/s v0xc4f2cc5a0 26, 39 0, o0xc4e845a50; 0 drivers
+o0xc4e845a80 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2cc5a0_27 .net/s v0xc4f2cc5a0 27, 39 0, o0xc4e845a80; 0 drivers
+o0xc4e845ab0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2cc5a0_28 .net/s v0xc4f2cc5a0 28, 39 0, o0xc4e845ab0; 0 drivers
+o0xc4e845ae0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2cc5a0_29 .net/s v0xc4f2cc5a0 29, 39 0, o0xc4e845ae0; 0 drivers
+o0xc4e845b10 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2cc5a0_30 .net/s v0xc4f2cc5a0 30, 39 0, o0xc4e845b10; 0 drivers
+o0xc4e845b40 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2cc5a0_31 .net/s v0xc4f2cc5a0 31, 39 0, o0xc4e845b40; 0 drivers
+v0xc4f2cc640_0 .net/s "w_bus", 127 0, L_0xc4f293de0;  alias, 1 drivers
+v0xc4f2cc6e0_0 .net/s "x_bus", 127 0, L_0xc4f293d40;  alias, 1 drivers
+L_0xc4f293f20 .part L_0xc4f293d40, 0, 16;
+L_0xc4f293ca0 .part L_0xc4f293de0, 0, 16;
+L_0xc4f2463a0 .part L_0xc4f293d40, 16, 16;
+L_0xc4f228b40 .part L_0xc4f293de0, 16, 16;
+L_0xc4f1ba1c0 .part L_0xc4f293d40, 32, 16;
+L_0xc4f1aaf80 .part L_0xc4f293de0, 32, 16;
+L_0xc4f15a6c0 .part L_0xc4f293d40, 48, 16;
+L_0xc4f190be0 .part L_0xc4f293de0, 48, 16;
+L_0xc4f193d40 .part L_0xc4f293d40, 64, 16;
+L_0xc4f190b40 .part L_0xc4f293de0, 64, 16;
+L_0xc4f2a8000 .part L_0xc4f293d40, 80, 16;
+L_0xc4f2a80a0 .part L_0xc4f293de0, 80, 16;
+L_0xc4f2a81e0 .part L_0xc4f293d40, 96, 16;
+L_0xc4f2a8280 .part L_0xc4f293de0, 96, 16;
+L_0xc4f2a83c0 .part L_0xc4f293d40, 112, 16;
+L_0xc4f2a8460 .part L_0xc4f293de0, 112, 16;
+L_0xc4f388640 .arith/sum 40, v0xc4f2cd040_0, L_0xc4f3885a0;
+S_0x102d139f0 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f2876c0 .param/l "i" 1 5 20, +C4<00>;
+S_0x102d10e30 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0x102d139f0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ac000 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ac040 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ac080 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f09d180_0 .net/s *"_ivl_0", 31 0, L_0xc4f386da0;  1 drivers
+v0xc4f09d220_0 .net/s *"_ivl_2", 31 0, L_0xc4f386e40;  1 drivers
+v0xc4f09d2c0_0 .net *"_ivl_7", 0 0, L_0xc4f293e80;  1 drivers
+v0xc4f09d360_0 .net *"_ivl_9", 7 0, L_0xc4eed97c0;  1 drivers
+L_0xc4e8781c0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f09d400_0 .net/s "acc_in", 39 0, L_0xc4e8781c0;  1 drivers
+v0xc4f09d4a0_0 .net/s "acc_out", 39 0, L_0xc4f386f80;  alias, 1 drivers
+v0xc4f09d540_0 .net/s "product", 31 0, L_0xc4eed9720;  1 drivers
+v0xc4f09d5e0_0 .net/s "product_ext", 39 0, L_0xc4f386ee0;  1 drivers
+v0xc4f09d680_0 .net/s "w", 15 0, L_0xc4f293ca0;  1 drivers
+v0xc4f09d720_0 .net/s "x", 15 0, L_0xc4f293f20;  1 drivers
+L_0xc4f386da0 .extend/s 32, L_0xc4f293f20;
+L_0xc4f386e40 .extend/s 32, L_0xc4f293ca0;
+L_0xc4eed9720 .arith/mult 32, L_0xc4f386da0, L_0xc4f386e40;
+L_0xc4f293e80 .part L_0xc4eed9720, 31, 1;
+L_0xc4eed97c0 .repeat 8, 8, L_0xc4f293e80;
+L_0xc4f386ee0 .concat [ 32 8 0 0], L_0xc4eed9720, L_0xc4eed97c0;
+L_0xc4f386f80 .arith/sum 40, L_0xc4e8781c0, L_0xc4f386ee0;
+S_0x102d10fb0 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f287700 .param/l "i" 1 5 20, +C4<01>;
+S_0x102d11b20 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0x102d10fb0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ac0c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ac100 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ac140 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f09d7c0_0 .net/s *"_ivl_0", 31 0, L_0xc4f387020;  1 drivers
+v0xc4f09d860_0 .net/s *"_ivl_2", 31 0, L_0xc4f3870c0;  1 drivers
+v0xc4f09d900_0 .net *"_ivl_7", 0 0, L_0xc4f290c80;  1 drivers
+v0xc4f09d9a0_0 .net *"_ivl_9", 7 0, L_0xc4eed9900;  1 drivers
+L_0xc4e878208 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f09da40_0 .net/s "acc_in", 39 0, L_0xc4e878208;  1 drivers
+v0xc4f09dae0_0 .net/s "acc_out", 39 0, L_0xc4f387200;  alias, 1 drivers
+v0xc4f09db80_0 .net/s "product", 31 0, L_0xc4eed9860;  1 drivers
+v0xc4f09dc20_0 .net/s "product_ext", 39 0, L_0xc4f387160;  1 drivers
+v0xc4f09dcc0_0 .net/s "w", 15 0, L_0xc4f228b40;  1 drivers
+v0xc4f09dd60_0 .net/s "x", 15 0, L_0xc4f2463a0;  1 drivers
+L_0xc4f387020 .extend/s 32, L_0xc4f2463a0;
+L_0xc4f3870c0 .extend/s 32, L_0xc4f228b40;
+L_0xc4eed9860 .arith/mult 32, L_0xc4f387020, L_0xc4f3870c0;
+L_0xc4f290c80 .part L_0xc4eed9860, 31, 1;
+L_0xc4eed9900 .repeat 8, 8, L_0xc4f290c80;
+L_0xc4f387160 .concat [ 32 8 0 0], L_0xc4eed9860, L_0xc4eed9900;
+L_0xc4f387200 .arith/sum 40, L_0xc4e878208, L_0xc4f387160;
+S_0x102d11ca0 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f287740 .param/l "i" 1 5 20, +C4<010>;
+S_0x102d0f3b0 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0x102d11ca0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ac180 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ac1c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ac200 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f09de00_0 .net/s *"_ivl_0", 31 0, L_0xc4f3872a0;  1 drivers
+v0xc4f09dea0_0 .net/s *"_ivl_2", 31 0, L_0xc4f387340;  1 drivers
+v0xc4f09df40_0 .net *"_ivl_7", 0 0, L_0xc4f1cd400;  1 drivers
+v0xc4f09dfe0_0 .net *"_ivl_9", 7 0, L_0xc4eed9a40;  1 drivers
+L_0xc4e878250 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f09e080_0 .net/s "acc_in", 39 0, L_0xc4e878250;  1 drivers
+v0xc4f09e120_0 .net/s "acc_out", 39 0, L_0xc4f387480;  alias, 1 drivers
+v0xc4f09e1c0_0 .net/s "product", 31 0, L_0xc4eed99a0;  1 drivers
+v0xc4f09e260_0 .net/s "product_ext", 39 0, L_0xc4f3873e0;  1 drivers
+v0xc4f09e300_0 .net/s "w", 15 0, L_0xc4f1aaf80;  1 drivers
+v0xc4f09e3a0_0 .net/s "x", 15 0, L_0xc4f1ba1c0;  1 drivers
+L_0xc4f3872a0 .extend/s 32, L_0xc4f1ba1c0;
+L_0xc4f387340 .extend/s 32, L_0xc4f1aaf80;
+L_0xc4eed99a0 .arith/mult 32, L_0xc4f3872a0, L_0xc4f387340;
+L_0xc4f1cd400 .part L_0xc4eed99a0, 31, 1;
+L_0xc4eed9a40 .repeat 8, 8, L_0xc4f1cd400;
+L_0xc4f3873e0 .concat [ 32 8 0 0], L_0xc4eed99a0, L_0xc4eed9a40;
+L_0xc4f387480 .arith/sum 40, L_0xc4e878250, L_0xc4f3873e0;
+S_0xc4f2c8000 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f287780 .param/l "i" 1 5 20, +C4<011>;
+S_0xc4f2c8180 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2c8000;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ac240 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ac280 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ac2c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f09e440_0 .net/s *"_ivl_0", 31 0, L_0xc4f387520;  1 drivers
+v0xc4f09e4e0_0 .net/s *"_ivl_2", 31 0, L_0xc4f3875c0;  1 drivers
+v0xc4f09e580_0 .net *"_ivl_7", 0 0, L_0xc4f175900;  1 drivers
+v0xc4f09e620_0 .net *"_ivl_9", 7 0, L_0xc4eed9b80;  1 drivers
+L_0xc4e878298 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f09e6c0_0 .net/s "acc_in", 39 0, L_0xc4e878298;  1 drivers
+v0xc4f09e760_0 .net/s "acc_out", 39 0, L_0xc4f387700;  alias, 1 drivers
+v0xc4f09e800_0 .net/s "product", 31 0, L_0xc4eed9ae0;  1 drivers
+v0xc4f09e8a0_0 .net/s "product_ext", 39 0, L_0xc4f387660;  1 drivers
+v0xc4f09e940_0 .net/s "w", 15 0, L_0xc4f190be0;  1 drivers
+v0xc4f09e9e0_0 .net/s "x", 15 0, L_0xc4f15a6c0;  1 drivers
+L_0xc4f387520 .extend/s 32, L_0xc4f15a6c0;
+L_0xc4f3875c0 .extend/s 32, L_0xc4f190be0;
+L_0xc4eed9ae0 .arith/mult 32, L_0xc4f387520, L_0xc4f3875c0;
+L_0xc4f175900 .part L_0xc4eed9ae0, 31, 1;
+L_0xc4eed9b80 .repeat 8, 8, L_0xc4f175900;
+L_0xc4f387660 .concat [ 32 8 0 0], L_0xc4eed9ae0, L_0xc4eed9b80;
+L_0xc4f387700 .arith/sum 40, L_0xc4e878298, L_0xc4f387660;
+S_0xc4f2c8300 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f287800 .param/l "i" 1 5 20, +C4<0100>;
+S_0xc4f2c8480 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2c8300;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ac300 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ac340 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ac380 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f09ea80_0 .net/s *"_ivl_0", 31 0, L_0xc4f3877a0;  1 drivers
+v0xc4f09eb20_0 .net/s *"_ivl_2", 31 0, L_0xc4f387840;  1 drivers
+v0xc4f09ebc0_0 .net *"_ivl_7", 0 0, L_0xc4f190c80;  1 drivers
+v0xc4f09ec60_0 .net *"_ivl_9", 7 0, L_0xc4eed9cc0;  1 drivers
+L_0xc4e8782e0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f09ed00_0 .net/s "acc_in", 39 0, L_0xc4e8782e0;  1 drivers
+v0xc4f09eda0_0 .net/s "acc_out", 39 0, L_0xc4f387980;  alias, 1 drivers
+v0xc4f09ee40_0 .net/s "product", 31 0, L_0xc4eed9c20;  1 drivers
+v0xc4f09eee0_0 .net/s "product_ext", 39 0, L_0xc4f3878e0;  1 drivers
+v0xc4f09ef80_0 .net/s "w", 15 0, L_0xc4f190b40;  1 drivers
+v0xc4f09f020_0 .net/s "x", 15 0, L_0xc4f193d40;  1 drivers
+L_0xc4f3877a0 .extend/s 32, L_0xc4f193d40;
+L_0xc4f387840 .extend/s 32, L_0xc4f190b40;
+L_0xc4eed9c20 .arith/mult 32, L_0xc4f3877a0, L_0xc4f387840;
+L_0xc4f190c80 .part L_0xc4eed9c20, 31, 1;
+L_0xc4eed9cc0 .repeat 8, 8, L_0xc4f190c80;
+L_0xc4f3878e0 .concat [ 32 8 0 0], L_0xc4eed9c20, L_0xc4eed9cc0;
+L_0xc4f387980 .arith/sum 40, L_0xc4e8782e0, L_0xc4f3878e0;
+S_0xc4f2c8600 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f287840 .param/l "i" 1 5 20, +C4<0101>;
+S_0xc4f2c8780 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2c8600;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ac3c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ac400 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ac440 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f09f0c0_0 .net/s *"_ivl_0", 31 0, L_0xc4f387a20;  1 drivers
+v0xc4f09f160_0 .net/s *"_ivl_2", 31 0, L_0xc4f387ac0;  1 drivers
+v0xc4f09f200_0 .net *"_ivl_7", 0 0, L_0xc4f190d20;  1 drivers
+v0xc4f09f2a0_0 .net *"_ivl_9", 7 0, L_0xc4eed9e00;  1 drivers
+L_0xc4e878328 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f09f340_0 .net/s "acc_in", 39 0, L_0xc4e878328;  1 drivers
+v0xc4f09f3e0_0 .net/s "acc_out", 39 0, L_0xc4f387c00;  alias, 1 drivers
+v0xc4f09f480_0 .net/s "product", 31 0, L_0xc4eed9d60;  1 drivers
+v0xc4f09f520_0 .net/s "product_ext", 39 0, L_0xc4f387b60;  1 drivers
+v0xc4f09f5c0_0 .net/s "w", 15 0, L_0xc4f2a80a0;  1 drivers
+v0xc4f09f660_0 .net/s "x", 15 0, L_0xc4f2a8000;  1 drivers
+L_0xc4f387a20 .extend/s 32, L_0xc4f2a8000;
+L_0xc4f387ac0 .extend/s 32, L_0xc4f2a80a0;
+L_0xc4eed9d60 .arith/mult 32, L_0xc4f387a20, L_0xc4f387ac0;
+L_0xc4f190d20 .part L_0xc4eed9d60, 31, 1;
+L_0xc4eed9e00 .repeat 8, 8, L_0xc4f190d20;
+L_0xc4f387b60 .concat [ 32 8 0 0], L_0xc4eed9d60, L_0xc4eed9e00;
+L_0xc4f387c00 .arith/sum 40, L_0xc4e878328, L_0xc4f387b60;
+S_0xc4f2c8900 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f287880 .param/l "i" 1 5 20, +C4<0110>;
+S_0xc4f2c8a80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2c8900;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ac480 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ac4c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ac500 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f09f700_0 .net/s *"_ivl_0", 31 0, L_0xc4f387ca0;  1 drivers
+v0xc4f09f7a0_0 .net/s *"_ivl_2", 31 0, L_0xc4f387d40;  1 drivers
+v0xc4f09f840_0 .net *"_ivl_7", 0 0, L_0xc4f2a8140;  1 drivers
+v0xc4f09f8e0_0 .net *"_ivl_9", 7 0, L_0xc4eed9f40;  1 drivers
+L_0xc4e878370 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f09f980_0 .net/s "acc_in", 39 0, L_0xc4e878370;  1 drivers
+v0xc4f09fa20_0 .net/s "acc_out", 39 0, L_0xc4f387e80;  alias, 1 drivers
+v0xc4f09fac0_0 .net/s "product", 31 0, L_0xc4eed9ea0;  1 drivers
+v0xc4f09fb60_0 .net/s "product_ext", 39 0, L_0xc4f387de0;  1 drivers
+v0xc4f09fc00_0 .net/s "w", 15 0, L_0xc4f2a8280;  1 drivers
+v0xc4f09fca0_0 .net/s "x", 15 0, L_0xc4f2a81e0;  1 drivers
+L_0xc4f387ca0 .extend/s 32, L_0xc4f2a81e0;
+L_0xc4f387d40 .extend/s 32, L_0xc4f2a8280;
+L_0xc4eed9ea0 .arith/mult 32, L_0xc4f387ca0, L_0xc4f387d40;
+L_0xc4f2a8140 .part L_0xc4eed9ea0, 31, 1;
+L_0xc4eed9f40 .repeat 8, 8, L_0xc4f2a8140;
+L_0xc4f387de0 .concat [ 32 8 0 0], L_0xc4eed9ea0, L_0xc4eed9f40;
+L_0xc4f387e80 .arith/sum 40, L_0xc4e878370, L_0xc4f387de0;
+S_0xc4f2c8c00 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f2878c0 .param/l "i" 1 5 20, +C4<0111>;
+S_0xc4f2c8d80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2c8c00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ac540 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ac580 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ac5c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f09fd40_0 .net/s *"_ivl_0", 31 0, L_0xc4f387f20;  1 drivers
+v0xc4f09fde0_0 .net/s *"_ivl_2", 31 0, L_0xc4f388000;  1 drivers
+v0xc4f09fe80_0 .net *"_ivl_7", 0 0, L_0xc4f2a8320;  1 drivers
+v0xc4f09ff20_0 .net *"_ivl_9", 7 0, L_0xc4eeda080;  1 drivers
+L_0xc4e8783b8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2cc000_0 .net/s "acc_in", 39 0, L_0xc4e8783b8;  1 drivers
+v0xc4f2cc0a0_0 .net/s "acc_out", 39 0, L_0xc4f388140;  alias, 1 drivers
+v0xc4f2cc140_0 .net/s "product", 31 0, L_0xc4eed9fe0;  1 drivers
+v0xc4f2cc1e0_0 .net/s "product_ext", 39 0, L_0xc4f3880a0;  1 drivers
+v0xc4f2cc280_0 .net/s "w", 15 0, L_0xc4f2a8460;  1 drivers
+v0xc4f2cc320_0 .net/s "x", 15 0, L_0xc4f2a83c0;  1 drivers
+L_0xc4f387f20 .extend/s 32, L_0xc4f2a83c0;
+L_0xc4f388000 .extend/s 32, L_0xc4f2a8460;
+L_0xc4eed9fe0 .arith/mult 32, L_0xc4f387f20, L_0xc4f388000;
+L_0xc4f2a8320 .part L_0xc4eed9fe0, 31, 1;
+L_0xc4eeda080 .repeat 8, 8, L_0xc4f2a8320;
+L_0xc4f3880a0 .concat [ 32 8 0 0], L_0xc4eed9fe0, L_0xc4eeda080;
+L_0xc4f388140 .arith/sum 40, L_0xc4e8783b8, L_0xc4f3880a0;
+S_0xc4f2c8f00 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f2877c0 .param/l "i" 1 5 80, +C4<00>;
+L_0xc4f064310 .functor BUFZ 40, L_0xc4f386f80, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2c9080 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f287900 .param/l "i" 1 5 80, +C4<01>;
+L_0xc4f064380 .functor BUFZ 40, L_0xc4f387200, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2c9200 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f287940 .param/l "i" 1 5 80, +C4<010>;
+L_0xc4f0643f0 .functor BUFZ 40, L_0xc4f387480, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2c9380 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f287980 .param/l "i" 1 5 80, +C4<011>;
+L_0xc4f064460 .functor BUFZ 40, L_0xc4f387700, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2c9500 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f2879c0 .param/l "i" 1 5 80, +C4<0100>;
+L_0xc4f0644d0 .functor BUFZ 40, L_0xc4f387980, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2c9680 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f287a00 .param/l "i" 1 5 80, +C4<0101>;
+L_0xc4f064540 .functor BUFZ 40, L_0xc4f387c00, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2c9800 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f287a40 .param/l "i" 1 5 80, +C4<0110>;
+L_0xc4f0645b0 .functor BUFZ 40, L_0xc4f387e80, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2c9980 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f287a80 .param/l "i" 1 5 80, +C4<0111>;
+L_0xc4f064620 .functor BUFZ 40, L_0xc4f388140, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2c9b00 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f287ac0 .param/l "level" 1 5 92, +C4<00>;
+S_0xc4f2c9c80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f2c9b00;
+ .timescale 0 0;
+P_0xc4f287b00 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3881e0 .arith/sum 40, L_0xc4f064310, L_0xc4f064380;
+S_0xc4f2c9e00 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f2c9b00;
+ .timescale 0 0;
+P_0xc4f287b40 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f388280 .arith/sum 40, L_0xc4f0643f0, L_0xc4f064460;
+S_0xc4f2c9f80 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xc4f2c9b00;
+ .timescale 0 0;
+P_0xc4f287b80 .param/l "node" 1 5 94, +C4<010>;
+L_0xc4f388320 .arith/sum 40, L_0xc4f0644d0, L_0xc4f064540;
+S_0xc4f2ca100 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xc4f2c9b00;
+ .timescale 0 0;
+P_0xc4f287bc0 .param/l "node" 1 5 94, +C4<011>;
+L_0xc4f3883c0 .arith/sum 40, L_0xc4f0645b0, L_0xc4f064620;
+S_0xc4f2ca280 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f287c00 .param/l "level" 1 5 92, +C4<01>;
+S_0xc4f2ca400 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f2ca280;
+ .timescale 0 0;
+P_0xc4f287c40 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f388460 .arith/sum 40, L_0xc4f3881e0, L_0xc4f388280;
+S_0xc4f2ca580 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f2ca280;
+ .timescale 0 0;
+P_0xc4f287c80 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f388500 .arith/sum 40, L_0xc4f388320, L_0xc4f3883c0;
+S_0xc4f2ca700 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0x102d13870;
+ .timescale 0 0;
+P_0xc4f287cc0 .param/l "level" 1 5 92, +C4<010>;
+S_0xc4f2ca880 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f2ca700;
+ .timescale 0 0;
+P_0xc4f287d00 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3885a0 .arith/sum 40, L_0xc4f388460, L_0xc4f388500;
+S_0xc4f2caa00 .scope generate, "GEN_NEURON[1]" "GEN_NEURON[1]" 3 34, 3 34 0, S_0x102d16e70;
+ .timescale 0 0;
+P_0xc4f287d80 .param/l "n" 1 3 34, +C4<01>;
+S_0xc4f2cab80 .scope module, "u_neuron" "neuron_parallel" 3 41, 4 1 0, S_0xc4f2caa00;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "start";
+    .port_info 3 /INPUT 1024 "x_bus";
+    .port_info 4 /INPUT 1024 "w_bus";
+    .port_info 5 /INPUT 16 "bias";
+    .port_info 6 /OUTPUT 16 "y";
+    .port_info 7 /OUTPUT 1 "busy";
+    .port_info 8 /OUTPUT 1 "done";
+P_0x102d0f530 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000101000>;
+P_0x102d0f570 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>;
+P_0x102d0f5b0 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000001000>;
+P_0x102d0f5f0 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000011>;
+P_0x102d0f630 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000001000000>;
+P_0x102d0f670 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>;
+v0xc4f2d9040_0 .net *"_ivl_0", 31 0, L_0xc4f388820;  1 drivers
+v0xc4f2d90e0_0 .net *"_ivl_11", 31 0, L_0xc4eeda300;  1 drivers
+v0xc4f2d9180_0 .net *"_ivl_14", 31 0, L_0xc4f3888c0;  1 drivers
+L_0xc4e8784d8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2d9220_0 .net *"_ivl_17", 28 0, L_0xc4e8784d8;  1 drivers
+L_0xc4e878520 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2d92c0_0 .net/2u *"_ivl_18", 31 0, L_0xc4e878520;  1 drivers
+v0xc4f2d9360_0 .net *"_ivl_21", 31 0, L_0xc4eeda3a0;  1 drivers
+L_0xc4e878568 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2d9400_0 .net/2u *"_ivl_22", 31 0, L_0xc4e878568;  1 drivers
+v0xc4f2d94a0_0 .net *"_ivl_25", 31 0, L_0xc4eeda440;  1 drivers
+v0xc4f2d9540_0 .net *"_ivl_29", 0 0, L_0xc4f2a9720;  1 drivers
+L_0xc4e878400 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2d95e0_0 .net *"_ivl_3", 28 0, L_0xc4e878400;  1 drivers
+v0xc4f2d9680_0 .net *"_ivl_31", 23 0, L_0xc4eedaf80;  1 drivers
+L_0xc4e878448 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2d9720_0 .net/2u *"_ivl_4", 31 0, L_0xc4e878448;  1 drivers
+v0xc4f2d97c0_0 .net *"_ivl_7", 31 0, L_0xc4eeda260;  1 drivers
+L_0xc4e878490 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2d9860_0 .net/2u *"_ivl_8", 31 0, L_0xc4e878490;  1 drivers
+v0xc4f2d9900_0 .var/s "acc", 39 0;
+v0xc4f2d99a0_0 .net/s "acc_next", 39 0, L_0xc4f38a1c0;  1 drivers
+v0xc4f2d9a40_0 .net/s "bias", 15 0, L_0xc4f2a9860;  1 drivers
+v0xc4f2d9ae0_0 .net/s "bias_ext", 39 0, L_0xc4f38a260;  1 drivers
+v0xc4f2d9b80_0 .var "busy", 0 0;
+v0xc4f2d9c20_0 .net "clk", 0 0, o0xc4e845fc0;  alias, 0 drivers
+v0xc4f2d9cc0_0 .var "done", 0 0;
+v0xc4f2d9d60_0 .net/s "final_acc", 39 0, L_0xc4f38a300;  1 drivers
+v0xc4f2d9e00_0 .var "group_index", 2 0;
+v0xc4f2d9ea0_0 .net "rst", 0 0, o0xc4e846080;  alias, 0 drivers
+v0xc4f2d9f40_0 .net "start", 0 0, o0xc4e8460b0;  alias, 0 drivers
+v0xc4f2d9fe0_0 .net/s "w_bus", 1023 0, L_0xc4f2a97c0;  1 drivers
+v0xc4f2da080_0 .net/s "w_group", 127 0, L_0xc4f2a8780;  1 drivers
+v0xc4f2da120_0 .net/s "x_bus", 1023 0, o0xc4e846110;  alias, 0 drivers
+v0xc4f2da1c0_0 .net/s "x_group", 127 0, L_0xc4f2a86e0;  1 drivers
+v0xc4f2da260_0 .var/s "y", 15 0;
+L_0xc4f388820 .concat [ 3 29 0 0], v0xc4f2d9e00_0, L_0xc4e878400;
+L_0xc4eeda260 .arith/mult 32, L_0xc4f388820, L_0xc4e878448;
+L_0xc4eeda300 .arith/mult 32, L_0xc4eeda260, L_0xc4e878490;
+L_0xc4f2a86e0 .part/v o0xc4e846110, L_0xc4eeda300, 128;
+L_0xc4f3888c0 .concat [ 3 29 0 0], v0xc4f2d9e00_0, L_0xc4e8784d8;
+L_0xc4eeda3a0 .arith/mult 32, L_0xc4f3888c0, L_0xc4e878520;
+L_0xc4eeda440 .arith/mult 32, L_0xc4eeda3a0, L_0xc4e878568;
+L_0xc4f2a8780 .part/v L_0xc4f2a97c0, L_0xc4eeda440, 128;
+L_0xc4f2a9720 .part L_0xc4f2a9860, 15, 1;
+L_0xc4eedaf80 .repeat 24, 24, L_0xc4f2a9720;
+L_0xc4f38a260 .concat [ 16 24 0 0], L_0xc4f2a9860, L_0xc4eedaf80;
+L_0xc4f38a300 .arith/sum 40, L_0xc4f38a1c0, L_0xc4f38a260;
+S_0xc4f2cad00 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xc4f2cab80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 128 "x_bus";
+    .port_info 1 /INPUT 128 "w_bus";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4ef0c300 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000101000>;
+P_0xc4ef0c340 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>;
+P_0xc4ef0c380 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>;
+P_0xc4ef0c3c0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>;
+v0xc4f2d8c80_0 .net/s "acc_in", 39 0, v0xc4f2d9900_0;  1 drivers
+v0xc4f2d8d20_0 .net/s "acc_out", 39 0, L_0xc4f38a1c0;  alias, 1 drivers
+v0xc4f2d8dc0 .array "products", 7 0;
+v0xc4f2d8dc0_0 .net/s v0xc4f2d8dc0 0, 39 0, L_0xc4f388b40; 1 drivers
+v0xc4f2d8dc0_1 .net/s v0xc4f2d8dc0 1, 39 0, L_0xc4f388dc0; 1 drivers
+v0xc4f2d8dc0_2 .net/s v0xc4f2d8dc0 2, 39 0, L_0xc4f389040; 1 drivers
+v0xc4f2d8dc0_3 .net/s v0xc4f2d8dc0 3, 39 0, L_0xc4f3892c0; 1 drivers
+v0xc4f2d8dc0_4 .net/s v0xc4f2d8dc0 4, 39 0, L_0xc4f389540; 1 drivers
+v0xc4f2d8dc0_5 .net/s v0xc4f2d8dc0 5, 39 0, L_0xc4f3897c0; 1 drivers
+v0xc4f2d8dc0_6 .net/s v0xc4f2d8dc0 6, 39 0, L_0xc4f389a40; 1 drivers
+v0xc4f2d8dc0_7 .net/s v0xc4f2d8dc0 7, 39 0, L_0xc4f389cc0; 1 drivers
+v0xc4f2d8e60 .array "tree", 31 0;
+v0xc4f2d8e60_0 .net/s v0xc4f2d8e60 0, 39 0, L_0xc4f064690; 1 drivers
+v0xc4f2d8e60_1 .net/s v0xc4f2d8e60 1, 39 0, L_0xc4f064700; 1 drivers
+v0xc4f2d8e60_2 .net/s v0xc4f2d8e60 2, 39 0, L_0xc4f064770; 1 drivers
+v0xc4f2d8e60_3 .net/s v0xc4f2d8e60 3, 39 0, L_0xc4f0647e0; 1 drivers
+v0xc4f2d8e60_4 .net/s v0xc4f2d8e60 4, 39 0, L_0xc4f064850; 1 drivers
+v0xc4f2d8e60_5 .net/s v0xc4f2d8e60 5, 39 0, L_0xc4f0648c0; 1 drivers
+v0xc4f2d8e60_6 .net/s v0xc4f2d8e60 6, 39 0, L_0xc4f064930; 1 drivers
+v0xc4f2d8e60_7 .net/s v0xc4f2d8e60 7, 39 0, L_0xc4f0649a0; 1 drivers
+v0xc4f2d8e60_8 .net/s v0xc4f2d8e60 8, 39 0, L_0xc4f389d60; 1 drivers
+v0xc4f2d8e60_9 .net/s v0xc4f2d8e60 9, 39 0, L_0xc4f389e00; 1 drivers
+v0xc4f2d8e60_10 .net/s v0xc4f2d8e60 10, 39 0, L_0xc4f389ea0; 1 drivers
+v0xc4f2d8e60_11 .net/s v0xc4f2d8e60 11, 39 0, L_0xc4f389f40; 1 drivers
+o0xc4e847ac0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2d8e60_12 .net/s v0xc4f2d8e60 12, 39 0, o0xc4e847ac0; 0 drivers
+o0xc4e847af0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2d8e60_13 .net/s v0xc4f2d8e60 13, 39 0, o0xc4e847af0; 0 drivers
+o0xc4e847b20 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2d8e60_14 .net/s v0xc4f2d8e60 14, 39 0, o0xc4e847b20; 0 drivers
+o0xc4e847b50 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2d8e60_15 .net/s v0xc4f2d8e60 15, 39 0, o0xc4e847b50; 0 drivers
+v0xc4f2d8e60_16 .net/s v0xc4f2d8e60 16, 39 0, L_0xc4f389fe0; 1 drivers
+v0xc4f2d8e60_17 .net/s v0xc4f2d8e60 17, 39 0, L_0xc4f38a080; 1 drivers
+o0xc4e847be0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2d8e60_18 .net/s v0xc4f2d8e60 18, 39 0, o0xc4e847be0; 0 drivers
+o0xc4e847c10 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2d8e60_19 .net/s v0xc4f2d8e60 19, 39 0, o0xc4e847c10; 0 drivers
+o0xc4e847c40 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2d8e60_20 .net/s v0xc4f2d8e60 20, 39 0, o0xc4e847c40; 0 drivers
+o0xc4e847c70 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2d8e60_21 .net/s v0xc4f2d8e60 21, 39 0, o0xc4e847c70; 0 drivers
+o0xc4e847ca0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2d8e60_22 .net/s v0xc4f2d8e60 22, 39 0, o0xc4e847ca0; 0 drivers
+o0xc4e847cd0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2d8e60_23 .net/s v0xc4f2d8e60 23, 39 0, o0xc4e847cd0; 0 drivers
+v0xc4f2d8e60_24 .net/s v0xc4f2d8e60 24, 39 0, L_0xc4f38a120; 1 drivers
+o0xc4e847d30 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2d8e60_25 .net/s v0xc4f2d8e60 25, 39 0, o0xc4e847d30; 0 drivers
+o0xc4e847d60 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2d8e60_26 .net/s v0xc4f2d8e60 26, 39 0, o0xc4e847d60; 0 drivers
+o0xc4e847d90 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2d8e60_27 .net/s v0xc4f2d8e60 27, 39 0, o0xc4e847d90; 0 drivers
+o0xc4e847dc0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2d8e60_28 .net/s v0xc4f2d8e60 28, 39 0, o0xc4e847dc0; 0 drivers
+o0xc4e847df0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2d8e60_29 .net/s v0xc4f2d8e60 29, 39 0, o0xc4e847df0; 0 drivers
+o0xc4e847e20 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2d8e60_30 .net/s v0xc4f2d8e60 30, 39 0, o0xc4e847e20; 0 drivers
+o0xc4e847e50 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2d8e60_31 .net/s v0xc4f2d8e60 31, 39 0, o0xc4e847e50; 0 drivers
+v0xc4f2d8f00_0 .net/s "w_bus", 127 0, L_0xc4f2a8780;  alias, 1 drivers
+v0xc4f2d8fa0_0 .net/s "x_bus", 127 0, L_0xc4f2a86e0;  alias, 1 drivers
+L_0xc4f2a88c0 .part L_0xc4f2a86e0, 0, 16;
+L_0xc4f2a8960 .part L_0xc4f2a8780, 0, 16;
+L_0xc4f2a8aa0 .part L_0xc4f2a86e0, 16, 16;
+L_0xc4f2a8b40 .part L_0xc4f2a8780, 16, 16;
+L_0xc4f2a8c80 .part L_0xc4f2a86e0, 32, 16;
+L_0xc4f2a8d20 .part L_0xc4f2a8780, 32, 16;
+L_0xc4f2a8e60 .part L_0xc4f2a86e0, 48, 16;
+L_0xc4f2a8f00 .part L_0xc4f2a8780, 48, 16;
+L_0xc4f2a9040 .part L_0xc4f2a86e0, 64, 16;
+L_0xc4f2a90e0 .part L_0xc4f2a8780, 64, 16;
+L_0xc4f2a9220 .part L_0xc4f2a86e0, 80, 16;
+L_0xc4f2a92c0 .part L_0xc4f2a8780, 80, 16;
+L_0xc4f2a9400 .part L_0xc4f2a86e0, 96, 16;
+L_0xc4f2a94a0 .part L_0xc4f2a8780, 96, 16;
+L_0xc4f2a95e0 .part L_0xc4f2a86e0, 112, 16;
+L_0xc4f2a9680 .part L_0xc4f2a8780, 112, 16;
+L_0xc4f38a1c0 .arith/sum 40, v0xc4f2d9900_0, L_0xc4f38a120;
+S_0xc4f2cae80 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f287dc0 .param/l "i" 1 5 20, +C4<00>;
+S_0xc4f2cb000 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2cae80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ac600 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ac640 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ac680 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2cda40_0 .net/s *"_ivl_0", 31 0, L_0xc4f388960;  1 drivers
+v0xc4f2cdae0_0 .net/s *"_ivl_2", 31 0, L_0xc4f388a00;  1 drivers
+v0xc4f2cdb80_0 .net *"_ivl_7", 0 0, L_0xc4f2a8820;  1 drivers
+v0xc4f2cdc20_0 .net *"_ivl_9", 7 0, L_0xc4eeda580;  1 drivers
+L_0xc4e8785b0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2cdcc0_0 .net/s "acc_in", 39 0, L_0xc4e8785b0;  1 drivers
+v0xc4f2cdd60_0 .net/s "acc_out", 39 0, L_0xc4f388b40;  alias, 1 drivers
+v0xc4f2cde00_0 .net/s "product", 31 0, L_0xc4eeda4e0;  1 drivers
+v0xc4f2cdea0_0 .net/s "product_ext", 39 0, L_0xc4f388aa0;  1 drivers
+v0xc4f2cdf40_0 .net/s "w", 15 0, L_0xc4f2a8960;  1 drivers
+v0xc4f2cdfe0_0 .net/s "x", 15 0, L_0xc4f2a88c0;  1 drivers
+L_0xc4f388960 .extend/s 32, L_0xc4f2a88c0;
+L_0xc4f388a00 .extend/s 32, L_0xc4f2a8960;
+L_0xc4eeda4e0 .arith/mult 32, L_0xc4f388960, L_0xc4f388a00;
+L_0xc4f2a8820 .part L_0xc4eeda4e0, 31, 1;
+L_0xc4eeda580 .repeat 8, 8, L_0xc4f2a8820;
+L_0xc4f388aa0 .concat [ 32 8 0 0], L_0xc4eeda4e0, L_0xc4eeda580;
+L_0xc4f388b40 .arith/sum 40, L_0xc4e8785b0, L_0xc4f388aa0;
+S_0xc4f2cb180 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f287e00 .param/l "i" 1 5 20, +C4<01>;
+S_0xc4f2cb300 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2cb180;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ac6c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ac700 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ac740 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2ce080_0 .net/s *"_ivl_0", 31 0, L_0xc4f388be0;  1 drivers
+v0xc4f2ce120_0 .net/s *"_ivl_2", 31 0, L_0xc4f388c80;  1 drivers
+v0xc4f2ce1c0_0 .net *"_ivl_7", 0 0, L_0xc4f2a8a00;  1 drivers
+v0xc4f2ce260_0 .net *"_ivl_9", 7 0, L_0xc4eeda6c0;  1 drivers
+L_0xc4e8785f8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2ce300_0 .net/s "acc_in", 39 0, L_0xc4e8785f8;  1 drivers
+v0xc4f2ce3a0_0 .net/s "acc_out", 39 0, L_0xc4f388dc0;  alias, 1 drivers
+v0xc4f2ce440_0 .net/s "product", 31 0, L_0xc4eeda620;  1 drivers
+v0xc4f2ce4e0_0 .net/s "product_ext", 39 0, L_0xc4f388d20;  1 drivers
+v0xc4f2ce580_0 .net/s "w", 15 0, L_0xc4f2a8b40;  1 drivers
+v0xc4f2ce620_0 .net/s "x", 15 0, L_0xc4f2a8aa0;  1 drivers
+L_0xc4f388be0 .extend/s 32, L_0xc4f2a8aa0;
+L_0xc4f388c80 .extend/s 32, L_0xc4f2a8b40;
+L_0xc4eeda620 .arith/mult 32, L_0xc4f388be0, L_0xc4f388c80;
+L_0xc4f2a8a00 .part L_0xc4eeda620, 31, 1;
+L_0xc4eeda6c0 .repeat 8, 8, L_0xc4f2a8a00;
+L_0xc4f388d20 .concat [ 32 8 0 0], L_0xc4eeda620, L_0xc4eeda6c0;
+L_0xc4f388dc0 .arith/sum 40, L_0xc4e8785f8, L_0xc4f388d20;
+S_0xc4f2cb480 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f287e40 .param/l "i" 1 5 20, +C4<010>;
+S_0xc4f2cb600 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2cb480;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ac780 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ac7c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ac800 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2ce6c0_0 .net/s *"_ivl_0", 31 0, L_0xc4f388e60;  1 drivers
+v0xc4f2ce760_0 .net/s *"_ivl_2", 31 0, L_0xc4f388f00;  1 drivers
+v0xc4f2ce800_0 .net *"_ivl_7", 0 0, L_0xc4f2a8be0;  1 drivers
+v0xc4f2ce8a0_0 .net *"_ivl_9", 7 0, L_0xc4eeda800;  1 drivers
+L_0xc4e878640 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2ce940_0 .net/s "acc_in", 39 0, L_0xc4e878640;  1 drivers
+v0xc4f2ce9e0_0 .net/s "acc_out", 39 0, L_0xc4f389040;  alias, 1 drivers
+v0xc4f2cea80_0 .net/s "product", 31 0, L_0xc4eeda760;  1 drivers
+v0xc4f2ceb20_0 .net/s "product_ext", 39 0, L_0xc4f388fa0;  1 drivers
+v0xc4f2cebc0_0 .net/s "w", 15 0, L_0xc4f2a8d20;  1 drivers
+v0xc4f2cec60_0 .net/s "x", 15 0, L_0xc4f2a8c80;  1 drivers
+L_0xc4f388e60 .extend/s 32, L_0xc4f2a8c80;
+L_0xc4f388f00 .extend/s 32, L_0xc4f2a8d20;
+L_0xc4eeda760 .arith/mult 32, L_0xc4f388e60, L_0xc4f388f00;
+L_0xc4f2a8be0 .part L_0xc4eeda760, 31, 1;
+L_0xc4eeda800 .repeat 8, 8, L_0xc4f2a8be0;
+L_0xc4f388fa0 .concat [ 32 8 0 0], L_0xc4eeda760, L_0xc4eeda800;
+L_0xc4f389040 .arith/sum 40, L_0xc4e878640, L_0xc4f388fa0;
+S_0xc4f2cb780 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f287e80 .param/l "i" 1 5 20, +C4<011>;
+S_0xc4f2cb900 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2cb780;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ac840 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ac880 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ac8c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2ced00_0 .net/s *"_ivl_0", 31 0, L_0xc4f3890e0;  1 drivers
+v0xc4f2ceda0_0 .net/s *"_ivl_2", 31 0, L_0xc4f389180;  1 drivers
+v0xc4f2cee40_0 .net *"_ivl_7", 0 0, L_0xc4f2a8dc0;  1 drivers
+v0xc4f2ceee0_0 .net *"_ivl_9", 7 0, L_0xc4eeda940;  1 drivers
+L_0xc4e878688 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2cef80_0 .net/s "acc_in", 39 0, L_0xc4e878688;  1 drivers
+v0xc4f2cf020_0 .net/s "acc_out", 39 0, L_0xc4f3892c0;  alias, 1 drivers
+v0xc4f2cf0c0_0 .net/s "product", 31 0, L_0xc4eeda8a0;  1 drivers
+v0xc4f2cf160_0 .net/s "product_ext", 39 0, L_0xc4f389220;  1 drivers
+v0xc4f2cf200_0 .net/s "w", 15 0, L_0xc4f2a8f00;  1 drivers
+v0xc4f2cf2a0_0 .net/s "x", 15 0, L_0xc4f2a8e60;  1 drivers
+L_0xc4f3890e0 .extend/s 32, L_0xc4f2a8e60;
+L_0xc4f389180 .extend/s 32, L_0xc4f2a8f00;
+L_0xc4eeda8a0 .arith/mult 32, L_0xc4f3890e0, L_0xc4f389180;
+L_0xc4f2a8dc0 .part L_0xc4eeda8a0, 31, 1;
+L_0xc4eeda940 .repeat 8, 8, L_0xc4f2a8dc0;
+L_0xc4f389220 .concat [ 32 8 0 0], L_0xc4eeda8a0, L_0xc4eeda940;
+L_0xc4f3892c0 .arith/sum 40, L_0xc4e878688, L_0xc4f389220;
+S_0xc4f2cba80 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f287f00 .param/l "i" 1 5 20, +C4<0100>;
+S_0xc4f2cbc00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2cba80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ac900 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ac940 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ac980 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2cf340_0 .net/s *"_ivl_0", 31 0, L_0xc4f389360;  1 drivers
+v0xc4f2cf3e0_0 .net/s *"_ivl_2", 31 0, L_0xc4f389400;  1 drivers
+v0xc4f2cf480_0 .net *"_ivl_7", 0 0, L_0xc4f2a8fa0;  1 drivers
+v0xc4f2cf520_0 .net *"_ivl_9", 7 0, L_0xc4eedaa80;  1 drivers
+L_0xc4e8786d0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2cf5c0_0 .net/s "acc_in", 39 0, L_0xc4e8786d0;  1 drivers
+v0xc4f2cf660_0 .net/s "acc_out", 39 0, L_0xc4f389540;  alias, 1 drivers
+v0xc4f2cf700_0 .net/s "product", 31 0, L_0xc4eeda9e0;  1 drivers
+v0xc4f2cf7a0_0 .net/s "product_ext", 39 0, L_0xc4f3894a0;  1 drivers
+v0xc4f2cf840_0 .net/s "w", 15 0, L_0xc4f2a90e0;  1 drivers
+v0xc4f2cf8e0_0 .net/s "x", 15 0, L_0xc4f2a9040;  1 drivers
+L_0xc4f389360 .extend/s 32, L_0xc4f2a9040;
+L_0xc4f389400 .extend/s 32, L_0xc4f2a90e0;
+L_0xc4eeda9e0 .arith/mult 32, L_0xc4f389360, L_0xc4f389400;
+L_0xc4f2a8fa0 .part L_0xc4eeda9e0, 31, 1;
+L_0xc4eedaa80 .repeat 8, 8, L_0xc4f2a8fa0;
+L_0xc4f3894a0 .concat [ 32 8 0 0], L_0xc4eeda9e0, L_0xc4eedaa80;
+L_0xc4f389540 .arith/sum 40, L_0xc4e8786d0, L_0xc4f3894a0;
+S_0xc4f2cbd80 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f287f40 .param/l "i" 1 5 20, +C4<0101>;
+S_0xc4f2d4000 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2cbd80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ac9c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2aca00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2aca40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2cf980_0 .net/s *"_ivl_0", 31 0, L_0xc4f3895e0;  1 drivers
+v0xc4f2cfa20_0 .net/s *"_ivl_2", 31 0, L_0xc4f389680;  1 drivers
+v0xc4f2cfac0_0 .net *"_ivl_7", 0 0, L_0xc4f2a9180;  1 drivers
+v0xc4f2cfb60_0 .net *"_ivl_9", 7 0, L_0xc4eedabc0;  1 drivers
+L_0xc4e878718 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2cfc00_0 .net/s "acc_in", 39 0, L_0xc4e878718;  1 drivers
+v0xc4f2cfca0_0 .net/s "acc_out", 39 0, L_0xc4f3897c0;  alias, 1 drivers
+v0xc4f2cfd40_0 .net/s "product", 31 0, L_0xc4eedab20;  1 drivers
+v0xc4f2cfde0_0 .net/s "product_ext", 39 0, L_0xc4f389720;  1 drivers
+v0xc4f2cfe80_0 .net/s "w", 15 0, L_0xc4f2a92c0;  1 drivers
+v0xc4f2cff20_0 .net/s "x", 15 0, L_0xc4f2a9220;  1 drivers
+L_0xc4f3895e0 .extend/s 32, L_0xc4f2a9220;
+L_0xc4f389680 .extend/s 32, L_0xc4f2a92c0;
+L_0xc4eedab20 .arith/mult 32, L_0xc4f3895e0, L_0xc4f389680;
+L_0xc4f2a9180 .part L_0xc4eedab20, 31, 1;
+L_0xc4eedabc0 .repeat 8, 8, L_0xc4f2a9180;
+L_0xc4f389720 .concat [ 32 8 0 0], L_0xc4eedab20, L_0xc4eedabc0;
+L_0xc4f3897c0 .arith/sum 40, L_0xc4e878718, L_0xc4f389720;
+S_0xc4f2d4180 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f287f80 .param/l "i" 1 5 20, +C4<0110>;
+S_0xc4f2d4300 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2d4180;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2aca80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2acac0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2acb00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2d8000_0 .net/s *"_ivl_0", 31 0, L_0xc4f389860;  1 drivers
+v0xc4f2d80a0_0 .net/s *"_ivl_2", 31 0, L_0xc4f389900;  1 drivers
+v0xc4f2d8140_0 .net *"_ivl_7", 0 0, L_0xc4f2a9360;  1 drivers
+v0xc4f2d81e0_0 .net *"_ivl_9", 7 0, L_0xc4eedad00;  1 drivers
+L_0xc4e878760 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2d8280_0 .net/s "acc_in", 39 0, L_0xc4e878760;  1 drivers
+v0xc4f2d8320_0 .net/s "acc_out", 39 0, L_0xc4f389a40;  alias, 1 drivers
+v0xc4f2d83c0_0 .net/s "product", 31 0, L_0xc4eedac60;  1 drivers
+v0xc4f2d8460_0 .net/s "product_ext", 39 0, L_0xc4f3899a0;  1 drivers
+v0xc4f2d8500_0 .net/s "w", 15 0, L_0xc4f2a94a0;  1 drivers
+v0xc4f2d85a0_0 .net/s "x", 15 0, L_0xc4f2a9400;  1 drivers
+L_0xc4f389860 .extend/s 32, L_0xc4f2a9400;
+L_0xc4f389900 .extend/s 32, L_0xc4f2a94a0;
+L_0xc4eedac60 .arith/mult 32, L_0xc4f389860, L_0xc4f389900;
+L_0xc4f2a9360 .part L_0xc4eedac60, 31, 1;
+L_0xc4eedad00 .repeat 8, 8, L_0xc4f2a9360;
+L_0xc4f3899a0 .concat [ 32 8 0 0], L_0xc4eedac60, L_0xc4eedad00;
+L_0xc4f389a40 .arith/sum 40, L_0xc4e878760, L_0xc4f3899a0;
+S_0xc4f2d4480 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f287fc0 .param/l "i" 1 5 20, +C4<0111>;
+S_0xc4f2d4600 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2d4480;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2acb40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2acb80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2acbc0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2d8640_0 .net/s *"_ivl_0", 31 0, L_0xc4f389ae0;  1 drivers
+v0xc4f2d86e0_0 .net/s *"_ivl_2", 31 0, L_0xc4f389b80;  1 drivers
+v0xc4f2d8780_0 .net *"_ivl_7", 0 0, L_0xc4f2a9540;  1 drivers
+v0xc4f2d8820_0 .net *"_ivl_9", 7 0, L_0xc4eedae40;  1 drivers
+L_0xc4e8787a8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2d88c0_0 .net/s "acc_in", 39 0, L_0xc4e8787a8;  1 drivers
+v0xc4f2d8960_0 .net/s "acc_out", 39 0, L_0xc4f389cc0;  alias, 1 drivers
+v0xc4f2d8a00_0 .net/s "product", 31 0, L_0xc4eedada0;  1 drivers
+v0xc4f2d8aa0_0 .net/s "product_ext", 39 0, L_0xc4f389c20;  1 drivers
+v0xc4f2d8b40_0 .net/s "w", 15 0, L_0xc4f2a9680;  1 drivers
+v0xc4f2d8be0_0 .net/s "x", 15 0, L_0xc4f2a95e0;  1 drivers
+L_0xc4f389ae0 .extend/s 32, L_0xc4f2a95e0;
+L_0xc4f389b80 .extend/s 32, L_0xc4f2a9680;
+L_0xc4eedada0 .arith/mult 32, L_0xc4f389ae0, L_0xc4f389b80;
+L_0xc4f2a9540 .part L_0xc4eedada0, 31, 1;
+L_0xc4eedae40 .repeat 8, 8, L_0xc4f2a9540;
+L_0xc4f389c20 .concat [ 32 8 0 0], L_0xc4eedada0, L_0xc4eedae40;
+L_0xc4f389cc0 .arith/sum 40, L_0xc4e8787a8, L_0xc4f389c20;
+S_0xc4f2d4780 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f287ec0 .param/l "i" 1 5 80, +C4<00>;
+L_0xc4f064690 .functor BUFZ 40, L_0xc4f388b40, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2d4900 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f2dc000 .param/l "i" 1 5 80, +C4<01>;
+L_0xc4f064700 .functor BUFZ 40, L_0xc4f388dc0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2d4a80 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f2dc040 .param/l "i" 1 5 80, +C4<010>;
+L_0xc4f064770 .functor BUFZ 40, L_0xc4f389040, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2d4c00 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f2dc080 .param/l "i" 1 5 80, +C4<011>;
+L_0xc4f0647e0 .functor BUFZ 40, L_0xc4f3892c0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2d4d80 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f2dc0c0 .param/l "i" 1 5 80, +C4<0100>;
+L_0xc4f064850 .functor BUFZ 40, L_0xc4f389540, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2d4f00 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f2dc100 .param/l "i" 1 5 80, +C4<0101>;
+L_0xc4f0648c0 .functor BUFZ 40, L_0xc4f3897c0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2d5080 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f2dc140 .param/l "i" 1 5 80, +C4<0110>;
+L_0xc4f064930 .functor BUFZ 40, L_0xc4f389a40, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2d5200 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f2dc180 .param/l "i" 1 5 80, +C4<0111>;
+L_0xc4f0649a0 .functor BUFZ 40, L_0xc4f389cc0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2d5380 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f2dc1c0 .param/l "level" 1 5 92, +C4<00>;
+S_0xc4f2d5500 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f2d5380;
+ .timescale 0 0;
+P_0xc4f2dc200 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f389d60 .arith/sum 40, L_0xc4f064690, L_0xc4f064700;
+S_0xc4f2d5680 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f2d5380;
+ .timescale 0 0;
+P_0xc4f2dc240 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f389e00 .arith/sum 40, L_0xc4f064770, L_0xc4f0647e0;
+S_0xc4f2d5800 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xc4f2d5380;
+ .timescale 0 0;
+P_0xc4f2dc280 .param/l "node" 1 5 94, +C4<010>;
+L_0xc4f389ea0 .arith/sum 40, L_0xc4f064850, L_0xc4f0648c0;
+S_0xc4f2d5980 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xc4f2d5380;
+ .timescale 0 0;
+P_0xc4f2dc2c0 .param/l "node" 1 5 94, +C4<011>;
+L_0xc4f389f40 .arith/sum 40, L_0xc4f064930, L_0xc4f0649a0;
+S_0xc4f2d5b00 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f2dc300 .param/l "level" 1 5 92, +C4<01>;
+S_0xc4f2d5c80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f2d5b00;
+ .timescale 0 0;
+P_0xc4f2dc340 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f389fe0 .arith/sum 40, L_0xc4f389d60, L_0xc4f389e00;
+S_0xc4f2d5e00 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f2d5b00;
+ .timescale 0 0;
+P_0xc4f2dc380 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f38a080 .arith/sum 40, L_0xc4f389ea0, L_0xc4f389f40;
+S_0xc4f2d5f80 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xc4f2cad00;
+ .timescale 0 0;
+P_0xc4f2dc3c0 .param/l "level" 1 5 92, +C4<010>;
+S_0xc4f2d6100 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f2d5f80;
+ .timescale 0 0;
+P_0xc4f2dc400 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f38a120 .arith/sum 40, L_0xc4f389fe0, L_0xc4f38a080;
+S_0xc4f2d6280 .scope generate, "GEN_NEURON[2]" "GEN_NEURON[2]" 3 34, 3 34 0, S_0x102d16e70;
+ .timescale 0 0;
+P_0xc4f2dc480 .param/l "n" 1 3 34, +C4<010>;
+S_0xc4f2d6400 .scope module, "u_neuron" "neuron_parallel" 3 41, 4 1 0, S_0xc4f2d6280;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "start";
+    .port_info 3 /INPUT 1024 "x_bus";
+    .port_info 4 /INPUT 1024 "w_bus";
+    .port_info 5 /INPUT 16 "bias";
+    .port_info 6 /OUTPUT 16 "y";
+    .port_info 7 /OUTPUT 1 "busy";
+    .port_info 8 /OUTPUT 1 "done";
+P_0x102d08260 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000101000>;
+P_0x102d082a0 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>;
+P_0x102d082e0 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000001000>;
+P_0x102d08320 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000011>;
+P_0x102d08360 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000001000000>;
+P_0x102d083a0 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>;
+v0xc4f2e1900_0 .net *"_ivl_0", 31 0, L_0xc4f38a3a0;  1 drivers
+v0xc4f2e19a0_0 .net *"_ivl_11", 31 0, L_0xc4eedb0c0;  1 drivers
+v0xc4f2e1a40_0 .net *"_ivl_14", 31 0, L_0xc4f38a440;  1 drivers
+L_0xc4e8788c8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2e1ae0_0 .net *"_ivl_17", 28 0, L_0xc4e8788c8;  1 drivers
+L_0xc4e878910 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2e1b80_0 .net/2u *"_ivl_18", 31 0, L_0xc4e878910;  1 drivers
+v0xc4f2e1c20_0 .net *"_ivl_21", 31 0, L_0xc4eedb160;  1 drivers
+L_0xc4e878958 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2e1cc0_0 .net/2u *"_ivl_22", 31 0, L_0xc4e878958;  1 drivers
+v0xc4f2e1d60_0 .net *"_ivl_25", 31 0, L_0xc4eedb200;  1 drivers
+v0xc4f2e1e00_0 .net *"_ivl_29", 0 0, L_0xc4f2aa940;  1 drivers
+L_0xc4e8787f0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2e1ea0_0 .net *"_ivl_3", 28 0, L_0xc4e8787f0;  1 drivers
+v0xc4f2e1f40_0 .net *"_ivl_31", 23 0, L_0xc4eedbd40;  1 drivers
+L_0xc4e878838 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2e1fe0_0 .net/2u *"_ivl_4", 31 0, L_0xc4e878838;  1 drivers
+v0xc4f2e2080_0 .net *"_ivl_7", 31 0, L_0xc4eedb020;  1 drivers
+L_0xc4e878880 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2e2120_0 .net/2u *"_ivl_8", 31 0, L_0xc4e878880;  1 drivers
+v0xc4f2e21c0_0 .var/s "acc", 39 0;
+v0xc4f2e2260_0 .net/s "acc_next", 39 0, L_0xc4f38bd40;  1 drivers
+v0xc4f2e2300_0 .net/s "bias", 15 0, L_0xc4f2aaa80;  1 drivers
+v0xc4f2e23a0_0 .net/s "bias_ext", 39 0, L_0xc4f38bde0;  1 drivers
+v0xc4f2e2440_0 .var "busy", 0 0;
+v0xc4f2e24e0_0 .net "clk", 0 0, o0xc4e845fc0;  alias, 0 drivers
+v0xc4f2e2580_0 .var "done", 0 0;
+v0xc4f2e2620_0 .net/s "final_acc", 39 0, L_0xc4f38be80;  1 drivers
+v0xc4f2e26c0_0 .var "group_index", 2 0;
+v0xc4f2e2760_0 .net "rst", 0 0, o0xc4e846080;  alias, 0 drivers
+v0xc4f2e2800_0 .net "start", 0 0, o0xc4e8460b0;  alias, 0 drivers
+v0xc4f2e28a0_0 .net/s "w_bus", 1023 0, L_0xc4f2aa9e0;  1 drivers
+v0xc4f2e2940_0 .net/s "w_group", 127 0, L_0xc4f2a99a0;  1 drivers
+v0xc4f2e29e0_0 .net/s "x_bus", 1023 0, o0xc4e846110;  alias, 0 drivers
+v0xc4f2e2a80_0 .net/s "x_group", 127 0, L_0xc4f2a9900;  1 drivers
+v0xc4f2e2b20_0 .var/s "y", 15 0;
+L_0xc4f38a3a0 .concat [ 3 29 0 0], v0xc4f2e26c0_0, L_0xc4e8787f0;
+L_0xc4eedb020 .arith/mult 32, L_0xc4f38a3a0, L_0xc4e878838;
+L_0xc4eedb0c0 .arith/mult 32, L_0xc4eedb020, L_0xc4e878880;
+L_0xc4f2a9900 .part/v o0xc4e846110, L_0xc4eedb0c0, 128;
+L_0xc4f38a440 .concat [ 3 29 0 0], v0xc4f2e26c0_0, L_0xc4e8788c8;
+L_0xc4eedb160 .arith/mult 32, L_0xc4f38a440, L_0xc4e878910;
+L_0xc4eedb200 .arith/mult 32, L_0xc4eedb160, L_0xc4e878958;
+L_0xc4f2a99a0 .part/v L_0xc4f2aa9e0, L_0xc4eedb200, 128;
+L_0xc4f2aa940 .part L_0xc4f2aaa80, 15, 1;
+L_0xc4eedbd40 .repeat 24, 24, L_0xc4f2aa940;
+L_0xc4f38bde0 .concat [ 16 24 0 0], L_0xc4f2aaa80, L_0xc4eedbd40;
+L_0xc4f38be80 .arith/sum 40, L_0xc4f38bd40, L_0xc4f38bde0;
+S_0xc4f2d6580 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xc4f2d6400;
+ .timescale 0 0;
+    .port_info 0 /INPUT 128 "x_bus";
+    .port_info 1 /INPUT 128 "w_bus";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4ef0c600 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000101000>;
+P_0xc4ef0c640 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>;
+P_0xc4ef0c680 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>;
+P_0xc4ef0c6c0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>;
+v0xc4f2e1540_0 .net/s "acc_in", 39 0, v0xc4f2e21c0_0;  1 drivers
+v0xc4f2e15e0_0 .net/s "acc_out", 39 0, L_0xc4f38bd40;  alias, 1 drivers
+v0xc4f2e1680 .array "products", 7 0;
+v0xc4f2e1680_0 .net/s v0xc4f2e1680 0, 39 0, L_0xc4f38a6c0; 1 drivers
+v0xc4f2e1680_1 .net/s v0xc4f2e1680 1, 39 0, L_0xc4f38a940; 1 drivers
+v0xc4f2e1680_2 .net/s v0xc4f2e1680 2, 39 0, L_0xc4f38abc0; 1 drivers
+v0xc4f2e1680_3 .net/s v0xc4f2e1680 3, 39 0, L_0xc4f38ae40; 1 drivers
+v0xc4f2e1680_4 .net/s v0xc4f2e1680 4, 39 0, L_0xc4f38b0c0; 1 drivers
+v0xc4f2e1680_5 .net/s v0xc4f2e1680 5, 39 0, L_0xc4f38b340; 1 drivers
+v0xc4f2e1680_6 .net/s v0xc4f2e1680 6, 39 0, L_0xc4f38b5c0; 1 drivers
+v0xc4f2e1680_7 .net/s v0xc4f2e1680 7, 39 0, L_0xc4f38b840; 1 drivers
+v0xc4f2e1720 .array "tree", 31 0;
+v0xc4f2e1720_0 .net/s v0xc4f2e1720 0, 39 0, L_0xc4f064a10; 1 drivers
+v0xc4f2e1720_1 .net/s v0xc4f2e1720 1, 39 0, L_0xc4f064a80; 1 drivers
+v0xc4f2e1720_2 .net/s v0xc4f2e1720 2, 39 0, L_0xc4f064af0; 1 drivers
+v0xc4f2e1720_3 .net/s v0xc4f2e1720 3, 39 0, L_0xc4f064b60; 1 drivers
+v0xc4f2e1720_4 .net/s v0xc4f2e1720 4, 39 0, L_0xc4f064bd0; 1 drivers
+v0xc4f2e1720_5 .net/s v0xc4f2e1720 5, 39 0, L_0xc4f064c40; 1 drivers
+v0xc4f2e1720_6 .net/s v0xc4f2e1720 6, 39 0, L_0xc4f064cb0; 1 drivers
+v0xc4f2e1720_7 .net/s v0xc4f2e1720 7, 39 0, L_0xc4f064d20; 1 drivers
+v0xc4f2e1720_8 .net/s v0xc4f2e1720 8, 39 0, L_0xc4f38b8e0; 1 drivers
+v0xc4f2e1720_9 .net/s v0xc4f2e1720 9, 39 0, L_0xc4f38b980; 1 drivers
+v0xc4f2e1720_10 .net/s v0xc4f2e1720 10, 39 0, L_0xc4f38ba20; 1 drivers
+v0xc4f2e1720_11 .net/s v0xc4f2e1720 11, 39 0, L_0xc4f38bac0; 1 drivers
+o0xc4e849d10 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e1720_12 .net/s v0xc4f2e1720 12, 39 0, o0xc4e849d10; 0 drivers
+o0xc4e849d40 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e1720_13 .net/s v0xc4f2e1720 13, 39 0, o0xc4e849d40; 0 drivers
+o0xc4e849d70 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e1720_14 .net/s v0xc4f2e1720 14, 39 0, o0xc4e849d70; 0 drivers
+o0xc4e849da0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e1720_15 .net/s v0xc4f2e1720 15, 39 0, o0xc4e849da0; 0 drivers
+v0xc4f2e1720_16 .net/s v0xc4f2e1720 16, 39 0, L_0xc4f38bb60; 1 drivers
+v0xc4f2e1720_17 .net/s v0xc4f2e1720 17, 39 0, L_0xc4f38bc00; 1 drivers
+o0xc4e849e30 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e1720_18 .net/s v0xc4f2e1720 18, 39 0, o0xc4e849e30; 0 drivers
+o0xc4e849e60 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e1720_19 .net/s v0xc4f2e1720 19, 39 0, o0xc4e849e60; 0 drivers
+o0xc4e849e90 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e1720_20 .net/s v0xc4f2e1720 20, 39 0, o0xc4e849e90; 0 drivers
+o0xc4e849ec0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e1720_21 .net/s v0xc4f2e1720 21, 39 0, o0xc4e849ec0; 0 drivers
+o0xc4e849ef0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e1720_22 .net/s v0xc4f2e1720 22, 39 0, o0xc4e849ef0; 0 drivers
+o0xc4e849f20 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e1720_23 .net/s v0xc4f2e1720 23, 39 0, o0xc4e849f20; 0 drivers
+v0xc4f2e1720_24 .net/s v0xc4f2e1720 24, 39 0, L_0xc4f38bca0; 1 drivers
+o0xc4e849f80 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e1720_25 .net/s v0xc4f2e1720 25, 39 0, o0xc4e849f80; 0 drivers
+o0xc4e849fb0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e1720_26 .net/s v0xc4f2e1720 26, 39 0, o0xc4e849fb0; 0 drivers
+o0xc4e849fe0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e1720_27 .net/s v0xc4f2e1720 27, 39 0, o0xc4e849fe0; 0 drivers
+o0xc4e84a010 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e1720_28 .net/s v0xc4f2e1720 28, 39 0, o0xc4e84a010; 0 drivers
+o0xc4e84a040 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e1720_29 .net/s v0xc4f2e1720 29, 39 0, o0xc4e84a040; 0 drivers
+o0xc4e84a070 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e1720_30 .net/s v0xc4f2e1720 30, 39 0, o0xc4e84a070; 0 drivers
+o0xc4e84a0a0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e1720_31 .net/s v0xc4f2e1720 31, 39 0, o0xc4e84a0a0; 0 drivers
+v0xc4f2e17c0_0 .net/s "w_bus", 127 0, L_0xc4f2a99a0;  alias, 1 drivers
+v0xc4f2e1860_0 .net/s "x_bus", 127 0, L_0xc4f2a9900;  alias, 1 drivers
+L_0xc4f2a9ae0 .part L_0xc4f2a9900, 0, 16;
+L_0xc4f2a9b80 .part L_0xc4f2a99a0, 0, 16;
+L_0xc4f2a9cc0 .part L_0xc4f2a9900, 16, 16;
+L_0xc4f2a9d60 .part L_0xc4f2a99a0, 16, 16;
+L_0xc4f2a9ea0 .part L_0xc4f2a9900, 32, 16;
+L_0xc4f2a9f40 .part L_0xc4f2a99a0, 32, 16;
+L_0xc4f2aa080 .part L_0xc4f2a9900, 48, 16;
+L_0xc4f2aa120 .part L_0xc4f2a99a0, 48, 16;
+L_0xc4f2aa260 .part L_0xc4f2a9900, 64, 16;
+L_0xc4f2aa300 .part L_0xc4f2a99a0, 64, 16;
+L_0xc4f2aa440 .part L_0xc4f2a9900, 80, 16;
+L_0xc4f2aa4e0 .part L_0xc4f2a99a0, 80, 16;
+L_0xc4f2aa620 .part L_0xc4f2a9900, 96, 16;
+L_0xc4f2aa6c0 .part L_0xc4f2a99a0, 96, 16;
+L_0xc4f2aa800 .part L_0xc4f2a9900, 112, 16;
+L_0xc4f2aa8a0 .part L_0xc4f2a99a0, 112, 16;
+L_0xc4f38bd40 .arith/sum 40, v0xc4f2e21c0_0, L_0xc4f38bca0;
+S_0xc4f2d6700 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dc4c0 .param/l "i" 1 5 20, +C4<00>;
+S_0xc4f2d6880 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2d6700;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2acc00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2acc40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2acc80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2da300_0 .net/s *"_ivl_0", 31 0, L_0xc4f38a4e0;  1 drivers
+v0xc4f2da3a0_0 .net/s *"_ivl_2", 31 0, L_0xc4f38a580;  1 drivers
+v0xc4f2da440_0 .net *"_ivl_7", 0 0, L_0xc4f2a9a40;  1 drivers
+v0xc4f2da4e0_0 .net *"_ivl_9", 7 0, L_0xc4eedb340;  1 drivers
+L_0xc4e8789a0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2da580_0 .net/s "acc_in", 39 0, L_0xc4e8789a0;  1 drivers
+v0xc4f2da620_0 .net/s "acc_out", 39 0, L_0xc4f38a6c0;  alias, 1 drivers
+v0xc4f2da6c0_0 .net/s "product", 31 0, L_0xc4eedb2a0;  1 drivers
+v0xc4f2da760_0 .net/s "product_ext", 39 0, L_0xc4f38a620;  1 drivers
+v0xc4f2da800_0 .net/s "w", 15 0, L_0xc4f2a9b80;  1 drivers
+v0xc4f2da8a0_0 .net/s "x", 15 0, L_0xc4f2a9ae0;  1 drivers
+L_0xc4f38a4e0 .extend/s 32, L_0xc4f2a9ae0;
+L_0xc4f38a580 .extend/s 32, L_0xc4f2a9b80;
+L_0xc4eedb2a0 .arith/mult 32, L_0xc4f38a4e0, L_0xc4f38a580;
+L_0xc4f2a9a40 .part L_0xc4eedb2a0, 31, 1;
+L_0xc4eedb340 .repeat 8, 8, L_0xc4f2a9a40;
+L_0xc4f38a620 .concat [ 32 8 0 0], L_0xc4eedb2a0, L_0xc4eedb340;
+L_0xc4f38a6c0 .arith/sum 40, L_0xc4e8789a0, L_0xc4f38a620;
+S_0xc4f2d6a00 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dc500 .param/l "i" 1 5 20, +C4<01>;
+S_0xc4f2d6b80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2d6a00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2accc0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2acd00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2acd40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2da940_0 .net/s *"_ivl_0", 31 0, L_0xc4f38a760;  1 drivers
+v0xc4f2da9e0_0 .net/s *"_ivl_2", 31 0, L_0xc4f38a800;  1 drivers
+v0xc4f2daa80_0 .net *"_ivl_7", 0 0, L_0xc4f2a9c20;  1 drivers
+v0xc4f2dab20_0 .net *"_ivl_9", 7 0, L_0xc4eedb480;  1 drivers
+L_0xc4e8789e8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2dabc0_0 .net/s "acc_in", 39 0, L_0xc4e8789e8;  1 drivers
+v0xc4f2dac60_0 .net/s "acc_out", 39 0, L_0xc4f38a940;  alias, 1 drivers
+v0xc4f2dad00_0 .net/s "product", 31 0, L_0xc4eedb3e0;  1 drivers
+v0xc4f2dada0_0 .net/s "product_ext", 39 0, L_0xc4f38a8a0;  1 drivers
+v0xc4f2dae40_0 .net/s "w", 15 0, L_0xc4f2a9d60;  1 drivers
+v0xc4f2daee0_0 .net/s "x", 15 0, L_0xc4f2a9cc0;  1 drivers
+L_0xc4f38a760 .extend/s 32, L_0xc4f2a9cc0;
+L_0xc4f38a800 .extend/s 32, L_0xc4f2a9d60;
+L_0xc4eedb3e0 .arith/mult 32, L_0xc4f38a760, L_0xc4f38a800;
+L_0xc4f2a9c20 .part L_0xc4eedb3e0, 31, 1;
+L_0xc4eedb480 .repeat 8, 8, L_0xc4f2a9c20;
+L_0xc4f38a8a0 .concat [ 32 8 0 0], L_0xc4eedb3e0, L_0xc4eedb480;
+L_0xc4f38a940 .arith/sum 40, L_0xc4e8789e8, L_0xc4f38a8a0;
+S_0xc4f2d6d00 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dc540 .param/l "i" 1 5 20, +C4<010>;
+S_0xc4f2d6e80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2d6d00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2acd80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2acdc0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ace00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2daf80_0 .net/s *"_ivl_0", 31 0, L_0xc4f38a9e0;  1 drivers
+v0xc4f2db020_0 .net/s *"_ivl_2", 31 0, L_0xc4f38aa80;  1 drivers
+v0xc4f2db0c0_0 .net *"_ivl_7", 0 0, L_0xc4f2a9e00;  1 drivers
+v0xc4f2db160_0 .net *"_ivl_9", 7 0, L_0xc4eedb5c0;  1 drivers
+L_0xc4e878a30 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2db200_0 .net/s "acc_in", 39 0, L_0xc4e878a30;  1 drivers
+v0xc4f2db2a0_0 .net/s "acc_out", 39 0, L_0xc4f38abc0;  alias, 1 drivers
+v0xc4f2db340_0 .net/s "product", 31 0, L_0xc4eedb520;  1 drivers
+v0xc4f2db3e0_0 .net/s "product_ext", 39 0, L_0xc4f38ab20;  1 drivers
+v0xc4f2db480_0 .net/s "w", 15 0, L_0xc4f2a9f40;  1 drivers
+v0xc4f2db520_0 .net/s "x", 15 0, L_0xc4f2a9ea0;  1 drivers
+L_0xc4f38a9e0 .extend/s 32, L_0xc4f2a9ea0;
+L_0xc4f38aa80 .extend/s 32, L_0xc4f2a9f40;
+L_0xc4eedb520 .arith/mult 32, L_0xc4f38a9e0, L_0xc4f38aa80;
+L_0xc4f2a9e00 .part L_0xc4eedb520, 31, 1;
+L_0xc4eedb5c0 .repeat 8, 8, L_0xc4f2a9e00;
+L_0xc4f38ab20 .concat [ 32 8 0 0], L_0xc4eedb520, L_0xc4eedb5c0;
+L_0xc4f38abc0 .arith/sum 40, L_0xc4e878a30, L_0xc4f38ab20;
+S_0xc4f2d7000 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dc580 .param/l "i" 1 5 20, +C4<011>;
+S_0xc4f2d7180 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2d7000;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ace40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ace80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2acec0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2db5c0_0 .net/s *"_ivl_0", 31 0, L_0xc4f38ac60;  1 drivers
+v0xc4f2db660_0 .net/s *"_ivl_2", 31 0, L_0xc4f38ad00;  1 drivers
+v0xc4f2db700_0 .net *"_ivl_7", 0 0, L_0xc4f2a9fe0;  1 drivers
+v0xc4f2db7a0_0 .net *"_ivl_9", 7 0, L_0xc4eedb700;  1 drivers
+L_0xc4e878a78 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2db840_0 .net/s "acc_in", 39 0, L_0xc4e878a78;  1 drivers
+v0xc4f2db8e0_0 .net/s "acc_out", 39 0, L_0xc4f38ae40;  alias, 1 drivers
+v0xc4f2db980_0 .net/s "product", 31 0, L_0xc4eedb660;  1 drivers
+v0xc4f2dba20_0 .net/s "product_ext", 39 0, L_0xc4f38ada0;  1 drivers
+v0xc4f2dbac0_0 .net/s "w", 15 0, L_0xc4f2aa120;  1 drivers
+v0xc4f2dbb60_0 .net/s "x", 15 0, L_0xc4f2aa080;  1 drivers
+L_0xc4f38ac60 .extend/s 32, L_0xc4f2aa080;
+L_0xc4f38ad00 .extend/s 32, L_0xc4f2aa120;
+L_0xc4eedb660 .arith/mult 32, L_0xc4f38ac60, L_0xc4f38ad00;
+L_0xc4f2a9fe0 .part L_0xc4eedb660, 31, 1;
+L_0xc4eedb700 .repeat 8, 8, L_0xc4f2a9fe0;
+L_0xc4f38ada0 .concat [ 32 8 0 0], L_0xc4eedb660, L_0xc4eedb700;
+L_0xc4f38ae40 .arith/sum 40, L_0xc4e878a78, L_0xc4f38ada0;
+S_0xc4f2d7300 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dc600 .param/l "i" 1 5 20, +C4<0100>;
+S_0xc4f2d7480 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2d7300;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2acf00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2acf40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2acf80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2dbc00_0 .net/s *"_ivl_0", 31 0, L_0xc4f38aee0;  1 drivers
+v0xc4f2dbca0_0 .net/s *"_ivl_2", 31 0, L_0xc4f38af80;  1 drivers
+v0xc4f2dbd40_0 .net *"_ivl_7", 0 0, L_0xc4f2aa1c0;  1 drivers
+v0xc4f2dbde0_0 .net *"_ivl_9", 7 0, L_0xc4eedb840;  1 drivers
+L_0xc4e878ac0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2dbe80_0 .net/s "acc_in", 39 0, L_0xc4e878ac0;  1 drivers
+v0xc4f2dbf20_0 .net/s "acc_out", 39 0, L_0xc4f38b0c0;  alias, 1 drivers
+v0xc4f2e0000_0 .net/s "product", 31 0, L_0xc4eedb7a0;  1 drivers
+v0xc4f2e00a0_0 .net/s "product_ext", 39 0, L_0xc4f38b020;  1 drivers
+v0xc4f2e0140_0 .net/s "w", 15 0, L_0xc4f2aa300;  1 drivers
+v0xc4f2e01e0_0 .net/s "x", 15 0, L_0xc4f2aa260;  1 drivers
+L_0xc4f38aee0 .extend/s 32, L_0xc4f2aa260;
+L_0xc4f38af80 .extend/s 32, L_0xc4f2aa300;
+L_0xc4eedb7a0 .arith/mult 32, L_0xc4f38aee0, L_0xc4f38af80;
+L_0xc4f2aa1c0 .part L_0xc4eedb7a0, 31, 1;
+L_0xc4eedb840 .repeat 8, 8, L_0xc4f2aa1c0;
+L_0xc4f38b020 .concat [ 32 8 0 0], L_0xc4eedb7a0, L_0xc4eedb840;
+L_0xc4f38b0c0 .arith/sum 40, L_0xc4e878ac0, L_0xc4f38b020;
+S_0xc4f2d7600 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dc640 .param/l "i" 1 5 20, +C4<0101>;
+S_0xc4f2d7780 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2d7600;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2acfc0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ad000 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ad040 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2e0280_0 .net/s *"_ivl_0", 31 0, L_0xc4f38b160;  1 drivers
+v0xc4f2e0320_0 .net/s *"_ivl_2", 31 0, L_0xc4f38b200;  1 drivers
+v0xc4f2e03c0_0 .net *"_ivl_7", 0 0, L_0xc4f2aa3a0;  1 drivers
+v0xc4f2e0460_0 .net *"_ivl_9", 7 0, L_0xc4eedb980;  1 drivers
+L_0xc4e878b08 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2e0500_0 .net/s "acc_in", 39 0, L_0xc4e878b08;  1 drivers
+v0xc4f2e05a0_0 .net/s "acc_out", 39 0, L_0xc4f38b340;  alias, 1 drivers
+v0xc4f2e0640_0 .net/s "product", 31 0, L_0xc4eedb8e0;  1 drivers
+v0xc4f2e06e0_0 .net/s "product_ext", 39 0, L_0xc4f38b2a0;  1 drivers
+v0xc4f2e0780_0 .net/s "w", 15 0, L_0xc4f2aa4e0;  1 drivers
+v0xc4f2e0820_0 .net/s "x", 15 0, L_0xc4f2aa440;  1 drivers
+L_0xc4f38b160 .extend/s 32, L_0xc4f2aa440;
+L_0xc4f38b200 .extend/s 32, L_0xc4f2aa4e0;
+L_0xc4eedb8e0 .arith/mult 32, L_0xc4f38b160, L_0xc4f38b200;
+L_0xc4f2aa3a0 .part L_0xc4eedb8e0, 31, 1;
+L_0xc4eedb980 .repeat 8, 8, L_0xc4f2aa3a0;
+L_0xc4f38b2a0 .concat [ 32 8 0 0], L_0xc4eedb8e0, L_0xc4eedb980;
+L_0xc4f38b340 .arith/sum 40, L_0xc4e878b08, L_0xc4f38b2a0;
+S_0xc4f2d7900 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dc680 .param/l "i" 1 5 20, +C4<0110>;
+S_0xc4f2d7a80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2d7900;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ad080 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ad0c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ad100 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2e08c0_0 .net/s *"_ivl_0", 31 0, L_0xc4f38b3e0;  1 drivers
+v0xc4f2e0960_0 .net/s *"_ivl_2", 31 0, L_0xc4f38b480;  1 drivers
+v0xc4f2e0a00_0 .net *"_ivl_7", 0 0, L_0xc4f2aa580;  1 drivers
+v0xc4f2e0aa0_0 .net *"_ivl_9", 7 0, L_0xc4eedbac0;  1 drivers
+L_0xc4e878b50 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2e0b40_0 .net/s "acc_in", 39 0, L_0xc4e878b50;  1 drivers
+v0xc4f2e0be0_0 .net/s "acc_out", 39 0, L_0xc4f38b5c0;  alias, 1 drivers
+v0xc4f2e0c80_0 .net/s "product", 31 0, L_0xc4eedba20;  1 drivers
+v0xc4f2e0d20_0 .net/s "product_ext", 39 0, L_0xc4f38b520;  1 drivers
+v0xc4f2e0dc0_0 .net/s "w", 15 0, L_0xc4f2aa6c0;  1 drivers
+v0xc4f2e0e60_0 .net/s "x", 15 0, L_0xc4f2aa620;  1 drivers
+L_0xc4f38b3e0 .extend/s 32, L_0xc4f2aa620;
+L_0xc4f38b480 .extend/s 32, L_0xc4f2aa6c0;
+L_0xc4eedba20 .arith/mult 32, L_0xc4f38b3e0, L_0xc4f38b480;
+L_0xc4f2aa580 .part L_0xc4eedba20, 31, 1;
+L_0xc4eedbac0 .repeat 8, 8, L_0xc4f2aa580;
+L_0xc4f38b520 .concat [ 32 8 0 0], L_0xc4eedba20, L_0xc4eedbac0;
+L_0xc4f38b5c0 .arith/sum 40, L_0xc4e878b50, L_0xc4f38b520;
+S_0xc4f2d7c00 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dc6c0 .param/l "i" 1 5 20, +C4<0111>;
+S_0xc4f2d7d80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2d7c00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ad140 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ad180 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ad1c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2e0f00_0 .net/s *"_ivl_0", 31 0, L_0xc4f38b660;  1 drivers
+v0xc4f2e0fa0_0 .net/s *"_ivl_2", 31 0, L_0xc4f38b700;  1 drivers
+v0xc4f2e1040_0 .net *"_ivl_7", 0 0, L_0xc4f2aa760;  1 drivers
+v0xc4f2e10e0_0 .net *"_ivl_9", 7 0, L_0xc4eedbc00;  1 drivers
+L_0xc4e878b98 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2e1180_0 .net/s "acc_in", 39 0, L_0xc4e878b98;  1 drivers
+v0xc4f2e1220_0 .net/s "acc_out", 39 0, L_0xc4f38b840;  alias, 1 drivers
+v0xc4f2e12c0_0 .net/s "product", 31 0, L_0xc4eedbb60;  1 drivers
+v0xc4f2e1360_0 .net/s "product_ext", 39 0, L_0xc4f38b7a0;  1 drivers
+v0xc4f2e1400_0 .net/s "w", 15 0, L_0xc4f2aa8a0;  1 drivers
+v0xc4f2e14a0_0 .net/s "x", 15 0, L_0xc4f2aa800;  1 drivers
+L_0xc4f38b660 .extend/s 32, L_0xc4f2aa800;
+L_0xc4f38b700 .extend/s 32, L_0xc4f2aa8a0;
+L_0xc4eedbb60 .arith/mult 32, L_0xc4f38b660, L_0xc4f38b700;
+L_0xc4f2aa760 .part L_0xc4eedbb60, 31, 1;
+L_0xc4eedbc00 .repeat 8, 8, L_0xc4f2aa760;
+L_0xc4f38b7a0 .concat [ 32 8 0 0], L_0xc4eedbb60, L_0xc4eedbc00;
+L_0xc4f38b840 .arith/sum 40, L_0xc4e878b98, L_0xc4f38b7a0;
+S_0xc4f2e4000 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dc5c0 .param/l "i" 1 5 80, +C4<00>;
+L_0xc4f064a10 .functor BUFZ 40, L_0xc4f38a6c0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2e4180 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dc700 .param/l "i" 1 5 80, +C4<01>;
+L_0xc4f064a80 .functor BUFZ 40, L_0xc4f38a940, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2e4300 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dc740 .param/l "i" 1 5 80, +C4<010>;
+L_0xc4f064af0 .functor BUFZ 40, L_0xc4f38abc0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2e4480 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dc780 .param/l "i" 1 5 80, +C4<011>;
+L_0xc4f064b60 .functor BUFZ 40, L_0xc4f38ae40, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2e4600 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dc7c0 .param/l "i" 1 5 80, +C4<0100>;
+L_0xc4f064bd0 .functor BUFZ 40, L_0xc4f38b0c0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2e4780 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dc800 .param/l "i" 1 5 80, +C4<0101>;
+L_0xc4f064c40 .functor BUFZ 40, L_0xc4f38b340, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2e4900 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dc840 .param/l "i" 1 5 80, +C4<0110>;
+L_0xc4f064cb0 .functor BUFZ 40, L_0xc4f38b5c0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2e4a80 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dc880 .param/l "i" 1 5 80, +C4<0111>;
+L_0xc4f064d20 .functor BUFZ 40, L_0xc4f38b840, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2e4c00 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dc8c0 .param/l "level" 1 5 92, +C4<00>;
+S_0xc4f2e4d80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f2e4c00;
+ .timescale 0 0;
+P_0xc4f2dc900 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f38b8e0 .arith/sum 40, L_0xc4f064a10, L_0xc4f064a80;
+S_0xc4f2e4f00 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f2e4c00;
+ .timescale 0 0;
+P_0xc4f2dc940 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f38b980 .arith/sum 40, L_0xc4f064af0, L_0xc4f064b60;
+S_0xc4f2e5080 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xc4f2e4c00;
+ .timescale 0 0;
+P_0xc4f2dc980 .param/l "node" 1 5 94, +C4<010>;
+L_0xc4f38ba20 .arith/sum 40, L_0xc4f064bd0, L_0xc4f064c40;
+S_0xc4f2e5200 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xc4f2e4c00;
+ .timescale 0 0;
+P_0xc4f2dc9c0 .param/l "node" 1 5 94, +C4<011>;
+L_0xc4f38bac0 .arith/sum 40, L_0xc4f064cb0, L_0xc4f064d20;
+S_0xc4f2e5380 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dca00 .param/l "level" 1 5 92, +C4<01>;
+S_0xc4f2e5500 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f2e5380;
+ .timescale 0 0;
+P_0xc4f2dca40 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f38bb60 .arith/sum 40, L_0xc4f38b8e0, L_0xc4f38b980;
+S_0xc4f2e5680 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f2e5380;
+ .timescale 0 0;
+P_0xc4f2dca80 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f38bc00 .arith/sum 40, L_0xc4f38ba20, L_0xc4f38bac0;
+S_0xc4f2e5800 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xc4f2d6580;
+ .timescale 0 0;
+P_0xc4f2dcac0 .param/l "level" 1 5 92, +C4<010>;
+S_0xc4f2e5980 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f2e5800;
+ .timescale 0 0;
+P_0xc4f2dcb00 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f38bca0 .arith/sum 40, L_0xc4f38bb60, L_0xc4f38bc00;
+S_0xc4f2e5b00 .scope generate, "GEN_NEURON[3]" "GEN_NEURON[3]" 3 34, 3 34 0, S_0x102d16e70;
+ .timescale 0 0;
+P_0xc4f2dcb80 .param/l "n" 1 3 34, +C4<011>;
+S_0xc4f2e5c80 .scope module, "u_neuron" "neuron_parallel" 3 41, 4 1 0, S_0xc4f2e5b00;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "start";
+    .port_info 3 /INPUT 1024 "x_bus";
+    .port_info 4 /INPUT 1024 "w_bus";
+    .port_info 5 /INPUT 16 "bias";
+    .port_info 6 /OUTPUT 16 "y";
+    .port_info 7 /OUTPUT 1 "busy";
+    .port_info 8 /OUTPUT 1 "done";
+P_0x102d083e0 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000101000>;
+P_0x102d08420 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>;
+P_0x102d08460 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000001000>;
+P_0x102d084a0 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000011>;
+P_0x102d084e0 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000001000000>;
+P_0x102d08520 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>;
+v0xc4f2ea1c0_0 .net *"_ivl_0", 31 0, L_0xc4f38bf20;  1 drivers
+v0xc4f2ea260_0 .net *"_ivl_11", 31 0, L_0xc4eedbe80;  1 drivers
+v0xc4f2ea300_0 .net *"_ivl_14", 31 0, L_0xc4f390000;  1 drivers
+L_0xc4e878cb8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2ea3a0_0 .net *"_ivl_17", 28 0, L_0xc4e878cb8;  1 drivers
+L_0xc4e878d00 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2ea440_0 .net/2u *"_ivl_18", 31 0, L_0xc4e878d00;  1 drivers
+v0xc4f2ea4e0_0 .net *"_ivl_21", 31 0, L_0xc4eedbf20;  1 drivers
+L_0xc4e878d48 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2ea580_0 .net/2u *"_ivl_22", 31 0, L_0xc4e878d48;  1 drivers
+v0xc4f2ea620_0 .net *"_ivl_25", 31 0, L_0xc4ef40000;  1 drivers
+v0xc4f2ea6c0_0 .net *"_ivl_29", 0 0, L_0xc4f2abb60;  1 drivers
+L_0xc4e878be0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2ea760_0 .net *"_ivl_3", 28 0, L_0xc4e878be0;  1 drivers
+v0xc4f2ea800_0 .net *"_ivl_31", 23 0, L_0xc4ef40b40;  1 drivers
+L_0xc4e878c28 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2ea8a0_0 .net/2u *"_ivl_4", 31 0, L_0xc4e878c28;  1 drivers
+v0xc4f2ea940_0 .net *"_ivl_7", 31 0, L_0xc4eedbde0;  1 drivers
+L_0xc4e878c70 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2ea9e0_0 .net/2u *"_ivl_8", 31 0, L_0xc4e878c70;  1 drivers
+v0xc4f2eaa80_0 .var/s "acc", 39 0;
+v0xc4f2eab20_0 .net/s "acc_next", 39 0, L_0xc4f391900;  1 drivers
+v0xc4f2eabc0_0 .net/s "bias", 15 0, L_0xc4f2abca0;  1 drivers
+v0xc4f2eac60_0 .net/s "bias_ext", 39 0, L_0xc4f3919a0;  1 drivers
+v0xc4f2ead00_0 .var "busy", 0 0;
+v0xc4f2eada0_0 .net "clk", 0 0, o0xc4e845fc0;  alias, 0 drivers
+v0xc4f2eae40_0 .var "done", 0 0;
+v0xc4f2eaee0_0 .net/s "final_acc", 39 0, L_0xc4f391a40;  1 drivers
+v0xc4f2eaf80_0 .var "group_index", 2 0;
+v0xc4f2eb020_0 .net "rst", 0 0, o0xc4e846080;  alias, 0 drivers
+v0xc4f2eb0c0_0 .net "start", 0 0, o0xc4e8460b0;  alias, 0 drivers
+v0xc4f2eb160_0 .net/s "w_bus", 1023 0, L_0xc4f2abc00;  1 drivers
+v0xc4f2eb200_0 .net/s "w_group", 127 0, L_0xc4f2aabc0;  1 drivers
+v0xc4f2eb2a0_0 .net/s "x_bus", 1023 0, o0xc4e846110;  alias, 0 drivers
+v0xc4f2eb340_0 .net/s "x_group", 127 0, L_0xc4f2aab20;  1 drivers
+v0xc4f2eb3e0_0 .var/s "y", 15 0;
+L_0xc4f38bf20 .concat [ 3 29 0 0], v0xc4f2eaf80_0, L_0xc4e878be0;
+L_0xc4eedbde0 .arith/mult 32, L_0xc4f38bf20, L_0xc4e878c28;
+L_0xc4eedbe80 .arith/mult 32, L_0xc4eedbde0, L_0xc4e878c70;
+L_0xc4f2aab20 .part/v o0xc4e846110, L_0xc4eedbe80, 128;
+L_0xc4f390000 .concat [ 3 29 0 0], v0xc4f2eaf80_0, L_0xc4e878cb8;
+L_0xc4eedbf20 .arith/mult 32, L_0xc4f390000, L_0xc4e878d00;
+L_0xc4ef40000 .arith/mult 32, L_0xc4eedbf20, L_0xc4e878d48;
+L_0xc4f2aabc0 .part/v L_0xc4f2abc00, L_0xc4ef40000, 128;
+L_0xc4f2abb60 .part L_0xc4f2abca0, 15, 1;
+L_0xc4ef40b40 .repeat 24, 24, L_0xc4f2abb60;
+L_0xc4f3919a0 .concat [ 16 24 0 0], L_0xc4f2abca0, L_0xc4ef40b40;
+L_0xc4f391a40 .arith/sum 40, L_0xc4f391900, L_0xc4f3919a0;
+S_0xc4f2e5e00 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xc4f2e5c80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 128 "x_bus";
+    .port_info 1 /INPUT 128 "w_bus";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4ef0c900 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000101000>;
+P_0xc4ef0c940 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>;
+P_0xc4ef0c980 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>;
+P_0xc4ef0c9c0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>;
+v0xc4f2e9e00_0 .net/s "acc_in", 39 0, v0xc4f2eaa80_0;  1 drivers
+v0xc4f2e9ea0_0 .net/s "acc_out", 39 0, L_0xc4f391900;  alias, 1 drivers
+v0xc4f2e9f40 .array "products", 7 0;
+v0xc4f2e9f40_0 .net/s v0xc4f2e9f40 0, 39 0, L_0xc4f390280; 1 drivers
+v0xc4f2e9f40_1 .net/s v0xc4f2e9f40 1, 39 0, L_0xc4f390500; 1 drivers
+v0xc4f2e9f40_2 .net/s v0xc4f2e9f40 2, 39 0, L_0xc4f390780; 1 drivers
+v0xc4f2e9f40_3 .net/s v0xc4f2e9f40 3, 39 0, L_0xc4f390a00; 1 drivers
+v0xc4f2e9f40_4 .net/s v0xc4f2e9f40 4, 39 0, L_0xc4f390c80; 1 drivers
+v0xc4f2e9f40_5 .net/s v0xc4f2e9f40 5, 39 0, L_0xc4f390f00; 1 drivers
+v0xc4f2e9f40_6 .net/s v0xc4f2e9f40 6, 39 0, L_0xc4f391180; 1 drivers
+v0xc4f2e9f40_7 .net/s v0xc4f2e9f40 7, 39 0, L_0xc4f391400; 1 drivers
+v0xc4f2e9fe0 .array "tree", 31 0;
+v0xc4f2e9fe0_0 .net/s v0xc4f2e9fe0 0, 39 0, L_0xc4f064d90; 1 drivers
+v0xc4f2e9fe0_1 .net/s v0xc4f2e9fe0 1, 39 0, L_0xc4f064e00; 1 drivers
+v0xc4f2e9fe0_2 .net/s v0xc4f2e9fe0 2, 39 0, L_0xc4f064e70; 1 drivers
+v0xc4f2e9fe0_3 .net/s v0xc4f2e9fe0 3, 39 0, L_0xc4f064ee0; 1 drivers
+v0xc4f2e9fe0_4 .net/s v0xc4f2e9fe0 4, 39 0, L_0xc4f064f50; 1 drivers
+v0xc4f2e9fe0_5 .net/s v0xc4f2e9fe0 5, 39 0, L_0xc4f064fc0; 1 drivers
+v0xc4f2e9fe0_6 .net/s v0xc4f2e9fe0 6, 39 0, L_0xc4f065030; 1 drivers
+v0xc4f2e9fe0_7 .net/s v0xc4f2e9fe0 7, 39 0, L_0xc4f0650a0; 1 drivers
+v0xc4f2e9fe0_8 .net/s v0xc4f2e9fe0 8, 39 0, L_0xc4f3914a0; 1 drivers
+v0xc4f2e9fe0_9 .net/s v0xc4f2e9fe0 9, 39 0, L_0xc4f391540; 1 drivers
+v0xc4f2e9fe0_10 .net/s v0xc4f2e9fe0 10, 39 0, L_0xc4f3915e0; 1 drivers
+v0xc4f2e9fe0_11 .net/s v0xc4f2e9fe0 11, 39 0, L_0xc4f391680; 1 drivers
+o0xc4e84bf60 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e9fe0_12 .net/s v0xc4f2e9fe0 12, 39 0, o0xc4e84bf60; 0 drivers
+o0xc4e84bf90 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e9fe0_13 .net/s v0xc4f2e9fe0 13, 39 0, o0xc4e84bf90; 0 drivers
+o0xc4e84bfc0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e9fe0_14 .net/s v0xc4f2e9fe0 14, 39 0, o0xc4e84bfc0; 0 drivers
+o0xc4e84bff0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e9fe0_15 .net/s v0xc4f2e9fe0 15, 39 0, o0xc4e84bff0; 0 drivers
+v0xc4f2e9fe0_16 .net/s v0xc4f2e9fe0 16, 39 0, L_0xc4f391720; 1 drivers
+v0xc4f2e9fe0_17 .net/s v0xc4f2e9fe0 17, 39 0, L_0xc4f3917c0; 1 drivers
+o0xc4e84c080 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e9fe0_18 .net/s v0xc4f2e9fe0 18, 39 0, o0xc4e84c080; 0 drivers
+o0xc4e84c0b0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e9fe0_19 .net/s v0xc4f2e9fe0 19, 39 0, o0xc4e84c0b0; 0 drivers
+o0xc4e84c0e0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e9fe0_20 .net/s v0xc4f2e9fe0 20, 39 0, o0xc4e84c0e0; 0 drivers
+o0xc4e84c110 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e9fe0_21 .net/s v0xc4f2e9fe0 21, 39 0, o0xc4e84c110; 0 drivers
+o0xc4e84c140 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e9fe0_22 .net/s v0xc4f2e9fe0 22, 39 0, o0xc4e84c140; 0 drivers
+o0xc4e84c170 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e9fe0_23 .net/s v0xc4f2e9fe0 23, 39 0, o0xc4e84c170; 0 drivers
+v0xc4f2e9fe0_24 .net/s v0xc4f2e9fe0 24, 39 0, L_0xc4f391860; 1 drivers
+o0xc4e84c1d0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e9fe0_25 .net/s v0xc4f2e9fe0 25, 39 0, o0xc4e84c1d0; 0 drivers
+o0xc4e84c200 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e9fe0_26 .net/s v0xc4f2e9fe0 26, 39 0, o0xc4e84c200; 0 drivers
+o0xc4e84c230 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e9fe0_27 .net/s v0xc4f2e9fe0 27, 39 0, o0xc4e84c230; 0 drivers
+o0xc4e84c260 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e9fe0_28 .net/s v0xc4f2e9fe0 28, 39 0, o0xc4e84c260; 0 drivers
+o0xc4e84c290 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e9fe0_29 .net/s v0xc4f2e9fe0 29, 39 0, o0xc4e84c290; 0 drivers
+o0xc4e84c2c0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e9fe0_30 .net/s v0xc4f2e9fe0 30, 39 0, o0xc4e84c2c0; 0 drivers
+o0xc4e84c2f0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2e9fe0_31 .net/s v0xc4f2e9fe0 31, 39 0, o0xc4e84c2f0; 0 drivers
+v0xc4f2ea080_0 .net/s "w_bus", 127 0, L_0xc4f2aabc0;  alias, 1 drivers
+v0xc4f2ea120_0 .net/s "x_bus", 127 0, L_0xc4f2aab20;  alias, 1 drivers
+L_0xc4f2aad00 .part L_0xc4f2aab20, 0, 16;
+L_0xc4f2aada0 .part L_0xc4f2aabc0, 0, 16;
+L_0xc4f2aaee0 .part L_0xc4f2aab20, 16, 16;
+L_0xc4f2aaf80 .part L_0xc4f2aabc0, 16, 16;
+L_0xc4f2ab0c0 .part L_0xc4f2aab20, 32, 16;
+L_0xc4f2ab160 .part L_0xc4f2aabc0, 32, 16;
+L_0xc4f2ab2a0 .part L_0xc4f2aab20, 48, 16;
+L_0xc4f2ab340 .part L_0xc4f2aabc0, 48, 16;
+L_0xc4f2ab480 .part L_0xc4f2aab20, 64, 16;
+L_0xc4f2ab520 .part L_0xc4f2aabc0, 64, 16;
+L_0xc4f2ab660 .part L_0xc4f2aab20, 80, 16;
+L_0xc4f2ab700 .part L_0xc4f2aabc0, 80, 16;
+L_0xc4f2ab840 .part L_0xc4f2aab20, 96, 16;
+L_0xc4f2ab8e0 .part L_0xc4f2aabc0, 96, 16;
+L_0xc4f2aba20 .part L_0xc4f2aab20, 112, 16;
+L_0xc4f2abac0 .part L_0xc4f2aabc0, 112, 16;
+L_0xc4f391900 .arith/sum 40, v0xc4f2eaa80_0, L_0xc4f391860;
+S_0xc4f2e5f80 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dcbc0 .param/l "i" 1 5 20, +C4<00>;
+S_0xc4f2e6100 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2e5f80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ad200 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ad240 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ad280 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2e2bc0_0 .net/s *"_ivl_0", 31 0, L_0xc4f3900a0;  1 drivers
+v0xc4f2e2c60_0 .net/s *"_ivl_2", 31 0, L_0xc4f390140;  1 drivers
+v0xc4f2e2d00_0 .net *"_ivl_7", 0 0, L_0xc4f2aac60;  1 drivers
+v0xc4f2e2da0_0 .net *"_ivl_9", 7 0, L_0xc4ef40140;  1 drivers
+L_0xc4e878d90 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2e2e40_0 .net/s "acc_in", 39 0, L_0xc4e878d90;  1 drivers
+v0xc4f2e2ee0_0 .net/s "acc_out", 39 0, L_0xc4f390280;  alias, 1 drivers
+v0xc4f2e2f80_0 .net/s "product", 31 0, L_0xc4ef400a0;  1 drivers
+v0xc4f2e3020_0 .net/s "product_ext", 39 0, L_0xc4f3901e0;  1 drivers
+v0xc4f2e30c0_0 .net/s "w", 15 0, L_0xc4f2aada0;  1 drivers
+v0xc4f2e3160_0 .net/s "x", 15 0, L_0xc4f2aad00;  1 drivers
+L_0xc4f3900a0 .extend/s 32, L_0xc4f2aad00;
+L_0xc4f390140 .extend/s 32, L_0xc4f2aada0;
+L_0xc4ef400a0 .arith/mult 32, L_0xc4f3900a0, L_0xc4f390140;
+L_0xc4f2aac60 .part L_0xc4ef400a0, 31, 1;
+L_0xc4ef40140 .repeat 8, 8, L_0xc4f2aac60;
+L_0xc4f3901e0 .concat [ 32 8 0 0], L_0xc4ef400a0, L_0xc4ef40140;
+L_0xc4f390280 .arith/sum 40, L_0xc4e878d90, L_0xc4f3901e0;
+S_0xc4f2e6280 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dcc00 .param/l "i" 1 5 20, +C4<01>;
+S_0xc4f2e6400 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2e6280;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ad2c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ad300 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ad340 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2e3200_0 .net/s *"_ivl_0", 31 0, L_0xc4f390320;  1 drivers
+v0xc4f2e32a0_0 .net/s *"_ivl_2", 31 0, L_0xc4f3903c0;  1 drivers
+v0xc4f2e3340_0 .net *"_ivl_7", 0 0, L_0xc4f2aae40;  1 drivers
+v0xc4f2e33e0_0 .net *"_ivl_9", 7 0, L_0xc4ef40280;  1 drivers
+L_0xc4e878dd8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2e3480_0 .net/s "acc_in", 39 0, L_0xc4e878dd8;  1 drivers
+v0xc4f2e3520_0 .net/s "acc_out", 39 0, L_0xc4f390500;  alias, 1 drivers
+v0xc4f2e35c0_0 .net/s "product", 31 0, L_0xc4ef401e0;  1 drivers
+v0xc4f2e3660_0 .net/s "product_ext", 39 0, L_0xc4f390460;  1 drivers
+v0xc4f2e3700_0 .net/s "w", 15 0, L_0xc4f2aaf80;  1 drivers
+v0xc4f2e37a0_0 .net/s "x", 15 0, L_0xc4f2aaee0;  1 drivers
+L_0xc4f390320 .extend/s 32, L_0xc4f2aaee0;
+L_0xc4f3903c0 .extend/s 32, L_0xc4f2aaf80;
+L_0xc4ef401e0 .arith/mult 32, L_0xc4f390320, L_0xc4f3903c0;
+L_0xc4f2aae40 .part L_0xc4ef401e0, 31, 1;
+L_0xc4ef40280 .repeat 8, 8, L_0xc4f2aae40;
+L_0xc4f390460 .concat [ 32 8 0 0], L_0xc4ef401e0, L_0xc4ef40280;
+L_0xc4f390500 .arith/sum 40, L_0xc4e878dd8, L_0xc4f390460;
+S_0xc4f2e6580 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dcc40 .param/l "i" 1 5 20, +C4<010>;
+S_0xc4f2e6700 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2e6580;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ad380 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ad3c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ad400 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2e3840_0 .net/s *"_ivl_0", 31 0, L_0xc4f3905a0;  1 drivers
+v0xc4f2e38e0_0 .net/s *"_ivl_2", 31 0, L_0xc4f390640;  1 drivers
+v0xc4f2e3980_0 .net *"_ivl_7", 0 0, L_0xc4f2ab020;  1 drivers
+v0xc4f2e3a20_0 .net *"_ivl_9", 7 0, L_0xc4ef403c0;  1 drivers
+L_0xc4e878e20 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2e3ac0_0 .net/s "acc_in", 39 0, L_0xc4e878e20;  1 drivers
+v0xc4f2e3b60_0 .net/s "acc_out", 39 0, L_0xc4f390780;  alias, 1 drivers
+v0xc4f2e3c00_0 .net/s "product", 31 0, L_0xc4ef40320;  1 drivers
+v0xc4f2e3ca0_0 .net/s "product_ext", 39 0, L_0xc4f3906e0;  1 drivers
+v0xc4f2e3d40_0 .net/s "w", 15 0, L_0xc4f2ab160;  1 drivers
+v0xc4f2e3de0_0 .net/s "x", 15 0, L_0xc4f2ab0c0;  1 drivers
+L_0xc4f3905a0 .extend/s 32, L_0xc4f2ab0c0;
+L_0xc4f390640 .extend/s 32, L_0xc4f2ab160;
+L_0xc4ef40320 .arith/mult 32, L_0xc4f3905a0, L_0xc4f390640;
+L_0xc4f2ab020 .part L_0xc4ef40320, 31, 1;
+L_0xc4ef403c0 .repeat 8, 8, L_0xc4f2ab020;
+L_0xc4f3906e0 .concat [ 32 8 0 0], L_0xc4ef40320, L_0xc4ef403c0;
+L_0xc4f390780 .arith/sum 40, L_0xc4e878e20, L_0xc4f3906e0;
+S_0xc4f2e6880 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dcc80 .param/l "i" 1 5 20, +C4<011>;
+S_0xc4f2e6a00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2e6880;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ad440 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ad480 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ad4c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2e3e80_0 .net/s *"_ivl_0", 31 0, L_0xc4f390820;  1 drivers
+v0xc4f2e3f20_0 .net/s *"_ivl_2", 31 0, L_0xc4f3908c0;  1 drivers
+v0xc4f2e8000_0 .net *"_ivl_7", 0 0, L_0xc4f2ab200;  1 drivers
+v0xc4f2e80a0_0 .net *"_ivl_9", 7 0, L_0xc4ef40500;  1 drivers
+L_0xc4e878e68 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2e8140_0 .net/s "acc_in", 39 0, L_0xc4e878e68;  1 drivers
+v0xc4f2e81e0_0 .net/s "acc_out", 39 0, L_0xc4f390a00;  alias, 1 drivers
+v0xc4f2e8280_0 .net/s "product", 31 0, L_0xc4ef40460;  1 drivers
+v0xc4f2e8320_0 .net/s "product_ext", 39 0, L_0xc4f390960;  1 drivers
+v0xc4f2e83c0_0 .net/s "w", 15 0, L_0xc4f2ab340;  1 drivers
+v0xc4f2e8460_0 .net/s "x", 15 0, L_0xc4f2ab2a0;  1 drivers
+L_0xc4f390820 .extend/s 32, L_0xc4f2ab2a0;
+L_0xc4f3908c0 .extend/s 32, L_0xc4f2ab340;
+L_0xc4ef40460 .arith/mult 32, L_0xc4f390820, L_0xc4f3908c0;
+L_0xc4f2ab200 .part L_0xc4ef40460, 31, 1;
+L_0xc4ef40500 .repeat 8, 8, L_0xc4f2ab200;
+L_0xc4f390960 .concat [ 32 8 0 0], L_0xc4ef40460, L_0xc4ef40500;
+L_0xc4f390a00 .arith/sum 40, L_0xc4e878e68, L_0xc4f390960;
+S_0xc4f2e6b80 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dcd00 .param/l "i" 1 5 20, +C4<0100>;
+S_0xc4f2e6d00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2e6b80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ad500 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ad540 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ad580 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2e8500_0 .net/s *"_ivl_0", 31 0, L_0xc4f390aa0;  1 drivers
+v0xc4f2e85a0_0 .net/s *"_ivl_2", 31 0, L_0xc4f390b40;  1 drivers
+v0xc4f2e8640_0 .net *"_ivl_7", 0 0, L_0xc4f2ab3e0;  1 drivers
+v0xc4f2e86e0_0 .net *"_ivl_9", 7 0, L_0xc4ef40640;  1 drivers
+L_0xc4e878eb0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2e8780_0 .net/s "acc_in", 39 0, L_0xc4e878eb0;  1 drivers
+v0xc4f2e8820_0 .net/s "acc_out", 39 0, L_0xc4f390c80;  alias, 1 drivers
+v0xc4f2e88c0_0 .net/s "product", 31 0, L_0xc4ef405a0;  1 drivers
+v0xc4f2e8960_0 .net/s "product_ext", 39 0, L_0xc4f390be0;  1 drivers
+v0xc4f2e8a00_0 .net/s "w", 15 0, L_0xc4f2ab520;  1 drivers
+v0xc4f2e8aa0_0 .net/s "x", 15 0, L_0xc4f2ab480;  1 drivers
+L_0xc4f390aa0 .extend/s 32, L_0xc4f2ab480;
+L_0xc4f390b40 .extend/s 32, L_0xc4f2ab520;
+L_0xc4ef405a0 .arith/mult 32, L_0xc4f390aa0, L_0xc4f390b40;
+L_0xc4f2ab3e0 .part L_0xc4ef405a0, 31, 1;
+L_0xc4ef40640 .repeat 8, 8, L_0xc4f2ab3e0;
+L_0xc4f390be0 .concat [ 32 8 0 0], L_0xc4ef405a0, L_0xc4ef40640;
+L_0xc4f390c80 .arith/sum 40, L_0xc4e878eb0, L_0xc4f390be0;
+S_0xc4f2e6e80 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dcd40 .param/l "i" 1 5 20, +C4<0101>;
+S_0xc4f2e7000 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2e6e80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ad5c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ad600 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ad640 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2e8b40_0 .net/s *"_ivl_0", 31 0, L_0xc4f390d20;  1 drivers
+v0xc4f2e8be0_0 .net/s *"_ivl_2", 31 0, L_0xc4f390dc0;  1 drivers
+v0xc4f2e8c80_0 .net *"_ivl_7", 0 0, L_0xc4f2ab5c0;  1 drivers
+v0xc4f2e8d20_0 .net *"_ivl_9", 7 0, L_0xc4ef40780;  1 drivers
+L_0xc4e878ef8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2e8dc0_0 .net/s "acc_in", 39 0, L_0xc4e878ef8;  1 drivers
+v0xc4f2e8e60_0 .net/s "acc_out", 39 0, L_0xc4f390f00;  alias, 1 drivers
+v0xc4f2e8f00_0 .net/s "product", 31 0, L_0xc4ef406e0;  1 drivers
+v0xc4f2e8fa0_0 .net/s "product_ext", 39 0, L_0xc4f390e60;  1 drivers
+v0xc4f2e9040_0 .net/s "w", 15 0, L_0xc4f2ab700;  1 drivers
+v0xc4f2e90e0_0 .net/s "x", 15 0, L_0xc4f2ab660;  1 drivers
+L_0xc4f390d20 .extend/s 32, L_0xc4f2ab660;
+L_0xc4f390dc0 .extend/s 32, L_0xc4f2ab700;
+L_0xc4ef406e0 .arith/mult 32, L_0xc4f390d20, L_0xc4f390dc0;
+L_0xc4f2ab5c0 .part L_0xc4ef406e0, 31, 1;
+L_0xc4ef40780 .repeat 8, 8, L_0xc4f2ab5c0;
+L_0xc4f390e60 .concat [ 32 8 0 0], L_0xc4ef406e0, L_0xc4ef40780;
+L_0xc4f390f00 .arith/sum 40, L_0xc4e878ef8, L_0xc4f390e60;
+S_0xc4f2e7180 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dcd80 .param/l "i" 1 5 20, +C4<0110>;
+S_0xc4f2e7300 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2e7180;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ad680 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ad6c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ad700 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2e9180_0 .net/s *"_ivl_0", 31 0, L_0xc4f390fa0;  1 drivers
+v0xc4f2e9220_0 .net/s *"_ivl_2", 31 0, L_0xc4f391040;  1 drivers
+v0xc4f2e92c0_0 .net *"_ivl_7", 0 0, L_0xc4f2ab7a0;  1 drivers
+v0xc4f2e9360_0 .net *"_ivl_9", 7 0, L_0xc4ef408c0;  1 drivers
+L_0xc4e878f40 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2e9400_0 .net/s "acc_in", 39 0, L_0xc4e878f40;  1 drivers
+v0xc4f2e94a0_0 .net/s "acc_out", 39 0, L_0xc4f391180;  alias, 1 drivers
+v0xc4f2e9540_0 .net/s "product", 31 0, L_0xc4ef40820;  1 drivers
+v0xc4f2e95e0_0 .net/s "product_ext", 39 0, L_0xc4f3910e0;  1 drivers
+v0xc4f2e9680_0 .net/s "w", 15 0, L_0xc4f2ab8e0;  1 drivers
+v0xc4f2e9720_0 .net/s "x", 15 0, L_0xc4f2ab840;  1 drivers
+L_0xc4f390fa0 .extend/s 32, L_0xc4f2ab840;
+L_0xc4f391040 .extend/s 32, L_0xc4f2ab8e0;
+L_0xc4ef40820 .arith/mult 32, L_0xc4f390fa0, L_0xc4f391040;
+L_0xc4f2ab7a0 .part L_0xc4ef40820, 31, 1;
+L_0xc4ef408c0 .repeat 8, 8, L_0xc4f2ab7a0;
+L_0xc4f3910e0 .concat [ 32 8 0 0], L_0xc4ef40820, L_0xc4ef408c0;
+L_0xc4f391180 .arith/sum 40, L_0xc4e878f40, L_0xc4f3910e0;
+S_0xc4f2e7480 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dcdc0 .param/l "i" 1 5 20, +C4<0111>;
+S_0xc4f2e7600 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2e7480;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ad740 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ad780 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ad7c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2e97c0_0 .net/s *"_ivl_0", 31 0, L_0xc4f391220;  1 drivers
+v0xc4f2e9860_0 .net/s *"_ivl_2", 31 0, L_0xc4f3912c0;  1 drivers
+v0xc4f2e9900_0 .net *"_ivl_7", 0 0, L_0xc4f2ab980;  1 drivers
+v0xc4f2e99a0_0 .net *"_ivl_9", 7 0, L_0xc4ef40a00;  1 drivers
+L_0xc4e878f88 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2e9a40_0 .net/s "acc_in", 39 0, L_0xc4e878f88;  1 drivers
+v0xc4f2e9ae0_0 .net/s "acc_out", 39 0, L_0xc4f391400;  alias, 1 drivers
+v0xc4f2e9b80_0 .net/s "product", 31 0, L_0xc4ef40960;  1 drivers
+v0xc4f2e9c20_0 .net/s "product_ext", 39 0, L_0xc4f391360;  1 drivers
+v0xc4f2e9cc0_0 .net/s "w", 15 0, L_0xc4f2abac0;  1 drivers
+v0xc4f2e9d60_0 .net/s "x", 15 0, L_0xc4f2aba20;  1 drivers
+L_0xc4f391220 .extend/s 32, L_0xc4f2aba20;
+L_0xc4f3912c0 .extend/s 32, L_0xc4f2abac0;
+L_0xc4ef40960 .arith/mult 32, L_0xc4f391220, L_0xc4f3912c0;
+L_0xc4f2ab980 .part L_0xc4ef40960, 31, 1;
+L_0xc4ef40a00 .repeat 8, 8, L_0xc4f2ab980;
+L_0xc4f391360 .concat [ 32 8 0 0], L_0xc4ef40960, L_0xc4ef40a00;
+L_0xc4f391400 .arith/sum 40, L_0xc4e878f88, L_0xc4f391360;
+S_0xc4f2e7780 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dccc0 .param/l "i" 1 5 80, +C4<00>;
+L_0xc4f064d90 .functor BUFZ 40, L_0xc4f390280, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2e7900 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dce00 .param/l "i" 1 5 80, +C4<01>;
+L_0xc4f064e00 .functor BUFZ 40, L_0xc4f390500, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2e7a80 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dce40 .param/l "i" 1 5 80, +C4<010>;
+L_0xc4f064e70 .functor BUFZ 40, L_0xc4f390780, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2e7c00 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dce80 .param/l "i" 1 5 80, +C4<011>;
+L_0xc4f064ee0 .functor BUFZ 40, L_0xc4f390a00, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2e7d80 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dcec0 .param/l "i" 1 5 80, +C4<0100>;
+L_0xc4f064f50 .functor BUFZ 40, L_0xc4f390c80, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2ec000 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dcf00 .param/l "i" 1 5 80, +C4<0101>;
+L_0xc4f064fc0 .functor BUFZ 40, L_0xc4f390f00, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2ec180 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dcf40 .param/l "i" 1 5 80, +C4<0110>;
+L_0xc4f065030 .functor BUFZ 40, L_0xc4f391180, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2ec300 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dcf80 .param/l "i" 1 5 80, +C4<0111>;
+L_0xc4f0650a0 .functor BUFZ 40, L_0xc4f391400, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2ec480 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dcfc0 .param/l "level" 1 5 92, +C4<00>;
+S_0xc4f2ec600 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f2ec480;
+ .timescale 0 0;
+P_0xc4f2dd000 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3914a0 .arith/sum 40, L_0xc4f064d90, L_0xc4f064e00;
+S_0xc4f2ec780 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f2ec480;
+ .timescale 0 0;
+P_0xc4f2dd040 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f391540 .arith/sum 40, L_0xc4f064e70, L_0xc4f064ee0;
+S_0xc4f2ec900 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xc4f2ec480;
+ .timescale 0 0;
+P_0xc4f2dd080 .param/l "node" 1 5 94, +C4<010>;
+L_0xc4f3915e0 .arith/sum 40, L_0xc4f064f50, L_0xc4f064fc0;
+S_0xc4f2eca80 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xc4f2ec480;
+ .timescale 0 0;
+P_0xc4f2dd0c0 .param/l "node" 1 5 94, +C4<011>;
+L_0xc4f391680 .arith/sum 40, L_0xc4f065030, L_0xc4f0650a0;
+S_0xc4f2ecc00 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dd100 .param/l "level" 1 5 92, +C4<01>;
+S_0xc4f2ecd80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f2ecc00;
+ .timescale 0 0;
+P_0xc4f2dd140 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f391720 .arith/sum 40, L_0xc4f3914a0, L_0xc4f391540;
+S_0xc4f2ecf00 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f2ecc00;
+ .timescale 0 0;
+P_0xc4f2dd180 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3917c0 .arith/sum 40, L_0xc4f3915e0, L_0xc4f391680;
+S_0xc4f2ed080 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xc4f2e5e00;
+ .timescale 0 0;
+P_0xc4f2dd1c0 .param/l "level" 1 5 92, +C4<010>;
+S_0xc4f2ed200 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f2ed080;
+ .timescale 0 0;
+P_0xc4f2dd200 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f391860 .arith/sum 40, L_0xc4f391720, L_0xc4f3917c0;
+S_0xc4f2ed380 .scope generate, "GEN_NEURON[4]" "GEN_NEURON[4]" 3 34, 3 34 0, S_0x102d16e70;
+ .timescale 0 0;
+P_0xc4f2dd2c0 .param/l "n" 1 3 34, +C4<0100>;
+S_0xc4f2ed500 .scope module, "u_neuron" "neuron_parallel" 3 41, 4 1 0, S_0xc4f2ed380;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "start";
+    .port_info 3 /INPUT 1024 "x_bus";
+    .port_info 4 /INPUT 1024 "w_bus";
+    .port_info 5 /INPUT 16 "bias";
+    .port_info 6 /OUTPUT 16 "y";
+    .port_info 7 /OUTPUT 1 "busy";
+    .port_info 8 /OUTPUT 1 "done";
+P_0x102d2bc90 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000101000>;
+P_0x102d2bcd0 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>;
+P_0x102d2bd10 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000001000>;
+P_0x102d2bd50 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000011>;
+P_0x102d2bd90 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000001000000>;
+P_0x102d2bdd0 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>;
+v0xc4f2f2a80_0 .net *"_ivl_0", 31 0, L_0xc4f391ae0;  1 drivers
+v0xc4f2f2b20_0 .net *"_ivl_11", 31 0, L_0xc4ef40c80;  1 drivers
+v0xc4f2f2bc0_0 .net *"_ivl_14", 31 0, L_0xc4f391b80;  1 drivers
+L_0xc4e8790a8 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2f2c60_0 .net *"_ivl_17", 28 0, L_0xc4e8790a8;  1 drivers
+L_0xc4e8790f0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2f2d00_0 .net/2u *"_ivl_18", 31 0, L_0xc4e8790f0;  1 drivers
+v0xc4f2f2da0_0 .net *"_ivl_21", 31 0, L_0xc4ef40d20;  1 drivers
+L_0xc4e879138 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2f2e40_0 .net/2u *"_ivl_22", 31 0, L_0xc4e879138;  1 drivers
+v0xc4f2f2ee0_0 .net *"_ivl_25", 31 0, L_0xc4ef40dc0;  1 drivers
+v0xc4f2f2f80_0 .net *"_ivl_29", 0 0, L_0xc4f394dc0;  1 drivers
+L_0xc4e878fd0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2f3020_0 .net *"_ivl_3", 28 0, L_0xc4e878fd0;  1 drivers
+v0xc4f2f30c0_0 .net *"_ivl_31", 23 0, L_0xc4ef41900;  1 drivers
+L_0xc4e879018 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2f3160_0 .net/2u *"_ivl_4", 31 0, L_0xc4e879018;  1 drivers
+v0xc4f2f3200_0 .net *"_ivl_7", 31 0, L_0xc4ef40be0;  1 drivers
+L_0xc4e879060 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2f32a0_0 .net/2u *"_ivl_8", 31 0, L_0xc4e879060;  1 drivers
+v0xc4f2f3340_0 .var/s "acc", 39 0;
+v0xc4f2f33e0_0 .net/s "acc_next", 39 0, L_0xc4f393480;  1 drivers
+v0xc4f2f3480_0 .net/s "bias", 15 0, L_0xc4f394f00;  1 drivers
+v0xc4f2f3520_0 .net/s "bias_ext", 39 0, L_0xc4f393520;  1 drivers
+v0xc4f2f35c0_0 .var "busy", 0 0;
+v0xc4f2f3660_0 .net "clk", 0 0, o0xc4e845fc0;  alias, 0 drivers
+v0xc4f2f3700_0 .var "done", 0 0;
+v0xc4f2f37a0_0 .net/s "final_acc", 39 0, L_0xc4f3935c0;  1 drivers
+v0xc4f2f3840_0 .var "group_index", 2 0;
+v0xc4f2f38e0_0 .net "rst", 0 0, o0xc4e846080;  alias, 0 drivers
+v0xc4f2f3980_0 .net "start", 0 0, o0xc4e8460b0;  alias, 0 drivers
+v0xc4f2f3a20_0 .net/s "w_bus", 1023 0, L_0xc4f394e60;  1 drivers
+v0xc4f2f3ac0_0 .net/s "w_group", 127 0, L_0xc4f2abde0;  1 drivers
+v0xc4f2f3b60_0 .net/s "x_bus", 1023 0, o0xc4e846110;  alias, 0 drivers
+v0xc4f2f3c00_0 .net/s "x_group", 127 0, L_0xc4f2abd40;  1 drivers
+v0xc4f2f3ca0_0 .var/s "y", 15 0;
+L_0xc4f391ae0 .concat [ 3 29 0 0], v0xc4f2f3840_0, L_0xc4e878fd0;
+L_0xc4ef40be0 .arith/mult 32, L_0xc4f391ae0, L_0xc4e879018;
+L_0xc4ef40c80 .arith/mult 32, L_0xc4ef40be0, L_0xc4e879060;
+L_0xc4f2abd40 .part/v o0xc4e846110, L_0xc4ef40c80, 128;
+L_0xc4f391b80 .concat [ 3 29 0 0], v0xc4f2f3840_0, L_0xc4e8790a8;
+L_0xc4ef40d20 .arith/mult 32, L_0xc4f391b80, L_0xc4e8790f0;
+L_0xc4ef40dc0 .arith/mult 32, L_0xc4ef40d20, L_0xc4e879138;
+L_0xc4f2abde0 .part/v L_0xc4f394e60, L_0xc4ef40dc0, 128;
+L_0xc4f394dc0 .part L_0xc4f394f00, 15, 1;
+L_0xc4ef41900 .repeat 24, 24, L_0xc4f394dc0;
+L_0xc4f393520 .concat [ 16 24 0 0], L_0xc4f394f00, L_0xc4ef41900;
+L_0xc4f3935c0 .arith/sum 40, L_0xc4f393480, L_0xc4f393520;
+S_0xc4f2ed680 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xc4f2ed500;
+ .timescale 0 0;
+    .port_info 0 /INPUT 128 "x_bus";
+    .port_info 1 /INPUT 128 "w_bus";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4ef0cc00 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000101000>;
+P_0xc4ef0cc40 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>;
+P_0xc4ef0cc80 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>;
+P_0xc4ef0ccc0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>;
+v0xc4f2f26c0_0 .net/s "acc_in", 39 0, v0xc4f2f3340_0;  1 drivers
+v0xc4f2f2760_0 .net/s "acc_out", 39 0, L_0xc4f393480;  alias, 1 drivers
+v0xc4f2f2800 .array "products", 7 0;
+v0xc4f2f2800_0 .net/s v0xc4f2f2800 0, 39 0, L_0xc4f391e00; 1 drivers
+v0xc4f2f2800_1 .net/s v0xc4f2f2800 1, 39 0, L_0xc4f392080; 1 drivers
+v0xc4f2f2800_2 .net/s v0xc4f2f2800 2, 39 0, L_0xc4f392300; 1 drivers
+v0xc4f2f2800_3 .net/s v0xc4f2f2800 3, 39 0, L_0xc4f392580; 1 drivers
+v0xc4f2f2800_4 .net/s v0xc4f2f2800 4, 39 0, L_0xc4f392800; 1 drivers
+v0xc4f2f2800_5 .net/s v0xc4f2f2800 5, 39 0, L_0xc4f392a80; 1 drivers
+v0xc4f2f2800_6 .net/s v0xc4f2f2800 6, 39 0, L_0xc4f392d00; 1 drivers
+v0xc4f2f2800_7 .net/s v0xc4f2f2800 7, 39 0, L_0xc4f392f80; 1 drivers
+v0xc4f2f28a0 .array "tree", 31 0;
+v0xc4f2f28a0_0 .net/s v0xc4f2f28a0 0, 39 0, L_0xc4f065110; 1 drivers
+v0xc4f2f28a0_1 .net/s v0xc4f2f28a0 1, 39 0, L_0xc4f065180; 1 drivers
+v0xc4f2f28a0_2 .net/s v0xc4f2f28a0 2, 39 0, L_0xc4f0651f0; 1 drivers
+v0xc4f2f28a0_3 .net/s v0xc4f2f28a0 3, 39 0, L_0xc4f065260; 1 drivers
+v0xc4f2f28a0_4 .net/s v0xc4f2f28a0 4, 39 0, L_0xc4f0652d0; 1 drivers
+v0xc4f2f28a0_5 .net/s v0xc4f2f28a0 5, 39 0, L_0xc4f065340; 1 drivers
+v0xc4f2f28a0_6 .net/s v0xc4f2f28a0 6, 39 0, L_0xc4f0653b0; 1 drivers
+v0xc4f2f28a0_7 .net/s v0xc4f2f28a0 7, 39 0, L_0xc4f065420; 1 drivers
+v0xc4f2f28a0_8 .net/s v0xc4f2f28a0 8, 39 0, L_0xc4f393020; 1 drivers
+v0xc4f2f28a0_9 .net/s v0xc4f2f28a0 9, 39 0, L_0xc4f3930c0; 1 drivers
+v0xc4f2f28a0_10 .net/s v0xc4f2f28a0 10, 39 0, L_0xc4f393160; 1 drivers
+v0xc4f2f28a0_11 .net/s v0xc4f2f28a0 11, 39 0, L_0xc4f393200; 1 drivers
+o0xc4e84e1b0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2f28a0_12 .net/s v0xc4f2f28a0 12, 39 0, o0xc4e84e1b0; 0 drivers
+o0xc4e84e1e0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2f28a0_13 .net/s v0xc4f2f28a0 13, 39 0, o0xc4e84e1e0; 0 drivers
+o0xc4e84e210 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2f28a0_14 .net/s v0xc4f2f28a0 14, 39 0, o0xc4e84e210; 0 drivers
+o0xc4e84e240 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2f28a0_15 .net/s v0xc4f2f28a0 15, 39 0, o0xc4e84e240; 0 drivers
+v0xc4f2f28a0_16 .net/s v0xc4f2f28a0 16, 39 0, L_0xc4f3932a0; 1 drivers
+v0xc4f2f28a0_17 .net/s v0xc4f2f28a0 17, 39 0, L_0xc4f393340; 1 drivers
+o0xc4e84e2d0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2f28a0_18 .net/s v0xc4f2f28a0 18, 39 0, o0xc4e84e2d0; 0 drivers
+o0xc4e84e300 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2f28a0_19 .net/s v0xc4f2f28a0 19, 39 0, o0xc4e84e300; 0 drivers
+o0xc4e84e330 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2f28a0_20 .net/s v0xc4f2f28a0 20, 39 0, o0xc4e84e330; 0 drivers
+o0xc4e84e360 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2f28a0_21 .net/s v0xc4f2f28a0 21, 39 0, o0xc4e84e360; 0 drivers
+o0xc4e84e390 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2f28a0_22 .net/s v0xc4f2f28a0 22, 39 0, o0xc4e84e390; 0 drivers
+o0xc4e84e3c0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2f28a0_23 .net/s v0xc4f2f28a0 23, 39 0, o0xc4e84e3c0; 0 drivers
+v0xc4f2f28a0_24 .net/s v0xc4f2f28a0 24, 39 0, L_0xc4f3933e0; 1 drivers
+o0xc4e84e420 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2f28a0_25 .net/s v0xc4f2f28a0 25, 39 0, o0xc4e84e420; 0 drivers
+o0xc4e84e450 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2f28a0_26 .net/s v0xc4f2f28a0 26, 39 0, o0xc4e84e450; 0 drivers
+o0xc4e84e480 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2f28a0_27 .net/s v0xc4f2f28a0 27, 39 0, o0xc4e84e480; 0 drivers
+o0xc4e84e4b0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2f28a0_28 .net/s v0xc4f2f28a0 28, 39 0, o0xc4e84e4b0; 0 drivers
+o0xc4e84e4e0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2f28a0_29 .net/s v0xc4f2f28a0 29, 39 0, o0xc4e84e4e0; 0 drivers
+o0xc4e84e510 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2f28a0_30 .net/s v0xc4f2f28a0 30, 39 0, o0xc4e84e510; 0 drivers
+o0xc4e84e540 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2f28a0_31 .net/s v0xc4f2f28a0 31, 39 0, o0xc4e84e540; 0 drivers
+v0xc4f2f2940_0 .net/s "w_bus", 127 0, L_0xc4f2abde0;  alias, 1 drivers
+v0xc4f2f29e0_0 .net/s "x_bus", 127 0, L_0xc4f2abd40;  alias, 1 drivers
+L_0xc4f2abf20 .part L_0xc4f2abd40, 0, 16;
+L_0xc4f394000 .part L_0xc4f2abde0, 0, 16;
+L_0xc4f394140 .part L_0xc4f2abd40, 16, 16;
+L_0xc4f3941e0 .part L_0xc4f2abde0, 16, 16;
+L_0xc4f394320 .part L_0xc4f2abd40, 32, 16;
+L_0xc4f3943c0 .part L_0xc4f2abde0, 32, 16;
+L_0xc4f394500 .part L_0xc4f2abd40, 48, 16;
+L_0xc4f3945a0 .part L_0xc4f2abde0, 48, 16;
+L_0xc4f3946e0 .part L_0xc4f2abd40, 64, 16;
+L_0xc4f394780 .part L_0xc4f2abde0, 64, 16;
+L_0xc4f3948c0 .part L_0xc4f2abd40, 80, 16;
+L_0xc4f394960 .part L_0xc4f2abde0, 80, 16;
+L_0xc4f394aa0 .part L_0xc4f2abd40, 96, 16;
+L_0xc4f394b40 .part L_0xc4f2abde0, 96, 16;
+L_0xc4f394c80 .part L_0xc4f2abd40, 112, 16;
+L_0xc4f394d20 .part L_0xc4f2abde0, 112, 16;
+L_0xc4f393480 .arith/sum 40, v0xc4f2f3340_0, L_0xc4f3933e0;
+S_0xc4f2ed800 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd300 .param/l "i" 1 5 20, +C4<00>;
+S_0xc4f2ed980 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2ed800;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ad800 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ad840 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ad880 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2eb480_0 .net/s *"_ivl_0", 31 0, L_0xc4f391c20;  1 drivers
+v0xc4f2eb520_0 .net/s *"_ivl_2", 31 0, L_0xc4f391cc0;  1 drivers
+v0xc4f2eb5c0_0 .net *"_ivl_7", 0 0, L_0xc4f2abe80;  1 drivers
+v0xc4f2eb660_0 .net *"_ivl_9", 7 0, L_0xc4ef40f00;  1 drivers
+L_0xc4e879180 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2eb700_0 .net/s "acc_in", 39 0, L_0xc4e879180;  1 drivers
+v0xc4f2eb7a0_0 .net/s "acc_out", 39 0, L_0xc4f391e00;  alias, 1 drivers
+v0xc4f2eb840_0 .net/s "product", 31 0, L_0xc4ef40e60;  1 drivers
+v0xc4f2eb8e0_0 .net/s "product_ext", 39 0, L_0xc4f391d60;  1 drivers
+v0xc4f2eb980_0 .net/s "w", 15 0, L_0xc4f394000;  1 drivers
+v0xc4f2eba20_0 .net/s "x", 15 0, L_0xc4f2abf20;  1 drivers
+L_0xc4f391c20 .extend/s 32, L_0xc4f2abf20;
+L_0xc4f391cc0 .extend/s 32, L_0xc4f394000;
+L_0xc4ef40e60 .arith/mult 32, L_0xc4f391c20, L_0xc4f391cc0;
+L_0xc4f2abe80 .part L_0xc4ef40e60, 31, 1;
+L_0xc4ef40f00 .repeat 8, 8, L_0xc4f2abe80;
+L_0xc4f391d60 .concat [ 32 8 0 0], L_0xc4ef40e60, L_0xc4ef40f00;
+L_0xc4f391e00 .arith/sum 40, L_0xc4e879180, L_0xc4f391d60;
+S_0xc4f2edb00 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd340 .param/l "i" 1 5 20, +C4<01>;
+S_0xc4f2edc80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2edb00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ad8c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ad900 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ad940 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2ebac0_0 .net/s *"_ivl_0", 31 0, L_0xc4f391ea0;  1 drivers
+v0xc4f2ebb60_0 .net/s *"_ivl_2", 31 0, L_0xc4f391f40;  1 drivers
+v0xc4f2ebc00_0 .net *"_ivl_7", 0 0, L_0xc4f3940a0;  1 drivers
+v0xc4f2ebca0_0 .net *"_ivl_9", 7 0, L_0xc4ef41040;  1 drivers
+L_0xc4e8791c8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2ebd40_0 .net/s "acc_in", 39 0, L_0xc4e8791c8;  1 drivers
+v0xc4f2ebde0_0 .net/s "acc_out", 39 0, L_0xc4f392080;  alias, 1 drivers
+v0xc4f2ebe80_0 .net/s "product", 31 0, L_0xc4ef40fa0;  1 drivers
+v0xc4f2ebf20_0 .net/s "product_ext", 39 0, L_0xc4f391fe0;  1 drivers
+v0xc4f2f0000_0 .net/s "w", 15 0, L_0xc4f3941e0;  1 drivers
+v0xc4f2f00a0_0 .net/s "x", 15 0, L_0xc4f394140;  1 drivers
+L_0xc4f391ea0 .extend/s 32, L_0xc4f394140;
+L_0xc4f391f40 .extend/s 32, L_0xc4f3941e0;
+L_0xc4ef40fa0 .arith/mult 32, L_0xc4f391ea0, L_0xc4f391f40;
+L_0xc4f3940a0 .part L_0xc4ef40fa0, 31, 1;
+L_0xc4ef41040 .repeat 8, 8, L_0xc4f3940a0;
+L_0xc4f391fe0 .concat [ 32 8 0 0], L_0xc4ef40fa0, L_0xc4ef41040;
+L_0xc4f392080 .arith/sum 40, L_0xc4e8791c8, L_0xc4f391fe0;
+S_0xc4f2ede00 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd380 .param/l "i" 1 5 20, +C4<010>;
+S_0xc4f2edf80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2ede00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ad980 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ad9c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ada00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2f0140_0 .net/s *"_ivl_0", 31 0, L_0xc4f392120;  1 drivers
+v0xc4f2f01e0_0 .net/s *"_ivl_2", 31 0, L_0xc4f3921c0;  1 drivers
+v0xc4f2f0280_0 .net *"_ivl_7", 0 0, L_0xc4f394280;  1 drivers
+v0xc4f2f0320_0 .net *"_ivl_9", 7 0, L_0xc4ef41180;  1 drivers
+L_0xc4e879210 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2f03c0_0 .net/s "acc_in", 39 0, L_0xc4e879210;  1 drivers
+v0xc4f2f0460_0 .net/s "acc_out", 39 0, L_0xc4f392300;  alias, 1 drivers
+v0xc4f2f0500_0 .net/s "product", 31 0, L_0xc4ef410e0;  1 drivers
+v0xc4f2f05a0_0 .net/s "product_ext", 39 0, L_0xc4f392260;  1 drivers
+v0xc4f2f0640_0 .net/s "w", 15 0, L_0xc4f3943c0;  1 drivers
+v0xc4f2f06e0_0 .net/s "x", 15 0, L_0xc4f394320;  1 drivers
+L_0xc4f392120 .extend/s 32, L_0xc4f394320;
+L_0xc4f3921c0 .extend/s 32, L_0xc4f3943c0;
+L_0xc4ef410e0 .arith/mult 32, L_0xc4f392120, L_0xc4f3921c0;
+L_0xc4f394280 .part L_0xc4ef410e0, 31, 1;
+L_0xc4ef41180 .repeat 8, 8, L_0xc4f394280;
+L_0xc4f392260 .concat [ 32 8 0 0], L_0xc4ef410e0, L_0xc4ef41180;
+L_0xc4f392300 .arith/sum 40, L_0xc4e879210, L_0xc4f392260;
+S_0xc4f2ee100 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd3c0 .param/l "i" 1 5 20, +C4<011>;
+S_0xc4f2ee280 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2ee100;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ada40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ada80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2adac0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2f0780_0 .net/s *"_ivl_0", 31 0, L_0xc4f3923a0;  1 drivers
+v0xc4f2f0820_0 .net/s *"_ivl_2", 31 0, L_0xc4f392440;  1 drivers
+v0xc4f2f08c0_0 .net *"_ivl_7", 0 0, L_0xc4f394460;  1 drivers
+v0xc4f2f0960_0 .net *"_ivl_9", 7 0, L_0xc4ef412c0;  1 drivers
+L_0xc4e879258 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2f0a00_0 .net/s "acc_in", 39 0, L_0xc4e879258;  1 drivers
+v0xc4f2f0aa0_0 .net/s "acc_out", 39 0, L_0xc4f392580;  alias, 1 drivers
+v0xc4f2f0b40_0 .net/s "product", 31 0, L_0xc4ef41220;  1 drivers
+v0xc4f2f0be0_0 .net/s "product_ext", 39 0, L_0xc4f3924e0;  1 drivers
+v0xc4f2f0c80_0 .net/s "w", 15 0, L_0xc4f3945a0;  1 drivers
+v0xc4f2f0d20_0 .net/s "x", 15 0, L_0xc4f394500;  1 drivers
+L_0xc4f3923a0 .extend/s 32, L_0xc4f394500;
+L_0xc4f392440 .extend/s 32, L_0xc4f3945a0;
+L_0xc4ef41220 .arith/mult 32, L_0xc4f3923a0, L_0xc4f392440;
+L_0xc4f394460 .part L_0xc4ef41220, 31, 1;
+L_0xc4ef412c0 .repeat 8, 8, L_0xc4f394460;
+L_0xc4f3924e0 .concat [ 32 8 0 0], L_0xc4ef41220, L_0xc4ef412c0;
+L_0xc4f392580 .arith/sum 40, L_0xc4e879258, L_0xc4f3924e0;
+S_0xc4f2ee400 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd440 .param/l "i" 1 5 20, +C4<0100>;
+S_0xc4f2ee580 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2ee400;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2adb00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2adb40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2adb80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2f0dc0_0 .net/s *"_ivl_0", 31 0, L_0xc4f392620;  1 drivers
+v0xc4f2f0e60_0 .net/s *"_ivl_2", 31 0, L_0xc4f3926c0;  1 drivers
+v0xc4f2f0f00_0 .net *"_ivl_7", 0 0, L_0xc4f394640;  1 drivers
+v0xc4f2f0fa0_0 .net *"_ivl_9", 7 0, L_0xc4ef41400;  1 drivers
+L_0xc4e8792a0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2f1040_0 .net/s "acc_in", 39 0, L_0xc4e8792a0;  1 drivers
+v0xc4f2f10e0_0 .net/s "acc_out", 39 0, L_0xc4f392800;  alias, 1 drivers
+v0xc4f2f1180_0 .net/s "product", 31 0, L_0xc4ef41360;  1 drivers
+v0xc4f2f1220_0 .net/s "product_ext", 39 0, L_0xc4f392760;  1 drivers
+v0xc4f2f12c0_0 .net/s "w", 15 0, L_0xc4f394780;  1 drivers
+v0xc4f2f1360_0 .net/s "x", 15 0, L_0xc4f3946e0;  1 drivers
+L_0xc4f392620 .extend/s 32, L_0xc4f3946e0;
+L_0xc4f3926c0 .extend/s 32, L_0xc4f394780;
+L_0xc4ef41360 .arith/mult 32, L_0xc4f392620, L_0xc4f3926c0;
+L_0xc4f394640 .part L_0xc4ef41360, 31, 1;
+L_0xc4ef41400 .repeat 8, 8, L_0xc4f394640;
+L_0xc4f392760 .concat [ 32 8 0 0], L_0xc4ef41360, L_0xc4ef41400;
+L_0xc4f392800 .arith/sum 40, L_0xc4e8792a0, L_0xc4f392760;
+S_0xc4f2ee700 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd480 .param/l "i" 1 5 20, +C4<0101>;
+S_0xc4f2ee880 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2ee700;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2adbc0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2adc00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2adc40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2f1400_0 .net/s *"_ivl_0", 31 0, L_0xc4f3928a0;  1 drivers
+v0xc4f2f14a0_0 .net/s *"_ivl_2", 31 0, L_0xc4f392940;  1 drivers
+v0xc4f2f1540_0 .net *"_ivl_7", 0 0, L_0xc4f394820;  1 drivers
+v0xc4f2f15e0_0 .net *"_ivl_9", 7 0, L_0xc4ef41540;  1 drivers
+L_0xc4e8792e8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2f1680_0 .net/s "acc_in", 39 0, L_0xc4e8792e8;  1 drivers
+v0xc4f2f1720_0 .net/s "acc_out", 39 0, L_0xc4f392a80;  alias, 1 drivers
+v0xc4f2f17c0_0 .net/s "product", 31 0, L_0xc4ef414a0;  1 drivers
+v0xc4f2f1860_0 .net/s "product_ext", 39 0, L_0xc4f3929e0;  1 drivers
+v0xc4f2f1900_0 .net/s "w", 15 0, L_0xc4f394960;  1 drivers
+v0xc4f2f19a0_0 .net/s "x", 15 0, L_0xc4f3948c0;  1 drivers
+L_0xc4f3928a0 .extend/s 32, L_0xc4f3948c0;
+L_0xc4f392940 .extend/s 32, L_0xc4f394960;
+L_0xc4ef414a0 .arith/mult 32, L_0xc4f3928a0, L_0xc4f392940;
+L_0xc4f394820 .part L_0xc4ef414a0, 31, 1;
+L_0xc4ef41540 .repeat 8, 8, L_0xc4f394820;
+L_0xc4f3929e0 .concat [ 32 8 0 0], L_0xc4ef414a0, L_0xc4ef41540;
+L_0xc4f392a80 .arith/sum 40, L_0xc4e8792e8, L_0xc4f3929e0;
+S_0xc4f2eea00 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd4c0 .param/l "i" 1 5 20, +C4<0110>;
+S_0xc4f2eeb80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2eea00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2adc80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2adcc0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2add00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2f1a40_0 .net/s *"_ivl_0", 31 0, L_0xc4f392b20;  1 drivers
+v0xc4f2f1ae0_0 .net/s *"_ivl_2", 31 0, L_0xc4f392bc0;  1 drivers
+v0xc4f2f1b80_0 .net *"_ivl_7", 0 0, L_0xc4f394a00;  1 drivers
+v0xc4f2f1c20_0 .net *"_ivl_9", 7 0, L_0xc4ef41680;  1 drivers
+L_0xc4e879330 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2f1cc0_0 .net/s "acc_in", 39 0, L_0xc4e879330;  1 drivers
+v0xc4f2f1d60_0 .net/s "acc_out", 39 0, L_0xc4f392d00;  alias, 1 drivers
+v0xc4f2f1e00_0 .net/s "product", 31 0, L_0xc4ef415e0;  1 drivers
+v0xc4f2f1ea0_0 .net/s "product_ext", 39 0, L_0xc4f392c60;  1 drivers
+v0xc4f2f1f40_0 .net/s "w", 15 0, L_0xc4f394b40;  1 drivers
+v0xc4f2f1fe0_0 .net/s "x", 15 0, L_0xc4f394aa0;  1 drivers
+L_0xc4f392b20 .extend/s 32, L_0xc4f394aa0;
+L_0xc4f392bc0 .extend/s 32, L_0xc4f394b40;
+L_0xc4ef415e0 .arith/mult 32, L_0xc4f392b20, L_0xc4f392bc0;
+L_0xc4f394a00 .part L_0xc4ef415e0, 31, 1;
+L_0xc4ef41680 .repeat 8, 8, L_0xc4f394a00;
+L_0xc4f392c60 .concat [ 32 8 0 0], L_0xc4ef415e0, L_0xc4ef41680;
+L_0xc4f392d00 .arith/sum 40, L_0xc4e879330, L_0xc4f392c60;
+S_0xc4f2eed00 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd500 .param/l "i" 1 5 20, +C4<0111>;
+S_0xc4f2eee80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2eed00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2add40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2add80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2addc0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2f2080_0 .net/s *"_ivl_0", 31 0, L_0xc4f392da0;  1 drivers
+v0xc4f2f2120_0 .net/s *"_ivl_2", 31 0, L_0xc4f392e40;  1 drivers
+v0xc4f2f21c0_0 .net *"_ivl_7", 0 0, L_0xc4f394be0;  1 drivers
+v0xc4f2f2260_0 .net *"_ivl_9", 7 0, L_0xc4ef417c0;  1 drivers
+L_0xc4e879378 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2f2300_0 .net/s "acc_in", 39 0, L_0xc4e879378;  1 drivers
+v0xc4f2f23a0_0 .net/s "acc_out", 39 0, L_0xc4f392f80;  alias, 1 drivers
+v0xc4f2f2440_0 .net/s "product", 31 0, L_0xc4ef41720;  1 drivers
+v0xc4f2f24e0_0 .net/s "product_ext", 39 0, L_0xc4f392ee0;  1 drivers
+v0xc4f2f2580_0 .net/s "w", 15 0, L_0xc4f394d20;  1 drivers
+v0xc4f2f2620_0 .net/s "x", 15 0, L_0xc4f394c80;  1 drivers
+L_0xc4f392da0 .extend/s 32, L_0xc4f394c80;
+L_0xc4f392e40 .extend/s 32, L_0xc4f394d20;
+L_0xc4ef41720 .arith/mult 32, L_0xc4f392da0, L_0xc4f392e40;
+L_0xc4f394be0 .part L_0xc4ef41720, 31, 1;
+L_0xc4ef417c0 .repeat 8, 8, L_0xc4f394be0;
+L_0xc4f392ee0 .concat [ 32 8 0 0], L_0xc4ef41720, L_0xc4ef417c0;
+L_0xc4f392f80 .arith/sum 40, L_0xc4e879378, L_0xc4f392ee0;
+S_0xc4f2ef000 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd400 .param/l "i" 1 5 80, +C4<00>;
+L_0xc4f065110 .functor BUFZ 40, L_0xc4f391e00, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2ef180 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd540 .param/l "i" 1 5 80, +C4<01>;
+L_0xc4f065180 .functor BUFZ 40, L_0xc4f392080, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2ef300 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd580 .param/l "i" 1 5 80, +C4<010>;
+L_0xc4f0651f0 .functor BUFZ 40, L_0xc4f392300, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2ef480 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd5c0 .param/l "i" 1 5 80, +C4<011>;
+L_0xc4f065260 .functor BUFZ 40, L_0xc4f392580, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2ef600 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd600 .param/l "i" 1 5 80, +C4<0100>;
+L_0xc4f0652d0 .functor BUFZ 40, L_0xc4f392800, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2ef780 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd640 .param/l "i" 1 5 80, +C4<0101>;
+L_0xc4f065340 .functor BUFZ 40, L_0xc4f392a80, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2ef900 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd680 .param/l "i" 1 5 80, +C4<0110>;
+L_0xc4f0653b0 .functor BUFZ 40, L_0xc4f392d00, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2efa80 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd6c0 .param/l "i" 1 5 80, +C4<0111>;
+L_0xc4f065420 .functor BUFZ 40, L_0xc4f392f80, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2efc00 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd700 .param/l "level" 1 5 92, +C4<00>;
+S_0xc4f2efd80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f2efc00;
+ .timescale 0 0;
+P_0xc4f2dd740 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f393020 .arith/sum 40, L_0xc4f065110, L_0xc4f065180;
+S_0xc4f2f8000 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f2efc00;
+ .timescale 0 0;
+P_0xc4f2dd780 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3930c0 .arith/sum 40, L_0xc4f0651f0, L_0xc4f065260;
+S_0xc4f2f8180 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xc4f2efc00;
+ .timescale 0 0;
+P_0xc4f2dd7c0 .param/l "node" 1 5 94, +C4<010>;
+L_0xc4f393160 .arith/sum 40, L_0xc4f0652d0, L_0xc4f065340;
+S_0xc4f2f8300 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xc4f2efc00;
+ .timescale 0 0;
+P_0xc4f2dd800 .param/l "node" 1 5 94, +C4<011>;
+L_0xc4f393200 .arith/sum 40, L_0xc4f0653b0, L_0xc4f065420;
+S_0xc4f2f8480 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd840 .param/l "level" 1 5 92, +C4<01>;
+S_0xc4f2f8600 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f2f8480;
+ .timescale 0 0;
+P_0xc4f2dd880 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3932a0 .arith/sum 40, L_0xc4f393020, L_0xc4f3930c0;
+S_0xc4f2f8780 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f2f8480;
+ .timescale 0 0;
+P_0xc4f2dd8c0 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f393340 .arith/sum 40, L_0xc4f393160, L_0xc4f393200;
+S_0xc4f2f8900 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xc4f2ed680;
+ .timescale 0 0;
+P_0xc4f2dd900 .param/l "level" 1 5 92, +C4<010>;
+S_0xc4f2f8a80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f2f8900;
+ .timescale 0 0;
+P_0xc4f2dd940 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3933e0 .arith/sum 40, L_0xc4f3932a0, L_0xc4f393340;
+S_0xc4f2f8c00 .scope generate, "GEN_NEURON[5]" "GEN_NEURON[5]" 3 34, 3 34 0, S_0x102d16e70;
+ .timescale 0 0;
+P_0xc4f2dd9c0 .param/l "n" 1 3 34, +C4<0101>;
+S_0xc4f2f8d80 .scope module, "u_neuron" "neuron_parallel" 3 41, 4 1 0, S_0xc4f2f8c00;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "start";
+    .port_info 3 /INPUT 1024 "x_bus";
+    .port_info 4 /INPUT 1024 "w_bus";
+    .port_info 5 /INPUT 16 "bias";
+    .port_info 6 /OUTPUT 16 "y";
+    .port_info 7 /OUTPUT 1 "busy";
+    .port_info 8 /OUTPUT 1 "done";
+P_0x102d27d90 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000101000>;
+P_0x102d27dd0 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>;
+P_0x102d27e10 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000001000>;
+P_0x102d27e50 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000011>;
+P_0x102d27e90 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000001000000>;
+P_0x102d27ed0 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>;
+v0xc4f2ff340_0 .net *"_ivl_0", 31 0, L_0xc4f393660;  1 drivers
+v0xc4f2ff3e0_0 .net *"_ivl_11", 31 0, L_0xc4ef41a40;  1 drivers
+v0xc4f2ff480_0 .net *"_ivl_14", 31 0, L_0xc4f393700;  1 drivers
+L_0xc4e879498 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2ff520_0 .net *"_ivl_17", 28 0, L_0xc4e879498;  1 drivers
+L_0xc4e8794e0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2ff5c0_0 .net/2u *"_ivl_18", 31 0, L_0xc4e8794e0;  1 drivers
+v0xc4f2ff660_0 .net *"_ivl_21", 31 0, L_0xc4ef41ae0;  1 drivers
+L_0xc4e879528 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2ff700_0 .net/2u *"_ivl_22", 31 0, L_0xc4e879528;  1 drivers
+v0xc4f2ff7a0_0 .net *"_ivl_25", 31 0, L_0xc4ef41b80;  1 drivers
+v0xc4f2ff840_0 .net *"_ivl_29", 0 0, L_0xc4f395fe0;  1 drivers
+L_0xc4e8793c0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2ff8e0_0 .net *"_ivl_3", 28 0, L_0xc4e8793c0;  1 drivers
+v0xc4f2ff980_0 .net *"_ivl_31", 23 0, L_0xc4ef426c0;  1 drivers
+L_0xc4e879408 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2ffa20_0 .net/2u *"_ivl_4", 31 0, L_0xc4e879408;  1 drivers
+v0xc4f2ffac0_0 .net *"_ivl_7", 31 0, L_0xc4ef419a0;  1 drivers
+L_0xc4e879450 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2ffb60_0 .net/2u *"_ivl_8", 31 0, L_0xc4e879450;  1 drivers
+v0xc4f2ffc00_0 .var/s "acc", 39 0;
+v0xc4f2ffca0_0 .net/s "acc_next", 39 0, L_0xc4f399040;  1 drivers
+v0xc4f2ffd40_0 .net/s "bias", 15 0, L_0xc4f396120;  1 drivers
+v0xc4f2ffde0_0 .net/s "bias_ext", 39 0, L_0xc4f3990e0;  1 drivers
+v0xc4f2ffe80_0 .var "busy", 0 0;
+v0xc4f2fff20_0 .net "clk", 0 0, o0xc4e845fc0;  alias, 0 drivers
+v0xc4f304000_0 .var "done", 0 0;
+v0xc4f3040a0_0 .net/s "final_acc", 39 0, L_0xc4f399180;  1 drivers
+v0xc4f304140_0 .var "group_index", 2 0;
+v0xc4f3041e0_0 .net "rst", 0 0, o0xc4e846080;  alias, 0 drivers
+v0xc4f304280_0 .net "start", 0 0, o0xc4e8460b0;  alias, 0 drivers
+v0xc4f304320_0 .net/s "w_bus", 1023 0, L_0xc4f396080;  1 drivers
+v0xc4f3043c0_0 .net/s "w_group", 127 0, L_0xc4f395040;  1 drivers
+v0xc4f304460_0 .net/s "x_bus", 1023 0, o0xc4e846110;  alias, 0 drivers
+v0xc4f304500_0 .net/s "x_group", 127 0, L_0xc4f394fa0;  1 drivers
+v0xc4f3045a0_0 .var/s "y", 15 0;
+L_0xc4f393660 .concat [ 3 29 0 0], v0xc4f304140_0, L_0xc4e8793c0;
+L_0xc4ef419a0 .arith/mult 32, L_0xc4f393660, L_0xc4e879408;
+L_0xc4ef41a40 .arith/mult 32, L_0xc4ef419a0, L_0xc4e879450;
+L_0xc4f394fa0 .part/v o0xc4e846110, L_0xc4ef41a40, 128;
+L_0xc4f393700 .concat [ 3 29 0 0], v0xc4f304140_0, L_0xc4e879498;
+L_0xc4ef41ae0 .arith/mult 32, L_0xc4f393700, L_0xc4e8794e0;
+L_0xc4ef41b80 .arith/mult 32, L_0xc4ef41ae0, L_0xc4e879528;
+L_0xc4f395040 .part/v L_0xc4f396080, L_0xc4ef41b80, 128;
+L_0xc4f395fe0 .part L_0xc4f396120, 15, 1;
+L_0xc4ef426c0 .repeat 24, 24, L_0xc4f395fe0;
+L_0xc4f3990e0 .concat [ 16 24 0 0], L_0xc4f396120, L_0xc4ef426c0;
+L_0xc4f399180 .arith/sum 40, L_0xc4f399040, L_0xc4f3990e0;
+S_0xc4f2f8f00 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xc4f2f8d80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 128 "x_bus";
+    .port_info 1 /INPUT 128 "w_bus";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4ef0cf00 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000101000>;
+P_0xc4ef0cf40 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>;
+P_0xc4ef0cf80 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>;
+P_0xc4ef0cfc0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>;
+v0xc4f2fef80_0 .net/s "acc_in", 39 0, v0xc4f2ffc00_0;  1 drivers
+v0xc4f2ff020_0 .net/s "acc_out", 39 0, L_0xc4f399040;  alias, 1 drivers
+v0xc4f2ff0c0 .array "products", 7 0;
+v0xc4f2ff0c0_0 .net/s v0xc4f2ff0c0 0, 39 0, L_0xc4f393980; 1 drivers
+v0xc4f2ff0c0_1 .net/s v0xc4f2ff0c0 1, 39 0, L_0xc4f393c00; 1 drivers
+v0xc4f2ff0c0_2 .net/s v0xc4f2ff0c0 2, 39 0, L_0xc4f393e80; 1 drivers
+v0xc4f2ff0c0_3 .net/s v0xc4f2ff0c0 3, 39 0, L_0xc4f398140; 1 drivers
+v0xc4f2ff0c0_4 .net/s v0xc4f2ff0c0 4, 39 0, L_0xc4f3983c0; 1 drivers
+v0xc4f2ff0c0_5 .net/s v0xc4f2ff0c0 5, 39 0, L_0xc4f398640; 1 drivers
+v0xc4f2ff0c0_6 .net/s v0xc4f2ff0c0 6, 39 0, L_0xc4f3988c0; 1 drivers
+v0xc4f2ff0c0_7 .net/s v0xc4f2ff0c0 7, 39 0, L_0xc4f398b40; 1 drivers
+v0xc4f2ff160 .array "tree", 31 0;
+v0xc4f2ff160_0 .net/s v0xc4f2ff160 0, 39 0, L_0xc4f065490; 1 drivers
+v0xc4f2ff160_1 .net/s v0xc4f2ff160 1, 39 0, L_0xc4f065500; 1 drivers
+v0xc4f2ff160_2 .net/s v0xc4f2ff160 2, 39 0, L_0xc4f065570; 1 drivers
+v0xc4f2ff160_3 .net/s v0xc4f2ff160 3, 39 0, L_0xc4f0655e0; 1 drivers
+v0xc4f2ff160_4 .net/s v0xc4f2ff160 4, 39 0, L_0xc4f065650; 1 drivers
+v0xc4f2ff160_5 .net/s v0xc4f2ff160 5, 39 0, L_0xc4f0656c0; 1 drivers
+v0xc4f2ff160_6 .net/s v0xc4f2ff160 6, 39 0, L_0xc4f065730; 1 drivers
+v0xc4f2ff160_7 .net/s v0xc4f2ff160 7, 39 0, L_0xc4f0657a0; 1 drivers
+v0xc4f2ff160_8 .net/s v0xc4f2ff160 8, 39 0, L_0xc4f398be0; 1 drivers
+v0xc4f2ff160_9 .net/s v0xc4f2ff160 9, 39 0, L_0xc4f398c80; 1 drivers
+v0xc4f2ff160_10 .net/s v0xc4f2ff160 10, 39 0, L_0xc4f398d20; 1 drivers
+v0xc4f2ff160_11 .net/s v0xc4f2ff160 11, 39 0, L_0xc4f398dc0; 1 drivers
+o0xc4e850400 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2ff160_12 .net/s v0xc4f2ff160 12, 39 0, o0xc4e850400; 0 drivers
+o0xc4e850430 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2ff160_13 .net/s v0xc4f2ff160 13, 39 0, o0xc4e850430; 0 drivers
+o0xc4e850460 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2ff160_14 .net/s v0xc4f2ff160 14, 39 0, o0xc4e850460; 0 drivers
+o0xc4e850490 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2ff160_15 .net/s v0xc4f2ff160 15, 39 0, o0xc4e850490; 0 drivers
+v0xc4f2ff160_16 .net/s v0xc4f2ff160 16, 39 0, L_0xc4f398e60; 1 drivers
+v0xc4f2ff160_17 .net/s v0xc4f2ff160 17, 39 0, L_0xc4f398f00; 1 drivers
+o0xc4e850520 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2ff160_18 .net/s v0xc4f2ff160 18, 39 0, o0xc4e850520; 0 drivers
+o0xc4e850550 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2ff160_19 .net/s v0xc4f2ff160 19, 39 0, o0xc4e850550; 0 drivers
+o0xc4e850580 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2ff160_20 .net/s v0xc4f2ff160 20, 39 0, o0xc4e850580; 0 drivers
+o0xc4e8505b0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2ff160_21 .net/s v0xc4f2ff160 21, 39 0, o0xc4e8505b0; 0 drivers
+o0xc4e8505e0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2ff160_22 .net/s v0xc4f2ff160 22, 39 0, o0xc4e8505e0; 0 drivers
+o0xc4e850610 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2ff160_23 .net/s v0xc4f2ff160 23, 39 0, o0xc4e850610; 0 drivers
+v0xc4f2ff160_24 .net/s v0xc4f2ff160 24, 39 0, L_0xc4f398fa0; 1 drivers
+o0xc4e850670 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2ff160_25 .net/s v0xc4f2ff160 25, 39 0, o0xc4e850670; 0 drivers
+o0xc4e8506a0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2ff160_26 .net/s v0xc4f2ff160 26, 39 0, o0xc4e8506a0; 0 drivers
+o0xc4e8506d0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2ff160_27 .net/s v0xc4f2ff160 27, 39 0, o0xc4e8506d0; 0 drivers
+o0xc4e850700 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2ff160_28 .net/s v0xc4f2ff160 28, 39 0, o0xc4e850700; 0 drivers
+o0xc4e850730 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2ff160_29 .net/s v0xc4f2ff160 29, 39 0, o0xc4e850730; 0 drivers
+o0xc4e850760 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2ff160_30 .net/s v0xc4f2ff160 30, 39 0, o0xc4e850760; 0 drivers
+o0xc4e850790 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f2ff160_31 .net/s v0xc4f2ff160 31, 39 0, o0xc4e850790; 0 drivers
+v0xc4f2ff200_0 .net/s "w_bus", 127 0, L_0xc4f395040;  alias, 1 drivers
+v0xc4f2ff2a0_0 .net/s "x_bus", 127 0, L_0xc4f394fa0;  alias, 1 drivers
+L_0xc4f395180 .part L_0xc4f394fa0, 0, 16;
+L_0xc4f395220 .part L_0xc4f395040, 0, 16;
+L_0xc4f395360 .part L_0xc4f394fa0, 16, 16;
+L_0xc4f395400 .part L_0xc4f395040, 16, 16;
+L_0xc4f395540 .part L_0xc4f394fa0, 32, 16;
+L_0xc4f3955e0 .part L_0xc4f395040, 32, 16;
+L_0xc4f395720 .part L_0xc4f394fa0, 48, 16;
+L_0xc4f3957c0 .part L_0xc4f395040, 48, 16;
+L_0xc4f395900 .part L_0xc4f394fa0, 64, 16;
+L_0xc4f3959a0 .part L_0xc4f395040, 64, 16;
+L_0xc4f395ae0 .part L_0xc4f394fa0, 80, 16;
+L_0xc4f395b80 .part L_0xc4f395040, 80, 16;
+L_0xc4f395cc0 .part L_0xc4f394fa0, 96, 16;
+L_0xc4f395d60 .part L_0xc4f395040, 96, 16;
+L_0xc4f395ea0 .part L_0xc4f394fa0, 112, 16;
+L_0xc4f395f40 .part L_0xc4f395040, 112, 16;
+L_0xc4f399040 .arith/sum 40, v0xc4f2ffc00_0, L_0xc4f398fa0;
+S_0xc4f2f9080 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2dda00 .param/l "i" 1 5 20, +C4<00>;
+S_0xc4f2f9200 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2f9080;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ade00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ade40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ade80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2f3d40_0 .net/s *"_ivl_0", 31 0, L_0xc4f3937a0;  1 drivers
+v0xc4f2f3de0_0 .net/s *"_ivl_2", 31 0, L_0xc4f393840;  1 drivers
+v0xc4f2f3e80_0 .net *"_ivl_7", 0 0, L_0xc4f3950e0;  1 drivers
+v0xc4f2f3f20_0 .net *"_ivl_9", 7 0, L_0xc4ef41cc0;  1 drivers
+L_0xc4e879570 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2fc000_0 .net/s "acc_in", 39 0, L_0xc4e879570;  1 drivers
+v0xc4f2fc0a0_0 .net/s "acc_out", 39 0, L_0xc4f393980;  alias, 1 drivers
+v0xc4f2fc140_0 .net/s "product", 31 0, L_0xc4ef41c20;  1 drivers
+v0xc4f2fc1e0_0 .net/s "product_ext", 39 0, L_0xc4f3938e0;  1 drivers
+v0xc4f2fc280_0 .net/s "w", 15 0, L_0xc4f395220;  1 drivers
+v0xc4f2fc320_0 .net/s "x", 15 0, L_0xc4f395180;  1 drivers
+L_0xc4f3937a0 .extend/s 32, L_0xc4f395180;
+L_0xc4f393840 .extend/s 32, L_0xc4f395220;
+L_0xc4ef41c20 .arith/mult 32, L_0xc4f3937a0, L_0xc4f393840;
+L_0xc4f3950e0 .part L_0xc4ef41c20, 31, 1;
+L_0xc4ef41cc0 .repeat 8, 8, L_0xc4f3950e0;
+L_0xc4f3938e0 .concat [ 32 8 0 0], L_0xc4ef41c20, L_0xc4ef41cc0;
+L_0xc4f393980 .arith/sum 40, L_0xc4e879570, L_0xc4f3938e0;
+S_0xc4f2f9380 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2dda40 .param/l "i" 1 5 20, +C4<01>;
+S_0xc4f2f9500 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2f9380;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2adec0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2adf00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2adf40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2fc3c0_0 .net/s *"_ivl_0", 31 0, L_0xc4f393a20;  1 drivers
+v0xc4f2fc460_0 .net/s *"_ivl_2", 31 0, L_0xc4f393ac0;  1 drivers
+v0xc4f2fc500_0 .net *"_ivl_7", 0 0, L_0xc4f3952c0;  1 drivers
+v0xc4f2fc5a0_0 .net *"_ivl_9", 7 0, L_0xc4ef41e00;  1 drivers
+L_0xc4e8795b8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2fc640_0 .net/s "acc_in", 39 0, L_0xc4e8795b8;  1 drivers
+v0xc4f2fc6e0_0 .net/s "acc_out", 39 0, L_0xc4f393c00;  alias, 1 drivers
+v0xc4f2fc780_0 .net/s "product", 31 0, L_0xc4ef41d60;  1 drivers
+v0xc4f2fc820_0 .net/s "product_ext", 39 0, L_0xc4f393b60;  1 drivers
+v0xc4f2fc8c0_0 .net/s "w", 15 0, L_0xc4f395400;  1 drivers
+v0xc4f2fc960_0 .net/s "x", 15 0, L_0xc4f395360;  1 drivers
+L_0xc4f393a20 .extend/s 32, L_0xc4f395360;
+L_0xc4f393ac0 .extend/s 32, L_0xc4f395400;
+L_0xc4ef41d60 .arith/mult 32, L_0xc4f393a20, L_0xc4f393ac0;
+L_0xc4f3952c0 .part L_0xc4ef41d60, 31, 1;
+L_0xc4ef41e00 .repeat 8, 8, L_0xc4f3952c0;
+L_0xc4f393b60 .concat [ 32 8 0 0], L_0xc4ef41d60, L_0xc4ef41e00;
+L_0xc4f393c00 .arith/sum 40, L_0xc4e8795b8, L_0xc4f393b60;
+S_0xc4f2f9680 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2dda80 .param/l "i" 1 5 20, +C4<010>;
+S_0xc4f2f9800 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2f9680;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2adf80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2adfc0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ae000 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2fca00_0 .net/s *"_ivl_0", 31 0, L_0xc4f393ca0;  1 drivers
+v0xc4f2fcaa0_0 .net/s *"_ivl_2", 31 0, L_0xc4f393d40;  1 drivers
+v0xc4f2fcb40_0 .net *"_ivl_7", 0 0, L_0xc4f3954a0;  1 drivers
+v0xc4f2fcbe0_0 .net *"_ivl_9", 7 0, L_0xc4ef41f40;  1 drivers
+L_0xc4e879600 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2fcc80_0 .net/s "acc_in", 39 0, L_0xc4e879600;  1 drivers
+v0xc4f2fcd20_0 .net/s "acc_out", 39 0, L_0xc4f393e80;  alias, 1 drivers
+v0xc4f2fcdc0_0 .net/s "product", 31 0, L_0xc4ef41ea0;  1 drivers
+v0xc4f2fce60_0 .net/s "product_ext", 39 0, L_0xc4f393de0;  1 drivers
+v0xc4f2fcf00_0 .net/s "w", 15 0, L_0xc4f3955e0;  1 drivers
+v0xc4f2fcfa0_0 .net/s "x", 15 0, L_0xc4f395540;  1 drivers
+L_0xc4f393ca0 .extend/s 32, L_0xc4f395540;
+L_0xc4f393d40 .extend/s 32, L_0xc4f3955e0;
+L_0xc4ef41ea0 .arith/mult 32, L_0xc4f393ca0, L_0xc4f393d40;
+L_0xc4f3954a0 .part L_0xc4ef41ea0, 31, 1;
+L_0xc4ef41f40 .repeat 8, 8, L_0xc4f3954a0;
+L_0xc4f393de0 .concat [ 32 8 0 0], L_0xc4ef41ea0, L_0xc4ef41f40;
+L_0xc4f393e80 .arith/sum 40, L_0xc4e879600, L_0xc4f393de0;
+S_0xc4f2f9980 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2ddac0 .param/l "i" 1 5 20, +C4<011>;
+S_0xc4f2f9b00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2f9980;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ae040 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ae080 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ae0c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2fd040_0 .net/s *"_ivl_0", 31 0, L_0xc4f393f20;  1 drivers
+v0xc4f2fd0e0_0 .net/s *"_ivl_2", 31 0, L_0xc4f398000;  1 drivers
+v0xc4f2fd180_0 .net *"_ivl_7", 0 0, L_0xc4f395680;  1 drivers
+v0xc4f2fd220_0 .net *"_ivl_9", 7 0, L_0xc4ef42080;  1 drivers
+L_0xc4e879648 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2fd2c0_0 .net/s "acc_in", 39 0, L_0xc4e879648;  1 drivers
+v0xc4f2fd360_0 .net/s "acc_out", 39 0, L_0xc4f398140;  alias, 1 drivers
+v0xc4f2fd400_0 .net/s "product", 31 0, L_0xc4ef41fe0;  1 drivers
+v0xc4f2fd4a0_0 .net/s "product_ext", 39 0, L_0xc4f3980a0;  1 drivers
+v0xc4f2fd540_0 .net/s "w", 15 0, L_0xc4f3957c0;  1 drivers
+v0xc4f2fd5e0_0 .net/s "x", 15 0, L_0xc4f395720;  1 drivers
+L_0xc4f393f20 .extend/s 32, L_0xc4f395720;
+L_0xc4f398000 .extend/s 32, L_0xc4f3957c0;
+L_0xc4ef41fe0 .arith/mult 32, L_0xc4f393f20, L_0xc4f398000;
+L_0xc4f395680 .part L_0xc4ef41fe0, 31, 1;
+L_0xc4ef42080 .repeat 8, 8, L_0xc4f395680;
+L_0xc4f3980a0 .concat [ 32 8 0 0], L_0xc4ef41fe0, L_0xc4ef42080;
+L_0xc4f398140 .arith/sum 40, L_0xc4e879648, L_0xc4f3980a0;
+S_0xc4f2f9c80 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2ddb40 .param/l "i" 1 5 20, +C4<0100>;
+S_0xc4f2f9e00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2f9c80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ae100 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ae140 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ae180 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2fd680_0 .net/s *"_ivl_0", 31 0, L_0xc4f3981e0;  1 drivers
+v0xc4f2fd720_0 .net/s *"_ivl_2", 31 0, L_0xc4f398280;  1 drivers
+v0xc4f2fd7c0_0 .net *"_ivl_7", 0 0, L_0xc4f395860;  1 drivers
+v0xc4f2fd860_0 .net *"_ivl_9", 7 0, L_0xc4ef421c0;  1 drivers
+L_0xc4e879690 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2fd900_0 .net/s "acc_in", 39 0, L_0xc4e879690;  1 drivers
+v0xc4f2fd9a0_0 .net/s "acc_out", 39 0, L_0xc4f3983c0;  alias, 1 drivers
+v0xc4f2fda40_0 .net/s "product", 31 0, L_0xc4ef42120;  1 drivers
+v0xc4f2fdae0_0 .net/s "product_ext", 39 0, L_0xc4f398320;  1 drivers
+v0xc4f2fdb80_0 .net/s "w", 15 0, L_0xc4f3959a0;  1 drivers
+v0xc4f2fdc20_0 .net/s "x", 15 0, L_0xc4f395900;  1 drivers
+L_0xc4f3981e0 .extend/s 32, L_0xc4f395900;
+L_0xc4f398280 .extend/s 32, L_0xc4f3959a0;
+L_0xc4ef42120 .arith/mult 32, L_0xc4f3981e0, L_0xc4f398280;
+L_0xc4f395860 .part L_0xc4ef42120, 31, 1;
+L_0xc4ef421c0 .repeat 8, 8, L_0xc4f395860;
+L_0xc4f398320 .concat [ 32 8 0 0], L_0xc4ef42120, L_0xc4ef421c0;
+L_0xc4f3983c0 .arith/sum 40, L_0xc4e879690, L_0xc4f398320;
+S_0xc4f2f9f80 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2ddb80 .param/l "i" 1 5 20, +C4<0101>;
+S_0xc4f2fa100 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2f9f80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ae1c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ae200 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ae240 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2fdcc0_0 .net/s *"_ivl_0", 31 0, L_0xc4f398460;  1 drivers
+v0xc4f2fdd60_0 .net/s *"_ivl_2", 31 0, L_0xc4f398500;  1 drivers
+v0xc4f2fde00_0 .net *"_ivl_7", 0 0, L_0xc4f395a40;  1 drivers
+v0xc4f2fdea0_0 .net *"_ivl_9", 7 0, L_0xc4ef42300;  1 drivers
+L_0xc4e8796d8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2fdf40_0 .net/s "acc_in", 39 0, L_0xc4e8796d8;  1 drivers
+v0xc4f2fdfe0_0 .net/s "acc_out", 39 0, L_0xc4f398640;  alias, 1 drivers
+v0xc4f2fe080_0 .net/s "product", 31 0, L_0xc4ef42260;  1 drivers
+v0xc4f2fe120_0 .net/s "product_ext", 39 0, L_0xc4f3985a0;  1 drivers
+v0xc4f2fe1c0_0 .net/s "w", 15 0, L_0xc4f395b80;  1 drivers
+v0xc4f2fe260_0 .net/s "x", 15 0, L_0xc4f395ae0;  1 drivers
+L_0xc4f398460 .extend/s 32, L_0xc4f395ae0;
+L_0xc4f398500 .extend/s 32, L_0xc4f395b80;
+L_0xc4ef42260 .arith/mult 32, L_0xc4f398460, L_0xc4f398500;
+L_0xc4f395a40 .part L_0xc4ef42260, 31, 1;
+L_0xc4ef42300 .repeat 8, 8, L_0xc4f395a40;
+L_0xc4f3985a0 .concat [ 32 8 0 0], L_0xc4ef42260, L_0xc4ef42300;
+L_0xc4f398640 .arith/sum 40, L_0xc4e8796d8, L_0xc4f3985a0;
+S_0xc4f2fa280 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2ddbc0 .param/l "i" 1 5 20, +C4<0110>;
+S_0xc4f2fa400 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2fa280;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ae280 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ae2c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ae300 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2fe300_0 .net/s *"_ivl_0", 31 0, L_0xc4f3986e0;  1 drivers
+v0xc4f2fe3a0_0 .net/s *"_ivl_2", 31 0, L_0xc4f398780;  1 drivers
+v0xc4f2fe440_0 .net *"_ivl_7", 0 0, L_0xc4f395c20;  1 drivers
+v0xc4f2fe4e0_0 .net *"_ivl_9", 7 0, L_0xc4ef42440;  1 drivers
+L_0xc4e879720 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2fe580_0 .net/s "acc_in", 39 0, L_0xc4e879720;  1 drivers
+v0xc4f2fe620_0 .net/s "acc_out", 39 0, L_0xc4f3988c0;  alias, 1 drivers
+v0xc4f2fe6c0_0 .net/s "product", 31 0, L_0xc4ef423a0;  1 drivers
+v0xc4f2fe760_0 .net/s "product_ext", 39 0, L_0xc4f398820;  1 drivers
+v0xc4f2fe800_0 .net/s "w", 15 0, L_0xc4f395d60;  1 drivers
+v0xc4f2fe8a0_0 .net/s "x", 15 0, L_0xc4f395cc0;  1 drivers
+L_0xc4f3986e0 .extend/s 32, L_0xc4f395cc0;
+L_0xc4f398780 .extend/s 32, L_0xc4f395d60;
+L_0xc4ef423a0 .arith/mult 32, L_0xc4f3986e0, L_0xc4f398780;
+L_0xc4f395c20 .part L_0xc4ef423a0, 31, 1;
+L_0xc4ef42440 .repeat 8, 8, L_0xc4f395c20;
+L_0xc4f398820 .concat [ 32 8 0 0], L_0xc4ef423a0, L_0xc4ef42440;
+L_0xc4f3988c0 .arith/sum 40, L_0xc4e879720, L_0xc4f398820;
+S_0xc4f2fa580 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2ddc00 .param/l "i" 1 5 20, +C4<0111>;
+S_0xc4f2fa700 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f2fa580;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ae340 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ae380 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ae3c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f2fe940_0 .net/s *"_ivl_0", 31 0, L_0xc4f398960;  1 drivers
+v0xc4f2fe9e0_0 .net/s *"_ivl_2", 31 0, L_0xc4f398a00;  1 drivers
+v0xc4f2fea80_0 .net *"_ivl_7", 0 0, L_0xc4f395e00;  1 drivers
+v0xc4f2feb20_0 .net *"_ivl_9", 7 0, L_0xc4ef42580;  1 drivers
+L_0xc4e879768 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f2febc0_0 .net/s "acc_in", 39 0, L_0xc4e879768;  1 drivers
+v0xc4f2fec60_0 .net/s "acc_out", 39 0, L_0xc4f398b40;  alias, 1 drivers
+v0xc4f2fed00_0 .net/s "product", 31 0, L_0xc4ef424e0;  1 drivers
+v0xc4f2feda0_0 .net/s "product_ext", 39 0, L_0xc4f398aa0;  1 drivers
+v0xc4f2fee40_0 .net/s "w", 15 0, L_0xc4f395f40;  1 drivers
+v0xc4f2feee0_0 .net/s "x", 15 0, L_0xc4f395ea0;  1 drivers
+L_0xc4f398960 .extend/s 32, L_0xc4f395ea0;
+L_0xc4f398a00 .extend/s 32, L_0xc4f395f40;
+L_0xc4ef424e0 .arith/mult 32, L_0xc4f398960, L_0xc4f398a00;
+L_0xc4f395e00 .part L_0xc4ef424e0, 31, 1;
+L_0xc4ef42580 .repeat 8, 8, L_0xc4f395e00;
+L_0xc4f398aa0 .concat [ 32 8 0 0], L_0xc4ef424e0, L_0xc4ef42580;
+L_0xc4f398b40 .arith/sum 40, L_0xc4e879768, L_0xc4f398aa0;
+S_0xc4f2fa880 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2ddb00 .param/l "i" 1 5 80, +C4<00>;
+L_0xc4f065490 .functor BUFZ 40, L_0xc4f393980, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2faa00 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2ddc40 .param/l "i" 1 5 80, +C4<01>;
+L_0xc4f065500 .functor BUFZ 40, L_0xc4f393c00, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2fab80 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2ddc80 .param/l "i" 1 5 80, +C4<010>;
+L_0xc4f065570 .functor BUFZ 40, L_0xc4f393e80, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2fad00 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2ddcc0 .param/l "i" 1 5 80, +C4<011>;
+L_0xc4f0655e0 .functor BUFZ 40, L_0xc4f398140, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2fae80 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2ddd00 .param/l "i" 1 5 80, +C4<0100>;
+L_0xc4f065650 .functor BUFZ 40, L_0xc4f3983c0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2fb000 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2ddd40 .param/l "i" 1 5 80, +C4<0101>;
+L_0xc4f0656c0 .functor BUFZ 40, L_0xc4f398640, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2fb180 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2ddd80 .param/l "i" 1 5 80, +C4<0110>;
+L_0xc4f065730 .functor BUFZ 40, L_0xc4f3988c0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2fb300 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2dddc0 .param/l "i" 1 5 80, +C4<0111>;
+L_0xc4f0657a0 .functor BUFZ 40, L_0xc4f398b40, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f2fb480 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2dde00 .param/l "level" 1 5 92, +C4<00>;
+S_0xc4f2fb600 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f2fb480;
+ .timescale 0 0;
+P_0xc4f2dde40 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f398be0 .arith/sum 40, L_0xc4f065490, L_0xc4f065500;
+S_0xc4f2fb780 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f2fb480;
+ .timescale 0 0;
+P_0xc4f2dde80 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f398c80 .arith/sum 40, L_0xc4f065570, L_0xc4f0655e0;
+S_0xc4f2fb900 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xc4f2fb480;
+ .timescale 0 0;
+P_0xc4f2ddec0 .param/l "node" 1 5 94, +C4<010>;
+L_0xc4f398d20 .arith/sum 40, L_0xc4f065650, L_0xc4f0656c0;
+S_0xc4f2fba80 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xc4f2fb480;
+ .timescale 0 0;
+P_0xc4f2ddf00 .param/l "node" 1 5 94, +C4<011>;
+L_0xc4f398dc0 .arith/sum 40, L_0xc4f065730, L_0xc4f0657a0;
+S_0xc4f2fbc00 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2ddf40 .param/l "level" 1 5 92, +C4<01>;
+S_0xc4f2fbd80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f2fbc00;
+ .timescale 0 0;
+P_0xc4f2ddf80 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f398e60 .arith/sum 40, L_0xc4f398be0, L_0xc4f398c80;
+S_0xc4f300000 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f2fbc00;
+ .timescale 0 0;
+P_0xc4f2ddfc0 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f398f00 .arith/sum 40, L_0xc4f398d20, L_0xc4f398dc0;
+S_0xc4f300180 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xc4f2f8f00;
+ .timescale 0 0;
+P_0xc4f2de000 .param/l "level" 1 5 92, +C4<010>;
+S_0xc4f300300 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f300180;
+ .timescale 0 0;
+P_0xc4f2de040 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f398fa0 .arith/sum 40, L_0xc4f398e60, L_0xc4f398f00;
+S_0xc4f300480 .scope generate, "GEN_NEURON[6]" "GEN_NEURON[6]" 3 34, 3 34 0, S_0x102d16e70;
+ .timescale 0 0;
+P_0xc4f2de0c0 .param/l "n" 1 3 34, +C4<0110>;
+S_0xc4f300600 .scope module, "u_neuron" "neuron_parallel" 3 41, 4 1 0, S_0xc4f300480;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "start";
+    .port_info 3 /INPUT 1024 "x_bus";
+    .port_info 4 /INPUT 1024 "w_bus";
+    .port_info 5 /INPUT 16 "bias";
+    .port_info 6 /OUTPUT 16 "y";
+    .port_info 7 /OUTPUT 1 "busy";
+    .port_info 8 /OUTPUT 1 "done";
+P_0x102d27f10 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000101000>;
+P_0x102d27f50 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>;
+P_0x102d27f90 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000001000>;
+P_0x102d27fd0 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000011>;
+P_0x102d28010 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000001000000>;
+P_0x102d28050 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>;
+v0xc4f307c00_0 .net *"_ivl_0", 31 0, L_0xc4f399220;  1 drivers
+v0xc4f307ca0_0 .net *"_ivl_11", 31 0, L_0xc4ef42800;  1 drivers
+v0xc4f307d40_0 .net *"_ivl_14", 31 0, L_0xc4f3992c0;  1 drivers
+L_0xc4e879888 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f307de0_0 .net *"_ivl_17", 28 0, L_0xc4e879888;  1 drivers
+L_0xc4e8798d0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f307e80_0 .net/2u *"_ivl_18", 31 0, L_0xc4e8798d0;  1 drivers
+v0xc4f307f20_0 .net *"_ivl_21", 31 0, L_0xc4ef428a0;  1 drivers
+L_0xc4e879918 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
+v0xc4f308000_0 .net/2u *"_ivl_22", 31 0, L_0xc4e879918;  1 drivers
+v0xc4f3080a0_0 .net *"_ivl_25", 31 0, L_0xc4ef42940;  1 drivers
+v0xc4f308140_0 .net *"_ivl_29", 0 0, L_0xc4f397200;  1 drivers
+L_0xc4e8797b0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3081e0_0 .net *"_ivl_3", 28 0, L_0xc4e8797b0;  1 drivers
+v0xc4f308280_0 .net *"_ivl_31", 23 0, L_0xc4ef43480;  1 drivers
+L_0xc4e8797f8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f308320_0 .net/2u *"_ivl_4", 31 0, L_0xc4e8797f8;  1 drivers
+v0xc4f3083c0_0 .net *"_ivl_7", 31 0, L_0xc4ef42760;  1 drivers
+L_0xc4e879840 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
+v0xc4f308460_0 .net/2u *"_ivl_8", 31 0, L_0xc4e879840;  1 drivers
+v0xc4f308500_0 .var/s "acc", 39 0;
+v0xc4f3085a0_0 .net/s "acc_next", 39 0, L_0xc4f39abc0;  1 drivers
+v0xc4f308640_0 .net/s "bias", 15 0, L_0xc4f397340;  1 drivers
+v0xc4f3086e0_0 .net/s "bias_ext", 39 0, L_0xc4f39ac60;  1 drivers
+v0xc4f308780_0 .var "busy", 0 0;
+v0xc4f308820_0 .net "clk", 0 0, o0xc4e845fc0;  alias, 0 drivers
+v0xc4f3088c0_0 .var "done", 0 0;
+v0xc4f308960_0 .net/s "final_acc", 39 0, L_0xc4f39ad00;  1 drivers
+v0xc4f308a00_0 .var "group_index", 2 0;
+v0xc4f308aa0_0 .net "rst", 0 0, o0xc4e846080;  alias, 0 drivers
+v0xc4f308b40_0 .net "start", 0 0, o0xc4e8460b0;  alias, 0 drivers
+v0xc4f308be0_0 .net/s "w_bus", 1023 0, L_0xc4f3972a0;  1 drivers
+v0xc4f308c80_0 .net/s "w_group", 127 0, L_0xc4f396260;  1 drivers
+v0xc4f308d20_0 .net/s "x_bus", 1023 0, o0xc4e846110;  alias, 0 drivers
+v0xc4f308dc0_0 .net/s "x_group", 127 0, L_0xc4f3961c0;  1 drivers
+v0xc4f308e60_0 .var/s "y", 15 0;
+L_0xc4f399220 .concat [ 3 29 0 0], v0xc4f308a00_0, L_0xc4e8797b0;
+L_0xc4ef42760 .arith/mult 32, L_0xc4f399220, L_0xc4e8797f8;
+L_0xc4ef42800 .arith/mult 32, L_0xc4ef42760, L_0xc4e879840;
+L_0xc4f3961c0 .part/v o0xc4e846110, L_0xc4ef42800, 128;
+L_0xc4f3992c0 .concat [ 3 29 0 0], v0xc4f308a00_0, L_0xc4e879888;
+L_0xc4ef428a0 .arith/mult 32, L_0xc4f3992c0, L_0xc4e8798d0;
+L_0xc4ef42940 .arith/mult 32, L_0xc4ef428a0, L_0xc4e879918;
+L_0xc4f396260 .part/v L_0xc4f3972a0, L_0xc4ef42940, 128;
+L_0xc4f397200 .part L_0xc4f397340, 15, 1;
+L_0xc4ef43480 .repeat 24, 24, L_0xc4f397200;
+L_0xc4f39ac60 .concat [ 16 24 0 0], L_0xc4f397340, L_0xc4ef43480;
+L_0xc4f39ad00 .arith/sum 40, L_0xc4f39abc0, L_0xc4f39ac60;
+S_0xc4f300780 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xc4f300600;
+ .timescale 0 0;
+    .port_info 0 /INPUT 128 "x_bus";
+    .port_info 1 /INPUT 128 "w_bus";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4ef0d200 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000101000>;
+P_0xc4ef0d240 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>;
+P_0xc4ef0d280 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>;
+P_0xc4ef0d2c0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>;
+v0xc4f307840_0 .net/s "acc_in", 39 0, v0xc4f308500_0;  1 drivers
+v0xc4f3078e0_0 .net/s "acc_out", 39 0, L_0xc4f39abc0;  alias, 1 drivers
+v0xc4f307980 .array "products", 7 0;
+v0xc4f307980_0 .net/s v0xc4f307980 0, 39 0, L_0xc4f399540; 1 drivers
+v0xc4f307980_1 .net/s v0xc4f307980 1, 39 0, L_0xc4f3997c0; 1 drivers
+v0xc4f307980_2 .net/s v0xc4f307980 2, 39 0, L_0xc4f399a40; 1 drivers
+v0xc4f307980_3 .net/s v0xc4f307980 3, 39 0, L_0xc4f399cc0; 1 drivers
+v0xc4f307980_4 .net/s v0xc4f307980 4, 39 0, L_0xc4f399f40; 1 drivers
+v0xc4f307980_5 .net/s v0xc4f307980 5, 39 0, L_0xc4f39a1c0; 1 drivers
+v0xc4f307980_6 .net/s v0xc4f307980 6, 39 0, L_0xc4f39a440; 1 drivers
+v0xc4f307980_7 .net/s v0xc4f307980 7, 39 0, L_0xc4f39a6c0; 1 drivers
+v0xc4f307a20 .array "tree", 31 0;
+v0xc4f307a20_0 .net/s v0xc4f307a20 0, 39 0, L_0xc4f065810; 1 drivers
+v0xc4f307a20_1 .net/s v0xc4f307a20 1, 39 0, L_0xc4f065880; 1 drivers
+v0xc4f307a20_2 .net/s v0xc4f307a20 2, 39 0, L_0xc4f0658f0; 1 drivers
+v0xc4f307a20_3 .net/s v0xc4f307a20 3, 39 0, L_0xc4f065960; 1 drivers
+v0xc4f307a20_4 .net/s v0xc4f307a20 4, 39 0, L_0xc4f0659d0; 1 drivers
+v0xc4f307a20_5 .net/s v0xc4f307a20 5, 39 0, L_0xc4f065a40; 1 drivers
+v0xc4f307a20_6 .net/s v0xc4f307a20 6, 39 0, L_0xc4f065ab0; 1 drivers
+v0xc4f307a20_7 .net/s v0xc4f307a20 7, 39 0, L_0xc4f065b20; 1 drivers
+v0xc4f307a20_8 .net/s v0xc4f307a20 8, 39 0, L_0xc4f39a760; 1 drivers
+v0xc4f307a20_9 .net/s v0xc4f307a20 9, 39 0, L_0xc4f39a800; 1 drivers
+v0xc4f307a20_10 .net/s v0xc4f307a20 10, 39 0, L_0xc4f39a8a0; 1 drivers
+v0xc4f307a20_11 .net/s v0xc4f307a20 11, 39 0, L_0xc4f39a940; 1 drivers
+o0xc4e852650 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f307a20_12 .net/s v0xc4f307a20 12, 39 0, o0xc4e852650; 0 drivers
+o0xc4e852680 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f307a20_13 .net/s v0xc4f307a20 13, 39 0, o0xc4e852680; 0 drivers
+o0xc4e8526b0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f307a20_14 .net/s v0xc4f307a20 14, 39 0, o0xc4e8526b0; 0 drivers
+o0xc4e8526e0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f307a20_15 .net/s v0xc4f307a20 15, 39 0, o0xc4e8526e0; 0 drivers
+v0xc4f307a20_16 .net/s v0xc4f307a20 16, 39 0, L_0xc4f39a9e0; 1 drivers
+v0xc4f307a20_17 .net/s v0xc4f307a20 17, 39 0, L_0xc4f39aa80; 1 drivers
+o0xc4e852770 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f307a20_18 .net/s v0xc4f307a20 18, 39 0, o0xc4e852770; 0 drivers
+o0xc4e8527a0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f307a20_19 .net/s v0xc4f307a20 19, 39 0, o0xc4e8527a0; 0 drivers
+o0xc4e8527d0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f307a20_20 .net/s v0xc4f307a20 20, 39 0, o0xc4e8527d0; 0 drivers
+o0xc4e852800 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f307a20_21 .net/s v0xc4f307a20 21, 39 0, o0xc4e852800; 0 drivers
+o0xc4e852830 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f307a20_22 .net/s v0xc4f307a20 22, 39 0, o0xc4e852830; 0 drivers
+o0xc4e852860 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f307a20_23 .net/s v0xc4f307a20 23, 39 0, o0xc4e852860; 0 drivers
+v0xc4f307a20_24 .net/s v0xc4f307a20 24, 39 0, L_0xc4f39ab20; 1 drivers
+o0xc4e8528c0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f307a20_25 .net/s v0xc4f307a20 25, 39 0, o0xc4e8528c0; 0 drivers
+o0xc4e8528f0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f307a20_26 .net/s v0xc4f307a20 26, 39 0, o0xc4e8528f0; 0 drivers
+o0xc4e852920 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f307a20_27 .net/s v0xc4f307a20 27, 39 0, o0xc4e852920; 0 drivers
+o0xc4e852950 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f307a20_28 .net/s v0xc4f307a20 28, 39 0, o0xc4e852950; 0 drivers
+o0xc4e852980 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f307a20_29 .net/s v0xc4f307a20 29, 39 0, o0xc4e852980; 0 drivers
+o0xc4e8529b0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f307a20_30 .net/s v0xc4f307a20 30, 39 0, o0xc4e8529b0; 0 drivers
+o0xc4e8529e0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f307a20_31 .net/s v0xc4f307a20 31, 39 0, o0xc4e8529e0; 0 drivers
+v0xc4f307ac0_0 .net/s "w_bus", 127 0, L_0xc4f396260;  alias, 1 drivers
+v0xc4f307b60_0 .net/s "x_bus", 127 0, L_0xc4f3961c0;  alias, 1 drivers
+L_0xc4f3963a0 .part L_0xc4f3961c0, 0, 16;
+L_0xc4f396440 .part L_0xc4f396260, 0, 16;
+L_0xc4f396580 .part L_0xc4f3961c0, 16, 16;
+L_0xc4f396620 .part L_0xc4f396260, 16, 16;
+L_0xc4f396760 .part L_0xc4f3961c0, 32, 16;
+L_0xc4f396800 .part L_0xc4f396260, 32, 16;
+L_0xc4f396940 .part L_0xc4f3961c0, 48, 16;
+L_0xc4f3969e0 .part L_0xc4f396260, 48, 16;
+L_0xc4f396b20 .part L_0xc4f3961c0, 64, 16;
+L_0xc4f396bc0 .part L_0xc4f396260, 64, 16;
+L_0xc4f396d00 .part L_0xc4f3961c0, 80, 16;
+L_0xc4f396da0 .part L_0xc4f396260, 80, 16;
+L_0xc4f396ee0 .part L_0xc4f3961c0, 96, 16;
+L_0xc4f396f80 .part L_0xc4f396260, 96, 16;
+L_0xc4f3970c0 .part L_0xc4f3961c0, 112, 16;
+L_0xc4f397160 .part L_0xc4f396260, 112, 16;
+L_0xc4f39abc0 .arith/sum 40, v0xc4f308500_0, L_0xc4f39ab20;
+S_0xc4f300900 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de100 .param/l "i" 1 5 20, +C4<00>;
+S_0xc4f300a80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f300900;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ae400 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ae440 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ae480 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f304640_0 .net/s *"_ivl_0", 31 0, L_0xc4f399360;  1 drivers
+v0xc4f3046e0_0 .net/s *"_ivl_2", 31 0, L_0xc4f399400;  1 drivers
+v0xc4f304780_0 .net *"_ivl_7", 0 0, L_0xc4f396300;  1 drivers
+v0xc4f304820_0 .net *"_ivl_9", 7 0, L_0xc4ef42a80;  1 drivers
+L_0xc4e879960 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3048c0_0 .net/s "acc_in", 39 0, L_0xc4e879960;  1 drivers
+v0xc4f304960_0 .net/s "acc_out", 39 0, L_0xc4f399540;  alias, 1 drivers
+v0xc4f304a00_0 .net/s "product", 31 0, L_0xc4ef429e0;  1 drivers
+v0xc4f304aa0_0 .net/s "product_ext", 39 0, L_0xc4f3994a0;  1 drivers
+v0xc4f304b40_0 .net/s "w", 15 0, L_0xc4f396440;  1 drivers
+v0xc4f304be0_0 .net/s "x", 15 0, L_0xc4f3963a0;  1 drivers
+L_0xc4f399360 .extend/s 32, L_0xc4f3963a0;
+L_0xc4f399400 .extend/s 32, L_0xc4f396440;
+L_0xc4ef429e0 .arith/mult 32, L_0xc4f399360, L_0xc4f399400;
+L_0xc4f396300 .part L_0xc4ef429e0, 31, 1;
+L_0xc4ef42a80 .repeat 8, 8, L_0xc4f396300;
+L_0xc4f3994a0 .concat [ 32 8 0 0], L_0xc4ef429e0, L_0xc4ef42a80;
+L_0xc4f399540 .arith/sum 40, L_0xc4e879960, L_0xc4f3994a0;
+S_0xc4f300c00 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de140 .param/l "i" 1 5 20, +C4<01>;
+S_0xc4f300d80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f300c00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ae4c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ae500 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ae540 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f304c80_0 .net/s *"_ivl_0", 31 0, L_0xc4f3995e0;  1 drivers
+v0xc4f304d20_0 .net/s *"_ivl_2", 31 0, L_0xc4f399680;  1 drivers
+v0xc4f304dc0_0 .net *"_ivl_7", 0 0, L_0xc4f3964e0;  1 drivers
+v0xc4f304e60_0 .net *"_ivl_9", 7 0, L_0xc4ef42bc0;  1 drivers
+L_0xc4e8799a8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f304f00_0 .net/s "acc_in", 39 0, L_0xc4e8799a8;  1 drivers
+v0xc4f304fa0_0 .net/s "acc_out", 39 0, L_0xc4f3997c0;  alias, 1 drivers
+v0xc4f305040_0 .net/s "product", 31 0, L_0xc4ef42b20;  1 drivers
+v0xc4f3050e0_0 .net/s "product_ext", 39 0, L_0xc4f399720;  1 drivers
+v0xc4f305180_0 .net/s "w", 15 0, L_0xc4f396620;  1 drivers
+v0xc4f305220_0 .net/s "x", 15 0, L_0xc4f396580;  1 drivers
+L_0xc4f3995e0 .extend/s 32, L_0xc4f396580;
+L_0xc4f399680 .extend/s 32, L_0xc4f396620;
+L_0xc4ef42b20 .arith/mult 32, L_0xc4f3995e0, L_0xc4f399680;
+L_0xc4f3964e0 .part L_0xc4ef42b20, 31, 1;
+L_0xc4ef42bc0 .repeat 8, 8, L_0xc4f3964e0;
+L_0xc4f399720 .concat [ 32 8 0 0], L_0xc4ef42b20, L_0xc4ef42bc0;
+L_0xc4f3997c0 .arith/sum 40, L_0xc4e8799a8, L_0xc4f399720;
+S_0xc4f300f00 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de180 .param/l "i" 1 5 20, +C4<010>;
+S_0xc4f301080 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f300f00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ae580 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ae5c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ae600 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f3052c0_0 .net/s *"_ivl_0", 31 0, L_0xc4f399860;  1 drivers
+v0xc4f305360_0 .net/s *"_ivl_2", 31 0, L_0xc4f399900;  1 drivers
+v0xc4f305400_0 .net *"_ivl_7", 0 0, L_0xc4f3966c0;  1 drivers
+v0xc4f3054a0_0 .net *"_ivl_9", 7 0, L_0xc4ef42d00;  1 drivers
+L_0xc4e8799f0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f305540_0 .net/s "acc_in", 39 0, L_0xc4e8799f0;  1 drivers
+v0xc4f3055e0_0 .net/s "acc_out", 39 0, L_0xc4f399a40;  alias, 1 drivers
+v0xc4f305680_0 .net/s "product", 31 0, L_0xc4ef42c60;  1 drivers
+v0xc4f305720_0 .net/s "product_ext", 39 0, L_0xc4f3999a0;  1 drivers
+v0xc4f3057c0_0 .net/s "w", 15 0, L_0xc4f396800;  1 drivers
+v0xc4f305860_0 .net/s "x", 15 0, L_0xc4f396760;  1 drivers
+L_0xc4f399860 .extend/s 32, L_0xc4f396760;
+L_0xc4f399900 .extend/s 32, L_0xc4f396800;
+L_0xc4ef42c60 .arith/mult 32, L_0xc4f399860, L_0xc4f399900;
+L_0xc4f3966c0 .part L_0xc4ef42c60, 31, 1;
+L_0xc4ef42d00 .repeat 8, 8, L_0xc4f3966c0;
+L_0xc4f3999a0 .concat [ 32 8 0 0], L_0xc4ef42c60, L_0xc4ef42d00;
+L_0xc4f399a40 .arith/sum 40, L_0xc4e8799f0, L_0xc4f3999a0;
+S_0xc4f301200 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de1c0 .param/l "i" 1 5 20, +C4<011>;
+S_0xc4f301380 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f301200;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ae640 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ae680 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ae6c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f305900_0 .net/s *"_ivl_0", 31 0, L_0xc4f399ae0;  1 drivers
+v0xc4f3059a0_0 .net/s *"_ivl_2", 31 0, L_0xc4f399b80;  1 drivers
+v0xc4f305a40_0 .net *"_ivl_7", 0 0, L_0xc4f3968a0;  1 drivers
+v0xc4f305ae0_0 .net *"_ivl_9", 7 0, L_0xc4ef42e40;  1 drivers
+L_0xc4e879a38 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f305b80_0 .net/s "acc_in", 39 0, L_0xc4e879a38;  1 drivers
+v0xc4f305c20_0 .net/s "acc_out", 39 0, L_0xc4f399cc0;  alias, 1 drivers
+v0xc4f305cc0_0 .net/s "product", 31 0, L_0xc4ef42da0;  1 drivers
+v0xc4f305d60_0 .net/s "product_ext", 39 0, L_0xc4f399c20;  1 drivers
+v0xc4f305e00_0 .net/s "w", 15 0, L_0xc4f3969e0;  1 drivers
+v0xc4f305ea0_0 .net/s "x", 15 0, L_0xc4f396940;  1 drivers
+L_0xc4f399ae0 .extend/s 32, L_0xc4f396940;
+L_0xc4f399b80 .extend/s 32, L_0xc4f3969e0;
+L_0xc4ef42da0 .arith/mult 32, L_0xc4f399ae0, L_0xc4f399b80;
+L_0xc4f3968a0 .part L_0xc4ef42da0, 31, 1;
+L_0xc4ef42e40 .repeat 8, 8, L_0xc4f3968a0;
+L_0xc4f399c20 .concat [ 32 8 0 0], L_0xc4ef42da0, L_0xc4ef42e40;
+L_0xc4f399cc0 .arith/sum 40, L_0xc4e879a38, L_0xc4f399c20;
+S_0xc4f301500 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de240 .param/l "i" 1 5 20, +C4<0100>;
+S_0xc4f301680 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f301500;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ae700 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ae740 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ae780 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f305f40_0 .net/s *"_ivl_0", 31 0, L_0xc4f399d60;  1 drivers
+v0xc4f305fe0_0 .net/s *"_ivl_2", 31 0, L_0xc4f399e00;  1 drivers
+v0xc4f306080_0 .net *"_ivl_7", 0 0, L_0xc4f396a80;  1 drivers
+v0xc4f306120_0 .net *"_ivl_9", 7 0, L_0xc4ef42f80;  1 drivers
+L_0xc4e879a80 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3061c0_0 .net/s "acc_in", 39 0, L_0xc4e879a80;  1 drivers
+v0xc4f306260_0 .net/s "acc_out", 39 0, L_0xc4f399f40;  alias, 1 drivers
+v0xc4f306300_0 .net/s "product", 31 0, L_0xc4ef42ee0;  1 drivers
+v0xc4f3063a0_0 .net/s "product_ext", 39 0, L_0xc4f399ea0;  1 drivers
+v0xc4f306440_0 .net/s "w", 15 0, L_0xc4f396bc0;  1 drivers
+v0xc4f3064e0_0 .net/s "x", 15 0, L_0xc4f396b20;  1 drivers
+L_0xc4f399d60 .extend/s 32, L_0xc4f396b20;
+L_0xc4f399e00 .extend/s 32, L_0xc4f396bc0;
+L_0xc4ef42ee0 .arith/mult 32, L_0xc4f399d60, L_0xc4f399e00;
+L_0xc4f396a80 .part L_0xc4ef42ee0, 31, 1;
+L_0xc4ef42f80 .repeat 8, 8, L_0xc4f396a80;
+L_0xc4f399ea0 .concat [ 32 8 0 0], L_0xc4ef42ee0, L_0xc4ef42f80;
+L_0xc4f399f40 .arith/sum 40, L_0xc4e879a80, L_0xc4f399ea0;
+S_0xc4f301800 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de280 .param/l "i" 1 5 20, +C4<0101>;
+S_0xc4f301980 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f301800;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ae7c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ae800 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ae840 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f306580_0 .net/s *"_ivl_0", 31 0, L_0xc4f399fe0;  1 drivers
+v0xc4f306620_0 .net/s *"_ivl_2", 31 0, L_0xc4f39a080;  1 drivers
+v0xc4f3066c0_0 .net *"_ivl_7", 0 0, L_0xc4f396c60;  1 drivers
+v0xc4f306760_0 .net *"_ivl_9", 7 0, L_0xc4ef430c0;  1 drivers
+L_0xc4e879ac8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f306800_0 .net/s "acc_in", 39 0, L_0xc4e879ac8;  1 drivers
+v0xc4f3068a0_0 .net/s "acc_out", 39 0, L_0xc4f39a1c0;  alias, 1 drivers
+v0xc4f306940_0 .net/s "product", 31 0, L_0xc4ef43020;  1 drivers
+v0xc4f3069e0_0 .net/s "product_ext", 39 0, L_0xc4f39a120;  1 drivers
+v0xc4f306a80_0 .net/s "w", 15 0, L_0xc4f396da0;  1 drivers
+v0xc4f306b20_0 .net/s "x", 15 0, L_0xc4f396d00;  1 drivers
+L_0xc4f399fe0 .extend/s 32, L_0xc4f396d00;
+L_0xc4f39a080 .extend/s 32, L_0xc4f396da0;
+L_0xc4ef43020 .arith/mult 32, L_0xc4f399fe0, L_0xc4f39a080;
+L_0xc4f396c60 .part L_0xc4ef43020, 31, 1;
+L_0xc4ef430c0 .repeat 8, 8, L_0xc4f396c60;
+L_0xc4f39a120 .concat [ 32 8 0 0], L_0xc4ef43020, L_0xc4ef430c0;
+L_0xc4f39a1c0 .arith/sum 40, L_0xc4e879ac8, L_0xc4f39a120;
+S_0xc4f301b00 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de2c0 .param/l "i" 1 5 20, +C4<0110>;
+S_0xc4f301c80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f301b00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ae880 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ae8c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ae900 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f306bc0_0 .net/s *"_ivl_0", 31 0, L_0xc4f39a260;  1 drivers
+v0xc4f306c60_0 .net/s *"_ivl_2", 31 0, L_0xc4f39a300;  1 drivers
+v0xc4f306d00_0 .net *"_ivl_7", 0 0, L_0xc4f396e40;  1 drivers
+v0xc4f306da0_0 .net *"_ivl_9", 7 0, L_0xc4ef43200;  1 drivers
+L_0xc4e879b10 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f306e40_0 .net/s "acc_in", 39 0, L_0xc4e879b10;  1 drivers
+v0xc4f306ee0_0 .net/s "acc_out", 39 0, L_0xc4f39a440;  alias, 1 drivers
+v0xc4f306f80_0 .net/s "product", 31 0, L_0xc4ef43160;  1 drivers
+v0xc4f307020_0 .net/s "product_ext", 39 0, L_0xc4f39a3a0;  1 drivers
+v0xc4f3070c0_0 .net/s "w", 15 0, L_0xc4f396f80;  1 drivers
+v0xc4f307160_0 .net/s "x", 15 0, L_0xc4f396ee0;  1 drivers
+L_0xc4f39a260 .extend/s 32, L_0xc4f396ee0;
+L_0xc4f39a300 .extend/s 32, L_0xc4f396f80;
+L_0xc4ef43160 .arith/mult 32, L_0xc4f39a260, L_0xc4f39a300;
+L_0xc4f396e40 .part L_0xc4ef43160, 31, 1;
+L_0xc4ef43200 .repeat 8, 8, L_0xc4f396e40;
+L_0xc4f39a3a0 .concat [ 32 8 0 0], L_0xc4ef43160, L_0xc4ef43200;
+L_0xc4f39a440 .arith/sum 40, L_0xc4e879b10, L_0xc4f39a3a0;
+S_0xc4f301e00 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de300 .param/l "i" 1 5 20, +C4<0111>;
+S_0xc4f301f80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f301e00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2ae940 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2ae980 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2ae9c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f307200_0 .net/s *"_ivl_0", 31 0, L_0xc4f39a4e0;  1 drivers
+v0xc4f3072a0_0 .net/s *"_ivl_2", 31 0, L_0xc4f39a580;  1 drivers
+v0xc4f307340_0 .net *"_ivl_7", 0 0, L_0xc4f397020;  1 drivers
+v0xc4f3073e0_0 .net *"_ivl_9", 7 0, L_0xc4ef43340;  1 drivers
+L_0xc4e879b58 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f307480_0 .net/s "acc_in", 39 0, L_0xc4e879b58;  1 drivers
+v0xc4f307520_0 .net/s "acc_out", 39 0, L_0xc4f39a6c0;  alias, 1 drivers
+v0xc4f3075c0_0 .net/s "product", 31 0, L_0xc4ef432a0;  1 drivers
+v0xc4f307660_0 .net/s "product_ext", 39 0, L_0xc4f39a620;  1 drivers
+v0xc4f307700_0 .net/s "w", 15 0, L_0xc4f397160;  1 drivers
+v0xc4f3077a0_0 .net/s "x", 15 0, L_0xc4f3970c0;  1 drivers
+L_0xc4f39a4e0 .extend/s 32, L_0xc4f3970c0;
+L_0xc4f39a580 .extend/s 32, L_0xc4f397160;
+L_0xc4ef432a0 .arith/mult 32, L_0xc4f39a4e0, L_0xc4f39a580;
+L_0xc4f397020 .part L_0xc4ef432a0, 31, 1;
+L_0xc4ef43340 .repeat 8, 8, L_0xc4f397020;
+L_0xc4f39a620 .concat [ 32 8 0 0], L_0xc4ef432a0, L_0xc4ef43340;
+L_0xc4f39a6c0 .arith/sum 40, L_0xc4e879b58, L_0xc4f39a620;
+S_0xc4f302100 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de200 .param/l "i" 1 5 80, +C4<00>;
+L_0xc4f065810 .functor BUFZ 40, L_0xc4f399540, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f302280 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de340 .param/l "i" 1 5 80, +C4<01>;
+L_0xc4f065880 .functor BUFZ 40, L_0xc4f3997c0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f302400 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de380 .param/l "i" 1 5 80, +C4<010>;
+L_0xc4f0658f0 .functor BUFZ 40, L_0xc4f399a40, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f302580 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de3c0 .param/l "i" 1 5 80, +C4<011>;
+L_0xc4f065960 .functor BUFZ 40, L_0xc4f399cc0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f302700 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de400 .param/l "i" 1 5 80, +C4<0100>;
+L_0xc4f0659d0 .functor BUFZ 40, L_0xc4f399f40, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f302880 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de440 .param/l "i" 1 5 80, +C4<0101>;
+L_0xc4f065a40 .functor BUFZ 40, L_0xc4f39a1c0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f302a00 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de480 .param/l "i" 1 5 80, +C4<0110>;
+L_0xc4f065ab0 .functor BUFZ 40, L_0xc4f39a440, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f302b80 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de4c0 .param/l "i" 1 5 80, +C4<0111>;
+L_0xc4f065b20 .functor BUFZ 40, L_0xc4f39a6c0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f302d00 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de500 .param/l "level" 1 5 92, +C4<00>;
+S_0xc4f302e80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f302d00;
+ .timescale 0 0;
+P_0xc4f2de540 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f39a760 .arith/sum 40, L_0xc4f065810, L_0xc4f065880;
+S_0xc4f303000 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f302d00;
+ .timescale 0 0;
+P_0xc4f2de580 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f39a800 .arith/sum 40, L_0xc4f0658f0, L_0xc4f065960;
+S_0xc4f303180 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xc4f302d00;
+ .timescale 0 0;
+P_0xc4f2de5c0 .param/l "node" 1 5 94, +C4<010>;
+L_0xc4f39a8a0 .arith/sum 40, L_0xc4f0659d0, L_0xc4f065a40;
+S_0xc4f303300 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xc4f302d00;
+ .timescale 0 0;
+P_0xc4f2de600 .param/l "node" 1 5 94, +C4<011>;
+L_0xc4f39a940 .arith/sum 40, L_0xc4f065ab0, L_0xc4f065b20;
+S_0xc4f303480 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de640 .param/l "level" 1 5 92, +C4<01>;
+S_0xc4f303600 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f303480;
+ .timescale 0 0;
+P_0xc4f2de680 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f39a9e0 .arith/sum 40, L_0xc4f39a760, L_0xc4f39a800;
+S_0xc4f303780 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f303480;
+ .timescale 0 0;
+P_0xc4f2de6c0 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f39aa80 .arith/sum 40, L_0xc4f39a8a0, L_0xc4f39a940;
+S_0xc4f303900 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xc4f300780;
+ .timescale 0 0;
+P_0xc4f2de700 .param/l "level" 1 5 92, +C4<010>;
+S_0xc4f303a80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f303900;
+ .timescale 0 0;
+P_0xc4f2de740 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f39ab20 .arith/sum 40, L_0xc4f39a9e0, L_0xc4f39aa80;
+S_0xc4f303c00 .scope generate, "GEN_NEURON[7]" "GEN_NEURON[7]" 3 34, 3 34 0, S_0x102d16e70;
+ .timescale 0 0;
+P_0xc4f2de7c0 .param/l "n" 1 3 34, +C4<0111>;
+S_0xc4f303d80 .scope module, "u_neuron" "neuron_parallel" 3 41, 4 1 0, S_0xc4f303c00;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "start";
+    .port_info 3 /INPUT 1024 "x_bus";
+    .port_info 4 /INPUT 1024 "w_bus";
+    .port_info 5 /INPUT 16 "bias";
+    .port_info 6 /OUTPUT 16 "y";
+    .port_info 7 /OUTPUT 1 "busy";
+    .port_info 8 /OUTPUT 1 "done";
+P_0x102d28090 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000101000>;
+P_0x102d280d0 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000010000>;
+P_0x102d28110 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000001000>;
+P_0x102d28150 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000011>;
+P_0x102d28190 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000001000000>;
+P_0x102d281d0 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>;
+v0xc4f314500_0 .net *"_ivl_0", 31 0, L_0xc4f39ada0;  1 drivers
+v0xc4f3145a0_0 .net *"_ivl_11", 31 0, L_0xc4ef435c0;  1 drivers
+v0xc4f314640_0 .net *"_ivl_14", 31 0, L_0xc4f39ae40;  1 drivers
+L_0xc4e879c78 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3146e0_0 .net *"_ivl_17", 28 0, L_0xc4e879c78;  1 drivers
+L_0xc4e879cc0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f314780_0 .net/2u *"_ivl_18", 31 0, L_0xc4e879cc0;  1 drivers
+v0xc4f314820_0 .net *"_ivl_21", 31 0, L_0xc4ef43660;  1 drivers
+L_0xc4e879d08 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3148c0_0 .net/2u *"_ivl_22", 31 0, L_0xc4e879d08;  1 drivers
+v0xc4f314960_0 .net *"_ivl_25", 31 0, L_0xc4ef43700;  1 drivers
+v0xc4f314a00_0 .net *"_ivl_29", 0 0, L_0xc4f39c460;  1 drivers
+L_0xc4e879ba0 .functor BUFT 1, C4<00000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f314aa0_0 .net *"_ivl_3", 28 0, L_0xc4e879ba0;  1 drivers
+v0xc4f314b40_0 .net *"_ivl_31", 23 0, L_0xc4ef50280;  1 drivers
+L_0xc4e879be8 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f314be0_0 .net/2u *"_ivl_4", 31 0, L_0xc4e879be8;  1 drivers
+v0xc4f314c80_0 .net *"_ivl_7", 31 0, L_0xc4ef43520;  1 drivers
+L_0xc4e879c30 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
+v0xc4f314d20_0 .net/2u *"_ivl_8", 31 0, L_0xc4e879c30;  1 drivers
+v0xc4f314dc0_0 .var/s "acc", 39 0;
+v0xc4f314e60_0 .net/s "acc_next", 39 0, L_0xc4f3a0780;  1 drivers
+v0xc4f314f00_0 .net/s "bias", 15 0, L_0xc4f39c5a0;  1 drivers
+v0xc4f314fa0_0 .net/s "bias_ext", 39 0, L_0xc4f3a0820;  1 drivers
+v0xc4f315040_0 .var "busy", 0 0;
+v0xc4f3150e0_0 .net "clk", 0 0, o0xc4e845fc0;  alias, 0 drivers
+v0xc4f315180_0 .var "done", 0 0;
+v0xc4f315220_0 .net/s "final_acc", 39 0, L_0xc4f3a08c0;  1 drivers
+v0xc4f3152c0_0 .var "group_index", 2 0;
+v0xc4f315360_0 .net "rst", 0 0, o0xc4e846080;  alias, 0 drivers
+v0xc4f315400_0 .net "start", 0 0, o0xc4e8460b0;  alias, 0 drivers
+v0xc4f3154a0_0 .net/s "w_bus", 1023 0, L_0xc4f39c500;  1 drivers
+v0xc4f315540_0 .net/s "w_group", 127 0, L_0xc4f397480;  1 drivers
+v0xc4f3155e0_0 .net/s "x_bus", 1023 0, o0xc4e846110;  alias, 0 drivers
+v0xc4f315680_0 .net/s "x_group", 127 0, L_0xc4f3973e0;  1 drivers
+v0xc4f315720_0 .var/s "y", 15 0;
+L_0xc4f39ada0 .concat [ 3 29 0 0], v0xc4f3152c0_0, L_0xc4e879ba0;
+L_0xc4ef43520 .arith/mult 32, L_0xc4f39ada0, L_0xc4e879be8;
+L_0xc4ef435c0 .arith/mult 32, L_0xc4ef43520, L_0xc4e879c30;
+L_0xc4f3973e0 .part/v o0xc4e846110, L_0xc4ef435c0, 128;
+L_0xc4f39ae40 .concat [ 3 29 0 0], v0xc4f3152c0_0, L_0xc4e879c78;
+L_0xc4ef43660 .arith/mult 32, L_0xc4f39ae40, L_0xc4e879cc0;
+L_0xc4ef43700 .arith/mult 32, L_0xc4ef43660, L_0xc4e879d08;
+L_0xc4f397480 .part/v L_0xc4f39c500, L_0xc4ef43700, 128;
+L_0xc4f39c460 .part L_0xc4f39c5a0, 15, 1;
+L_0xc4ef50280 .repeat 24, 24, L_0xc4f39c460;
+L_0xc4f3a0820 .concat [ 16 24 0 0], L_0xc4f39c5a0, L_0xc4ef50280;
+L_0xc4f3a08c0 .arith/sum 40, L_0xc4f3a0780, L_0xc4f3a0820;
+S_0xc4f30c000 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xc4f303d80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 128 "x_bus";
+    .port_info 1 /INPUT 128 "w_bus";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4ef0d500 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000101000>;
+P_0xc4ef0d540 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000010000>;
+P_0xc4ef0d580 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>;
+P_0xc4ef0d5c0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>;
+v0xc4f314140_0 .net/s "acc_in", 39 0, v0xc4f314dc0_0;  1 drivers
+v0xc4f3141e0_0 .net/s "acc_out", 39 0, L_0xc4f3a0780;  alias, 1 drivers
+v0xc4f314280 .array "products", 7 0;
+v0xc4f314280_0 .net/s v0xc4f314280 0, 39 0, L_0xc4f39b0c0; 1 drivers
+v0xc4f314280_1 .net/s v0xc4f314280 1, 39 0, L_0xc4f39b340; 1 drivers
+v0xc4f314280_2 .net/s v0xc4f314280 2, 39 0, L_0xc4f39b5c0; 1 drivers
+v0xc4f314280_3 .net/s v0xc4f314280 3, 39 0, L_0xc4f39b840; 1 drivers
+v0xc4f314280_4 .net/s v0xc4f314280 4, 39 0, L_0xc4f39bac0; 1 drivers
+v0xc4f314280_5 .net/s v0xc4f314280 5, 39 0, L_0xc4f39bd40; 1 drivers
+v0xc4f314280_6 .net/s v0xc4f314280 6, 39 0, L_0xc4f3a0000; 1 drivers
+v0xc4f314280_7 .net/s v0xc4f314280 7, 39 0, L_0xc4f3a0280; 1 drivers
+v0xc4f314320 .array "tree", 31 0;
+v0xc4f314320_0 .net/s v0xc4f314320 0, 39 0, L_0xc4f065b90; 1 drivers
+v0xc4f314320_1 .net/s v0xc4f314320 1, 39 0, L_0xc4f065c00; 1 drivers
+v0xc4f314320_2 .net/s v0xc4f314320 2, 39 0, L_0xc4f065c70; 1 drivers
+v0xc4f314320_3 .net/s v0xc4f314320 3, 39 0, L_0xc4f065ce0; 1 drivers
+v0xc4f314320_4 .net/s v0xc4f314320 4, 39 0, L_0xc4f065d50; 1 drivers
+v0xc4f314320_5 .net/s v0xc4f314320 5, 39 0, L_0xc4f065dc0; 1 drivers
+v0xc4f314320_6 .net/s v0xc4f314320 6, 39 0, L_0xc4f065e30; 1 drivers
+v0xc4f314320_7 .net/s v0xc4f314320 7, 39 0, L_0xc4f065ea0; 1 drivers
+v0xc4f314320_8 .net/s v0xc4f314320 8, 39 0, L_0xc4f3a0320; 1 drivers
+v0xc4f314320_9 .net/s v0xc4f314320 9, 39 0, L_0xc4f3a03c0; 1 drivers
+v0xc4f314320_10 .net/s v0xc4f314320 10, 39 0, L_0xc4f3a0460; 1 drivers
+v0xc4f314320_11 .net/s v0xc4f314320 11, 39 0, L_0xc4f3a0500; 1 drivers
+o0xc4e8548a0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f314320_12 .net/s v0xc4f314320 12, 39 0, o0xc4e8548a0; 0 drivers
+o0xc4e8548d0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f314320_13 .net/s v0xc4f314320 13, 39 0, o0xc4e8548d0; 0 drivers
+o0xc4e854900 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f314320_14 .net/s v0xc4f314320 14, 39 0, o0xc4e854900; 0 drivers
+o0xc4e854930 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f314320_15 .net/s v0xc4f314320 15, 39 0, o0xc4e854930; 0 drivers
+v0xc4f314320_16 .net/s v0xc4f314320 16, 39 0, L_0xc4f3a05a0; 1 drivers
+v0xc4f314320_17 .net/s v0xc4f314320 17, 39 0, L_0xc4f3a0640; 1 drivers
+o0xc4e8549c0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f314320_18 .net/s v0xc4f314320 18, 39 0, o0xc4e8549c0; 0 drivers
+o0xc4e8549f0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f314320_19 .net/s v0xc4f314320 19, 39 0, o0xc4e8549f0; 0 drivers
+o0xc4e854a20 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f314320_20 .net/s v0xc4f314320 20, 39 0, o0xc4e854a20; 0 drivers
+o0xc4e854a50 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f314320_21 .net/s v0xc4f314320 21, 39 0, o0xc4e854a50; 0 drivers
+o0xc4e854a80 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f314320_22 .net/s v0xc4f314320 22, 39 0, o0xc4e854a80; 0 drivers
+o0xc4e854ab0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f314320_23 .net/s v0xc4f314320 23, 39 0, o0xc4e854ab0; 0 drivers
+v0xc4f314320_24 .net/s v0xc4f314320 24, 39 0, L_0xc4f3a06e0; 1 drivers
+o0xc4e854b10 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f314320_25 .net/s v0xc4f314320 25, 39 0, o0xc4e854b10; 0 drivers
+o0xc4e854b40 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f314320_26 .net/s v0xc4f314320 26, 39 0, o0xc4e854b40; 0 drivers
+o0xc4e854b70 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f314320_27 .net/s v0xc4f314320 27, 39 0, o0xc4e854b70; 0 drivers
+o0xc4e854ba0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f314320_28 .net/s v0xc4f314320 28, 39 0, o0xc4e854ba0; 0 drivers
+o0xc4e854bd0 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f314320_29 .net/s v0xc4f314320 29, 39 0, o0xc4e854bd0; 0 drivers
+o0xc4e854c00 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f314320_30 .net/s v0xc4f314320 30, 39 0, o0xc4e854c00; 0 drivers
+o0xc4e854c30 .functor BUFZ 40, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f314320_31 .net/s v0xc4f314320 31, 39 0, o0xc4e854c30; 0 drivers
+v0xc4f3143c0_0 .net/s "w_bus", 127 0, L_0xc4f397480;  alias, 1 drivers
+v0xc4f314460_0 .net/s "x_bus", 127 0, L_0xc4f3973e0;  alias, 1 drivers
+L_0xc4f3975c0 .part L_0xc4f3973e0, 0, 16;
+L_0xc4f397660 .part L_0xc4f397480, 0, 16;
+L_0xc4f3977a0 .part L_0xc4f3973e0, 16, 16;
+L_0xc4f397840 .part L_0xc4f397480, 16, 16;
+L_0xc4f397980 .part L_0xc4f3973e0, 32, 16;
+L_0xc4f397a20 .part L_0xc4f397480, 32, 16;
+L_0xc4f397b60 .part L_0xc4f3973e0, 48, 16;
+L_0xc4f397c00 .part L_0xc4f397480, 48, 16;
+L_0xc4f397d40 .part L_0xc4f3973e0, 64, 16;
+L_0xc4f397de0 .part L_0xc4f397480, 64, 16;
+L_0xc4f397f20 .part L_0xc4f3973e0, 80, 16;
+L_0xc4f39c000 .part L_0xc4f397480, 80, 16;
+L_0xc4f39c140 .part L_0xc4f3973e0, 96, 16;
+L_0xc4f39c1e0 .part L_0xc4f397480, 96, 16;
+L_0xc4f39c320 .part L_0xc4f3973e0, 112, 16;
+L_0xc4f39c3c0 .part L_0xc4f397480, 112, 16;
+L_0xc4f3a0780 .arith/sum 40, v0xc4f314dc0_0, L_0xc4f3a06e0;
+S_0xc4f30c180 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2de800 .param/l "i" 1 5 20, +C4<00>;
+S_0xc4f30c300 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f30c180;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2aea00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2aea40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2aea80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f308f00_0 .net/s *"_ivl_0", 31 0, L_0xc4f39aee0;  1 drivers
+v0xc4f308fa0_0 .net/s *"_ivl_2", 31 0, L_0xc4f39af80;  1 drivers
+v0xc4f309040_0 .net *"_ivl_7", 0 0, L_0xc4f397520;  1 drivers
+v0xc4f3090e0_0 .net *"_ivl_9", 7 0, L_0xc4ef43840;  1 drivers
+L_0xc4e879d50 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f309180_0 .net/s "acc_in", 39 0, L_0xc4e879d50;  1 drivers
+v0xc4f309220_0 .net/s "acc_out", 39 0, L_0xc4f39b0c0;  alias, 1 drivers
+v0xc4f3092c0_0 .net/s "product", 31 0, L_0xc4ef437a0;  1 drivers
+v0xc4f309360_0 .net/s "product_ext", 39 0, L_0xc4f39b020;  1 drivers
+v0xc4f309400_0 .net/s "w", 15 0, L_0xc4f397660;  1 drivers
+v0xc4f3094a0_0 .net/s "x", 15 0, L_0xc4f3975c0;  1 drivers
+L_0xc4f39aee0 .extend/s 32, L_0xc4f3975c0;
+L_0xc4f39af80 .extend/s 32, L_0xc4f397660;
+L_0xc4ef437a0 .arith/mult 32, L_0xc4f39aee0, L_0xc4f39af80;
+L_0xc4f397520 .part L_0xc4ef437a0, 31, 1;
+L_0xc4ef43840 .repeat 8, 8, L_0xc4f397520;
+L_0xc4f39b020 .concat [ 32 8 0 0], L_0xc4ef437a0, L_0xc4ef43840;
+L_0xc4f39b0c0 .arith/sum 40, L_0xc4e879d50, L_0xc4f39b020;
+S_0xc4f30c480 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2de840 .param/l "i" 1 5 20, +C4<01>;
+S_0xc4f30c600 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f30c480;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2aeac0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2aeb00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2aeb40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f309540_0 .net/s *"_ivl_0", 31 0, L_0xc4f39b160;  1 drivers
+v0xc4f3095e0_0 .net/s *"_ivl_2", 31 0, L_0xc4f39b200;  1 drivers
+v0xc4f309680_0 .net *"_ivl_7", 0 0, L_0xc4f397700;  1 drivers
+v0xc4f309720_0 .net *"_ivl_9", 7 0, L_0xc4ef43980;  1 drivers
+L_0xc4e879d98 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3097c0_0 .net/s "acc_in", 39 0, L_0xc4e879d98;  1 drivers
+v0xc4f309860_0 .net/s "acc_out", 39 0, L_0xc4f39b340;  alias, 1 drivers
+v0xc4f309900_0 .net/s "product", 31 0, L_0xc4ef438e0;  1 drivers
+v0xc4f3099a0_0 .net/s "product_ext", 39 0, L_0xc4f39b2a0;  1 drivers
+v0xc4f309a40_0 .net/s "w", 15 0, L_0xc4f397840;  1 drivers
+v0xc4f309ae0_0 .net/s "x", 15 0, L_0xc4f3977a0;  1 drivers
+L_0xc4f39b160 .extend/s 32, L_0xc4f3977a0;
+L_0xc4f39b200 .extend/s 32, L_0xc4f397840;
+L_0xc4ef438e0 .arith/mult 32, L_0xc4f39b160, L_0xc4f39b200;
+L_0xc4f397700 .part L_0xc4ef438e0, 31, 1;
+L_0xc4ef43980 .repeat 8, 8, L_0xc4f397700;
+L_0xc4f39b2a0 .concat [ 32 8 0 0], L_0xc4ef438e0, L_0xc4ef43980;
+L_0xc4f39b340 .arith/sum 40, L_0xc4e879d98, L_0xc4f39b2a0;
+S_0xc4f30c780 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2de880 .param/l "i" 1 5 20, +C4<010>;
+S_0xc4f30c900 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f30c780;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2aeb80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2aebc0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2aec00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f309b80_0 .net/s *"_ivl_0", 31 0, L_0xc4f39b3e0;  1 drivers
+v0xc4f309c20_0 .net/s *"_ivl_2", 31 0, L_0xc4f39b480;  1 drivers
+v0xc4f309cc0_0 .net *"_ivl_7", 0 0, L_0xc4f3978e0;  1 drivers
+v0xc4f309d60_0 .net *"_ivl_9", 7 0, L_0xc4ef43ac0;  1 drivers
+L_0xc4e879de0 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f309e00_0 .net/s "acc_in", 39 0, L_0xc4e879de0;  1 drivers
+v0xc4f309ea0_0 .net/s "acc_out", 39 0, L_0xc4f39b5c0;  alias, 1 drivers
+v0xc4f309f40_0 .net/s "product", 31 0, L_0xc4ef43a20;  1 drivers
+v0xc4f309fe0_0 .net/s "product_ext", 39 0, L_0xc4f39b520;  1 drivers
+v0xc4f30a080_0 .net/s "w", 15 0, L_0xc4f397a20;  1 drivers
+v0xc4f30a120_0 .net/s "x", 15 0, L_0xc4f397980;  1 drivers
+L_0xc4f39b3e0 .extend/s 32, L_0xc4f397980;
+L_0xc4f39b480 .extend/s 32, L_0xc4f397a20;
+L_0xc4ef43a20 .arith/mult 32, L_0xc4f39b3e0, L_0xc4f39b480;
+L_0xc4f3978e0 .part L_0xc4ef43a20, 31, 1;
+L_0xc4ef43ac0 .repeat 8, 8, L_0xc4f3978e0;
+L_0xc4f39b520 .concat [ 32 8 0 0], L_0xc4ef43a20, L_0xc4ef43ac0;
+L_0xc4f39b5c0 .arith/sum 40, L_0xc4e879de0, L_0xc4f39b520;
+S_0xc4f30ca80 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2de8c0 .param/l "i" 1 5 20, +C4<011>;
+S_0xc4f30cc00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f30ca80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2aec40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2aec80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2aecc0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f30a1c0_0 .net/s *"_ivl_0", 31 0, L_0xc4f39b660;  1 drivers
+v0xc4f30a260_0 .net/s *"_ivl_2", 31 0, L_0xc4f39b700;  1 drivers
+v0xc4f30a300_0 .net *"_ivl_7", 0 0, L_0xc4f397ac0;  1 drivers
+v0xc4f30a3a0_0 .net *"_ivl_9", 7 0, L_0xc4ef43c00;  1 drivers
+L_0xc4e879e28 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f30a440_0 .net/s "acc_in", 39 0, L_0xc4e879e28;  1 drivers
+v0xc4f30a4e0_0 .net/s "acc_out", 39 0, L_0xc4f39b840;  alias, 1 drivers
+v0xc4f30a580_0 .net/s "product", 31 0, L_0xc4ef43b60;  1 drivers
+v0xc4f30a620_0 .net/s "product_ext", 39 0, L_0xc4f39b7a0;  1 drivers
+v0xc4f30a6c0_0 .net/s "w", 15 0, L_0xc4f397c00;  1 drivers
+v0xc4f30a760_0 .net/s "x", 15 0, L_0xc4f397b60;  1 drivers
+L_0xc4f39b660 .extend/s 32, L_0xc4f397b60;
+L_0xc4f39b700 .extend/s 32, L_0xc4f397c00;
+L_0xc4ef43b60 .arith/mult 32, L_0xc4f39b660, L_0xc4f39b700;
+L_0xc4f397ac0 .part L_0xc4ef43b60, 31, 1;
+L_0xc4ef43c00 .repeat 8, 8, L_0xc4f397ac0;
+L_0xc4f39b7a0 .concat [ 32 8 0 0], L_0xc4ef43b60, L_0xc4ef43c00;
+L_0xc4f39b840 .arith/sum 40, L_0xc4e879e28, L_0xc4f39b7a0;
+S_0xc4f30cd80 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2de940 .param/l "i" 1 5 20, +C4<0100>;
+S_0xc4f30cf00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f30cd80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2aed00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2aed40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2aed80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f30a800_0 .net/s *"_ivl_0", 31 0, L_0xc4f39b8e0;  1 drivers
+v0xc4f30a8a0_0 .net/s *"_ivl_2", 31 0, L_0xc4f39b980;  1 drivers
+v0xc4f30a940_0 .net *"_ivl_7", 0 0, L_0xc4f397ca0;  1 drivers
+v0xc4f30a9e0_0 .net *"_ivl_9", 7 0, L_0xc4ef43d40;  1 drivers
+L_0xc4e879e70 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f30aa80_0 .net/s "acc_in", 39 0, L_0xc4e879e70;  1 drivers
+v0xc4f30ab20_0 .net/s "acc_out", 39 0, L_0xc4f39bac0;  alias, 1 drivers
+v0xc4f30abc0_0 .net/s "product", 31 0, L_0xc4ef43ca0;  1 drivers
+v0xc4f30ac60_0 .net/s "product_ext", 39 0, L_0xc4f39ba20;  1 drivers
+v0xc4f30ad00_0 .net/s "w", 15 0, L_0xc4f397de0;  1 drivers
+v0xc4f30ada0_0 .net/s "x", 15 0, L_0xc4f397d40;  1 drivers
+L_0xc4f39b8e0 .extend/s 32, L_0xc4f397d40;
+L_0xc4f39b980 .extend/s 32, L_0xc4f397de0;
+L_0xc4ef43ca0 .arith/mult 32, L_0xc4f39b8e0, L_0xc4f39b980;
+L_0xc4f397ca0 .part L_0xc4ef43ca0, 31, 1;
+L_0xc4ef43d40 .repeat 8, 8, L_0xc4f397ca0;
+L_0xc4f39ba20 .concat [ 32 8 0 0], L_0xc4ef43ca0, L_0xc4ef43d40;
+L_0xc4f39bac0 .arith/sum 40, L_0xc4e879e70, L_0xc4f39ba20;
+S_0xc4f30d080 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2de980 .param/l "i" 1 5 20, +C4<0101>;
+S_0xc4f30d200 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f30d080;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2aedc0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2aee00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2aee40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f30ae40_0 .net/s *"_ivl_0", 31 0, L_0xc4f39bb60;  1 drivers
+v0xc4f30aee0_0 .net/s *"_ivl_2", 31 0, L_0xc4f39bc00;  1 drivers
+v0xc4f30af80_0 .net *"_ivl_7", 0 0, L_0xc4f397e80;  1 drivers
+v0xc4f30b020_0 .net *"_ivl_9", 7 0, L_0xc4ef43e80;  1 drivers
+L_0xc4e879eb8 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f30b0c0_0 .net/s "acc_in", 39 0, L_0xc4e879eb8;  1 drivers
+v0xc4f30b160_0 .net/s "acc_out", 39 0, L_0xc4f39bd40;  alias, 1 drivers
+v0xc4f30b200_0 .net/s "product", 31 0, L_0xc4ef43de0;  1 drivers
+v0xc4f30b2a0_0 .net/s "product_ext", 39 0, L_0xc4f39bca0;  1 drivers
+v0xc4f30b340_0 .net/s "w", 15 0, L_0xc4f39c000;  1 drivers
+v0xc4f30b3e0_0 .net/s "x", 15 0, L_0xc4f397f20;  1 drivers
+L_0xc4f39bb60 .extend/s 32, L_0xc4f397f20;
+L_0xc4f39bc00 .extend/s 32, L_0xc4f39c000;
+L_0xc4ef43de0 .arith/mult 32, L_0xc4f39bb60, L_0xc4f39bc00;
+L_0xc4f397e80 .part L_0xc4ef43de0, 31, 1;
+L_0xc4ef43e80 .repeat 8, 8, L_0xc4f397e80;
+L_0xc4f39bca0 .concat [ 32 8 0 0], L_0xc4ef43de0, L_0xc4ef43e80;
+L_0xc4f39bd40 .arith/sum 40, L_0xc4e879eb8, L_0xc4f39bca0;
+S_0xc4f30d380 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2de9c0 .param/l "i" 1 5 20, +C4<0110>;
+S_0xc4f30d500 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f30d380;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2aee80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2aeec0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2aef00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f30b480_0 .net/s *"_ivl_0", 31 0, L_0xc4f39bde0;  1 drivers
+v0xc4f30b520_0 .net/s *"_ivl_2", 31 0, L_0xc4f39be80;  1 drivers
+v0xc4f30b5c0_0 .net *"_ivl_7", 0 0, L_0xc4f39c0a0;  1 drivers
+v0xc4f30b660_0 .net *"_ivl_9", 7 0, L_0xc4ef50000;  1 drivers
+L_0xc4e879f00 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f30b700_0 .net/s "acc_in", 39 0, L_0xc4e879f00;  1 drivers
+v0xc4f30b7a0_0 .net/s "acc_out", 39 0, L_0xc4f3a0000;  alias, 1 drivers
+v0xc4f30b840_0 .net/s "product", 31 0, L_0xc4ef43f20;  1 drivers
+v0xc4f30b8e0_0 .net/s "product_ext", 39 0, L_0xc4f39bf20;  1 drivers
+v0xc4f30b980_0 .net/s "w", 15 0, L_0xc4f39c1e0;  1 drivers
+v0xc4f30ba20_0 .net/s "x", 15 0, L_0xc4f39c140;  1 drivers
+L_0xc4f39bde0 .extend/s 32, L_0xc4f39c140;
+L_0xc4f39be80 .extend/s 32, L_0xc4f39c1e0;
+L_0xc4ef43f20 .arith/mult 32, L_0xc4f39bde0, L_0xc4f39be80;
+L_0xc4f39c0a0 .part L_0xc4ef43f20, 31, 1;
+L_0xc4ef50000 .repeat 8, 8, L_0xc4f39c0a0;
+L_0xc4f39bf20 .concat [ 32 8 0 0], L_0xc4ef43f20, L_0xc4ef50000;
+L_0xc4f3a0000 .arith/sum 40, L_0xc4e879f00, L_0xc4f39bf20;
+S_0xc4f30d680 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2dea00 .param/l "i" 1 5 20, +C4<0111>;
+S_0xc4f30d800 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f30d680;
+ .timescale 0 0;
+    .port_info 0 /INPUT 16 "x";
+    .port_info 1 /INPUT 16 "w";
+    .port_info 2 /INPUT 40 "acc_in";
+    .port_info 3 /OUTPUT 40 "acc_out";
+P_0xc4f2aef40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000101000>;
+P_0xc4f2aef80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000010000>;
+P_0xc4f2aefc0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000100000>;
+v0xc4f30bac0_0 .net/s *"_ivl_0", 31 0, L_0xc4f3a00a0;  1 drivers
+v0xc4f30bb60_0 .net/s *"_ivl_2", 31 0, L_0xc4f3a0140;  1 drivers
+v0xc4f30bc00_0 .net *"_ivl_7", 0 0, L_0xc4f39c280;  1 drivers
+v0xc4f30bca0_0 .net *"_ivl_9", 7 0, L_0xc4ef50140;  1 drivers
+L_0xc4e879f48 .functor BUFT 1, C4<0000000000000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f30bd40_0 .net/s "acc_in", 39 0, L_0xc4e879f48;  1 drivers
+v0xc4f30bde0_0 .net/s "acc_out", 39 0, L_0xc4f3a0280;  alias, 1 drivers
+v0xc4f30be80_0 .net/s "product", 31 0, L_0xc4ef500a0;  1 drivers
+v0xc4f30bf20_0 .net/s "product_ext", 39 0, L_0xc4f3a01e0;  1 drivers
+v0xc4f314000_0 .net/s "w", 15 0, L_0xc4f39c3c0;  1 drivers
+v0xc4f3140a0_0 .net/s "x", 15 0, L_0xc4f39c320;  1 drivers
+L_0xc4f3a00a0 .extend/s 32, L_0xc4f39c320;
+L_0xc4f3a0140 .extend/s 32, L_0xc4f39c3c0;
+L_0xc4ef500a0 .arith/mult 32, L_0xc4f3a00a0, L_0xc4f3a0140;
+L_0xc4f39c280 .part L_0xc4ef500a0, 31, 1;
+L_0xc4ef50140 .repeat 8, 8, L_0xc4f39c280;
+L_0xc4f3a01e0 .concat [ 32 8 0 0], L_0xc4ef500a0, L_0xc4ef50140;
+L_0xc4f3a0280 .arith/sum 40, L_0xc4e879f48, L_0xc4f3a01e0;
+S_0xc4f30d980 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2de900 .param/l "i" 1 5 80, +C4<00>;
+L_0xc4f065b90 .functor BUFZ 40, L_0xc4f39b0c0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f30db00 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2dea40 .param/l "i" 1 5 80, +C4<01>;
+L_0xc4f065c00 .functor BUFZ 40, L_0xc4f39b340, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f30dc80 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2dea80 .param/l "i" 1 5 80, +C4<010>;
+L_0xc4f065c70 .functor BUFZ 40, L_0xc4f39b5c0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f30de00 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2deac0 .param/l "i" 1 5 80, +C4<011>;
+L_0xc4f065ce0 .functor BUFZ 40, L_0xc4f39b840, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f30df80 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2deb00 .param/l "i" 1 5 80, +C4<0100>;
+L_0xc4f065d50 .functor BUFZ 40, L_0xc4f39bac0, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f30e100 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2deb40 .param/l "i" 1 5 80, +C4<0101>;
+L_0xc4f065dc0 .functor BUFZ 40, L_0xc4f39bd40, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f30e280 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2deb80 .param/l "i" 1 5 80, +C4<0110>;
+L_0xc4f065e30 .functor BUFZ 40, L_0xc4f3a0000, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f30e400 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2debc0 .param/l "i" 1 5 80, +C4<0111>;
+L_0xc4f065ea0 .functor BUFZ 40, L_0xc4f3a0280, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000>;
+S_0xc4f30e580 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2dec00 .param/l "level" 1 5 92, +C4<00>;
+S_0xc4f30e700 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f30e580;
+ .timescale 0 0;
+P_0xc4f2dec40 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3a0320 .arith/sum 40, L_0xc4f065b90, L_0xc4f065c00;
+S_0xc4f30e880 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f30e580;
+ .timescale 0 0;
+P_0xc4f2dec80 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3a03c0 .arith/sum 40, L_0xc4f065c70, L_0xc4f065ce0;
+S_0xc4f30ea00 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xc4f30e580;
+ .timescale 0 0;
+P_0xc4f2decc0 .param/l "node" 1 5 94, +C4<010>;
+L_0xc4f3a0460 .arith/sum 40, L_0xc4f065d50, L_0xc4f065dc0;
+S_0xc4f30eb80 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xc4f30e580;
+ .timescale 0 0;
+P_0xc4f2ded00 .param/l "node" 1 5 94, +C4<011>;
+L_0xc4f3a0500 .arith/sum 40, L_0xc4f065e30, L_0xc4f065ea0;
+S_0xc4f30ed00 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2ded40 .param/l "level" 1 5 92, +C4<01>;
+S_0xc4f30ee80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f30ed00;
+ .timescale 0 0;
+P_0xc4f2ded80 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3a05a0 .arith/sum 40, L_0xc4f3a0320, L_0xc4f3a03c0;
+S_0xc4f30f000 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f30ed00;
+ .timescale 0 0;
+P_0xc4f2dedc0 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3a0640 .arith/sum 40, L_0xc4f3a0460, L_0xc4f3a0500;
+S_0xc4f30f180 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xc4f30c000;
+ .timescale 0 0;
+P_0xc4f2dee00 .param/l "level" 1 5 92, +C4<010>;
+S_0xc4f30f300 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f30f180;
+ .timescale 0 0;
+P_0xc4f2dee40 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3a06e0 .arith/sum 40, L_0xc4f3a05a0, L_0xc4f3a0640;
+S_0x102d16ff0 .scope module, "memory_interface" "memory_interface" 7 1;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "req";
+    .port_info 3 /INPUT 1 "wr";
+    .port_info 4 /INPUT 22 "addr";
+    .port_info 5 /INPUT 16 "wdata";
+    .port_info 6 /INPUT 1 "lb_n";
+    .port_info 7 /INPUT 1 "ub_n";
+    .port_info 8 /OUTPUT 16 "rdata";
+    .port_info 9 /OUTPUT 1 "ready";
+    .port_info 10 /OUTPUT 1 "mem_req";
+    .port_info 11 /OUTPUT 1 "mem_wr";
+    .port_info 12 /OUTPUT 22 "mem_addr";
+    .port_info 13 /OUTPUT 16 "mem_wdata";
+    .port_info 14 /OUTPUT 1 "mem_lb_n";
+    .port_info 15 /OUTPUT 1 "mem_ub_n";
+    .port_info 16 /INPUT 16 "mem_rdata";
+    .port_info 17 /INPUT 1 "mem_ready";
+P_0x102d25010 .param/l "ADDR_WIDTH" 0 7 2, +C4<00000000000000000000000000010110>;
+P_0x102d25050 .param/l "DATA_WIDTH" 0 7 3, +C4<00000000000000000000000000010000>;
+P_0x102d25090 .param/l "STATE_IDLE" 1 7 28, C4<00>;
+P_0x102d250d0 .param/l "STATE_WAIT" 1 7 29, C4<01>;
+o0xc4e855650 .functor BUFZ 22, c4<zzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f315ea0_0 .net "addr", 21 0, o0xc4e855650;  0 drivers
+o0xc4e855680 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f315f40_0 .net "clk", 0 0, o0xc4e855680;  0 drivers
+o0xc4e8556b0 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f315fe0_0 .net "lb_n", 0 0, o0xc4e8556b0;  0 drivers
+v0xc4f316080_0 .var "mem_addr", 21 0;
+v0xc4f316120_0 .var "mem_lb_n", 0 0;
+o0xc4e855740 .functor BUFZ 16, c4<zzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f3161c0_0 .net "mem_rdata", 15 0, o0xc4e855740;  0 drivers
+o0xc4e855770 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f316260_0 .net "mem_ready", 0 0, o0xc4e855770;  0 drivers
+v0xc4f316300_0 .var "mem_req", 0 0;
+v0xc4f3163a0_0 .var "mem_ub_n", 0 0;
+v0xc4f316440_0 .var "mem_wdata", 15 0;
+v0xc4f3164e0_0 .var "mem_wr", 0 0;
+v0xc4f316580_0 .var "rdata", 15 0;
+v0xc4f316620_0 .var "ready", 0 0;
+o0xc4e8558c0 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f3166c0_0 .net "req", 0 0, o0xc4e8558c0;  0 drivers
+o0xc4e8558f0 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f316760_0 .net "rst", 0 0, o0xc4e8558f0;  0 drivers
+v0xc4f316800_0 .var "state", 1 0;
+o0xc4e855950 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f3168a0_0 .net "ub_n", 0 0, o0xc4e855950;  0 drivers
+o0xc4e855980 .functor BUFZ 16, c4<zzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f316940_0 .net "wdata", 15 0, o0xc4e855980;  0 drivers
+o0xc4e8559b0 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f3169e0_0 .net "wr", 0 0, o0xc4e8559b0;  0 drivers
+E_0xc4ef18800 .event posedge, v0xc4f315f40_0;
+S_0x102d24bb0 .scope module, "memory_model" "memory_model" 8 1;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "req";
+    .port_info 3 /INPUT 1 "wr";
+    .port_info 4 /INPUT 22 "addr";
+    .port_info 5 /INPUT 16 "wdata";
+    .port_info 6 /OUTPUT 16 "rdata";
+    .port_info 7 /OUTPUT 1 "ready";
+P_0x102d24d30 .param/l "ADDR_WIDTH" 0 8 2, +C4<00000000000000000000000000010110>;
+P_0x102d24d70 .param/l "DATA_WIDTH" 0 8 3, +C4<00000000000000000000000000010000>;
+P_0x102d24db0 .param/l "DEPTH" 0 8 4, +C4<00000000000000000001000000000000>;
+P_0x102d24df0 .param/l "READ_LATENCY" 0 8 5, +C4<00000000000000000000000000000010>;
+o0xc4e855d40 .functor BUFZ 22, c4<zzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f316a80_0 .net "addr", 21 0, o0xc4e855d40;  0 drivers
+v0xc4f316b20_0 .var "busy", 0 0;
+o0xc4e855da0 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f316bc0_0 .net "clk", 0 0, o0xc4e855da0;  0 drivers
+v0xc4f316c60_0 .var/i "delay_count", 31 0;
+v0xc4f316d00_0 .var/i "i", 31 0;
+v0xc4f316da0 .array "mem", 4095 0, 15 0;
+v0xc4f316e40_0 .var "pending_addr", 21 0;
+v0xc4f316ee0_0 .var "pending_wdata", 15 0;
+v0xc4f316f80_0 .var "pending_wr", 0 0;
+v0xc4f317020_0 .var "rdata", 15 0;
+v0xc4f3170c0_0 .var "ready", 0 0;
+o0xc4e855f20 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f317160_0 .net "req", 0 0, o0xc4e855f20;  0 drivers
+o0xc4e855f50 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f317200_0 .net "rst", 0 0, o0xc4e855f50;  0 drivers
+o0xc4e855f80 .functor BUFZ 16, c4<zzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f3172a0_0 .net "wdata", 15 0, o0xc4e855f80;  0 drivers
+o0xc4e855fb0 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f317340_0 .net "wr", 0 0, o0xc4e855fb0;  0 drivers
+E_0xc4ef18840 .event posedge, v0xc4f316bc0_0;
+S_0x102d16640 .scope module, "neuron_memory" "neuron_memory" 9 3;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "start";
+    .port_info 3 /OUTPUT 1 "mem_req";
+    .port_info 4 /OUTPUT 1 "mem_wr";
+    .port_info 5 /OUTPUT 22 "mem_addr";
+    .port_info 6 /OUTPUT 8 "mem_wdata";
+    .port_info 7 /INPUT 8 "mem_rdata";
+    .port_info 8 /INPUT 1 "mem_ready";
+    .port_info 9 /INPUT 22 "x_base";
+    .port_info 10 /INPUT 22 "w_base";
+    .port_info 11 /INPUT 22 "bias_addr";
+    .port_info 12 /OUTPUT 8 "y";
+    .port_info 13 /OUTPUT 1 "busy";
+    .port_info 14 /OUTPUT 1 "done";
+P_0x102d2c510 .param/l "ACC_WIDTH" 0 9 8, +C4<00000000000000000000000000100000>;
+P_0x102d2c550 .param/l "ADDR_WIDTH" 0 9 4, +C4<00000000000000000000000000010110>;
+P_0x102d2c590 .param/l "DATA_WIDTH" 0 9 5, +C4<00000000000000000000000000001000>;
+P_0x102d2c5d0 .param/l "N_INPUTS" 0 9 6, +C4<00000000000000000000000000100000>;
+P_0x102d2c610 .param/l "PARALLEL" 0 9 7, +C4<00000000000000000000000000001000>;
+P_0x102d2c650 .param/l "STATE_IDLE" 1 9 49, C4<0000>;
+P_0x102d2c690 .param/l "STATE_READ_BIAS" 1 9 52, C4<0011>;
+P_0x102d2c6d0 .param/l "STATE_READ_W" 1 9 51, C4<0010>;
+P_0x102d2c710 .param/l "STATE_READ_X" 1 9 50, C4<0001>;
+P_0x102d2c750 .param/l "STATE_START_N" 1 9 53, C4<0100>;
+P_0x102d2c790 .param/l "STATE_WAIT_N" 1 9 54, C4<0101>;
+L_0xc4f067b10 .functor BUFZ 1, v0xc4f322080_0, C4<0>, C4<0>, C4<0>;
+L_0xc4f067b80 .functor BUFZ 1, v0xc4f322260_0, C4<0>, C4<0>, C4<0>;
+L_0xc4f067bf0 .functor BUFZ 22, v0xc4f327340_0, C4<0000000000000000000000>, C4<0000000000000000000000>, C4<0000000000000000000000>;
+L_0xc4f067c60 .functor BUFZ 8, v0xc4f327a20_0, C4<00000000>, C4<00000000>, C4<00000000>;
+v0xc4f327020_0 .net *"_ivl_131", 0 0, L_0xc4f39c780;  1 drivers
+L_0xc4e879f90 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3270c0_0 .net/2u *"_ivl_132", 7 0, L_0xc4e879f90;  1 drivers
+v0xc4f327160_0 .net *"_ivl_134", 15 0, L_0xc4f3a0c80;  1 drivers
+L_0xc4e879fd8 .functor BUFT 1, C4<00000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f327200_0 .net/2u *"_ivl_136", 7 0, L_0xc4e879fd8;  1 drivers
+v0xc4f3272a0_0 .net *"_ivl_138", 15 0, L_0xc4f3a0d20;  1 drivers
+v0xc4f327340_0 .var "access_addr", 21 0;
+v0xc4f3273e0_0 .net "access_mem_addr", 21 0, v0xc4f321e00_0;  1 drivers
+v0xc4f327480_0 .net "access_mem_lb_n", 0 0, v0xc4f321ea0_0;  1 drivers
+v0xc4f327520_0 .net "access_mem_rdata", 15 0, L_0xc4f39c820;  1 drivers
+v0xc4f3275c0_0 .net "access_mem_req", 0 0, v0xc4f322080_0;  1 drivers
+v0xc4f327660_0 .net "access_mem_ub_n", 0 0, v0xc4f322120_0;  1 drivers
+v0xc4f327700_0 .net "access_mem_wdata", 15 0, v0xc4f3221c0_0;  1 drivers
+v0xc4f3277a0_0 .net "access_mem_wr", 0 0, v0xc4f322260_0;  1 drivers
+v0xc4f327840_0 .net/s "access_rdata", 7 0, v0xc4f322300_0;  1 drivers
+v0xc4f3278e0_0 .net "access_ready", 0 0, v0xc4f3223a0_0;  1 drivers
+v0xc4f327980_0 .var "access_req", 0 0;
+v0xc4f327a20_0 .var/s "access_wdata", 7 0;
+v0xc4f327ac0_0 .var "access_wr", 0 0;
+o0xc4e859760 .functor BUFZ 22, c4<zzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f327b60_0 .net "bias_addr", 21 0, o0xc4e859760;  0 drivers
+v0xc4f327c00_0 .var/s "bias_reg", 7 0;
+v0xc4f327ca0_0 .var "busy", 0 0;
+o0xc4e856dc0 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f327d40_0 .net "clk", 0 0, o0xc4e856dc0;  0 drivers
+v0xc4f327de0_0 .var "done", 0 0;
+v0xc4f327e80_0 .var "index", 5 0;
+v0xc4f327f20_0 .net "mem_addr", 21 0, L_0xc4f067bf0;  1 drivers
+o0xc4e859850 .functor BUFZ 8, c4<zzzzzzzz>; HiZ drive
+v0xc4f32c000_0 .net/s "mem_rdata", 7 0, o0xc4e859850;  0 drivers
+o0xc4e856e80 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f32c0a0_0 .net "mem_ready", 0 0, o0xc4e856e80;  0 drivers
+v0xc4f32c140_0 .net "mem_req", 0 0, L_0xc4f067b10;  1 drivers
+v0xc4f32c1e0_0 .net/s "mem_wdata", 7 0, L_0xc4f067c60;  1 drivers
+v0xc4f32c280_0 .net "mem_wr", 0 0, L_0xc4f067b80;  1 drivers
+v0xc4f32c320_0 .net "neuron_busy", 0 0, v0xc4f3268a0_0;  1 drivers
+v0xc4f32c3c0_0 .net "neuron_done", 0 0, v0xc4f3269e0_0;  1 drivers
+v0xc4f32c460_0 .var "neuron_start", 0 0;
+v0xc4f32c500_0 .net/s "neuron_y", 7 0, v0xc4f326f80_0;  1 drivers
+o0xc4e857000 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f32c5a0_0 .net "rst", 0 0, o0xc4e857000;  0 drivers
+o0xc4e859910 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f32c640_0 .net "start", 0 0, o0xc4e859910;  0 drivers
+v0xc4f32c6e0_0 .var "state", 3 0;
+o0xc4e859970 .functor BUFZ 22, c4<zzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f32c780_0 .net "w_base", 21 0, o0xc4e859970;  0 drivers
+v0xc4f32c820_0 .net/s "w_bus", 255 0, L_0xc4f3a0be0;  1 drivers
+v0xc4f32c8c0 .array/s "w_mem", 31 0, 7 0;
+o0xc4e859fa0 .functor BUFZ 22, c4<zzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f32c960_0 .net "x_base", 21 0, o0xc4e859fa0;  0 drivers
+v0xc4f32ca00_0 .net/s "x_bus", 255 0, L_0xc4f3a0b40;  1 drivers
+v0xc4f32caa0 .array/s "x_mem", 31 0, 7 0;
+v0xc4f32cb40_0 .var/s "y", 7 0;
+v0xc4f32caa0_0 .array/port v0xc4f32caa0, 0;
+v0xc4f32caa0_1 .array/port v0xc4f32caa0, 1;
+v0xc4f32caa0_2 .array/port v0xc4f32caa0, 2;
+v0xc4f32caa0_3 .array/port v0xc4f32caa0, 3;
+LS_0xc4f3a0b40_0_0 .concat8 [ 8 8 8 8], v0xc4f32caa0_0, v0xc4f32caa0_1, v0xc4f32caa0_2, v0xc4f32caa0_3;
+v0xc4f32caa0_4 .array/port v0xc4f32caa0, 4;
+v0xc4f32caa0_5 .array/port v0xc4f32caa0, 5;
+v0xc4f32caa0_6 .array/port v0xc4f32caa0, 6;
+v0xc4f32caa0_7 .array/port v0xc4f32caa0, 7;
+LS_0xc4f3a0b40_0_4 .concat8 [ 8 8 8 8], v0xc4f32caa0_4, v0xc4f32caa0_5, v0xc4f32caa0_6, v0xc4f32caa0_7;
+v0xc4f32caa0_8 .array/port v0xc4f32caa0, 8;
+v0xc4f32caa0_9 .array/port v0xc4f32caa0, 9;
+v0xc4f32caa0_10 .array/port v0xc4f32caa0, 10;
+v0xc4f32caa0_11 .array/port v0xc4f32caa0, 11;
+LS_0xc4f3a0b40_0_8 .concat8 [ 8 8 8 8], v0xc4f32caa0_8, v0xc4f32caa0_9, v0xc4f32caa0_10, v0xc4f32caa0_11;
+v0xc4f32caa0_12 .array/port v0xc4f32caa0, 12;
+v0xc4f32caa0_13 .array/port v0xc4f32caa0, 13;
+v0xc4f32caa0_14 .array/port v0xc4f32caa0, 14;
+v0xc4f32caa0_15 .array/port v0xc4f32caa0, 15;
+LS_0xc4f3a0b40_0_12 .concat8 [ 8 8 8 8], v0xc4f32caa0_12, v0xc4f32caa0_13, v0xc4f32caa0_14, v0xc4f32caa0_15;
+v0xc4f32caa0_16 .array/port v0xc4f32caa0, 16;
+v0xc4f32caa0_17 .array/port v0xc4f32caa0, 17;
+v0xc4f32caa0_18 .array/port v0xc4f32caa0, 18;
+v0xc4f32caa0_19 .array/port v0xc4f32caa0, 19;
+LS_0xc4f3a0b40_0_16 .concat8 [ 8 8 8 8], v0xc4f32caa0_16, v0xc4f32caa0_17, v0xc4f32caa0_18, v0xc4f32caa0_19;
+v0xc4f32caa0_20 .array/port v0xc4f32caa0, 20;
+v0xc4f32caa0_21 .array/port v0xc4f32caa0, 21;
+v0xc4f32caa0_22 .array/port v0xc4f32caa0, 22;
+v0xc4f32caa0_23 .array/port v0xc4f32caa0, 23;
+LS_0xc4f3a0b40_0_20 .concat8 [ 8 8 8 8], v0xc4f32caa0_20, v0xc4f32caa0_21, v0xc4f32caa0_22, v0xc4f32caa0_23;
+v0xc4f32caa0_24 .array/port v0xc4f32caa0, 24;
+v0xc4f32caa0_25 .array/port v0xc4f32caa0, 25;
+v0xc4f32caa0_26 .array/port v0xc4f32caa0, 26;
+v0xc4f32caa0_27 .array/port v0xc4f32caa0, 27;
+LS_0xc4f3a0b40_0_24 .concat8 [ 8 8 8 8], v0xc4f32caa0_24, v0xc4f32caa0_25, v0xc4f32caa0_26, v0xc4f32caa0_27;
+v0xc4f32caa0_28 .array/port v0xc4f32caa0, 28;
+v0xc4f32caa0_29 .array/port v0xc4f32caa0, 29;
+v0xc4f32caa0_30 .array/port v0xc4f32caa0, 30;
+v0xc4f32caa0_31 .array/port v0xc4f32caa0, 31;
+LS_0xc4f3a0b40_0_28 .concat8 [ 8 8 8 8], v0xc4f32caa0_28, v0xc4f32caa0_29, v0xc4f32caa0_30, v0xc4f32caa0_31;
+LS_0xc4f3a0b40_1_0 .concat8 [ 32 32 32 32], LS_0xc4f3a0b40_0_0, LS_0xc4f3a0b40_0_4, LS_0xc4f3a0b40_0_8, LS_0xc4f3a0b40_0_12;
+LS_0xc4f3a0b40_1_4 .concat8 [ 32 32 32 32], LS_0xc4f3a0b40_0_16, LS_0xc4f3a0b40_0_20, LS_0xc4f3a0b40_0_24, LS_0xc4f3a0b40_0_28;
+L_0xc4f3a0b40 .concat8 [ 128 128 0 0], LS_0xc4f3a0b40_1_0, LS_0xc4f3a0b40_1_4;
+v0xc4f32c8c0_0 .array/port v0xc4f32c8c0, 0;
+v0xc4f32c8c0_1 .array/port v0xc4f32c8c0, 1;
+v0xc4f32c8c0_2 .array/port v0xc4f32c8c0, 2;
+v0xc4f32c8c0_3 .array/port v0xc4f32c8c0, 3;
+LS_0xc4f3a0be0_0_0 .concat8 [ 8 8 8 8], v0xc4f32c8c0_0, v0xc4f32c8c0_1, v0xc4f32c8c0_2, v0xc4f32c8c0_3;
+v0xc4f32c8c0_4 .array/port v0xc4f32c8c0, 4;
+v0xc4f32c8c0_5 .array/port v0xc4f32c8c0, 5;
+v0xc4f32c8c0_6 .array/port v0xc4f32c8c0, 6;
+v0xc4f32c8c0_7 .array/port v0xc4f32c8c0, 7;
+LS_0xc4f3a0be0_0_4 .concat8 [ 8 8 8 8], v0xc4f32c8c0_4, v0xc4f32c8c0_5, v0xc4f32c8c0_6, v0xc4f32c8c0_7;
+v0xc4f32c8c0_8 .array/port v0xc4f32c8c0, 8;
+v0xc4f32c8c0_9 .array/port v0xc4f32c8c0, 9;
+v0xc4f32c8c0_10 .array/port v0xc4f32c8c0, 10;
+v0xc4f32c8c0_11 .array/port v0xc4f32c8c0, 11;
+LS_0xc4f3a0be0_0_8 .concat8 [ 8 8 8 8], v0xc4f32c8c0_8, v0xc4f32c8c0_9, v0xc4f32c8c0_10, v0xc4f32c8c0_11;
+v0xc4f32c8c0_12 .array/port v0xc4f32c8c0, 12;
+v0xc4f32c8c0_13 .array/port v0xc4f32c8c0, 13;
+v0xc4f32c8c0_14 .array/port v0xc4f32c8c0, 14;
+v0xc4f32c8c0_15 .array/port v0xc4f32c8c0, 15;
+LS_0xc4f3a0be0_0_12 .concat8 [ 8 8 8 8], v0xc4f32c8c0_12, v0xc4f32c8c0_13, v0xc4f32c8c0_14, v0xc4f32c8c0_15;
+v0xc4f32c8c0_16 .array/port v0xc4f32c8c0, 16;
+v0xc4f32c8c0_17 .array/port v0xc4f32c8c0, 17;
+v0xc4f32c8c0_18 .array/port v0xc4f32c8c0, 18;
+v0xc4f32c8c0_19 .array/port v0xc4f32c8c0, 19;
+LS_0xc4f3a0be0_0_16 .concat8 [ 8 8 8 8], v0xc4f32c8c0_16, v0xc4f32c8c0_17, v0xc4f32c8c0_18, v0xc4f32c8c0_19;
+v0xc4f32c8c0_20 .array/port v0xc4f32c8c0, 20;
+v0xc4f32c8c0_21 .array/port v0xc4f32c8c0, 21;
+v0xc4f32c8c0_22 .array/port v0xc4f32c8c0, 22;
+v0xc4f32c8c0_23 .array/port v0xc4f32c8c0, 23;
+LS_0xc4f3a0be0_0_20 .concat8 [ 8 8 8 8], v0xc4f32c8c0_20, v0xc4f32c8c0_21, v0xc4f32c8c0_22, v0xc4f32c8c0_23;
+v0xc4f32c8c0_24 .array/port v0xc4f32c8c0, 24;
+v0xc4f32c8c0_25 .array/port v0xc4f32c8c0, 25;
+v0xc4f32c8c0_26 .array/port v0xc4f32c8c0, 26;
+v0xc4f32c8c0_27 .array/port v0xc4f32c8c0, 27;
+LS_0xc4f3a0be0_0_24 .concat8 [ 8 8 8 8], v0xc4f32c8c0_24, v0xc4f32c8c0_25, v0xc4f32c8c0_26, v0xc4f32c8c0_27;
+v0xc4f32c8c0_28 .array/port v0xc4f32c8c0, 28;
+v0xc4f32c8c0_29 .array/port v0xc4f32c8c0, 29;
+v0xc4f32c8c0_30 .array/port v0xc4f32c8c0, 30;
+v0xc4f32c8c0_31 .array/port v0xc4f32c8c0, 31;
+LS_0xc4f3a0be0_0_28 .concat8 [ 8 8 8 8], v0xc4f32c8c0_28, v0xc4f32c8c0_29, v0xc4f32c8c0_30, v0xc4f32c8c0_31;
+LS_0xc4f3a0be0_1_0 .concat8 [ 32 32 32 32], LS_0xc4f3a0be0_0_0, LS_0xc4f3a0be0_0_4, LS_0xc4f3a0be0_0_8, LS_0xc4f3a0be0_0_12;
+LS_0xc4f3a0be0_1_4 .concat8 [ 32 32 32 32], LS_0xc4f3a0be0_0_16, LS_0xc4f3a0be0_0_20, LS_0xc4f3a0be0_0_24, LS_0xc4f3a0be0_0_28;
+L_0xc4f3a0be0 .concat8 [ 128 128 0 0], LS_0xc4f3a0be0_1_0, LS_0xc4f3a0be0_1_4;
+L_0xc4f39c780 .part v0xc4f327340_0, 0, 1;
+L_0xc4f3a0c80 .concat [ 8 8 0 0], L_0xc4e879f90, o0xc4e859850;
+L_0xc4f3a0d20 .concat [ 8 8 0 0], o0xc4e859850, L_0xc4e879fd8;
+L_0xc4f39c820 .functor MUXZ 16, L_0xc4f3a0d20, L_0xc4f3a0c80, L_0xc4f39c780, C4<>;
+S_0xc4f30f480 .scope generate, "GEN_BUS[0]" "GEN_BUS[0]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2deec0 .param/l "i" 1 9 79, +C4<00>;
+v0xc4f3173e0_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_0;  1 drivers
+v0xc4f317480_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_0;  1 drivers
+S_0xc4f30f600 .scope generate, "GEN_BUS[1]" "GEN_BUS[1]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2def00 .param/l "i" 1 9 79, +C4<01>;
+v0xc4f317520_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_1;  1 drivers
+v0xc4f3175c0_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_1;  1 drivers
+S_0xc4f30f780 .scope generate, "GEN_BUS[2]" "GEN_BUS[2]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2def40 .param/l "i" 1 9 79, +C4<010>;
+v0xc4f317660_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_2;  1 drivers
+v0xc4f317700_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_2;  1 drivers
+S_0xc4f30f900 .scope generate, "GEN_BUS[3]" "GEN_BUS[3]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2def80 .param/l "i" 1 9 79, +C4<011>;
+v0xc4f3177a0_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_3;  1 drivers
+v0xc4f317840_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_3;  1 drivers
+S_0xc4f30fa80 .scope generate, "GEN_BUS[4]" "GEN_BUS[4]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df000 .param/l "i" 1 9 79, +C4<0100>;
+v0xc4f3178e0_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_4;  1 drivers
+v0xc4f317980_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_4;  1 drivers
+S_0xc4f30fc00 .scope generate, "GEN_BUS[5]" "GEN_BUS[5]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df040 .param/l "i" 1 9 79, +C4<0101>;
+v0xc4f317a20_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_5;  1 drivers
+v0xc4f317ac0_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_5;  1 drivers
+S_0xc4f30fd80 .scope generate, "GEN_BUS[6]" "GEN_BUS[6]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df080 .param/l "i" 1 9 79, +C4<0110>;
+v0xc4f317b60_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_6;  1 drivers
+v0xc4f317c00_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_6;  1 drivers
+S_0xc4f31c000 .scope generate, "GEN_BUS[7]" "GEN_BUS[7]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df0c0 .param/l "i" 1 9 79, +C4<0111>;
+v0xc4f317ca0_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_7;  1 drivers
+v0xc4f317d40_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_7;  1 drivers
+S_0xc4f31c180 .scope generate, "GEN_BUS[8]" "GEN_BUS[8]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2defc0 .param/l "i" 1 9 79, +C4<01000>;
+v0xc4f317de0_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_8;  1 drivers
+v0xc4f317e80_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_8;  1 drivers
+S_0xc4f31c300 .scope generate, "GEN_BUS[9]" "GEN_BUS[9]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df100 .param/l "i" 1 9 79, +C4<01001>;
+v0xc4f317f20_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_9;  1 drivers
+v0xc4f320000_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_9;  1 drivers
+S_0xc4f31c480 .scope generate, "GEN_BUS[10]" "GEN_BUS[10]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df140 .param/l "i" 1 9 79, +C4<01010>;
+v0xc4f3200a0_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_10;  1 drivers
+v0xc4f320140_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_10;  1 drivers
+S_0xc4f31c600 .scope generate, "GEN_BUS[11]" "GEN_BUS[11]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df180 .param/l "i" 1 9 79, +C4<01011>;
+v0xc4f3201e0_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_11;  1 drivers
+v0xc4f320280_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_11;  1 drivers
+S_0xc4f31c780 .scope generate, "GEN_BUS[12]" "GEN_BUS[12]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df1c0 .param/l "i" 1 9 79, +C4<01100>;
+v0xc4f320320_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_12;  1 drivers
+v0xc4f3203c0_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_12;  1 drivers
+S_0xc4f31c900 .scope generate, "GEN_BUS[13]" "GEN_BUS[13]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df200 .param/l "i" 1 9 79, +C4<01101>;
+v0xc4f320460_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_13;  1 drivers
+v0xc4f320500_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_13;  1 drivers
+S_0xc4f31ca80 .scope generate, "GEN_BUS[14]" "GEN_BUS[14]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df240 .param/l "i" 1 9 79, +C4<01110>;
+v0xc4f3205a0_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_14;  1 drivers
+v0xc4f320640_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_14;  1 drivers
+S_0xc4f31cc00 .scope generate, "GEN_BUS[15]" "GEN_BUS[15]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df280 .param/l "i" 1 9 79, +C4<01111>;
+v0xc4f3206e0_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_15;  1 drivers
+v0xc4f320780_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_15;  1 drivers
+S_0xc4f31cd80 .scope generate, "GEN_BUS[16]" "GEN_BUS[16]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df2c0 .param/l "i" 1 9 79, +C4<010000>;
+v0xc4f320820_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_16;  1 drivers
+v0xc4f3208c0_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_16;  1 drivers
+S_0xc4f31cf00 .scope generate, "GEN_BUS[17]" "GEN_BUS[17]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df300 .param/l "i" 1 9 79, +C4<010001>;
+v0xc4f320960_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_17;  1 drivers
+v0xc4f320a00_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_17;  1 drivers
+S_0xc4f31d080 .scope generate, "GEN_BUS[18]" "GEN_BUS[18]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df340 .param/l "i" 1 9 79, +C4<010010>;
+v0xc4f320aa0_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_18;  1 drivers
+v0xc4f320b40_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_18;  1 drivers
+S_0xc4f31d200 .scope generate, "GEN_BUS[19]" "GEN_BUS[19]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df380 .param/l "i" 1 9 79, +C4<010011>;
+v0xc4f320be0_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_19;  1 drivers
+v0xc4f320c80_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_19;  1 drivers
+S_0xc4f31d380 .scope generate, "GEN_BUS[20]" "GEN_BUS[20]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df3c0 .param/l "i" 1 9 79, +C4<010100>;
+v0xc4f320d20_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_20;  1 drivers
+v0xc4f320dc0_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_20;  1 drivers
+S_0xc4f31d500 .scope generate, "GEN_BUS[21]" "GEN_BUS[21]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df400 .param/l "i" 1 9 79, +C4<010101>;
+v0xc4f320e60_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_21;  1 drivers
+v0xc4f320f00_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_21;  1 drivers
+S_0xc4f31d680 .scope generate, "GEN_BUS[22]" "GEN_BUS[22]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df440 .param/l "i" 1 9 79, +C4<010110>;
+v0xc4f320fa0_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_22;  1 drivers
+v0xc4f321040_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_22;  1 drivers
+S_0xc4f31d800 .scope generate, "GEN_BUS[23]" "GEN_BUS[23]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df480 .param/l "i" 1 9 79, +C4<010111>;
+v0xc4f3210e0_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_23;  1 drivers
+v0xc4f321180_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_23;  1 drivers
+S_0xc4f31d980 .scope generate, "GEN_BUS[24]" "GEN_BUS[24]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df4c0 .param/l "i" 1 9 79, +C4<011000>;
+v0xc4f321220_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_24;  1 drivers
+v0xc4f3212c0_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_24;  1 drivers
+S_0xc4f31db00 .scope generate, "GEN_BUS[25]" "GEN_BUS[25]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df500 .param/l "i" 1 9 79, +C4<011001>;
+v0xc4f321360_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_25;  1 drivers
+v0xc4f321400_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_25;  1 drivers
+S_0xc4f31dc80 .scope generate, "GEN_BUS[26]" "GEN_BUS[26]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df540 .param/l "i" 1 9 79, +C4<011010>;
+v0xc4f3214a0_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_26;  1 drivers
+v0xc4f321540_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_26;  1 drivers
+S_0xc4f31de00 .scope generate, "GEN_BUS[27]" "GEN_BUS[27]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df580 .param/l "i" 1 9 79, +C4<011011>;
+v0xc4f3215e0_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_27;  1 drivers
+v0xc4f321680_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_27;  1 drivers
+S_0xc4f31df80 .scope generate, "GEN_BUS[28]" "GEN_BUS[28]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df5c0 .param/l "i" 1 9 79, +C4<011100>;
+v0xc4f321720_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_28;  1 drivers
+v0xc4f3217c0_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_28;  1 drivers
+S_0xc4f31e100 .scope generate, "GEN_BUS[29]" "GEN_BUS[29]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df600 .param/l "i" 1 9 79, +C4<011101>;
+v0xc4f321860_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_29;  1 drivers
+v0xc4f321900_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_29;  1 drivers
+S_0xc4f31e280 .scope generate, "GEN_BUS[30]" "GEN_BUS[30]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df640 .param/l "i" 1 9 79, +C4<011110>;
+v0xc4f3219a0_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_30;  1 drivers
+v0xc4f321a40_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_30;  1 drivers
+S_0xc4f31e400 .scope generate, "GEN_BUS[31]" "GEN_BUS[31]" 9 79, 9 79 0, S_0x102d16640;
+ .timescale -9 -12;
+P_0xc4f2df680 .param/l "i" 1 9 79, +C4<011111>;
+v0xc4f321ae0_0 .net *"_ivl_2", 7 0, v0xc4f32caa0_31;  1 drivers
+v0xc4f321b80_0 .net *"_ivl_5", 7 0, v0xc4f32c8c0_31;  1 drivers
+S_0xc4f31e580 .scope module, "u_mem" "int8_memory_access" 9 142, 10 1 0, S_0x102d16640;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "req";
+    .port_info 3 /INPUT 1 "wr";
+    .port_info 4 /INPUT 22 "addr";
+    .port_info 5 /INPUT 8 "wdata";
+    .port_info 6 /OUTPUT 8 "rdata";
+    .port_info 7 /OUTPUT 1 "ready";
+    .port_info 8 /OUTPUT 1 "mem_req";
+    .port_info 9 /OUTPUT 1 "mem_wr";
+    .port_info 10 /OUTPUT 22 "mem_addr";
+    .port_info 11 /OUTPUT 16 "mem_wdata";
+    .port_info 12 /OUTPUT 1 "mem_lb_n";
+    .port_info 13 /OUTPUT 1 "mem_ub_n";
+    .port_info 14 /INPUT 16 "mem_rdata";
+    .port_info 15 /INPUT 1 "mem_ready";
+P_0xc4f2af000 .param/l "ADDR_WIDTH" 0 10 2, +C4<00000000000000000000000000010110>;
+P_0xc4f2af040 .param/l "STATE_IDLE" 1 10 40, C4<00>;
+P_0xc4f2af080 .param/l "STATE_WAIT" 1 10 41, C4<01>;
+v0xc4f321c20_0 .net "addr", 21 0, v0xc4f327340_0;  1 drivers
+v0xc4f321cc0_0 .var "addr_reg", 21 0;
+v0xc4f321d60_0 .net "clk", 0 0, o0xc4e856dc0;  alias, 0 drivers
+v0xc4f321e00_0 .var "mem_addr", 21 0;
+v0xc4f321ea0_0 .var "mem_lb_n", 0 0;
+v0xc4f321f40_0 .net "mem_rdata", 15 0, L_0xc4f39c820;  alias, 1 drivers
+v0xc4f321fe0_0 .net "mem_ready", 0 0, o0xc4e856e80;  alias, 0 drivers
+v0xc4f322080_0 .var "mem_req", 0 0;
+v0xc4f322120_0 .var "mem_ub_n", 0 0;
+v0xc4f3221c0_0 .var "mem_wdata", 15 0;
+v0xc4f322260_0 .var "mem_wr", 0 0;
+v0xc4f322300_0 .var/s "rdata", 7 0;
+v0xc4f3223a0_0 .var "ready", 0 0;
+v0xc4f322440_0 .net "req", 0 0, v0xc4f327980_0;  1 drivers
+v0xc4f3224e0_0 .net "rst", 0 0, o0xc4e857000;  alias, 0 drivers
+v0xc4f322580_0 .var "state", 1 0;
+v0xc4f322620_0 .net/s "wdata", 7 0, v0xc4f327a20_0;  1 drivers
+v0xc4f3226c0_0 .net "wr", 0 0, v0xc4f327ac0_0;  1 drivers
+E_0xc4ef188c0 .event posedge, v0xc4f321d60_0;
+S_0xc4f31e700 .scope module, "u_neuron" "neuron_parallel" 9 203, 4 1 0, S_0x102d16640;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "start";
+    .port_info 3 /INPUT 256 "x_bus";
+    .port_info 4 /INPUT 256 "w_bus";
+    .port_info 5 /INPUT 8 "bias";
+    .port_info 6 /OUTPUT 8 "y";
+    .port_info 7 /OUTPUT 1 "busy";
+    .port_info 8 /OUTPUT 1 "done";
+P_0x102d2da10 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000100000>;
+P_0x102d2da50 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000001000>;
+P_0x102d2da90 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000000100>;
+P_0x102d2dad0 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000010>;
+P_0x102d2db10 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000000100000>;
+P_0x102d2db50 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>;
+v0xc4f325d60_0 .net *"_ivl_0", 31 0, L_0xc4f3a0dc0;  1 drivers
+v0xc4f325e00_0 .net *"_ivl_11", 31 0, L_0xc4ef503c0;  1 drivers
+v0xc4f325ea0_0 .net *"_ivl_14", 31 0, L_0xc4f3a0e60;  1 drivers
+L_0xc4e87a0f8 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f325f40_0 .net *"_ivl_17", 29 0, L_0xc4e87a0f8;  1 drivers
+L_0xc4e87a140 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f325fe0_0 .net/2u *"_ivl_18", 31 0, L_0xc4e87a140;  1 drivers
+v0xc4f326080_0 .net *"_ivl_21", 31 0, L_0xc4ef50460;  1 drivers
+L_0xc4e87a188 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f326120_0 .net/2u *"_ivl_22", 31 0, L_0xc4e87a188;  1 drivers
+v0xc4f3261c0_0 .net *"_ivl_25", 31 0, L_0xc4ef50500;  1 drivers
+v0xc4f326260_0 .net *"_ivl_29", 0 0, L_0xc4f39d900;  1 drivers
+L_0xc4e87a020 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f326300_0 .net *"_ivl_3", 29 0, L_0xc4e87a020;  1 drivers
+v0xc4f3263a0_0 .net *"_ivl_31", 23 0, L_0xc4ef51040;  1 drivers
+L_0xc4e87a068 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f326440_0 .net/2u *"_ivl_4", 31 0, L_0xc4e87a068;  1 drivers
+v0xc4f3264e0_0 .net *"_ivl_7", 31 0, L_0xc4ef50320;  1 drivers
+L_0xc4e87a0b0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f326580_0 .net/2u *"_ivl_8", 31 0, L_0xc4e87a0b0;  1 drivers
+v0xc4f326620_0 .var/s "acc", 31 0;
+v0xc4f3266c0_0 .net/s "acc_next", 31 0, L_0xc4f3a2760;  1 drivers
+v0xc4f326760_0 .net/s "bias", 7 0, v0xc4f327c00_0;  1 drivers
+v0xc4f326800_0 .net/s "bias_ext", 31 0, L_0xc4f3a2800;  1 drivers
+v0xc4f3268a0_0 .var "busy", 0 0;
+v0xc4f326940_0 .net "clk", 0 0, o0xc4e856dc0;  alias, 0 drivers
+v0xc4f3269e0_0 .var "done", 0 0;
+v0xc4f326a80_0 .net/s "final_acc", 31 0, L_0xc4f3a28a0;  1 drivers
+v0xc4f326b20_0 .var "group_index", 1 0;
+v0xc4f326bc0_0 .net "rst", 0 0, o0xc4e857000;  alias, 0 drivers
+v0xc4f326c60_0 .net "start", 0 0, v0xc4f32c460_0;  1 drivers
+v0xc4f326d00_0 .net/s "w_bus", 255 0, L_0xc4f3a0be0;  alias, 1 drivers
+v0xc4f326da0_0 .net/s "w_group", 63 0, L_0xc4f39c960;  1 drivers
+v0xc4f326e40_0 .net/s "x_bus", 255 0, L_0xc4f3a0b40;  alias, 1 drivers
+v0xc4f326ee0_0 .net/s "x_group", 63 0, L_0xc4f39c8c0;  1 drivers
+v0xc4f326f80_0 .var/s "y", 7 0;
+L_0xc4f3a0dc0 .concat [ 2 30 0 0], v0xc4f326b20_0, L_0xc4e87a020;
+L_0xc4ef50320 .arith/mult 32, L_0xc4f3a0dc0, L_0xc4e87a068;
+L_0xc4ef503c0 .arith/mult 32, L_0xc4ef50320, L_0xc4e87a0b0;
+L_0xc4f39c8c0 .part/v L_0xc4f3a0b40, L_0xc4ef503c0, 64;
+L_0xc4f3a0e60 .concat [ 2 30 0 0], v0xc4f326b20_0, L_0xc4e87a0f8;
+L_0xc4ef50460 .arith/mult 32, L_0xc4f3a0e60, L_0xc4e87a140;
+L_0xc4ef50500 .arith/mult 32, L_0xc4ef50460, L_0xc4e87a188;
+L_0xc4f39c960 .part/v L_0xc4f3a0be0, L_0xc4ef50500, 64;
+L_0xc4f39d900 .part v0xc4f327c00_0, 7, 1;
+L_0xc4ef51040 .repeat 24, 24, L_0xc4f39d900;
+L_0xc4f3a2800 .concat [ 8 24 0 0], v0xc4f327c00_0, L_0xc4ef51040;
+L_0xc4f3a28a0 .arith/sum 32, L_0xc4f3a2760, L_0xc4f3a2800;
+S_0xc4f31e880 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xc4f31e700;
+ .timescale 0 0;
+    .port_info 0 /INPUT 64 "x_bus";
+    .port_info 1 /INPUT 64 "w_bus";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4ef0da00 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000100000>;
+P_0xc4ef0da40 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000001000>;
+P_0xc4ef0da80 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>;
+P_0xc4ef0dac0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>;
+v0xc4f3259a0_0 .net/s "acc_in", 31 0, v0xc4f326620_0;  1 drivers
+v0xc4f325a40_0 .net/s "acc_out", 31 0, L_0xc4f3a2760;  alias, 1 drivers
+v0xc4f325ae0 .array "products", 7 0;
+v0xc4f325ae0_0 .net/s v0xc4f325ae0 0, 31 0, L_0xc4f3a10e0; 1 drivers
+v0xc4f325ae0_1 .net/s v0xc4f325ae0 1, 31 0, L_0xc4f3a1360; 1 drivers
+v0xc4f325ae0_2 .net/s v0xc4f325ae0 2, 31 0, L_0xc4f3a15e0; 1 drivers
+v0xc4f325ae0_3 .net/s v0xc4f325ae0 3, 31 0, L_0xc4f3a1860; 1 drivers
+v0xc4f325ae0_4 .net/s v0xc4f325ae0 4, 31 0, L_0xc4f3a1ae0; 1 drivers
+v0xc4f325ae0_5 .net/s v0xc4f325ae0 5, 31 0, L_0xc4f3a1d60; 1 drivers
+v0xc4f325ae0_6 .net/s v0xc4f325ae0 6, 31 0, L_0xc4f3a1fe0; 1 drivers
+v0xc4f325ae0_7 .net/s v0xc4f325ae0 7, 31 0, L_0xc4f3a2260; 1 drivers
+v0xc4f325b80 .array "tree", 31 0;
+v0xc4f325b80_0 .net/s v0xc4f325b80 0, 31 0, L_0xc4f067cd0; 1 drivers
+v0xc4f325b80_1 .net/s v0xc4f325b80 1, 31 0, L_0xc4f067d40; 1 drivers
+v0xc4f325b80_2 .net/s v0xc4f325b80 2, 31 0, L_0xc4f067db0; 1 drivers
+v0xc4f325b80_3 .net/s v0xc4f325b80 3, 31 0, L_0xc4f067e20; 1 drivers
+v0xc4f325b80_4 .net/s v0xc4f325b80 4, 31 0, L_0xc4f067e90; 1 drivers
+v0xc4f325b80_5 .net/s v0xc4f325b80 5, 31 0, L_0xc4f067f00; 1 drivers
+v0xc4f325b80_6 .net/s v0xc4f325b80 6, 31 0, L_0xc4f067f70; 1 drivers
+v0xc4f325b80_7 .net/s v0xc4f325b80 7, 31 0, L_0xc4f3a4000; 1 drivers
+v0xc4f325b80_8 .net/s v0xc4f325b80 8, 31 0, L_0xc4f3a2300; 1 drivers
+v0xc4f325b80_9 .net/s v0xc4f325b80 9, 31 0, L_0xc4f3a23a0; 1 drivers
+v0xc4f325b80_10 .net/s v0xc4f325b80 10, 31 0, L_0xc4f3a2440; 1 drivers
+v0xc4f325b80_11 .net/s v0xc4f325b80 11, 31 0, L_0xc4f3a24e0; 1 drivers
+o0xc4e858b60 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f325b80_12 .net/s v0xc4f325b80 12, 31 0, o0xc4e858b60; 0 drivers
+o0xc4e858b90 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f325b80_13 .net/s v0xc4f325b80 13, 31 0, o0xc4e858b90; 0 drivers
+o0xc4e858bc0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f325b80_14 .net/s v0xc4f325b80 14, 31 0, o0xc4e858bc0; 0 drivers
+o0xc4e858bf0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f325b80_15 .net/s v0xc4f325b80 15, 31 0, o0xc4e858bf0; 0 drivers
+v0xc4f325b80_16 .net/s v0xc4f325b80 16, 31 0, L_0xc4f3a2580; 1 drivers
+v0xc4f325b80_17 .net/s v0xc4f325b80 17, 31 0, L_0xc4f3a2620; 1 drivers
+o0xc4e858c80 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f325b80_18 .net/s v0xc4f325b80 18, 31 0, o0xc4e858c80; 0 drivers
+o0xc4e858cb0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f325b80_19 .net/s v0xc4f325b80 19, 31 0, o0xc4e858cb0; 0 drivers
+o0xc4e858ce0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f325b80_20 .net/s v0xc4f325b80 20, 31 0, o0xc4e858ce0; 0 drivers
+o0xc4e858d10 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f325b80_21 .net/s v0xc4f325b80 21, 31 0, o0xc4e858d10; 0 drivers
+o0xc4e858d40 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f325b80_22 .net/s v0xc4f325b80 22, 31 0, o0xc4e858d40; 0 drivers
+o0xc4e858d70 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f325b80_23 .net/s v0xc4f325b80 23, 31 0, o0xc4e858d70; 0 drivers
+v0xc4f325b80_24 .net/s v0xc4f325b80 24, 31 0, L_0xc4f3a26c0; 1 drivers
+o0xc4e858dd0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f325b80_25 .net/s v0xc4f325b80 25, 31 0, o0xc4e858dd0; 0 drivers
+o0xc4e858e00 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f325b80_26 .net/s v0xc4f325b80 26, 31 0, o0xc4e858e00; 0 drivers
+o0xc4e858e30 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f325b80_27 .net/s v0xc4f325b80 27, 31 0, o0xc4e858e30; 0 drivers
+o0xc4e858e60 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f325b80_28 .net/s v0xc4f325b80 28, 31 0, o0xc4e858e60; 0 drivers
+o0xc4e858e90 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f325b80_29 .net/s v0xc4f325b80 29, 31 0, o0xc4e858e90; 0 drivers
+o0xc4e858ec0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f325b80_30 .net/s v0xc4f325b80 30, 31 0, o0xc4e858ec0; 0 drivers
+o0xc4e858ef0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f325b80_31 .net/s v0xc4f325b80 31, 31 0, o0xc4e858ef0; 0 drivers
+v0xc4f325c20_0 .net/s "w_bus", 63 0, L_0xc4f39c960;  alias, 1 drivers
+v0xc4f325cc0_0 .net/s "x_bus", 63 0, L_0xc4f39c8c0;  alias, 1 drivers
+L_0xc4f39caa0 .part L_0xc4f39c8c0, 0, 8;
+L_0xc4f39cb40 .part L_0xc4f39c960, 0, 8;
+L_0xc4f39cc80 .part L_0xc4f39c8c0, 8, 8;
+L_0xc4f39cd20 .part L_0xc4f39c960, 8, 8;
+L_0xc4f39ce60 .part L_0xc4f39c8c0, 16, 8;
+L_0xc4f39cf00 .part L_0xc4f39c960, 16, 8;
+L_0xc4f39d040 .part L_0xc4f39c8c0, 24, 8;
+L_0xc4f39d0e0 .part L_0xc4f39c960, 24, 8;
+L_0xc4f39d220 .part L_0xc4f39c8c0, 32, 8;
+L_0xc4f39d2c0 .part L_0xc4f39c960, 32, 8;
+L_0xc4f39d400 .part L_0xc4f39c8c0, 40, 8;
+L_0xc4f39d4a0 .part L_0xc4f39c960, 40, 8;
+L_0xc4f39d5e0 .part L_0xc4f39c8c0, 48, 8;
+L_0xc4f39d680 .part L_0xc4f39c960, 48, 8;
+L_0xc4f39d7c0 .part L_0xc4f39c8c0, 56, 8;
+L_0xc4f39d860 .part L_0xc4f39c960, 56, 8;
+L_0xc4f3a2760 .arith/sum 32, v0xc4f326620_0, L_0xc4f3a26c0;
+S_0xc4f31ea00 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2df6c0 .param/l "i" 1 5 20, +C4<00>;
+S_0xc4f31eb80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f31ea00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2af0c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2af100 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2af140 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f322760_0 .net/s *"_ivl_0", 15 0, L_0xc4f3a0f00;  1 drivers
+v0xc4f322800_0 .net/s *"_ivl_2", 15 0, L_0xc4f3a0fa0;  1 drivers
+v0xc4f3228a0_0 .net *"_ivl_7", 0 0, L_0xc4f39ca00;  1 drivers
+v0xc4f322940_0 .net *"_ivl_9", 15 0, L_0xc4ef50640;  1 drivers
+L_0xc4e87a1d0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3229e0_0 .net/s "acc_in", 31 0, L_0xc4e87a1d0;  1 drivers
+v0xc4f322a80_0 .net/s "acc_out", 31 0, L_0xc4f3a10e0;  alias, 1 drivers
+v0xc4f322b20_0 .net/s "product", 15 0, L_0xc4ef505a0;  1 drivers
+v0xc4f322bc0_0 .net/s "product_ext", 31 0, L_0xc4f3a1040;  1 drivers
+v0xc4f322c60_0 .net/s "w", 7 0, L_0xc4f39cb40;  1 drivers
+v0xc4f322d00_0 .net/s "x", 7 0, L_0xc4f39caa0;  1 drivers
+L_0xc4f3a0f00 .extend/s 16, L_0xc4f39caa0;
+L_0xc4f3a0fa0 .extend/s 16, L_0xc4f39cb40;
+L_0xc4ef505a0 .arith/mult 16, L_0xc4f3a0f00, L_0xc4f3a0fa0;
+L_0xc4f39ca00 .part L_0xc4ef505a0, 15, 1;
+L_0xc4ef50640 .repeat 16, 16, L_0xc4f39ca00;
+L_0xc4f3a1040 .concat [ 16 16 0 0], L_0xc4ef505a0, L_0xc4ef50640;
+L_0xc4f3a10e0 .arith/sum 32, L_0xc4e87a1d0, L_0xc4f3a1040;
+S_0xc4f31ed00 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2df700 .param/l "i" 1 5 20, +C4<01>;
+S_0xc4f31ee80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f31ed00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2af180 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2af1c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2af200 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f322da0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3a1180;  1 drivers
+v0xc4f322e40_0 .net/s *"_ivl_2", 15 0, L_0xc4f3a1220;  1 drivers
+v0xc4f322ee0_0 .net *"_ivl_7", 0 0, L_0xc4f39cbe0;  1 drivers
+v0xc4f322f80_0 .net *"_ivl_9", 15 0, L_0xc4ef50780;  1 drivers
+L_0xc4e87a218 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f323020_0 .net/s "acc_in", 31 0, L_0xc4e87a218;  1 drivers
+v0xc4f3230c0_0 .net/s "acc_out", 31 0, L_0xc4f3a1360;  alias, 1 drivers
+v0xc4f323160_0 .net/s "product", 15 0, L_0xc4ef506e0;  1 drivers
+v0xc4f323200_0 .net/s "product_ext", 31 0, L_0xc4f3a12c0;  1 drivers
+v0xc4f3232a0_0 .net/s "w", 7 0, L_0xc4f39cd20;  1 drivers
+v0xc4f323340_0 .net/s "x", 7 0, L_0xc4f39cc80;  1 drivers
+L_0xc4f3a1180 .extend/s 16, L_0xc4f39cc80;
+L_0xc4f3a1220 .extend/s 16, L_0xc4f39cd20;
+L_0xc4ef506e0 .arith/mult 16, L_0xc4f3a1180, L_0xc4f3a1220;
+L_0xc4f39cbe0 .part L_0xc4ef506e0, 15, 1;
+L_0xc4ef50780 .repeat 16, 16, L_0xc4f39cbe0;
+L_0xc4f3a12c0 .concat [ 16 16 0 0], L_0xc4ef506e0, L_0xc4ef50780;
+L_0xc4f3a1360 .arith/sum 32, L_0xc4e87a218, L_0xc4f3a12c0;
+S_0xc4f31f000 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2df740 .param/l "i" 1 5 20, +C4<010>;
+S_0xc4f31f180 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f31f000;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2af240 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2af280 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2af2c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f3233e0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3a1400;  1 drivers
+v0xc4f323480_0 .net/s *"_ivl_2", 15 0, L_0xc4f3a14a0;  1 drivers
+v0xc4f323520_0 .net *"_ivl_7", 0 0, L_0xc4f39cdc0;  1 drivers
+v0xc4f3235c0_0 .net *"_ivl_9", 15 0, L_0xc4ef508c0;  1 drivers
+L_0xc4e87a260 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f323660_0 .net/s "acc_in", 31 0, L_0xc4e87a260;  1 drivers
+v0xc4f323700_0 .net/s "acc_out", 31 0, L_0xc4f3a15e0;  alias, 1 drivers
+v0xc4f3237a0_0 .net/s "product", 15 0, L_0xc4ef50820;  1 drivers
+v0xc4f323840_0 .net/s "product_ext", 31 0, L_0xc4f3a1540;  1 drivers
+v0xc4f3238e0_0 .net/s "w", 7 0, L_0xc4f39cf00;  1 drivers
+v0xc4f323980_0 .net/s "x", 7 0, L_0xc4f39ce60;  1 drivers
+L_0xc4f3a1400 .extend/s 16, L_0xc4f39ce60;
+L_0xc4f3a14a0 .extend/s 16, L_0xc4f39cf00;
+L_0xc4ef50820 .arith/mult 16, L_0xc4f3a1400, L_0xc4f3a14a0;
+L_0xc4f39cdc0 .part L_0xc4ef50820, 15, 1;
+L_0xc4ef508c0 .repeat 16, 16, L_0xc4f39cdc0;
+L_0xc4f3a1540 .concat [ 16 16 0 0], L_0xc4ef50820, L_0xc4ef508c0;
+L_0xc4f3a15e0 .arith/sum 32, L_0xc4e87a260, L_0xc4f3a1540;
+S_0xc4f31f300 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2df780 .param/l "i" 1 5 20, +C4<011>;
+S_0xc4f31f480 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f31f300;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2af300 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2af340 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2af380 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f323a20_0 .net/s *"_ivl_0", 15 0, L_0xc4f3a1680;  1 drivers
+v0xc4f323ac0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3a1720;  1 drivers
+v0xc4f323b60_0 .net *"_ivl_7", 0 0, L_0xc4f39cfa0;  1 drivers
+v0xc4f323c00_0 .net *"_ivl_9", 15 0, L_0xc4ef50a00;  1 drivers
+L_0xc4e87a2a8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f323ca0_0 .net/s "acc_in", 31 0, L_0xc4e87a2a8;  1 drivers
+v0xc4f323d40_0 .net/s "acc_out", 31 0, L_0xc4f3a1860;  alias, 1 drivers
+v0xc4f323de0_0 .net/s "product", 15 0, L_0xc4ef50960;  1 drivers
+v0xc4f323e80_0 .net/s "product_ext", 31 0, L_0xc4f3a17c0;  1 drivers
+v0xc4f323f20_0 .net/s "w", 7 0, L_0xc4f39d0e0;  1 drivers
+v0xc4f324000_0 .net/s "x", 7 0, L_0xc4f39d040;  1 drivers
+L_0xc4f3a1680 .extend/s 16, L_0xc4f39d040;
+L_0xc4f3a1720 .extend/s 16, L_0xc4f39d0e0;
+L_0xc4ef50960 .arith/mult 16, L_0xc4f3a1680, L_0xc4f3a1720;
+L_0xc4f39cfa0 .part L_0xc4ef50960, 15, 1;
+L_0xc4ef50a00 .repeat 16, 16, L_0xc4f39cfa0;
+L_0xc4f3a17c0 .concat [ 16 16 0 0], L_0xc4ef50960, L_0xc4ef50a00;
+L_0xc4f3a1860 .arith/sum 32, L_0xc4e87a2a8, L_0xc4f3a17c0;
+S_0xc4f31f600 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2df800 .param/l "i" 1 5 20, +C4<0100>;
+S_0xc4f31f780 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f31f600;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2af3c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2af400 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2af440 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f3240a0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3a1900;  1 drivers
+v0xc4f324140_0 .net/s *"_ivl_2", 15 0, L_0xc4f3a19a0;  1 drivers
+v0xc4f3241e0_0 .net *"_ivl_7", 0 0, L_0xc4f39d180;  1 drivers
+v0xc4f324280_0 .net *"_ivl_9", 15 0, L_0xc4ef50b40;  1 drivers
+L_0xc4e87a2f0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f324320_0 .net/s "acc_in", 31 0, L_0xc4e87a2f0;  1 drivers
+v0xc4f3243c0_0 .net/s "acc_out", 31 0, L_0xc4f3a1ae0;  alias, 1 drivers
+v0xc4f324460_0 .net/s "product", 15 0, L_0xc4ef50aa0;  1 drivers
+v0xc4f324500_0 .net/s "product_ext", 31 0, L_0xc4f3a1a40;  1 drivers
+v0xc4f3245a0_0 .net/s "w", 7 0, L_0xc4f39d2c0;  1 drivers
+v0xc4f324640_0 .net/s "x", 7 0, L_0xc4f39d220;  1 drivers
+L_0xc4f3a1900 .extend/s 16, L_0xc4f39d220;
+L_0xc4f3a19a0 .extend/s 16, L_0xc4f39d2c0;
+L_0xc4ef50aa0 .arith/mult 16, L_0xc4f3a1900, L_0xc4f3a19a0;
+L_0xc4f39d180 .part L_0xc4ef50aa0, 15, 1;
+L_0xc4ef50b40 .repeat 16, 16, L_0xc4f39d180;
+L_0xc4f3a1a40 .concat [ 16 16 0 0], L_0xc4ef50aa0, L_0xc4ef50b40;
+L_0xc4f3a1ae0 .arith/sum 32, L_0xc4e87a2f0, L_0xc4f3a1a40;
+S_0xc4f31f900 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2df840 .param/l "i" 1 5 20, +C4<0101>;
+S_0xc4f31fa80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f31f900;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2af480 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2af4c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2af500 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f3246e0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3a1b80;  1 drivers
+v0xc4f324780_0 .net/s *"_ivl_2", 15 0, L_0xc4f3a1c20;  1 drivers
+v0xc4f324820_0 .net *"_ivl_7", 0 0, L_0xc4f39d360;  1 drivers
+v0xc4f3248c0_0 .net *"_ivl_9", 15 0, L_0xc4ef50c80;  1 drivers
+L_0xc4e87a338 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f324960_0 .net/s "acc_in", 31 0, L_0xc4e87a338;  1 drivers
+v0xc4f324a00_0 .net/s "acc_out", 31 0, L_0xc4f3a1d60;  alias, 1 drivers
+v0xc4f324aa0_0 .net/s "product", 15 0, L_0xc4ef50be0;  1 drivers
+v0xc4f324b40_0 .net/s "product_ext", 31 0, L_0xc4f3a1cc0;  1 drivers
+v0xc4f324be0_0 .net/s "w", 7 0, L_0xc4f39d4a0;  1 drivers
+v0xc4f324c80_0 .net/s "x", 7 0, L_0xc4f39d400;  1 drivers
+L_0xc4f3a1b80 .extend/s 16, L_0xc4f39d400;
+L_0xc4f3a1c20 .extend/s 16, L_0xc4f39d4a0;
+L_0xc4ef50be0 .arith/mult 16, L_0xc4f3a1b80, L_0xc4f3a1c20;
+L_0xc4f39d360 .part L_0xc4ef50be0, 15, 1;
+L_0xc4ef50c80 .repeat 16, 16, L_0xc4f39d360;
+L_0xc4f3a1cc0 .concat [ 16 16 0 0], L_0xc4ef50be0, L_0xc4ef50c80;
+L_0xc4f3a1d60 .arith/sum 32, L_0xc4e87a338, L_0xc4f3a1cc0;
+S_0xc4f31fc00 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2df880 .param/l "i" 1 5 20, +C4<0110>;
+S_0xc4f31fd80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f31fc00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2af540 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2af580 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2af5c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f324d20_0 .net/s *"_ivl_0", 15 0, L_0xc4f3a1e00;  1 drivers
+v0xc4f324dc0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3a1ea0;  1 drivers
+v0xc4f324e60_0 .net *"_ivl_7", 0 0, L_0xc4f39d540;  1 drivers
+v0xc4f324f00_0 .net *"_ivl_9", 15 0, L_0xc4ef50dc0;  1 drivers
+L_0xc4e87a380 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f324fa0_0 .net/s "acc_in", 31 0, L_0xc4e87a380;  1 drivers
+v0xc4f325040_0 .net/s "acc_out", 31 0, L_0xc4f3a1fe0;  alias, 1 drivers
+v0xc4f3250e0_0 .net/s "product", 15 0, L_0xc4ef50d20;  1 drivers
+v0xc4f325180_0 .net/s "product_ext", 31 0, L_0xc4f3a1f40;  1 drivers
+v0xc4f325220_0 .net/s "w", 7 0, L_0xc4f39d680;  1 drivers
+v0xc4f3252c0_0 .net/s "x", 7 0, L_0xc4f39d5e0;  1 drivers
+L_0xc4f3a1e00 .extend/s 16, L_0xc4f39d5e0;
+L_0xc4f3a1ea0 .extend/s 16, L_0xc4f39d680;
+L_0xc4ef50d20 .arith/mult 16, L_0xc4f3a1e00, L_0xc4f3a1ea0;
+L_0xc4f39d540 .part L_0xc4ef50d20, 15, 1;
+L_0xc4ef50dc0 .repeat 16, 16, L_0xc4f39d540;
+L_0xc4f3a1f40 .concat [ 16 16 0 0], L_0xc4ef50d20, L_0xc4ef50dc0;
+L_0xc4f3a1fe0 .arith/sum 32, L_0xc4e87a380, L_0xc4f3a1f40;
+S_0xc4f328000 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2df8c0 .param/l "i" 1 5 20, +C4<0111>;
+S_0xc4f328180 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f328000;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2af600 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2af640 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2af680 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f325360_0 .net/s *"_ivl_0", 15 0, L_0xc4f3a2080;  1 drivers
+v0xc4f325400_0 .net/s *"_ivl_2", 15 0, L_0xc4f3a2120;  1 drivers
+v0xc4f3254a0_0 .net *"_ivl_7", 0 0, L_0xc4f39d720;  1 drivers
+v0xc4f325540_0 .net *"_ivl_9", 15 0, L_0xc4ef50f00;  1 drivers
+L_0xc4e87a3c8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3255e0_0 .net/s "acc_in", 31 0, L_0xc4e87a3c8;  1 drivers
+v0xc4f325680_0 .net/s "acc_out", 31 0, L_0xc4f3a2260;  alias, 1 drivers
+v0xc4f325720_0 .net/s "product", 15 0, L_0xc4ef50e60;  1 drivers
+v0xc4f3257c0_0 .net/s "product_ext", 31 0, L_0xc4f3a21c0;  1 drivers
+v0xc4f325860_0 .net/s "w", 7 0, L_0xc4f39d860;  1 drivers
+v0xc4f325900_0 .net/s "x", 7 0, L_0xc4f39d7c0;  1 drivers
+L_0xc4f3a2080 .extend/s 16, L_0xc4f39d7c0;
+L_0xc4f3a2120 .extend/s 16, L_0xc4f39d860;
+L_0xc4ef50e60 .arith/mult 16, L_0xc4f3a2080, L_0xc4f3a2120;
+L_0xc4f39d720 .part L_0xc4ef50e60, 15, 1;
+L_0xc4ef50f00 .repeat 16, 16, L_0xc4f39d720;
+L_0xc4f3a21c0 .concat [ 16 16 0 0], L_0xc4ef50e60, L_0xc4ef50f00;
+L_0xc4f3a2260 .arith/sum 32, L_0xc4e87a3c8, L_0xc4f3a21c0;
+S_0xc4f328300 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2df7c0 .param/l "i" 1 5 80, +C4<00>;
+L_0xc4f067cd0 .functor BUFZ 32, L_0xc4f3a10e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f328480 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2df900 .param/l "i" 1 5 80, +C4<01>;
+L_0xc4f067d40 .functor BUFZ 32, L_0xc4f3a1360, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f328600 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2df940 .param/l "i" 1 5 80, +C4<010>;
+L_0xc4f067db0 .functor BUFZ 32, L_0xc4f3a15e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f328780 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2df980 .param/l "i" 1 5 80, +C4<011>;
+L_0xc4f067e20 .functor BUFZ 32, L_0xc4f3a1860, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f328900 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2df9c0 .param/l "i" 1 5 80, +C4<0100>;
+L_0xc4f067e90 .functor BUFZ 32, L_0xc4f3a1ae0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f328a80 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2dfa00 .param/l "i" 1 5 80, +C4<0101>;
+L_0xc4f067f00 .functor BUFZ 32, L_0xc4f3a1d60, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f328c00 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2dfa40 .param/l "i" 1 5 80, +C4<0110>;
+L_0xc4f067f70 .functor BUFZ 32, L_0xc4f3a1fe0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f328d80 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2dfa80 .param/l "i" 1 5 80, +C4<0111>;
+L_0xc4f3a4000 .functor BUFZ 32, L_0xc4f3a2260, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f328f00 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2dfac0 .param/l "level" 1 5 92, +C4<00>;
+S_0xc4f329080 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f328f00;
+ .timescale 0 0;
+P_0xc4f2dfb00 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3a2300 .arith/sum 32, L_0xc4f067cd0, L_0xc4f067d40;
+S_0xc4f329200 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f328f00;
+ .timescale 0 0;
+P_0xc4f2dfb40 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3a23a0 .arith/sum 32, L_0xc4f067db0, L_0xc4f067e20;
+S_0xc4f329380 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xc4f328f00;
+ .timescale 0 0;
+P_0xc4f2dfb80 .param/l "node" 1 5 94, +C4<010>;
+L_0xc4f3a2440 .arith/sum 32, L_0xc4f067e90, L_0xc4f067f00;
+S_0xc4f329500 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xc4f328f00;
+ .timescale 0 0;
+P_0xc4f2dfbc0 .param/l "node" 1 5 94, +C4<011>;
+L_0xc4f3a24e0 .arith/sum 32, L_0xc4f067f70, L_0xc4f3a4000;
+S_0xc4f329680 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2dfc00 .param/l "level" 1 5 92, +C4<01>;
+S_0xc4f329800 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f329680;
+ .timescale 0 0;
+P_0xc4f2dfc40 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3a2580 .arith/sum 32, L_0xc4f3a2300, L_0xc4f3a23a0;
+S_0xc4f329980 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f329680;
+ .timescale 0 0;
+P_0xc4f2dfc80 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3a2620 .arith/sum 32, L_0xc4f3a2440, L_0xc4f3a24e0;
+S_0xc4f329b00 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xc4f31e880;
+ .timescale 0 0;
+P_0xc4f2dfcc0 .param/l "level" 1 5 92, +C4<010>;
+S_0xc4f329c80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f329b00;
+ .timescale 0 0;
+P_0xc4f2dfd00 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3a26c0 .arith/sum 32, L_0xc4f3a2580, L_0xc4f3a2620;
+S_0x102d167c0 .scope module, "psram_controller" "psram_controller" 11 1;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "mem_req";
+    .port_info 3 /INPUT 1 "mem_wr";
+    .port_info 4 /INPUT 22 "mem_addr";
+    .port_info 5 /INPUT 16 "mem_wdata";
+    .port_info 6 /INPUT 1 "mem_lb_n";
+    .port_info 7 /INPUT 1 "mem_ub_n";
+    .port_info 8 /OUTPUT 16 "mem_rdata";
+    .port_info 9 /OUTPUT 1 "mem_ready";
+    .port_info 10 /OUTPUT 22 "psram_a";
+    .port_info 11 /INOUT 16 "psram_dq";
+    .port_info 12 /OUTPUT 1 "psram_ce_n";
+    .port_info 13 /OUTPUT 1 "psram_oe_n";
+    .port_info 14 /OUTPUT 1 "psram_we_n";
+    .port_info 15 /OUTPUT 1 "psram_lb_n";
+    .port_info 16 /OUTPUT 1 "psram_ub_n";
+    .port_info 17 /OUTPUT 1 "psram_zz_n";
+P_0x102d29510 .param/l "ACCESS_CYCLES" 1 11 43, +C4<00000000000000000000000000000110>;
+P_0x102d29550 .param/l "ADDR_WIDTH" 0 11 2, +C4<00000000000000000000000000010110>;
+P_0x102d29590 .param/l "CLK_FREQ_MHZ" 0 11 4, +C4<00000000000000000000000001010000>;
+P_0x102d295d0 .param/l "COUNTER_WIDTH" 1 11 49, +C4<00000000000000000000000000001110>;
+P_0x102d29610 .param/l "DATA_WIDTH" 0 11 3, +C4<00000000000000000000000000010000>;
+P_0x102d29650 .param/l "INIT_CYCLES" 1 11 46, +C4<00000000000000000010111011100000>;
+P_0x102d29690 .param/l "STATE_IDLE" 1 11 58, C4<001>;
+P_0x102d296d0 .param/l "STATE_INIT" 1 11 57, C4<000>;
+P_0x102d29710 .param/l "STATE_READ" 1 11 59, C4<010>;
+P_0x102d29750 .param/l "STATE_WRITE" 1 11 60, C4<011>;
+P_0x102d29790 .param/l "STATE_WRITE_WAIT" 1 11 61, C4<100>;
+o0xc4e85a8d0 .functor BUFZ 16, c4<zzzzzzzzzzzzzzzz>; HiZ drive
+; Elide local net with no drivers, v0xc4f32cbe0_0 name=_ivl_0
+v0xc4f32cc80_0 .var "address_reg", 21 0;
+o0xc4e85a930 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f32cd20_0 .net "clk", 0 0, o0xc4e85a930;  0 drivers
+v0xc4f32cdc0_0 .var "counter", 13 0;
+v0xc4f32ce60_0 .var "dq_oe", 0 0;
+v0xc4f32cf00_0 .var "dq_out", 15 0;
+v0xc4f32cfa0_0 .var "lb_reg", 0 0;
+o0xc4e85aa20 .functor BUFZ 22, c4<zzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f32d040_0 .net "mem_addr", 21 0, o0xc4e85aa20;  0 drivers
+o0xc4e85aa50 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f32d0e0_0 .net "mem_lb_n", 0 0, o0xc4e85aa50;  0 drivers
+v0xc4f32d180_0 .var "mem_rdata", 15 0;
+v0xc4f32d220_0 .var "mem_ready", 0 0;
+o0xc4e85aae0 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f32d2c0_0 .net "mem_req", 0 0, o0xc4e85aae0;  0 drivers
+o0xc4e85ab10 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f32d360_0 .net "mem_ub_n", 0 0, o0xc4e85ab10;  0 drivers
+o0xc4e85ab40 .functor BUFZ 16, c4<zzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f32d400_0 .net "mem_wdata", 15 0, o0xc4e85ab40;  0 drivers
+o0xc4e85ab70 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f32d4a0_0 .net "mem_wr", 0 0, o0xc4e85ab70;  0 drivers
+v0xc4f32d540_0 .var "psram_a", 21 0;
+v0xc4f32d5e0_0 .var "psram_ce_n", 0 0;
+v0xc4f32d680_0 .net "psram_dq", 15 0, L_0xc4f39d9a0;  1 drivers
+v0xc4f32d720_0 .var "psram_lb_n", 0 0;
+v0xc4f32d7c0_0 .var "psram_oe_n", 0 0;
+v0xc4f32d860_0 .var "psram_ub_n", 0 0;
+v0xc4f32d900_0 .var "psram_we_n", 0 0;
+v0xc4f32d9a0_0 .var "psram_zz_n", 0 0;
+o0xc4e85ad20 .functor BUFZ 1, c4<z>; HiZ drive
+v0xc4f32da40_0 .net "rst", 0 0, o0xc4e85ad20;  0 drivers
+v0xc4f32dae0_0 .var "state", 2 0;
+v0xc4f32db80_0 .var "ub_reg", 0 0;
+v0xc4f32dc20_0 .var "wdata_reg", 15 0;
+v0xc4f32dcc0_0 .var "wr_reg", 0 0;
+E_0xc4ef18b40 .event posedge, v0xc4f32cd20_0;
+L_0xc4f39d9a0 .functor MUXZ 16, o0xc4e85a8d0, v0xc4f32cf00_0, v0xc4f32ce60_0, C4<>;
+S_0x102d15030 .scope module, "tb" "tb" 12 22;
+ .timescale -9 -12;
+P_0xc4f2bc000 .param/l "A_ACC_WIDTH" 1 12 43, +C4<00000000000000000000000000100000>;
+P_0xc4f2bc040 .param/l "A_DATA_WIDTH" 1 12 40, +C4<00000000000000000000000000001000>;
+P_0xc4f2bc080 .param/l "A_N_INPUTS" 1 12 41, +C4<00000000000000000000000000100000>;
+P_0xc4f2bc0c0 .param/l "A_PARALLEL" 1 12 42, +C4<00000000000000000000000000001000>;
+P_0xc4f2bc100 .param/l "B_ACC_WIDTH" 1 12 71, +C4<00000000000000000000000000100000>;
+P_0xc4f2bc140 .param/l "B_DATA_WIDTH" 1 12 68, +C4<00000000000000000000000000001000>;
+P_0xc4f2bc180 .param/l "B_N_INPUTS" 1 12 69, +C4<00000000000000000000000000011110>;
+P_0xc4f2bc1c0 .param/l "B_PARALLEL" 1 12 70, +C4<00000000000000000000000000001000>;
+P_0xc4f2bc200 .param/l "C_ACC_WIDTH" 1 12 99, +C4<00000000000000000000000000100000>;
+P_0xc4f2bc240 .param/l "C_DATA_WIDTH" 1 12 96, +C4<00000000000000000000000000001000>;
+P_0xc4f2bc280 .param/l "C_N_INPUTS" 1 12 97, +C4<00000000000000000000000000010100>;
+P_0xc4f2bc2c0 .param/l "C_PARALLEL" 1 12 98, +C4<00000000000000000000000000010000>;
+P_0xc4f2bc300 .param/l "D_ACC_WIDTH" 1 12 127, +C4<00000000000000000000000000100000>;
+P_0xc4f2bc340 .param/l "D_DATA_WIDTH" 1 12 124, +C4<00000000000000000000000000001000>;
+P_0xc4f2bc380 .param/l "D_N_INPUTS" 1 12 125, +C4<00000000000000000000000001000000>;
+P_0xc4f2bc3c0 .param/l "D_PARALLEL" 1 12 126, +C4<00000000000000000000000000100000>;
+P_0xc4f2bc400 .param/l "E_ACC_WIDTH" 1 12 157, +C4<00000000000000000000000000100000>;
+P_0xc4f2bc440 .param/l "E_DATA_WIDTH" 1 12 154, +C4<00000000000000000000000000001000>;
+P_0xc4f2bc480 .param/l "E_N_INPUTS" 1 12 155, +C4<00000000000000000000000000000100>;
+P_0xc4f2bc4c0 .param/l "E_PARALLEL" 1 12 156, +C4<00000000000000000000000000001000>;
+v0xc4f385220_0 .var/s "bias_a", 7 0;
+v0xc4f3852c0_0 .var/s "bias_b", 7 0;
+v0xc4f385360_0 .var/s "bias_c", 7 0;
+v0xc4f385400_0 .var/s "bias_d", 7 0;
+v0xc4f3854a0_0 .var/s "bias_e", 7 0;
+v0xc4f385540_0 .net "busy_a", 0 0, v0xc4f331ea0_0;  1 drivers
+v0xc4f3855e0_0 .net "busy_b", 0 0, v0xc4f346760_0;  1 drivers
+v0xc4f385680_0 .net "busy_c", 0 0, v0xc4f352260_0;  1 drivers
+v0xc4f385720_0 .net "busy_d", 0 0, v0xc4f3801e0_0;  1 drivers
+v0xc4f3857c0_0 .net "busy_e", 0 0, v0xc4f384aa0_0;  1 drivers
+v0xc4f385860_0 .var "clk", 0 0;
+v0xc4f385900_0 .var/i "count", 31 0;
+v0xc4f3859a0_0 .net "done_a", 0 0, v0xc4f331fe0_0;  1 drivers
+v0xc4f385a40_0 .net "done_b", 0 0, v0xc4f3468a0_0;  1 drivers
+v0xc4f385ae0_0 .net "done_c", 0 0, v0xc4f3523a0_0;  1 drivers
+v0xc4f385b80_0 .net "done_d", 0 0, v0xc4f380320_0;  1 drivers
+v0xc4f385c20_0 .net "done_e", 0 0, v0xc4f384be0_0;  1 drivers
+v0xc4f385cc0_0 .var/i "errors", 31 0;
+v0xc4f385d60_0 .var/i "findings", 31 0;
+v0xc4f385e00_0 .var/i "max_cycles", 31 0;
+v0xc4f385ea0_0 .var "rst", 0 0;
+v0xc4f385f40_0 .var "start_a", 0 0;
+v0xc4f385fe0_0 .var "start_b", 0 0;
+v0xc4f386080_0 .var "start_c", 0 0;
+v0xc4f386120_0 .var "start_d", 0 0;
+v0xc4f3861c0_0 .var "start_e", 0 0;
+v0xc4f386260_0 .var "timed_out", 0 0;
+v0xc4f386300_0 .var/s "w_bus_a", 255 0;
+v0xc4f3863a0_0 .var/s "w_bus_b", 239 0;
+v0xc4f386440_0 .var/s "w_bus_c", 159 0;
+v0xc4f3864e0_0 .var/s "w_bus_d", 511 0;
+v0xc4f386580_0 .var/s "w_bus_e", 31 0;
+v0xc4f386620_0 .var/s "x_bus_a", 255 0;
+v0xc4f3866c0_0 .var/s "x_bus_b", 239 0;
+v0xc4f386760_0 .var/s "x_bus_c", 159 0;
+v0xc4f386800_0 .var/s "x_bus_d", 511 0;
+v0xc4f3868a0_0 .var/s "x_bus_e", 31 0;
+v0xc4f386940_0 .net/s "y_a", 7 0, v0xc4f332580_0;  1 drivers
+v0xc4f3869e0_0 .net/s "y_b", 7 0, v0xc4f346e40_0;  1 drivers
+v0xc4f386a80_0 .net/s "y_c", 7 0, v0xc4f352940_0;  1 drivers
+v0xc4f386b20_0 .net/s "y_d", 7 0, v0xc4f3808c0_0;  1 drivers
+v0xc4f386bc0_0 .net/s "y_e", 7 0, v0xc4f385180_0;  1 drivers
+S_0xc4f329e00 .scope module, "u_a" "neuron_parallel" 12 57, 4 1 0, S_0x102d15030;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "start";
+    .port_info 3 /INPUT 256 "x_bus";
+    .port_info 4 /INPUT 256 "w_bus";
+    .port_info 5 /INPUT 8 "bias";
+    .port_info 6 /OUTPUT 8 "y";
+    .port_info 7 /OUTPUT 1 "busy";
+    .port_info 8 /OUTPUT 1 "done";
+P_0x102d2dd90 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000100000>;
+P_0x102d2ddd0 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000001000>;
+P_0x102d2de10 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000000100>;
+P_0x102d2de50 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000010>;
+P_0x102d2de90 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000000100000>;
+P_0x102d2ded0 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>;
+v0xc4f331360_0 .net *"_ivl_0", 31 0, L_0xc4f3a2940;  1 drivers
+v0xc4f331400_0 .net *"_ivl_11", 31 0, L_0xc4ef51180;  1 drivers
+v0xc4f3314a0_0 .net *"_ivl_14", 31 0, L_0xc4f3a29e0;  1 drivers
+L_0xc4e87a4e8 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f331540_0 .net *"_ivl_17", 29 0, L_0xc4e87a4e8;  1 drivers
+L_0xc4e87a530 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3315e0_0 .net/2u *"_ivl_18", 31 0, L_0xc4e87a530;  1 drivers
+v0xc4f331680_0 .net *"_ivl_21", 31 0, L_0xc4ef51220;  1 drivers
+L_0xc4e87a578 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f331720_0 .net/2u *"_ivl_22", 31 0, L_0xc4e87a578;  1 drivers
+v0xc4f3317c0_0 .net *"_ivl_25", 31 0, L_0xc4ef512c0;  1 drivers
+v0xc4f331860_0 .net *"_ivl_29", 0 0, L_0xc4f39ea80;  1 drivers
+L_0xc4e87a410 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f331900_0 .net *"_ivl_3", 29 0, L_0xc4e87a410;  1 drivers
+v0xc4f3319a0_0 .net *"_ivl_31", 23 0, L_0xc4ef51e00;  1 drivers
+L_0xc4e87a458 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f331a40_0 .net/2u *"_ivl_4", 31 0, L_0xc4e87a458;  1 drivers
+v0xc4f331ae0_0 .net *"_ivl_7", 31 0, L_0xc4ef510e0;  1 drivers
+L_0xc4e87a4a0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f331b80_0 .net/2u *"_ivl_8", 31 0, L_0xc4e87a4a0;  1 drivers
+v0xc4f331c20_0 .var/s "acc", 31 0;
+v0xc4f331cc0_0 .net/s "acc_next", 31 0, L_0xc4f3ac320;  1 drivers
+v0xc4f331d60_0 .net/s "bias", 7 0, v0xc4f385220_0;  1 drivers
+v0xc4f331e00_0 .net/s "bias_ext", 31 0, L_0xc4f3ac3c0;  1 drivers
+v0xc4f331ea0_0 .var "busy", 0 0;
+v0xc4f331f40_0 .net "clk", 0 0, v0xc4f385860_0;  1 drivers
+v0xc4f331fe0_0 .var "done", 0 0;
+v0xc4f332080_0 .net/s "final_acc", 31 0, L_0xc4f3ac460;  1 drivers
+v0xc4f332120_0 .var "group_index", 1 0;
+v0xc4f3321c0_0 .net "rst", 0 0, v0xc4f385ea0_0;  1 drivers
+v0xc4f332260_0 .net "start", 0 0, v0xc4f385f40_0;  1 drivers
+v0xc4f332300_0 .net/s "w_bus", 255 0, v0xc4f386300_0;  1 drivers
+v0xc4f3323a0_0 .net/s "w_group", 63 0, L_0xc4f39dae0;  1 drivers
+v0xc4f332440_0 .net/s "x_bus", 255 0, v0xc4f386620_0;  1 drivers
+v0xc4f3324e0_0 .net/s "x_group", 63 0, L_0xc4f39da40;  1 drivers
+v0xc4f332580_0 .var/s "y", 7 0;
+E_0xc4ef18b80 .event posedge, v0xc4f331f40_0;
+L_0xc4f3a2940 .concat [ 2 30 0 0], v0xc4f332120_0, L_0xc4e87a410;
+L_0xc4ef510e0 .arith/mult 32, L_0xc4f3a2940, L_0xc4e87a458;
+L_0xc4ef51180 .arith/mult 32, L_0xc4ef510e0, L_0xc4e87a4a0;
+L_0xc4f39da40 .part/v v0xc4f386620_0, L_0xc4ef51180, 64;
+L_0xc4f3a29e0 .concat [ 2 30 0 0], v0xc4f332120_0, L_0xc4e87a4e8;
+L_0xc4ef51220 .arith/mult 32, L_0xc4f3a29e0, L_0xc4e87a530;
+L_0xc4ef512c0 .arith/mult 32, L_0xc4ef51220, L_0xc4e87a578;
+L_0xc4f39dae0 .part/v v0xc4f386300_0, L_0xc4ef512c0, 64;
+L_0xc4f39ea80 .part v0xc4f385220_0, 7, 1;
+L_0xc4ef51e00 .repeat 24, 24, L_0xc4f39ea80;
+L_0xc4f3ac3c0 .concat [ 8 24 0 0], v0xc4f385220_0, L_0xc4ef51e00;
+L_0xc4f3ac460 .arith/sum 32, L_0xc4f3ac320, L_0xc4f3ac3c0;
+S_0xc4f329f80 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xc4f329e00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 64 "x_bus";
+    .port_info 1 /INPUT 64 "w_bus";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4ef0de00 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000100000>;
+P_0xc4ef0de40 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000001000>;
+P_0xc4ef0de80 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>;
+P_0xc4ef0dec0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>;
+v0xc4f330fa0_0 .net/s "acc_in", 31 0, v0xc4f331c20_0;  1 drivers
+v0xc4f331040_0 .net/s "acc_out", 31 0, L_0xc4f3ac320;  alias, 1 drivers
+v0xc4f3310e0 .array "products", 7 0;
+v0xc4f3310e0_0 .net/s v0xc4f3310e0 0, 31 0, L_0xc4f3a2c60; 1 drivers
+v0xc4f3310e0_1 .net/s v0xc4f3310e0 1, 31 0, L_0xc4f3a2ee0; 1 drivers
+v0xc4f3310e0_2 .net/s v0xc4f3310e0 2, 31 0, L_0xc4f3a3160; 1 drivers
+v0xc4f3310e0_3 .net/s v0xc4f3310e0 3, 31 0, L_0xc4f3a33e0; 1 drivers
+v0xc4f3310e0_4 .net/s v0xc4f3310e0 4, 31 0, L_0xc4f3a3660; 1 drivers
+v0xc4f3310e0_5 .net/s v0xc4f3310e0 5, 31 0, L_0xc4f3a38e0; 1 drivers
+v0xc4f3310e0_6 .net/s v0xc4f3310e0 6, 31 0, L_0xc4f3a3b60; 1 drivers
+v0xc4f3310e0_7 .net/s v0xc4f3310e0 7, 31 0, L_0xc4f3a3de0; 1 drivers
+v0xc4f331180 .array "tree", 31 0;
+v0xc4f331180_0 .net/s v0xc4f331180 0, 31 0, L_0xc4f3a8000; 1 drivers
+v0xc4f331180_1 .net/s v0xc4f331180 1, 31 0, L_0xc4f3a8070; 1 drivers
+v0xc4f331180_2 .net/s v0xc4f331180 2, 31 0, L_0xc4f3a80e0; 1 drivers
+v0xc4f331180_3 .net/s v0xc4f331180 3, 31 0, L_0xc4f3a8150; 1 drivers
+v0xc4f331180_4 .net/s v0xc4f331180 4, 31 0, L_0xc4f3a81c0; 1 drivers
+v0xc4f331180_5 .net/s v0xc4f331180 5, 31 0, L_0xc4f3a8230; 1 drivers
+v0xc4f331180_6 .net/s v0xc4f331180 6, 31 0, L_0xc4f3a82a0; 1 drivers
+v0xc4f331180_7 .net/s v0xc4f331180 7, 31 0, L_0xc4f3a8310; 1 drivers
+v0xc4f331180_8 .net/s v0xc4f331180 8, 31 0, L_0xc4f3a3e80; 1 drivers
+v0xc4f331180_9 .net/s v0xc4f331180 9, 31 0, L_0xc4f3a3f20; 1 drivers
+v0xc4f331180_10 .net/s v0xc4f331180 10, 31 0, L_0xc4f3ac000; 1 drivers
+v0xc4f331180_11 .net/s v0xc4f331180 11, 31 0, L_0xc4f3ac0a0; 1 drivers
+o0xc4e85c910 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f331180_12 .net/s v0xc4f331180 12, 31 0, o0xc4e85c910; 0 drivers
+o0xc4e85c940 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f331180_13 .net/s v0xc4f331180 13, 31 0, o0xc4e85c940; 0 drivers
+o0xc4e85c970 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f331180_14 .net/s v0xc4f331180 14, 31 0, o0xc4e85c970; 0 drivers
+o0xc4e85c9a0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f331180_15 .net/s v0xc4f331180 15, 31 0, o0xc4e85c9a0; 0 drivers
+v0xc4f331180_16 .net/s v0xc4f331180 16, 31 0, L_0xc4f3ac140; 1 drivers
+v0xc4f331180_17 .net/s v0xc4f331180 17, 31 0, L_0xc4f3ac1e0; 1 drivers
+o0xc4e85ca30 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f331180_18 .net/s v0xc4f331180 18, 31 0, o0xc4e85ca30; 0 drivers
+o0xc4e85ca60 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f331180_19 .net/s v0xc4f331180 19, 31 0, o0xc4e85ca60; 0 drivers
+o0xc4e85ca90 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f331180_20 .net/s v0xc4f331180 20, 31 0, o0xc4e85ca90; 0 drivers
+o0xc4e85cac0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f331180_21 .net/s v0xc4f331180 21, 31 0, o0xc4e85cac0; 0 drivers
+o0xc4e85caf0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f331180_22 .net/s v0xc4f331180 22, 31 0, o0xc4e85caf0; 0 drivers
+o0xc4e85cb20 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f331180_23 .net/s v0xc4f331180 23, 31 0, o0xc4e85cb20; 0 drivers
+v0xc4f331180_24 .net/s v0xc4f331180 24, 31 0, L_0xc4f3ac280; 1 drivers
+o0xc4e85cb80 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f331180_25 .net/s v0xc4f331180 25, 31 0, o0xc4e85cb80; 0 drivers
+o0xc4e85cbb0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f331180_26 .net/s v0xc4f331180 26, 31 0, o0xc4e85cbb0; 0 drivers
+o0xc4e85cbe0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f331180_27 .net/s v0xc4f331180 27, 31 0, o0xc4e85cbe0; 0 drivers
+o0xc4e85cc10 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f331180_28 .net/s v0xc4f331180 28, 31 0, o0xc4e85cc10; 0 drivers
+o0xc4e85cc40 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f331180_29 .net/s v0xc4f331180 29, 31 0, o0xc4e85cc40; 0 drivers
+o0xc4e85cc70 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f331180_30 .net/s v0xc4f331180 30, 31 0, o0xc4e85cc70; 0 drivers
+o0xc4e85cca0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f331180_31 .net/s v0xc4f331180 31, 31 0, o0xc4e85cca0; 0 drivers
+v0xc4f331220_0 .net/s "w_bus", 63 0, L_0xc4f39dae0;  alias, 1 drivers
+v0xc4f3312c0_0 .net/s "x_bus", 63 0, L_0xc4f39da40;  alias, 1 drivers
+L_0xc4f39dc20 .part L_0xc4f39da40, 0, 8;
+L_0xc4f39dcc0 .part L_0xc4f39dae0, 0, 8;
+L_0xc4f39de00 .part L_0xc4f39da40, 8, 8;
+L_0xc4f39dea0 .part L_0xc4f39dae0, 8, 8;
+L_0xc4f39dfe0 .part L_0xc4f39da40, 16, 8;
+L_0xc4f39e080 .part L_0xc4f39dae0, 16, 8;
+L_0xc4f39e1c0 .part L_0xc4f39da40, 24, 8;
+L_0xc4f39e260 .part L_0xc4f39dae0, 24, 8;
+L_0xc4f39e3a0 .part L_0xc4f39da40, 32, 8;
+L_0xc4f39e440 .part L_0xc4f39dae0, 32, 8;
+L_0xc4f39e580 .part L_0xc4f39da40, 40, 8;
+L_0xc4f39e620 .part L_0xc4f39dae0, 40, 8;
+L_0xc4f39e760 .part L_0xc4f39da40, 48, 8;
+L_0xc4f39e800 .part L_0xc4f39dae0, 48, 8;
+L_0xc4f39e940 .part L_0xc4f39da40, 56, 8;
+L_0xc4f39e9e0 .part L_0xc4f39dae0, 56, 8;
+L_0xc4f3ac320 .arith/sum 32, v0xc4f331c20_0, L_0xc4f3ac280;
+S_0xc4f32a100 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f2dfd80 .param/l "i" 1 5 20, +C4<00>;
+S_0xc4f32a280 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f32a100;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2af6c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2af700 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2af740 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f32dd60_0 .net/s *"_ivl_0", 15 0, L_0xc4f3a2a80;  1 drivers
+v0xc4f32de00_0 .net/s *"_ivl_2", 15 0, L_0xc4f3a2b20;  1 drivers
+v0xc4f32dea0_0 .net *"_ivl_7", 0 0, L_0xc4f39db80;  1 drivers
+v0xc4f32df40_0 .net *"_ivl_9", 15 0, L_0xc4ef51400;  1 drivers
+L_0xc4e87a5c0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f32dfe0_0 .net/s "acc_in", 31 0, L_0xc4e87a5c0;  1 drivers
+v0xc4f32e080_0 .net/s "acc_out", 31 0, L_0xc4f3a2c60;  alias, 1 drivers
+v0xc4f32e120_0 .net/s "product", 15 0, L_0xc4ef51360;  1 drivers
+v0xc4f32e1c0_0 .net/s "product_ext", 31 0, L_0xc4f3a2bc0;  1 drivers
+v0xc4f32e260_0 .net/s "w", 7 0, L_0xc4f39dcc0;  1 drivers
+v0xc4f32e300_0 .net/s "x", 7 0, L_0xc4f39dc20;  1 drivers
+L_0xc4f3a2a80 .extend/s 16, L_0xc4f39dc20;
+L_0xc4f3a2b20 .extend/s 16, L_0xc4f39dcc0;
+L_0xc4ef51360 .arith/mult 16, L_0xc4f3a2a80, L_0xc4f3a2b20;
+L_0xc4f39db80 .part L_0xc4ef51360, 15, 1;
+L_0xc4ef51400 .repeat 16, 16, L_0xc4f39db80;
+L_0xc4f3a2bc0 .concat [ 16 16 0 0], L_0xc4ef51360, L_0xc4ef51400;
+L_0xc4f3a2c60 .arith/sum 32, L_0xc4e87a5c0, L_0xc4f3a2bc0;
+S_0xc4f32a400 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f2dfdc0 .param/l "i" 1 5 20, +C4<01>;
+S_0xc4f32a580 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f32a400;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2af780 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2af7c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2af800 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f32e3a0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3a2d00;  1 drivers
+v0xc4f32e440_0 .net/s *"_ivl_2", 15 0, L_0xc4f3a2da0;  1 drivers
+v0xc4f32e4e0_0 .net *"_ivl_7", 0 0, L_0xc4f39dd60;  1 drivers
+v0xc4f32e580_0 .net *"_ivl_9", 15 0, L_0xc4ef51540;  1 drivers
+L_0xc4e87a608 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f32e620_0 .net/s "acc_in", 31 0, L_0xc4e87a608;  1 drivers
+v0xc4f32e6c0_0 .net/s "acc_out", 31 0, L_0xc4f3a2ee0;  alias, 1 drivers
+v0xc4f32e760_0 .net/s "product", 15 0, L_0xc4ef514a0;  1 drivers
+v0xc4f32e800_0 .net/s "product_ext", 31 0, L_0xc4f3a2e40;  1 drivers
+v0xc4f32e8a0_0 .net/s "w", 7 0, L_0xc4f39dea0;  1 drivers
+v0xc4f32e940_0 .net/s "x", 7 0, L_0xc4f39de00;  1 drivers
+L_0xc4f3a2d00 .extend/s 16, L_0xc4f39de00;
+L_0xc4f3a2da0 .extend/s 16, L_0xc4f39dea0;
+L_0xc4ef514a0 .arith/mult 16, L_0xc4f3a2d00, L_0xc4f3a2da0;
+L_0xc4f39dd60 .part L_0xc4ef514a0, 15, 1;
+L_0xc4ef51540 .repeat 16, 16, L_0xc4f39dd60;
+L_0xc4f3a2e40 .concat [ 16 16 0 0], L_0xc4ef514a0, L_0xc4ef51540;
+L_0xc4f3a2ee0 .arith/sum 32, L_0xc4e87a608, L_0xc4f3a2e40;
+S_0xc4f32a700 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f2dfe00 .param/l "i" 1 5 20, +C4<010>;
+S_0xc4f32a880 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f32a700;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2af840 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2af880 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2af8c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f32e9e0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3a2f80;  1 drivers
+v0xc4f32ea80_0 .net/s *"_ivl_2", 15 0, L_0xc4f3a3020;  1 drivers
+v0xc4f32eb20_0 .net *"_ivl_7", 0 0, L_0xc4f39df40;  1 drivers
+v0xc4f32ebc0_0 .net *"_ivl_9", 15 0, L_0xc4ef51680;  1 drivers
+L_0xc4e87a650 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f32ec60_0 .net/s "acc_in", 31 0, L_0xc4e87a650;  1 drivers
+v0xc4f32ed00_0 .net/s "acc_out", 31 0, L_0xc4f3a3160;  alias, 1 drivers
+v0xc4f32eda0_0 .net/s "product", 15 0, L_0xc4ef515e0;  1 drivers
+v0xc4f32ee40_0 .net/s "product_ext", 31 0, L_0xc4f3a30c0;  1 drivers
+v0xc4f32eee0_0 .net/s "w", 7 0, L_0xc4f39e080;  1 drivers
+v0xc4f32ef80_0 .net/s "x", 7 0, L_0xc4f39dfe0;  1 drivers
+L_0xc4f3a2f80 .extend/s 16, L_0xc4f39dfe0;
+L_0xc4f3a3020 .extend/s 16, L_0xc4f39e080;
+L_0xc4ef515e0 .arith/mult 16, L_0xc4f3a2f80, L_0xc4f3a3020;
+L_0xc4f39df40 .part L_0xc4ef515e0, 15, 1;
+L_0xc4ef51680 .repeat 16, 16, L_0xc4f39df40;
+L_0xc4f3a30c0 .concat [ 16 16 0 0], L_0xc4ef515e0, L_0xc4ef51680;
+L_0xc4f3a3160 .arith/sum 32, L_0xc4e87a650, L_0xc4f3a30c0;
+S_0xc4f32aa00 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f2dfe40 .param/l "i" 1 5 20, +C4<011>;
+S_0xc4f32ab80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f32aa00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2af900 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2af940 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2af980 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f32f020_0 .net/s *"_ivl_0", 15 0, L_0xc4f3a3200;  1 drivers
+v0xc4f32f0c0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3a32a0;  1 drivers
+v0xc4f32f160_0 .net *"_ivl_7", 0 0, L_0xc4f39e120;  1 drivers
+v0xc4f32f200_0 .net *"_ivl_9", 15 0, L_0xc4ef517c0;  1 drivers
+L_0xc4e87a698 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f32f2a0_0 .net/s "acc_in", 31 0, L_0xc4e87a698;  1 drivers
+v0xc4f32f340_0 .net/s "acc_out", 31 0, L_0xc4f3a33e0;  alias, 1 drivers
+v0xc4f32f3e0_0 .net/s "product", 15 0, L_0xc4ef51720;  1 drivers
+v0xc4f32f480_0 .net/s "product_ext", 31 0, L_0xc4f3a3340;  1 drivers
+v0xc4f32f520_0 .net/s "w", 7 0, L_0xc4f39e260;  1 drivers
+v0xc4f32f5c0_0 .net/s "x", 7 0, L_0xc4f39e1c0;  1 drivers
+L_0xc4f3a3200 .extend/s 16, L_0xc4f39e1c0;
+L_0xc4f3a32a0 .extend/s 16, L_0xc4f39e260;
+L_0xc4ef51720 .arith/mult 16, L_0xc4f3a3200, L_0xc4f3a32a0;
+L_0xc4f39e120 .part L_0xc4ef51720, 15, 1;
+L_0xc4ef517c0 .repeat 16, 16, L_0xc4f39e120;
+L_0xc4f3a3340 .concat [ 16 16 0 0], L_0xc4ef51720, L_0xc4ef517c0;
+L_0xc4f3a33e0 .arith/sum 32, L_0xc4e87a698, L_0xc4f3a3340;
+S_0xc4f32ad00 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f2dfec0 .param/l "i" 1 5 20, +C4<0100>;
+S_0xc4f32ae80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f32ad00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2af9c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2afa00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2afa40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f32f660_0 .net/s *"_ivl_0", 15 0, L_0xc4f3a3480;  1 drivers
+v0xc4f32f700_0 .net/s *"_ivl_2", 15 0, L_0xc4f3a3520;  1 drivers
+v0xc4f32f7a0_0 .net *"_ivl_7", 0 0, L_0xc4f39e300;  1 drivers
+v0xc4f32f840_0 .net *"_ivl_9", 15 0, L_0xc4ef51900;  1 drivers
+L_0xc4e87a6e0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f32f8e0_0 .net/s "acc_in", 31 0, L_0xc4e87a6e0;  1 drivers
+v0xc4f32f980_0 .net/s "acc_out", 31 0, L_0xc4f3a3660;  alias, 1 drivers
+v0xc4f32fa20_0 .net/s "product", 15 0, L_0xc4ef51860;  1 drivers
+v0xc4f32fac0_0 .net/s "product_ext", 31 0, L_0xc4f3a35c0;  1 drivers
+v0xc4f32fb60_0 .net/s "w", 7 0, L_0xc4f39e440;  1 drivers
+v0xc4f32fc00_0 .net/s "x", 7 0, L_0xc4f39e3a0;  1 drivers
+L_0xc4f3a3480 .extend/s 16, L_0xc4f39e3a0;
+L_0xc4f3a3520 .extend/s 16, L_0xc4f39e440;
+L_0xc4ef51860 .arith/mult 16, L_0xc4f3a3480, L_0xc4f3a3520;
+L_0xc4f39e300 .part L_0xc4ef51860, 15, 1;
+L_0xc4ef51900 .repeat 16, 16, L_0xc4f39e300;
+L_0xc4f3a35c0 .concat [ 16 16 0 0], L_0xc4ef51860, L_0xc4ef51900;
+L_0xc4f3a3660 .arith/sum 32, L_0xc4e87a6e0, L_0xc4f3a35c0;
+S_0xc4f32b000 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f2dff00 .param/l "i" 1 5 20, +C4<0101>;
+S_0xc4f32b180 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f32b000;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2afa80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2afac0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2afb00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f32fca0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3a3700;  1 drivers
+v0xc4f32fd40_0 .net/s *"_ivl_2", 15 0, L_0xc4f3a37a0;  1 drivers
+v0xc4f32fde0_0 .net *"_ivl_7", 0 0, L_0xc4f39e4e0;  1 drivers
+v0xc4f32fe80_0 .net *"_ivl_9", 15 0, L_0xc4ef51a40;  1 drivers
+L_0xc4e87a728 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f32ff20_0 .net/s "acc_in", 31 0, L_0xc4e87a728;  1 drivers
+v0xc4f330000_0 .net/s "acc_out", 31 0, L_0xc4f3a38e0;  alias, 1 drivers
+v0xc4f3300a0_0 .net/s "product", 15 0, L_0xc4ef519a0;  1 drivers
+v0xc4f330140_0 .net/s "product_ext", 31 0, L_0xc4f3a3840;  1 drivers
+v0xc4f3301e0_0 .net/s "w", 7 0, L_0xc4f39e620;  1 drivers
+v0xc4f330280_0 .net/s "x", 7 0, L_0xc4f39e580;  1 drivers
+L_0xc4f3a3700 .extend/s 16, L_0xc4f39e580;
+L_0xc4f3a37a0 .extend/s 16, L_0xc4f39e620;
+L_0xc4ef519a0 .arith/mult 16, L_0xc4f3a3700, L_0xc4f3a37a0;
+L_0xc4f39e4e0 .part L_0xc4ef519a0, 15, 1;
+L_0xc4ef51a40 .repeat 16, 16, L_0xc4f39e4e0;
+L_0xc4f3a3840 .concat [ 16 16 0 0], L_0xc4ef519a0, L_0xc4ef51a40;
+L_0xc4f3a38e0 .arith/sum 32, L_0xc4e87a728, L_0xc4f3a3840;
+S_0xc4f32b300 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f2dff40 .param/l "i" 1 5 20, +C4<0110>;
+S_0xc4f32b480 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f32b300;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2afb40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2afb80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2afbc0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f330320_0 .net/s *"_ivl_0", 15 0, L_0xc4f3a3980;  1 drivers
+v0xc4f3303c0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3a3a20;  1 drivers
+v0xc4f330460_0 .net *"_ivl_7", 0 0, L_0xc4f39e6c0;  1 drivers
+v0xc4f330500_0 .net *"_ivl_9", 15 0, L_0xc4ef51b80;  1 drivers
+L_0xc4e87a770 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3305a0_0 .net/s "acc_in", 31 0, L_0xc4e87a770;  1 drivers
+v0xc4f330640_0 .net/s "acc_out", 31 0, L_0xc4f3a3b60;  alias, 1 drivers
+v0xc4f3306e0_0 .net/s "product", 15 0, L_0xc4ef51ae0;  1 drivers
+v0xc4f330780_0 .net/s "product_ext", 31 0, L_0xc4f3a3ac0;  1 drivers
+v0xc4f330820_0 .net/s "w", 7 0, L_0xc4f39e800;  1 drivers
+v0xc4f3308c0_0 .net/s "x", 7 0, L_0xc4f39e760;  1 drivers
+L_0xc4f3a3980 .extend/s 16, L_0xc4f39e760;
+L_0xc4f3a3a20 .extend/s 16, L_0xc4f39e800;
+L_0xc4ef51ae0 .arith/mult 16, L_0xc4f3a3980, L_0xc4f3a3a20;
+L_0xc4f39e6c0 .part L_0xc4ef51ae0, 15, 1;
+L_0xc4ef51b80 .repeat 16, 16, L_0xc4f39e6c0;
+L_0xc4f3a3ac0 .concat [ 16 16 0 0], L_0xc4ef51ae0, L_0xc4ef51b80;
+L_0xc4f3a3b60 .arith/sum 32, L_0xc4e87a770, L_0xc4f3a3ac0;
+S_0xc4f32b600 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f2dff80 .param/l "i" 1 5 20, +C4<0111>;
+S_0xc4f32b780 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f32b600;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2afc00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2afc40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2afc80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f330960_0 .net/s *"_ivl_0", 15 0, L_0xc4f3a3c00;  1 drivers
+v0xc4f330a00_0 .net/s *"_ivl_2", 15 0, L_0xc4f3a3ca0;  1 drivers
+v0xc4f330aa0_0 .net *"_ivl_7", 0 0, L_0xc4f39e8a0;  1 drivers
+v0xc4f330b40_0 .net *"_ivl_9", 15 0, L_0xc4ef51cc0;  1 drivers
+L_0xc4e87a7b8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f330be0_0 .net/s "acc_in", 31 0, L_0xc4e87a7b8;  1 drivers
+v0xc4f330c80_0 .net/s "acc_out", 31 0, L_0xc4f3a3de0;  alias, 1 drivers
+v0xc4f330d20_0 .net/s "product", 15 0, L_0xc4ef51c20;  1 drivers
+v0xc4f330dc0_0 .net/s "product_ext", 31 0, L_0xc4f3a3d40;  1 drivers
+v0xc4f330e60_0 .net/s "w", 7 0, L_0xc4f39e9e0;  1 drivers
+v0xc4f330f00_0 .net/s "x", 7 0, L_0xc4f39e940;  1 drivers
+L_0xc4f3a3c00 .extend/s 16, L_0xc4f39e940;
+L_0xc4f3a3ca0 .extend/s 16, L_0xc4f39e9e0;
+L_0xc4ef51c20 .arith/mult 16, L_0xc4f3a3c00, L_0xc4f3a3ca0;
+L_0xc4f39e8a0 .part L_0xc4ef51c20, 15, 1;
+L_0xc4ef51cc0 .repeat 16, 16, L_0xc4f39e8a0;
+L_0xc4f3a3d40 .concat [ 16 16 0 0], L_0xc4ef51c20, L_0xc4ef51cc0;
+L_0xc4f3a3de0 .arith/sum 32, L_0xc4e87a7b8, L_0xc4f3a3d40;
+S_0xc4f32b900 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f2dfe80 .param/l "i" 1 5 80, +C4<00>;
+L_0xc4f3a8000 .functor BUFZ 32, L_0xc4f3a2c60, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f32ba80 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f2dffc0 .param/l "i" 1 5 80, +C4<01>;
+L_0xc4f3a8070 .functor BUFZ 32, L_0xc4f3a2ee0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f32bc00 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f334000 .param/l "i" 1 5 80, +C4<010>;
+L_0xc4f3a80e0 .functor BUFZ 32, L_0xc4f3a3160, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f32bd80 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f334040 .param/l "i" 1 5 80, +C4<011>;
+L_0xc4f3a8150 .functor BUFZ 32, L_0xc4f3a33e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f338000 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f334080 .param/l "i" 1 5 80, +C4<0100>;
+L_0xc4f3a81c0 .functor BUFZ 32, L_0xc4f3a3660, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f338180 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f3340c0 .param/l "i" 1 5 80, +C4<0101>;
+L_0xc4f3a8230 .functor BUFZ 32, L_0xc4f3a38e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f338300 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f334100 .param/l "i" 1 5 80, +C4<0110>;
+L_0xc4f3a82a0 .functor BUFZ 32, L_0xc4f3a3b60, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f338480 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f334140 .param/l "i" 1 5 80, +C4<0111>;
+L_0xc4f3a8310 .functor BUFZ 32, L_0xc4f3a3de0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f338600 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f334180 .param/l "level" 1 5 92, +C4<00>;
+S_0xc4f338780 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f338600;
+ .timescale 0 0;
+P_0xc4f3341c0 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3a3e80 .arith/sum 32, L_0xc4f3a8000, L_0xc4f3a8070;
+S_0xc4f338900 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f338600;
+ .timescale 0 0;
+P_0xc4f334200 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3a3f20 .arith/sum 32, L_0xc4f3a80e0, L_0xc4f3a8150;
+S_0xc4f338a80 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xc4f338600;
+ .timescale 0 0;
+P_0xc4f334240 .param/l "node" 1 5 94, +C4<010>;
+L_0xc4f3ac000 .arith/sum 32, L_0xc4f3a81c0, L_0xc4f3a8230;
+S_0xc4f338c00 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xc4f338600;
+ .timescale 0 0;
+P_0xc4f334280 .param/l "node" 1 5 94, +C4<011>;
+L_0xc4f3ac0a0 .arith/sum 32, L_0xc4f3a82a0, L_0xc4f3a8310;
+S_0xc4f338d80 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f3342c0 .param/l "level" 1 5 92, +C4<01>;
+S_0xc4f338f00 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f338d80;
+ .timescale 0 0;
+P_0xc4f334300 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3ac140 .arith/sum 32, L_0xc4f3a3e80, L_0xc4f3a3f20;
+S_0xc4f339080 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f338d80;
+ .timescale 0 0;
+P_0xc4f334340 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3ac1e0 .arith/sum 32, L_0xc4f3ac000, L_0xc4f3ac0a0;
+S_0xc4f339200 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xc4f329f80;
+ .timescale 0 0;
+P_0xc4f334380 .param/l "level" 1 5 92, +C4<010>;
+S_0xc4f339380 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f339200;
+ .timescale 0 0;
+P_0xc4f3343c0 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3ac280 .arith/sum 32, L_0xc4f3ac140, L_0xc4f3ac1e0;
+S_0xc4f339500 .scope module, "u_b" "neuron_parallel" 12 85, 4 1 0, S_0x102d15030;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "start";
+    .port_info 3 /INPUT 240 "x_bus";
+    .port_info 4 /INPUT 240 "w_bus";
+    .port_info 5 /INPUT 8 "bias";
+    .port_info 6 /OUTPUT 8 "y";
+    .port_info 7 /OUTPUT 1 "busy";
+    .port_info 8 /OUTPUT 1 "done";
+P_0xc4ef2c000 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000100000>;
+P_0xc4ef2c040 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000001000>;
+P_0xc4ef2c080 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000000011>;
+P_0xc4ef2c0c0 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000010>;
+P_0xc4ef2c100 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000000011110>;
+P_0xc4ef2c140 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>;
+v0xc4f345c20_0 .net *"_ivl_0", 31 0, L_0xc4f3ac500;  1 drivers
+v0xc4f345cc0_0 .net *"_ivl_11", 31 0, L_0xc4ef51f40;  1 drivers
+v0xc4f345d60_0 .net *"_ivl_14", 31 0, L_0xc4f3ac5a0;  1 drivers
+L_0xc4e87a8d8 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f345e00_0 .net *"_ivl_17", 29 0, L_0xc4e87a8d8;  1 drivers
+L_0xc4e87a920 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f345ea0_0 .net/2u *"_ivl_18", 31 0, L_0xc4e87a920;  1 drivers
+v0xc4f345f40_0 .net *"_ivl_21", 31 0, L_0xc4ef51fe0;  1 drivers
+L_0xc4e87a968 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f345fe0_0 .net/2u *"_ivl_22", 31 0, L_0xc4e87a968;  1 drivers
+v0xc4f346080_0 .net *"_ivl_25", 31 0, L_0xc4ef52080;  1 drivers
+v0xc4f346120_0 .net *"_ivl_29", 0 0, L_0xc4f39fb60;  1 drivers
+L_0xc4e87a800 .functor BUFT 1, C4<000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3461c0_0 .net *"_ivl_3", 29 0, L_0xc4e87a800;  1 drivers
+v0xc4f346260_0 .net *"_ivl_31", 23 0, L_0xc4ef52bc0;  1 drivers
+L_0xc4e87a848 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f346300_0 .net/2u *"_ivl_4", 31 0, L_0xc4e87a848;  1 drivers
+v0xc4f3463a0_0 .net *"_ivl_7", 31 0, L_0xc4ef51ea0;  1 drivers
+L_0xc4e87a890 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f346440_0 .net/2u *"_ivl_8", 31 0, L_0xc4e87a890;  1 drivers
+v0xc4f3464e0_0 .var/s "acc", 31 0;
+v0xc4f346580_0 .net/s "acc_next", 31 0, L_0xc4f3adea0;  1 drivers
+v0xc4f346620_0 .net/s "bias", 7 0, v0xc4f3852c0_0;  1 drivers
+v0xc4f3466c0_0 .net/s "bias_ext", 31 0, L_0xc4f3adf40;  1 drivers
+v0xc4f346760_0 .var "busy", 0 0;
+v0xc4f346800_0 .net "clk", 0 0, v0xc4f385860_0;  alias, 1 drivers
+v0xc4f3468a0_0 .var "done", 0 0;
+v0xc4f346940_0 .net/s "final_acc", 31 0, L_0xc4f3adfe0;  1 drivers
+v0xc4f3469e0_0 .var "group_index", 1 0;
+v0xc4f346a80_0 .net "rst", 0 0, v0xc4f385ea0_0;  alias, 1 drivers
+v0xc4f346b20_0 .net "start", 0 0, v0xc4f385fe0_0;  1 drivers
+v0xc4f346bc0_0 .net/s "w_bus", 239 0, v0xc4f3863a0_0;  1 drivers
+v0xc4f346c60_0 .net/s "w_group", 63 0, L_0xc4f39ebc0;  1 drivers
+v0xc4f346d00_0 .net/s "x_bus", 239 0, v0xc4f3866c0_0;  1 drivers
+v0xc4f346da0_0 .net/s "x_group", 63 0, L_0xc4f39eb20;  1 drivers
+v0xc4f346e40_0 .var/s "y", 7 0;
+L_0xc4f3ac500 .concat [ 2 30 0 0], v0xc4f3469e0_0, L_0xc4e87a800;
+L_0xc4ef51ea0 .arith/mult 32, L_0xc4f3ac500, L_0xc4e87a848;
+L_0xc4ef51f40 .arith/mult 32, L_0xc4ef51ea0, L_0xc4e87a890;
+L_0xc4f39eb20 .part/v v0xc4f3866c0_0, L_0xc4ef51f40, 64;
+L_0xc4f3ac5a0 .concat [ 2 30 0 0], v0xc4f3469e0_0, L_0xc4e87a8d8;
+L_0xc4ef51fe0 .arith/mult 32, L_0xc4f3ac5a0, L_0xc4e87a920;
+L_0xc4ef52080 .arith/mult 32, L_0xc4ef51fe0, L_0xc4e87a968;
+L_0xc4f39ebc0 .part/v v0xc4f3863a0_0, L_0xc4ef52080, 64;
+L_0xc4f39fb60 .part v0xc4f3852c0_0, 7, 1;
+L_0xc4ef52bc0 .repeat 24, 24, L_0xc4f39fb60;
+L_0xc4f3adf40 .concat [ 8 24 0 0], v0xc4f3852c0_0, L_0xc4ef52bc0;
+L_0xc4f3adfe0 .arith/sum 32, L_0xc4f3adea0, L_0xc4f3adf40;
+S_0xc4f339680 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xc4f339500;
+ .timescale 0 0;
+    .port_info 0 /INPUT 64 "x_bus";
+    .port_info 1 /INPUT 64 "w_bus";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4ef0e100 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000100000>;
+P_0xc4ef0e140 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000001000>;
+P_0xc4ef0e180 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>;
+P_0xc4ef0e1c0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>;
+v0xc4f345860_0 .net/s "acc_in", 31 0, v0xc4f3464e0_0;  1 drivers
+v0xc4f345900_0 .net/s "acc_out", 31 0, L_0xc4f3adea0;  alias, 1 drivers
+v0xc4f3459a0 .array "products", 7 0;
+v0xc4f3459a0_0 .net/s v0xc4f3459a0 0, 31 0, L_0xc4f3ac820; 1 drivers
+v0xc4f3459a0_1 .net/s v0xc4f3459a0 1, 31 0, L_0xc4f3acaa0; 1 drivers
+v0xc4f3459a0_2 .net/s v0xc4f3459a0 2, 31 0, L_0xc4f3acd20; 1 drivers
+v0xc4f3459a0_3 .net/s v0xc4f3459a0 3, 31 0, L_0xc4f3acfa0; 1 drivers
+v0xc4f3459a0_4 .net/s v0xc4f3459a0 4, 31 0, L_0xc4f3ad220; 1 drivers
+v0xc4f3459a0_5 .net/s v0xc4f3459a0 5, 31 0, L_0xc4f3ad4a0; 1 drivers
+v0xc4f3459a0_6 .net/s v0xc4f3459a0 6, 31 0, L_0xc4f3ad720; 1 drivers
+v0xc4f3459a0_7 .net/s v0xc4f3459a0 7, 31 0, L_0xc4f3ad9a0; 1 drivers
+v0xc4f345a40 .array "tree", 31 0;
+v0xc4f345a40_0 .net/s v0xc4f345a40 0, 31 0, L_0xc4f3a8380; 1 drivers
+v0xc4f345a40_1 .net/s v0xc4f345a40 1, 31 0, L_0xc4f3a83f0; 1 drivers
+v0xc4f345a40_2 .net/s v0xc4f345a40 2, 31 0, L_0xc4f3a8460; 1 drivers
+v0xc4f345a40_3 .net/s v0xc4f345a40 3, 31 0, L_0xc4f3a84d0; 1 drivers
+v0xc4f345a40_4 .net/s v0xc4f345a40 4, 31 0, L_0xc4f3a8540; 1 drivers
+v0xc4f345a40_5 .net/s v0xc4f345a40 5, 31 0, L_0xc4f3a85b0; 1 drivers
+v0xc4f345a40_6 .net/s v0xc4f345a40 6, 31 0, L_0xc4f3a8620; 1 drivers
+v0xc4f345a40_7 .net/s v0xc4f345a40 7, 31 0, L_0xc4f3a8690; 1 drivers
+v0xc4f345a40_8 .net/s v0xc4f345a40 8, 31 0, L_0xc4f3ada40; 1 drivers
+v0xc4f345a40_9 .net/s v0xc4f345a40 9, 31 0, L_0xc4f3adae0; 1 drivers
+v0xc4f345a40_10 .net/s v0xc4f345a40 10, 31 0, L_0xc4f3adb80; 1 drivers
+v0xc4f345a40_11 .net/s v0xc4f345a40 11, 31 0, L_0xc4f3adc20; 1 drivers
+o0xc4e85ec20 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f345a40_12 .net/s v0xc4f345a40 12, 31 0, o0xc4e85ec20; 0 drivers
+o0xc4e85ec50 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f345a40_13 .net/s v0xc4f345a40 13, 31 0, o0xc4e85ec50; 0 drivers
+o0xc4e85ec80 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f345a40_14 .net/s v0xc4f345a40 14, 31 0, o0xc4e85ec80; 0 drivers
+o0xc4e85ecb0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f345a40_15 .net/s v0xc4f345a40 15, 31 0, o0xc4e85ecb0; 0 drivers
+v0xc4f345a40_16 .net/s v0xc4f345a40 16, 31 0, L_0xc4f3adcc0; 1 drivers
+v0xc4f345a40_17 .net/s v0xc4f345a40 17, 31 0, L_0xc4f3add60; 1 drivers
+o0xc4e85ed40 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f345a40_18 .net/s v0xc4f345a40 18, 31 0, o0xc4e85ed40; 0 drivers
+o0xc4e85ed70 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f345a40_19 .net/s v0xc4f345a40 19, 31 0, o0xc4e85ed70; 0 drivers
+o0xc4e85eda0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f345a40_20 .net/s v0xc4f345a40 20, 31 0, o0xc4e85eda0; 0 drivers
+o0xc4e85edd0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f345a40_21 .net/s v0xc4f345a40 21, 31 0, o0xc4e85edd0; 0 drivers
+o0xc4e85ee00 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f345a40_22 .net/s v0xc4f345a40 22, 31 0, o0xc4e85ee00; 0 drivers
+o0xc4e85ee30 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f345a40_23 .net/s v0xc4f345a40 23, 31 0, o0xc4e85ee30; 0 drivers
+v0xc4f345a40_24 .net/s v0xc4f345a40 24, 31 0, L_0xc4f3ade00; 1 drivers
+o0xc4e85ee90 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f345a40_25 .net/s v0xc4f345a40 25, 31 0, o0xc4e85ee90; 0 drivers
+o0xc4e85eec0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f345a40_26 .net/s v0xc4f345a40 26, 31 0, o0xc4e85eec0; 0 drivers
+o0xc4e85eef0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f345a40_27 .net/s v0xc4f345a40 27, 31 0, o0xc4e85eef0; 0 drivers
+o0xc4e85ef20 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f345a40_28 .net/s v0xc4f345a40 28, 31 0, o0xc4e85ef20; 0 drivers
+o0xc4e85ef50 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f345a40_29 .net/s v0xc4f345a40 29, 31 0, o0xc4e85ef50; 0 drivers
+o0xc4e85ef80 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f345a40_30 .net/s v0xc4f345a40 30, 31 0, o0xc4e85ef80; 0 drivers
+o0xc4e85efb0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f345a40_31 .net/s v0xc4f345a40 31, 31 0, o0xc4e85efb0; 0 drivers
+v0xc4f345ae0_0 .net/s "w_bus", 63 0, L_0xc4f39ebc0;  alias, 1 drivers
+v0xc4f345b80_0 .net/s "x_bus", 63 0, L_0xc4f39eb20;  alias, 1 drivers
+L_0xc4f39ed00 .part L_0xc4f39eb20, 0, 8;
+L_0xc4f39eda0 .part L_0xc4f39ebc0, 0, 8;
+L_0xc4f39eee0 .part L_0xc4f39eb20, 8, 8;
+L_0xc4f39ef80 .part L_0xc4f39ebc0, 8, 8;
+L_0xc4f39f0c0 .part L_0xc4f39eb20, 16, 8;
+L_0xc4f39f160 .part L_0xc4f39ebc0, 16, 8;
+L_0xc4f39f2a0 .part L_0xc4f39eb20, 24, 8;
+L_0xc4f39f340 .part L_0xc4f39ebc0, 24, 8;
+L_0xc4f39f480 .part L_0xc4f39eb20, 32, 8;
+L_0xc4f39f520 .part L_0xc4f39ebc0, 32, 8;
+L_0xc4f39f660 .part L_0xc4f39eb20, 40, 8;
+L_0xc4f39f700 .part L_0xc4f39ebc0, 40, 8;
+L_0xc4f39f840 .part L_0xc4f39eb20, 48, 8;
+L_0xc4f39f8e0 .part L_0xc4f39ebc0, 48, 8;
+L_0xc4f39fa20 .part L_0xc4f39eb20, 56, 8;
+L_0xc4f39fac0 .part L_0xc4f39ebc0, 56, 8;
+L_0xc4f3adea0 .arith/sum 32, v0xc4f3464e0_0, L_0xc4f3ade00;
+S_0xc4f339800 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f334440 .param/l "i" 1 5 20, +C4<00>;
+S_0xc4f339980 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f339800;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2afcc0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2afd00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2afd40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f332620_0 .net/s *"_ivl_0", 15 0, L_0xc4f3ac640;  1 drivers
+v0xc4f3326c0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3ac6e0;  1 drivers
+v0xc4f332760_0 .net *"_ivl_7", 0 0, L_0xc4f39ec60;  1 drivers
+v0xc4f332800_0 .net *"_ivl_9", 15 0, L_0xc4ef521c0;  1 drivers
+L_0xc4e87a9b0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3328a0_0 .net/s "acc_in", 31 0, L_0xc4e87a9b0;  1 drivers
+v0xc4f332940_0 .net/s "acc_out", 31 0, L_0xc4f3ac820;  alias, 1 drivers
+v0xc4f3329e0_0 .net/s "product", 15 0, L_0xc4ef52120;  1 drivers
+v0xc4f332a80_0 .net/s "product_ext", 31 0, L_0xc4f3ac780;  1 drivers
+v0xc4f332b20_0 .net/s "w", 7 0, L_0xc4f39eda0;  1 drivers
+v0xc4f332bc0_0 .net/s "x", 7 0, L_0xc4f39ed00;  1 drivers
+L_0xc4f3ac640 .extend/s 16, L_0xc4f39ed00;
+L_0xc4f3ac6e0 .extend/s 16, L_0xc4f39eda0;
+L_0xc4ef52120 .arith/mult 16, L_0xc4f3ac640, L_0xc4f3ac6e0;
+L_0xc4f39ec60 .part L_0xc4ef52120, 15, 1;
+L_0xc4ef521c0 .repeat 16, 16, L_0xc4f39ec60;
+L_0xc4f3ac780 .concat [ 16 16 0 0], L_0xc4ef52120, L_0xc4ef521c0;
+L_0xc4f3ac820 .arith/sum 32, L_0xc4e87a9b0, L_0xc4f3ac780;
+S_0xc4f339b00 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f334480 .param/l "i" 1 5 20, +C4<01>;
+S_0xc4f339c80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f339b00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2afd80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2afdc0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2afe00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f332c60_0 .net/s *"_ivl_0", 15 0, L_0xc4f3ac8c0;  1 drivers
+v0xc4f332d00_0 .net/s *"_ivl_2", 15 0, L_0xc4f3ac960;  1 drivers
+v0xc4f332da0_0 .net *"_ivl_7", 0 0, L_0xc4f39ee40;  1 drivers
+v0xc4f332e40_0 .net *"_ivl_9", 15 0, L_0xc4ef52300;  1 drivers
+L_0xc4e87a9f8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f332ee0_0 .net/s "acc_in", 31 0, L_0xc4e87a9f8;  1 drivers
+v0xc4f332f80_0 .net/s "acc_out", 31 0, L_0xc4f3acaa0;  alias, 1 drivers
+v0xc4f333020_0 .net/s "product", 15 0, L_0xc4ef52260;  1 drivers
+v0xc4f3330c0_0 .net/s "product_ext", 31 0, L_0xc4f3aca00;  1 drivers
+v0xc4f333160_0 .net/s "w", 7 0, L_0xc4f39ef80;  1 drivers
+v0xc4f333200_0 .net/s "x", 7 0, L_0xc4f39eee0;  1 drivers
+L_0xc4f3ac8c0 .extend/s 16, L_0xc4f39eee0;
+L_0xc4f3ac960 .extend/s 16, L_0xc4f39ef80;
+L_0xc4ef52260 .arith/mult 16, L_0xc4f3ac8c0, L_0xc4f3ac960;
+L_0xc4f39ee40 .part L_0xc4ef52260, 15, 1;
+L_0xc4ef52300 .repeat 16, 16, L_0xc4f39ee40;
+L_0xc4f3aca00 .concat [ 16 16 0 0], L_0xc4ef52260, L_0xc4ef52300;
+L_0xc4f3acaa0 .arith/sum 32, L_0xc4e87a9f8, L_0xc4f3aca00;
+S_0xc4f339e00 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f3344c0 .param/l "i" 1 5 20, +C4<010>;
+S_0xc4f339f80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f339e00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2afe40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2afe80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2afec0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f3332a0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3acb40;  1 drivers
+v0xc4f333340_0 .net/s *"_ivl_2", 15 0, L_0xc4f3acbe0;  1 drivers
+v0xc4f3333e0_0 .net *"_ivl_7", 0 0, L_0xc4f39f020;  1 drivers
+v0xc4f333480_0 .net *"_ivl_9", 15 0, L_0xc4ef52440;  1 drivers
+L_0xc4e87aa40 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f333520_0 .net/s "acc_in", 31 0, L_0xc4e87aa40;  1 drivers
+v0xc4f3335c0_0 .net/s "acc_out", 31 0, L_0xc4f3acd20;  alias, 1 drivers
+v0xc4f333660_0 .net/s "product", 15 0, L_0xc4ef523a0;  1 drivers
+v0xc4f333700_0 .net/s "product_ext", 31 0, L_0xc4f3acc80;  1 drivers
+v0xc4f3337a0_0 .net/s "w", 7 0, L_0xc4f39f160;  1 drivers
+v0xc4f333840_0 .net/s "x", 7 0, L_0xc4f39f0c0;  1 drivers
+L_0xc4f3acb40 .extend/s 16, L_0xc4f39f0c0;
+L_0xc4f3acbe0 .extend/s 16, L_0xc4f39f160;
+L_0xc4ef523a0 .arith/mult 16, L_0xc4f3acb40, L_0xc4f3acbe0;
+L_0xc4f39f020 .part L_0xc4ef523a0, 15, 1;
+L_0xc4ef52440 .repeat 16, 16, L_0xc4f39f020;
+L_0xc4f3acc80 .concat [ 16 16 0 0], L_0xc4ef523a0, L_0xc4ef52440;
+L_0xc4f3acd20 .arith/sum 32, L_0xc4e87aa40, L_0xc4f3acc80;
+S_0xc4f33a100 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f334500 .param/l "i" 1 5 20, +C4<011>;
+S_0xc4f33a280 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f33a100;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f2aff00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f2aff40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f2aff80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f3338e0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3acdc0;  1 drivers
+v0xc4f333980_0 .net/s *"_ivl_2", 15 0, L_0xc4f3ace60;  1 drivers
+v0xc4f333a20_0 .net *"_ivl_7", 0 0, L_0xc4f39f200;  1 drivers
+v0xc4f333ac0_0 .net *"_ivl_9", 15 0, L_0xc4ef52580;  1 drivers
+L_0xc4e87aa88 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f333b60_0 .net/s "acc_in", 31 0, L_0xc4e87aa88;  1 drivers
+v0xc4f333c00_0 .net/s "acc_out", 31 0, L_0xc4f3acfa0;  alias, 1 drivers
+v0xc4f333ca0_0 .net/s "product", 15 0, L_0xc4ef524e0;  1 drivers
+v0xc4f333d40_0 .net/s "product_ext", 31 0, L_0xc4f3acf00;  1 drivers
+v0xc4f333de0_0 .net/s "w", 7 0, L_0xc4f39f340;  1 drivers
+v0xc4f333e80_0 .net/s "x", 7 0, L_0xc4f39f2a0;  1 drivers
+L_0xc4f3acdc0 .extend/s 16, L_0xc4f39f2a0;
+L_0xc4f3ace60 .extend/s 16, L_0xc4f39f340;
+L_0xc4ef524e0 .arith/mult 16, L_0xc4f3acdc0, L_0xc4f3ace60;
+L_0xc4f39f200 .part L_0xc4ef524e0, 15, 1;
+L_0xc4ef52580 .repeat 16, 16, L_0xc4f39f200;
+L_0xc4f3acf00 .concat [ 16 16 0 0], L_0xc4ef524e0, L_0xc4ef52580;
+L_0xc4f3acfa0 .arith/sum 32, L_0xc4e87aa88, L_0xc4f3acf00;
+S_0xc4f33a400 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f334580 .param/l "i" 1 5 20, +C4<0100>;
+S_0xc4f33a580 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f33a400;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f340000 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f340040 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f340080 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f333f20_0 .net/s *"_ivl_0", 15 0, L_0xc4f3ad040;  1 drivers
+v0xc4f344000_0 .net/s *"_ivl_2", 15 0, L_0xc4f3ad0e0;  1 drivers
+v0xc4f3440a0_0 .net *"_ivl_7", 0 0, L_0xc4f39f3e0;  1 drivers
+v0xc4f344140_0 .net *"_ivl_9", 15 0, L_0xc4ef526c0;  1 drivers
+L_0xc4e87aad0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3441e0_0 .net/s "acc_in", 31 0, L_0xc4e87aad0;  1 drivers
+v0xc4f344280_0 .net/s "acc_out", 31 0, L_0xc4f3ad220;  alias, 1 drivers
+v0xc4f344320_0 .net/s "product", 15 0, L_0xc4ef52620;  1 drivers
+v0xc4f3443c0_0 .net/s "product_ext", 31 0, L_0xc4f3ad180;  1 drivers
+v0xc4f344460_0 .net/s "w", 7 0, L_0xc4f39f520;  1 drivers
+v0xc4f344500_0 .net/s "x", 7 0, L_0xc4f39f480;  1 drivers
+L_0xc4f3ad040 .extend/s 16, L_0xc4f39f480;
+L_0xc4f3ad0e0 .extend/s 16, L_0xc4f39f520;
+L_0xc4ef52620 .arith/mult 16, L_0xc4f3ad040, L_0xc4f3ad0e0;
+L_0xc4f39f3e0 .part L_0xc4ef52620, 15, 1;
+L_0xc4ef526c0 .repeat 16, 16, L_0xc4f39f3e0;
+L_0xc4f3ad180 .concat [ 16 16 0 0], L_0xc4ef52620, L_0xc4ef526c0;
+L_0xc4f3ad220 .arith/sum 32, L_0xc4e87aad0, L_0xc4f3ad180;
+S_0xc4f33a700 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f3345c0 .param/l "i" 1 5 20, +C4<0101>;
+S_0xc4f33a880 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f33a700;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f3400c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f340100 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f340140 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f3445a0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3ad2c0;  1 drivers
+v0xc4f344640_0 .net/s *"_ivl_2", 15 0, L_0xc4f3ad360;  1 drivers
+v0xc4f3446e0_0 .net *"_ivl_7", 0 0, L_0xc4f39f5c0;  1 drivers
+v0xc4f344780_0 .net *"_ivl_9", 15 0, L_0xc4ef52800;  1 drivers
+L_0xc4e87ab18 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f344820_0 .net/s "acc_in", 31 0, L_0xc4e87ab18;  1 drivers
+v0xc4f3448c0_0 .net/s "acc_out", 31 0, L_0xc4f3ad4a0;  alias, 1 drivers
+v0xc4f344960_0 .net/s "product", 15 0, L_0xc4ef52760;  1 drivers
+v0xc4f344a00_0 .net/s "product_ext", 31 0, L_0xc4f3ad400;  1 drivers
+v0xc4f344aa0_0 .net/s "w", 7 0, L_0xc4f39f700;  1 drivers
+v0xc4f344b40_0 .net/s "x", 7 0, L_0xc4f39f660;  1 drivers
+L_0xc4f3ad2c0 .extend/s 16, L_0xc4f39f660;
+L_0xc4f3ad360 .extend/s 16, L_0xc4f39f700;
+L_0xc4ef52760 .arith/mult 16, L_0xc4f3ad2c0, L_0xc4f3ad360;
+L_0xc4f39f5c0 .part L_0xc4ef52760, 15, 1;
+L_0xc4ef52800 .repeat 16, 16, L_0xc4f39f5c0;
+L_0xc4f3ad400 .concat [ 16 16 0 0], L_0xc4ef52760, L_0xc4ef52800;
+L_0xc4f3ad4a0 .arith/sum 32, L_0xc4e87ab18, L_0xc4f3ad400;
+S_0xc4f33aa00 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f334600 .param/l "i" 1 5 20, +C4<0110>;
+S_0xc4f33ab80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f33aa00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f340180 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f3401c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f340200 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f344be0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3ad540;  1 drivers
+v0xc4f344c80_0 .net/s *"_ivl_2", 15 0, L_0xc4f3ad5e0;  1 drivers
+v0xc4f344d20_0 .net *"_ivl_7", 0 0, L_0xc4f39f7a0;  1 drivers
+v0xc4f344dc0_0 .net *"_ivl_9", 15 0, L_0xc4ef52940;  1 drivers
+L_0xc4e87ab60 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f344e60_0 .net/s "acc_in", 31 0, L_0xc4e87ab60;  1 drivers
+v0xc4f344f00_0 .net/s "acc_out", 31 0, L_0xc4f3ad720;  alias, 1 drivers
+v0xc4f344fa0_0 .net/s "product", 15 0, L_0xc4ef528a0;  1 drivers
+v0xc4f345040_0 .net/s "product_ext", 31 0, L_0xc4f3ad680;  1 drivers
+v0xc4f3450e0_0 .net/s "w", 7 0, L_0xc4f39f8e0;  1 drivers
+v0xc4f345180_0 .net/s "x", 7 0, L_0xc4f39f840;  1 drivers
+L_0xc4f3ad540 .extend/s 16, L_0xc4f39f840;
+L_0xc4f3ad5e0 .extend/s 16, L_0xc4f39f8e0;
+L_0xc4ef528a0 .arith/mult 16, L_0xc4f3ad540, L_0xc4f3ad5e0;
+L_0xc4f39f7a0 .part L_0xc4ef528a0, 15, 1;
+L_0xc4ef52940 .repeat 16, 16, L_0xc4f39f7a0;
+L_0xc4f3ad680 .concat [ 16 16 0 0], L_0xc4ef528a0, L_0xc4ef52940;
+L_0xc4f3ad720 .arith/sum 32, L_0xc4e87ab60, L_0xc4f3ad680;
+S_0xc4f33ad00 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f334640 .param/l "i" 1 5 20, +C4<0111>;
+S_0xc4f33ae80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f33ad00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f340240 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f340280 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f3402c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f345220_0 .net/s *"_ivl_0", 15 0, L_0xc4f3ad7c0;  1 drivers
+v0xc4f3452c0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3ad860;  1 drivers
+v0xc4f345360_0 .net *"_ivl_7", 0 0, L_0xc4f39f980;  1 drivers
+v0xc4f345400_0 .net *"_ivl_9", 15 0, L_0xc4ef52a80;  1 drivers
+L_0xc4e87aba8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3454a0_0 .net/s "acc_in", 31 0, L_0xc4e87aba8;  1 drivers
+v0xc4f345540_0 .net/s "acc_out", 31 0, L_0xc4f3ad9a0;  alias, 1 drivers
+v0xc4f3455e0_0 .net/s "product", 15 0, L_0xc4ef529e0;  1 drivers
+v0xc4f345680_0 .net/s "product_ext", 31 0, L_0xc4f3ad900;  1 drivers
+v0xc4f345720_0 .net/s "w", 7 0, L_0xc4f39fac0;  1 drivers
+v0xc4f3457c0_0 .net/s "x", 7 0, L_0xc4f39fa20;  1 drivers
+L_0xc4f3ad7c0 .extend/s 16, L_0xc4f39fa20;
+L_0xc4f3ad860 .extend/s 16, L_0xc4f39fac0;
+L_0xc4ef529e0 .arith/mult 16, L_0xc4f3ad7c0, L_0xc4f3ad860;
+L_0xc4f39f980 .part L_0xc4ef529e0, 15, 1;
+L_0xc4ef52a80 .repeat 16, 16, L_0xc4f39f980;
+L_0xc4f3ad900 .concat [ 16 16 0 0], L_0xc4ef529e0, L_0xc4ef52a80;
+L_0xc4f3ad9a0 .arith/sum 32, L_0xc4e87aba8, L_0xc4f3ad900;
+S_0xc4f33b000 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f334540 .param/l "i" 1 5 80, +C4<00>;
+L_0xc4f3a8380 .functor BUFZ 32, L_0xc4f3ac820, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f33b180 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f334680 .param/l "i" 1 5 80, +C4<01>;
+L_0xc4f3a83f0 .functor BUFZ 32, L_0xc4f3acaa0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f33b300 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f3346c0 .param/l "i" 1 5 80, +C4<010>;
+L_0xc4f3a8460 .functor BUFZ 32, L_0xc4f3acd20, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f33b480 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f334700 .param/l "i" 1 5 80, +C4<011>;
+L_0xc4f3a84d0 .functor BUFZ 32, L_0xc4f3acfa0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f33b600 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f334740 .param/l "i" 1 5 80, +C4<0100>;
+L_0xc4f3a8540 .functor BUFZ 32, L_0xc4f3ad220, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f33b780 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f334780 .param/l "i" 1 5 80, +C4<0101>;
+L_0xc4f3a85b0 .functor BUFZ 32, L_0xc4f3ad4a0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f33b900 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f3347c0 .param/l "i" 1 5 80, +C4<0110>;
+L_0xc4f3a8620 .functor BUFZ 32, L_0xc4f3ad720, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f33ba80 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f334800 .param/l "i" 1 5 80, +C4<0111>;
+L_0xc4f3a8690 .functor BUFZ 32, L_0xc4f3ad9a0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f33bc00 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f334840 .param/l "level" 1 5 92, +C4<00>;
+S_0xc4f33bd80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f33bc00;
+ .timescale 0 0;
+P_0xc4f334880 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3ada40 .arith/sum 32, L_0xc4f3a8380, L_0xc4f3a83f0;
+S_0xc4f348000 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f33bc00;
+ .timescale 0 0;
+P_0xc4f3348c0 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3adae0 .arith/sum 32, L_0xc4f3a8460, L_0xc4f3a84d0;
+S_0xc4f348180 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xc4f33bc00;
+ .timescale 0 0;
+P_0xc4f334900 .param/l "node" 1 5 94, +C4<010>;
+L_0xc4f3adb80 .arith/sum 32, L_0xc4f3a8540, L_0xc4f3a85b0;
+S_0xc4f348300 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xc4f33bc00;
+ .timescale 0 0;
+P_0xc4f334940 .param/l "node" 1 5 94, +C4<011>;
+L_0xc4f3adc20 .arith/sum 32, L_0xc4f3a8620, L_0xc4f3a8690;
+S_0xc4f348480 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f334980 .param/l "level" 1 5 92, +C4<01>;
+S_0xc4f348600 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f348480;
+ .timescale 0 0;
+P_0xc4f3349c0 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3adcc0 .arith/sum 32, L_0xc4f3ada40, L_0xc4f3adae0;
+S_0xc4f348780 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f348480;
+ .timescale 0 0;
+P_0xc4f334a00 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3add60 .arith/sum 32, L_0xc4f3adb80, L_0xc4f3adc20;
+S_0xc4f348900 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xc4f339680;
+ .timescale 0 0;
+P_0xc4f334a40 .param/l "level" 1 5 92, +C4<010>;
+S_0xc4f348a80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f348900;
+ .timescale 0 0;
+P_0xc4f334a80 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3ade00 .arith/sum 32, L_0xc4f3adcc0, L_0xc4f3add60;
+S_0xc4f348c00 .scope module, "u_c" "neuron_parallel" 12 113, 4 1 0, S_0x102d15030;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "start";
+    .port_info 3 /INPUT 160 "x_bus";
+    .port_info 4 /INPUT 160 "w_bus";
+    .port_info 5 /INPUT 8 "bias";
+    .port_info 6 /OUTPUT 8 "y";
+    .port_info 7 /OUTPUT 1 "busy";
+    .port_info 8 /OUTPUT 1 "done";
+P_0xc4ef2c180 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000100000>;
+P_0xc4ef2c1c0 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000001000>;
+P_0xc4ef2c200 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000000001>;
+P_0xc4ef2c240 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000001>;
+P_0xc4ef2c280 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000000010100>;
+P_0xc4ef2c2c0 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000010000>;
+v0xc4f351720_0 .net *"_ivl_0", 31 0, L_0xc4f3ae080;  1 drivers
+v0xc4f3517c0_0 .net *"_ivl_11", 31 0, L_0xc4ef52d00;  1 drivers
+v0xc4f351860_0 .net *"_ivl_14", 31 0, L_0xc4f3ae120;  1 drivers
+L_0xc4e87acc8 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f351900_0 .net *"_ivl_17", 30 0, L_0xc4e87acc8;  1 drivers
+L_0xc4e87ad10 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3519a0_0 .net/2u *"_ivl_18", 31 0, L_0xc4e87ad10;  1 drivers
+v0xc4f351a40_0 .net *"_ivl_21", 31 0, L_0xc4ef52da0;  1 drivers
+L_0xc4e87ad58 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f351ae0_0 .net/2u *"_ivl_22", 31 0, L_0xc4e87ad58;  1 drivers
+v0xc4f351b80_0 .net *"_ivl_25", 31 0, L_0xc4ef52e40;  1 drivers
+v0xc4f351c20_0 .net *"_ivl_29", 0 0, L_0xc4f3b1b80;  1 drivers
+L_0xc4e87abf0 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f351cc0_0 .net *"_ivl_3", 30 0, L_0xc4e87abf0;  1 drivers
+v0xc4f351d60_0 .net *"_ivl_31", 23 0, L_0xc4ef5c320;  1 drivers
+L_0xc4e87ac38 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
+v0xc4f351e00_0 .net/2u *"_ivl_4", 31 0, L_0xc4e87ac38;  1 drivers
+v0xc4f351ea0_0 .net *"_ivl_7", 31 0, L_0xc4ef52c60;  1 drivers
+L_0xc4e87ac80 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f351f40_0 .net/2u *"_ivl_8", 31 0, L_0xc4e87ac80;  1 drivers
+v0xc4f351fe0_0 .var/s "acc", 31 0;
+v0xc4f352080_0 .net/s "acc_next", 31 0, L_0xc4f3b5360;  1 drivers
+v0xc4f352120_0 .net/s "bias", 7 0, v0xc4f385360_0;  1 drivers
+v0xc4f3521c0_0 .net/s "bias_ext", 31 0, L_0xc4f3b5400;  1 drivers
+v0xc4f352260_0 .var "busy", 0 0;
+v0xc4f352300_0 .net "clk", 0 0, v0xc4f385860_0;  alias, 1 drivers
+v0xc4f3523a0_0 .var "done", 0 0;
+v0xc4f352440_0 .net/s "final_acc", 31 0, L_0xc4f3b54a0;  1 drivers
+v0xc4f3524e0_0 .var "group_index", 0 0;
+v0xc4f352580_0 .net "rst", 0 0, v0xc4f385ea0_0;  alias, 1 drivers
+v0xc4f352620_0 .net "start", 0 0, v0xc4f386080_0;  1 drivers
+v0xc4f3526c0_0 .net/s "w_bus", 159 0, v0xc4f386440_0;  1 drivers
+v0xc4f352760_0 .net/s "w_group", 127 0, L_0xc4f39fca0;  1 drivers
+v0xc4f352800_0 .net/s "x_bus", 159 0, v0xc4f386760_0;  1 drivers
+v0xc4f3528a0_0 .net/s "x_group", 127 0, L_0xc4f39fc00;  1 drivers
+v0xc4f352940_0 .var/s "y", 7 0;
+L_0xc4f3ae080 .concat [ 1 31 0 0], v0xc4f3524e0_0, L_0xc4e87abf0;
+L_0xc4ef52c60 .arith/mult 32, L_0xc4f3ae080, L_0xc4e87ac38;
+L_0xc4ef52d00 .arith/mult 32, L_0xc4ef52c60, L_0xc4e87ac80;
+L_0xc4f39fc00 .part/v v0xc4f386760_0, L_0xc4ef52d00, 128;
+L_0xc4f3ae120 .concat [ 1 31 0 0], v0xc4f3524e0_0, L_0xc4e87acc8;
+L_0xc4ef52da0 .arith/mult 32, L_0xc4f3ae120, L_0xc4e87ad10;
+L_0xc4ef52e40 .arith/mult 32, L_0xc4ef52da0, L_0xc4e87ad58;
+L_0xc4f39fca0 .part/v v0xc4f386440_0, L_0xc4ef52e40, 128;
+L_0xc4f3b1b80 .part v0xc4f385360_0, 7, 1;
+L_0xc4ef5c320 .repeat 24, 24, L_0xc4f3b1b80;
+L_0xc4f3b5400 .concat [ 8 24 0 0], v0xc4f385360_0, L_0xc4ef5c320;
+L_0xc4f3b54a0 .arith/sum 32, L_0xc4f3b5360, L_0xc4f3b5400;
+S_0xc4f348d80 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xc4f348c00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 128 "x_bus";
+    .port_info 1 /INPUT 128 "w_bus";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4ef0e400 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000100000>;
+P_0xc4ef0e440 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000001000>;
+P_0xc4ef0e480 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000010000>;
+P_0xc4ef0e4c0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000100>;
+v0xc4f351360_0 .net/s "acc_in", 31 0, v0xc4f351fe0_0;  1 drivers
+v0xc4f351400_0 .net/s "acc_out", 31 0, L_0xc4f3b5360;  alias, 1 drivers
+v0xc4f3514a0 .array "products", 15 0;
+v0xc4f3514a0_0 .net/s v0xc4f3514a0 0, 31 0, L_0xc4f3ae3a0; 1 drivers
+v0xc4f3514a0_1 .net/s v0xc4f3514a0 1, 31 0, L_0xc4f3ae620; 1 drivers
+v0xc4f3514a0_2 .net/s v0xc4f3514a0 2, 31 0, L_0xc4f3ae8a0; 1 drivers
+v0xc4f3514a0_3 .net/s v0xc4f3514a0 3, 31 0, L_0xc4f3aeb20; 1 drivers
+v0xc4f3514a0_4 .net/s v0xc4f3514a0 4, 31 0, L_0xc4f3aeda0; 1 drivers
+v0xc4f3514a0_5 .net/s v0xc4f3514a0 5, 31 0, L_0xc4f3af020; 1 drivers
+v0xc4f3514a0_6 .net/s v0xc4f3514a0 6, 31 0, L_0xc4f3af2a0; 1 drivers
+v0xc4f3514a0_7 .net/s v0xc4f3514a0 7, 31 0, L_0xc4f3af520; 1 drivers
+v0xc4f3514a0_8 .net/s v0xc4f3514a0 8, 31 0, L_0xc4f3af7a0; 1 drivers
+v0xc4f3514a0_9 .net/s v0xc4f3514a0 9, 31 0, L_0xc4f3afa20; 1 drivers
+v0xc4f3514a0_10 .net/s v0xc4f3514a0 10, 31 0, L_0xc4f3afca0; 1 drivers
+v0xc4f3514a0_11 .net/s v0xc4f3514a0 11, 31 0, L_0xc4f3aff20; 1 drivers
+v0xc4f3514a0_12 .net/s v0xc4f3514a0 12, 31 0, L_0xc4f3b41e0; 1 drivers
+v0xc4f3514a0_13 .net/s v0xc4f3514a0 13, 31 0, L_0xc4f3b4460; 1 drivers
+v0xc4f3514a0_14 .net/s v0xc4f3514a0 14, 31 0, L_0xc4f3b46e0; 1 drivers
+v0xc4f3514a0_15 .net/s v0xc4f3514a0 15, 31 0, L_0xc4f3b4960; 1 drivers
+v0xc4f351540 .array "tree", 79 0;
+v0xc4f351540_0 .net/s v0xc4f351540 0, 31 0, L_0xc4f3a8700; 1 drivers
+v0xc4f351540_1 .net/s v0xc4f351540 1, 31 0, L_0xc4f3a8770; 1 drivers
+v0xc4f351540_2 .net/s v0xc4f351540 2, 31 0, L_0xc4f3a87e0; 1 drivers
+v0xc4f351540_3 .net/s v0xc4f351540 3, 31 0, L_0xc4f3a8850; 1 drivers
+v0xc4f351540_4 .net/s v0xc4f351540 4, 31 0, L_0xc4f3a88c0; 1 drivers
+v0xc4f351540_5 .net/s v0xc4f351540 5, 31 0, L_0xc4f3a8930; 1 drivers
+v0xc4f351540_6 .net/s v0xc4f351540 6, 31 0, L_0xc4f3a89a0; 1 drivers
+v0xc4f351540_7 .net/s v0xc4f351540 7, 31 0, L_0xc4f3a8a10; 1 drivers
+v0xc4f351540_8 .net/s v0xc4f351540 8, 31 0, L_0xc4f3a8a80; 1 drivers
+v0xc4f351540_9 .net/s v0xc4f351540 9, 31 0, L_0xc4f3a8af0; 1 drivers
+v0xc4f351540_10 .net/s v0xc4f351540 10, 31 0, L_0xc4f3a8b60; 1 drivers
+v0xc4f351540_11 .net/s v0xc4f351540 11, 31 0, L_0xc4f3a8bd0; 1 drivers
+v0xc4f351540_12 .net/s v0xc4f351540 12, 31 0, L_0xc4f3a8c40; 1 drivers
+v0xc4f351540_13 .net/s v0xc4f351540 13, 31 0, L_0xc4f3a8cb0; 1 drivers
+v0xc4f351540_14 .net/s v0xc4f351540 14, 31 0, L_0xc4f3a8d20; 1 drivers
+v0xc4f351540_15 .net/s v0xc4f351540 15, 31 0, L_0xc4f3a8d90; 1 drivers
+v0xc4f351540_16 .net/s v0xc4f351540 16, 31 0, L_0xc4f3b4a00; 1 drivers
+v0xc4f351540_17 .net/s v0xc4f351540 17, 31 0, L_0xc4f3b4aa0; 1 drivers
+v0xc4f351540_18 .net/s v0xc4f351540 18, 31 0, L_0xc4f3b4b40; 1 drivers
+v0xc4f351540_19 .net/s v0xc4f351540 19, 31 0, L_0xc4f3b4be0; 1 drivers
+v0xc4f351540_20 .net/s v0xc4f351540 20, 31 0, L_0xc4f3b4c80; 1 drivers
+v0xc4f351540_21 .net/s v0xc4f351540 21, 31 0, L_0xc4f3b4d20; 1 drivers
+v0xc4f351540_22 .net/s v0xc4f351540 22, 31 0, L_0xc4f3b4dc0; 1 drivers
+v0xc4f351540_23 .net/s v0xc4f351540 23, 31 0, L_0xc4f3b4e60; 1 drivers
+o0xc4e862610 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_24 .net/s v0xc4f351540 24, 31 0, o0xc4e862610; 0 drivers
+o0xc4e862640 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_25 .net/s v0xc4f351540 25, 31 0, o0xc4e862640; 0 drivers
+o0xc4e862670 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_26 .net/s v0xc4f351540 26, 31 0, o0xc4e862670; 0 drivers
+o0xc4e8626a0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_27 .net/s v0xc4f351540 27, 31 0, o0xc4e8626a0; 0 drivers
+o0xc4e8626d0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_28 .net/s v0xc4f351540 28, 31 0, o0xc4e8626d0; 0 drivers
+o0xc4e862700 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_29 .net/s v0xc4f351540 29, 31 0, o0xc4e862700; 0 drivers
+o0xc4e862730 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_30 .net/s v0xc4f351540 30, 31 0, o0xc4e862730; 0 drivers
+o0xc4e862760 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_31 .net/s v0xc4f351540 31, 31 0, o0xc4e862760; 0 drivers
+v0xc4f351540_32 .net/s v0xc4f351540 32, 31 0, L_0xc4f3b4f00; 1 drivers
+v0xc4f351540_33 .net/s v0xc4f351540 33, 31 0, L_0xc4f3b4fa0; 1 drivers
+v0xc4f351540_34 .net/s v0xc4f351540 34, 31 0, L_0xc4f3b5040; 1 drivers
+v0xc4f351540_35 .net/s v0xc4f351540 35, 31 0, L_0xc4f3b50e0; 1 drivers
+o0xc4e862850 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_36 .net/s v0xc4f351540 36, 31 0, o0xc4e862850; 0 drivers
+o0xc4e862880 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_37 .net/s v0xc4f351540 37, 31 0, o0xc4e862880; 0 drivers
+o0xc4e8628b0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_38 .net/s v0xc4f351540 38, 31 0, o0xc4e8628b0; 0 drivers
+o0xc4e8628e0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_39 .net/s v0xc4f351540 39, 31 0, o0xc4e8628e0; 0 drivers
+o0xc4e862910 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_40 .net/s v0xc4f351540 40, 31 0, o0xc4e862910; 0 drivers
+o0xc4e862940 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_41 .net/s v0xc4f351540 41, 31 0, o0xc4e862940; 0 drivers
+o0xc4e862970 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_42 .net/s v0xc4f351540 42, 31 0, o0xc4e862970; 0 drivers
+o0xc4e8629a0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_43 .net/s v0xc4f351540 43, 31 0, o0xc4e8629a0; 0 drivers
+o0xc4e8629d0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_44 .net/s v0xc4f351540 44, 31 0, o0xc4e8629d0; 0 drivers
+o0xc4e862a00 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_45 .net/s v0xc4f351540 45, 31 0, o0xc4e862a00; 0 drivers
+o0xc4e862a30 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_46 .net/s v0xc4f351540 46, 31 0, o0xc4e862a30; 0 drivers
+o0xc4e862a60 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_47 .net/s v0xc4f351540 47, 31 0, o0xc4e862a60; 0 drivers
+v0xc4f351540_48 .net/s v0xc4f351540 48, 31 0, L_0xc4f3b5180; 1 drivers
+v0xc4f351540_49 .net/s v0xc4f351540 49, 31 0, L_0xc4f3b5220; 1 drivers
+o0xc4e862af0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_50 .net/s v0xc4f351540 50, 31 0, o0xc4e862af0; 0 drivers
+o0xc4e862b20 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_51 .net/s v0xc4f351540 51, 31 0, o0xc4e862b20; 0 drivers
+o0xc4e862b50 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_52 .net/s v0xc4f351540 52, 31 0, o0xc4e862b50; 0 drivers
+o0xc4e862b80 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_53 .net/s v0xc4f351540 53, 31 0, o0xc4e862b80; 0 drivers
+o0xc4e862bb0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_54 .net/s v0xc4f351540 54, 31 0, o0xc4e862bb0; 0 drivers
+o0xc4e862be0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_55 .net/s v0xc4f351540 55, 31 0, o0xc4e862be0; 0 drivers
+o0xc4e862c10 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_56 .net/s v0xc4f351540 56, 31 0, o0xc4e862c10; 0 drivers
+o0xc4e862c40 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_57 .net/s v0xc4f351540 57, 31 0, o0xc4e862c40; 0 drivers
+o0xc4e862c70 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_58 .net/s v0xc4f351540 58, 31 0, o0xc4e862c70; 0 drivers
+o0xc4e862ca0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_59 .net/s v0xc4f351540 59, 31 0, o0xc4e862ca0; 0 drivers
+o0xc4e862cd0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_60 .net/s v0xc4f351540 60, 31 0, o0xc4e862cd0; 0 drivers
+o0xc4e862d00 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_61 .net/s v0xc4f351540 61, 31 0, o0xc4e862d00; 0 drivers
+o0xc4e862d30 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_62 .net/s v0xc4f351540 62, 31 0, o0xc4e862d30; 0 drivers
+o0xc4e862d60 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_63 .net/s v0xc4f351540 63, 31 0, o0xc4e862d60; 0 drivers
+v0xc4f351540_64 .net/s v0xc4f351540 64, 31 0, L_0xc4f3b52c0; 1 drivers
+o0xc4e862dc0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_65 .net/s v0xc4f351540 65, 31 0, o0xc4e862dc0; 0 drivers
+o0xc4e862df0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_66 .net/s v0xc4f351540 66, 31 0, o0xc4e862df0; 0 drivers
+o0xc4e862e20 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_67 .net/s v0xc4f351540 67, 31 0, o0xc4e862e20; 0 drivers
+o0xc4e862e50 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_68 .net/s v0xc4f351540 68, 31 0, o0xc4e862e50; 0 drivers
+o0xc4e862e80 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_69 .net/s v0xc4f351540 69, 31 0, o0xc4e862e80; 0 drivers
+o0xc4e862eb0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_70 .net/s v0xc4f351540 70, 31 0, o0xc4e862eb0; 0 drivers
+o0xc4e862ee0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_71 .net/s v0xc4f351540 71, 31 0, o0xc4e862ee0; 0 drivers
+o0xc4e862f10 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_72 .net/s v0xc4f351540 72, 31 0, o0xc4e862f10; 0 drivers
+o0xc4e862f40 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_73 .net/s v0xc4f351540 73, 31 0, o0xc4e862f40; 0 drivers
+o0xc4e862f70 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_74 .net/s v0xc4f351540 74, 31 0, o0xc4e862f70; 0 drivers
+o0xc4e862fa0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_75 .net/s v0xc4f351540 75, 31 0, o0xc4e862fa0; 0 drivers
+o0xc4e862fd0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_76 .net/s v0xc4f351540 76, 31 0, o0xc4e862fd0; 0 drivers
+o0xc4e863000 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_77 .net/s v0xc4f351540 77, 31 0, o0xc4e863000; 0 drivers
+o0xc4e863030 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_78 .net/s v0xc4f351540 78, 31 0, o0xc4e863030; 0 drivers
+o0xc4e863060 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f351540_79 .net/s v0xc4f351540 79, 31 0, o0xc4e863060; 0 drivers
+v0xc4f3515e0_0 .net/s "w_bus", 127 0, L_0xc4f39fca0;  alias, 1 drivers
+v0xc4f351680_0 .net/s "x_bus", 127 0, L_0xc4f39fc00;  alias, 1 drivers
+L_0xc4f39fde0 .part L_0xc4f39fc00, 0, 8;
+L_0xc4f39fe80 .part L_0xc4f39fca0, 0, 8;
+L_0xc4f3b0000 .part L_0xc4f39fc00, 8, 8;
+L_0xc4f3b00a0 .part L_0xc4f39fca0, 8, 8;
+L_0xc4f3b01e0 .part L_0xc4f39fc00, 16, 8;
+L_0xc4f3b0280 .part L_0xc4f39fca0, 16, 8;
+L_0xc4f3b03c0 .part L_0xc4f39fc00, 24, 8;
+L_0xc4f3b0460 .part L_0xc4f39fca0, 24, 8;
+L_0xc4f3b05a0 .part L_0xc4f39fc00, 32, 8;
+L_0xc4f3b0640 .part L_0xc4f39fca0, 32, 8;
+L_0xc4f3b0780 .part L_0xc4f39fc00, 40, 8;
+L_0xc4f3b0820 .part L_0xc4f39fca0, 40, 8;
+L_0xc4f3b0960 .part L_0xc4f39fc00, 48, 8;
+L_0xc4f3b0a00 .part L_0xc4f39fca0, 48, 8;
+L_0xc4f3b0b40 .part L_0xc4f39fc00, 56, 8;
+L_0xc4f3b0be0 .part L_0xc4f39fca0, 56, 8;
+L_0xc4f3b0d20 .part L_0xc4f39fc00, 64, 8;
+L_0xc4f3b0dc0 .part L_0xc4f39fca0, 64, 8;
+L_0xc4f3b0f00 .part L_0xc4f39fc00, 72, 8;
+L_0xc4f3b0fa0 .part L_0xc4f39fca0, 72, 8;
+L_0xc4f3b10e0 .part L_0xc4f39fc00, 80, 8;
+L_0xc4f3b1180 .part L_0xc4f39fca0, 80, 8;
+L_0xc4f3b12c0 .part L_0xc4f39fc00, 88, 8;
+L_0xc4f3b1360 .part L_0xc4f39fca0, 88, 8;
+L_0xc4f3b14a0 .part L_0xc4f39fc00, 96, 8;
+L_0xc4f3b1540 .part L_0xc4f39fca0, 96, 8;
+L_0xc4f3b1680 .part L_0xc4f39fc00, 104, 8;
+L_0xc4f3b1720 .part L_0xc4f39fca0, 104, 8;
+L_0xc4f3b1860 .part L_0xc4f39fc00, 112, 8;
+L_0xc4f3b1900 .part L_0xc4f39fca0, 112, 8;
+L_0xc4f3b1a40 .part L_0xc4f39fc00, 120, 8;
+L_0xc4f3b1ae0 .part L_0xc4f39fca0, 120, 8;
+L_0xc4f3b5360 .arith/sum 32, v0xc4f351fe0_0, L_0xc4f3b52c0;
+S_0xc4f348f00 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334b00 .param/l "i" 1 5 20, +C4<00>;
+S_0xc4f349080 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f348f00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f340300 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f340340 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f340380 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f346ee0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3ae1c0;  1 drivers
+v0xc4f346f80_0 .net/s *"_ivl_2", 15 0, L_0xc4f3ae260;  1 drivers
+v0xc4f347020_0 .net *"_ivl_7", 0 0, L_0xc4f39fd40;  1 drivers
+v0xc4f3470c0_0 .net *"_ivl_9", 15 0, L_0xc4ef52f80;  1 drivers
+L_0xc4e87ada0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f347160_0 .net/s "acc_in", 31 0, L_0xc4e87ada0;  1 drivers
+v0xc4f347200_0 .net/s "acc_out", 31 0, L_0xc4f3ae3a0;  alias, 1 drivers
+v0xc4f3472a0_0 .net/s "product", 15 0, L_0xc4ef52ee0;  1 drivers
+v0xc4f347340_0 .net/s "product_ext", 31 0, L_0xc4f3ae300;  1 drivers
+v0xc4f3473e0_0 .net/s "w", 7 0, L_0xc4f39fe80;  1 drivers
+v0xc4f347480_0 .net/s "x", 7 0, L_0xc4f39fde0;  1 drivers
+L_0xc4f3ae1c0 .extend/s 16, L_0xc4f39fde0;
+L_0xc4f3ae260 .extend/s 16, L_0xc4f39fe80;
+L_0xc4ef52ee0 .arith/mult 16, L_0xc4f3ae1c0, L_0xc4f3ae260;
+L_0xc4f39fd40 .part L_0xc4ef52ee0, 15, 1;
+L_0xc4ef52f80 .repeat 16, 16, L_0xc4f39fd40;
+L_0xc4f3ae300 .concat [ 16 16 0 0], L_0xc4ef52ee0, L_0xc4ef52f80;
+L_0xc4f3ae3a0 .arith/sum 32, L_0xc4e87ada0, L_0xc4f3ae300;
+S_0xc4f349200 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334b40 .param/l "i" 1 5 20, +C4<01>;
+S_0xc4f349380 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f349200;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f3403c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f340400 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f340440 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f347520_0 .net/s *"_ivl_0", 15 0, L_0xc4f3ae440;  1 drivers
+v0xc4f3475c0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3ae4e0;  1 drivers
+v0xc4f347660_0 .net *"_ivl_7", 0 0, L_0xc4f39ff20;  1 drivers
+v0xc4f347700_0 .net *"_ivl_9", 15 0, L_0xc4ef530c0;  1 drivers
+L_0xc4e87ade8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3477a0_0 .net/s "acc_in", 31 0, L_0xc4e87ade8;  1 drivers
+v0xc4f347840_0 .net/s "acc_out", 31 0, L_0xc4f3ae620;  alias, 1 drivers
+v0xc4f3478e0_0 .net/s "product", 15 0, L_0xc4ef53020;  1 drivers
+v0xc4f347980_0 .net/s "product_ext", 31 0, L_0xc4f3ae580;  1 drivers
+v0xc4f347a20_0 .net/s "w", 7 0, L_0xc4f3b00a0;  1 drivers
+v0xc4f347ac0_0 .net/s "x", 7 0, L_0xc4f3b0000;  1 drivers
+L_0xc4f3ae440 .extend/s 16, L_0xc4f3b0000;
+L_0xc4f3ae4e0 .extend/s 16, L_0xc4f3b00a0;
+L_0xc4ef53020 .arith/mult 16, L_0xc4f3ae440, L_0xc4f3ae4e0;
+L_0xc4f39ff20 .part L_0xc4ef53020, 15, 1;
+L_0xc4ef530c0 .repeat 16, 16, L_0xc4f39ff20;
+L_0xc4f3ae580 .concat [ 16 16 0 0], L_0xc4ef53020, L_0xc4ef530c0;
+L_0xc4f3ae620 .arith/sum 32, L_0xc4e87ade8, L_0xc4f3ae580;
+S_0xc4f349500 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334b80 .param/l "i" 1 5 20, +C4<010>;
+S_0xc4f349680 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f349500;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f340480 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f3404c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f340500 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f347b60_0 .net/s *"_ivl_0", 15 0, L_0xc4f3ae6c0;  1 drivers
+v0xc4f347c00_0 .net/s *"_ivl_2", 15 0, L_0xc4f3ae760;  1 drivers
+v0xc4f347ca0_0 .net *"_ivl_7", 0 0, L_0xc4f3b0140;  1 drivers
+v0xc4f347d40_0 .net *"_ivl_9", 15 0, L_0xc4ef53200;  1 drivers
+L_0xc4e87ae30 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f347de0_0 .net/s "acc_in", 31 0, L_0xc4e87ae30;  1 drivers
+v0xc4f347e80_0 .net/s "acc_out", 31 0, L_0xc4f3ae8a0;  alias, 1 drivers
+v0xc4f347f20_0 .net/s "product", 15 0, L_0xc4ef53160;  1 drivers
+v0xc4f34c000_0 .net/s "product_ext", 31 0, L_0xc4f3ae800;  1 drivers
+v0xc4f34c0a0_0 .net/s "w", 7 0, L_0xc4f3b0280;  1 drivers
+v0xc4f34c140_0 .net/s "x", 7 0, L_0xc4f3b01e0;  1 drivers
+L_0xc4f3ae6c0 .extend/s 16, L_0xc4f3b01e0;
+L_0xc4f3ae760 .extend/s 16, L_0xc4f3b0280;
+L_0xc4ef53160 .arith/mult 16, L_0xc4f3ae6c0, L_0xc4f3ae760;
+L_0xc4f3b0140 .part L_0xc4ef53160, 15, 1;
+L_0xc4ef53200 .repeat 16, 16, L_0xc4f3b0140;
+L_0xc4f3ae800 .concat [ 16 16 0 0], L_0xc4ef53160, L_0xc4ef53200;
+L_0xc4f3ae8a0 .arith/sum 32, L_0xc4e87ae30, L_0xc4f3ae800;
+S_0xc4f349800 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334bc0 .param/l "i" 1 5 20, +C4<011>;
+S_0xc4f349980 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f349800;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f340540 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f340580 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f3405c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f34c1e0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3ae940;  1 drivers
+v0xc4f34c280_0 .net/s *"_ivl_2", 15 0, L_0xc4f3ae9e0;  1 drivers
+v0xc4f34c320_0 .net *"_ivl_7", 0 0, L_0xc4f3b0320;  1 drivers
+v0xc4f34c3c0_0 .net *"_ivl_9", 15 0, L_0xc4ef53340;  1 drivers
+L_0xc4e87ae78 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f34c460_0 .net/s "acc_in", 31 0, L_0xc4e87ae78;  1 drivers
+v0xc4f34c500_0 .net/s "acc_out", 31 0, L_0xc4f3aeb20;  alias, 1 drivers
+v0xc4f34c5a0_0 .net/s "product", 15 0, L_0xc4ef532a0;  1 drivers
+v0xc4f34c640_0 .net/s "product_ext", 31 0, L_0xc4f3aea80;  1 drivers
+v0xc4f34c6e0_0 .net/s "w", 7 0, L_0xc4f3b0460;  1 drivers
+v0xc4f34c780_0 .net/s "x", 7 0, L_0xc4f3b03c0;  1 drivers
+L_0xc4f3ae940 .extend/s 16, L_0xc4f3b03c0;
+L_0xc4f3ae9e0 .extend/s 16, L_0xc4f3b0460;
+L_0xc4ef532a0 .arith/mult 16, L_0xc4f3ae940, L_0xc4f3ae9e0;
+L_0xc4f3b0320 .part L_0xc4ef532a0, 15, 1;
+L_0xc4ef53340 .repeat 16, 16, L_0xc4f3b0320;
+L_0xc4f3aea80 .concat [ 16 16 0 0], L_0xc4ef532a0, L_0xc4ef53340;
+L_0xc4f3aeb20 .arith/sum 32, L_0xc4e87ae78, L_0xc4f3aea80;
+S_0xc4f349b00 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334c40 .param/l "i" 1 5 20, +C4<0100>;
+S_0xc4f349c80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f349b00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f340600 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f340640 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f340680 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f34c820_0 .net/s *"_ivl_0", 15 0, L_0xc4f3aebc0;  1 drivers
+v0xc4f34c8c0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3aec60;  1 drivers
+v0xc4f34c960_0 .net *"_ivl_7", 0 0, L_0xc4f3b0500;  1 drivers
+v0xc4f34ca00_0 .net *"_ivl_9", 15 0, L_0xc4ef53480;  1 drivers
+L_0xc4e87aec0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f34caa0_0 .net/s "acc_in", 31 0, L_0xc4e87aec0;  1 drivers
+v0xc4f34cb40_0 .net/s "acc_out", 31 0, L_0xc4f3aeda0;  alias, 1 drivers
+v0xc4f34cbe0_0 .net/s "product", 15 0, L_0xc4ef533e0;  1 drivers
+v0xc4f34cc80_0 .net/s "product_ext", 31 0, L_0xc4f3aed00;  1 drivers
+v0xc4f34cd20_0 .net/s "w", 7 0, L_0xc4f3b0640;  1 drivers
+v0xc4f34cdc0_0 .net/s "x", 7 0, L_0xc4f3b05a0;  1 drivers
+L_0xc4f3aebc0 .extend/s 16, L_0xc4f3b05a0;
+L_0xc4f3aec60 .extend/s 16, L_0xc4f3b0640;
+L_0xc4ef533e0 .arith/mult 16, L_0xc4f3aebc0, L_0xc4f3aec60;
+L_0xc4f3b0500 .part L_0xc4ef533e0, 15, 1;
+L_0xc4ef53480 .repeat 16, 16, L_0xc4f3b0500;
+L_0xc4f3aed00 .concat [ 16 16 0 0], L_0xc4ef533e0, L_0xc4ef53480;
+L_0xc4f3aeda0 .arith/sum 32, L_0xc4e87aec0, L_0xc4f3aed00;
+S_0xc4f349e00 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334c80 .param/l "i" 1 5 20, +C4<0101>;
+S_0xc4f349f80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f349e00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f3406c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f340700 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f340740 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f34ce60_0 .net/s *"_ivl_0", 15 0, L_0xc4f3aee40;  1 drivers
+v0xc4f34cf00_0 .net/s *"_ivl_2", 15 0, L_0xc4f3aeee0;  1 drivers
+v0xc4f34cfa0_0 .net *"_ivl_7", 0 0, L_0xc4f3b06e0;  1 drivers
+v0xc4f34d040_0 .net *"_ivl_9", 15 0, L_0xc4ef535c0;  1 drivers
+L_0xc4e87af08 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f34d0e0_0 .net/s "acc_in", 31 0, L_0xc4e87af08;  1 drivers
+v0xc4f34d180_0 .net/s "acc_out", 31 0, L_0xc4f3af020;  alias, 1 drivers
+v0xc4f34d220_0 .net/s "product", 15 0, L_0xc4ef53520;  1 drivers
+v0xc4f34d2c0_0 .net/s "product_ext", 31 0, L_0xc4f3aef80;  1 drivers
+v0xc4f34d360_0 .net/s "w", 7 0, L_0xc4f3b0820;  1 drivers
+v0xc4f34d400_0 .net/s "x", 7 0, L_0xc4f3b0780;  1 drivers
+L_0xc4f3aee40 .extend/s 16, L_0xc4f3b0780;
+L_0xc4f3aeee0 .extend/s 16, L_0xc4f3b0820;
+L_0xc4ef53520 .arith/mult 16, L_0xc4f3aee40, L_0xc4f3aeee0;
+L_0xc4f3b06e0 .part L_0xc4ef53520, 15, 1;
+L_0xc4ef535c0 .repeat 16, 16, L_0xc4f3b06e0;
+L_0xc4f3aef80 .concat [ 16 16 0 0], L_0xc4ef53520, L_0xc4ef535c0;
+L_0xc4f3af020 .arith/sum 32, L_0xc4e87af08, L_0xc4f3aef80;
+S_0xc4f34a100 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334cc0 .param/l "i" 1 5 20, +C4<0110>;
+S_0xc4f34a280 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f34a100;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f340780 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f3407c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f340800 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f34d4a0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3af0c0;  1 drivers
+v0xc4f34d540_0 .net/s *"_ivl_2", 15 0, L_0xc4f3af160;  1 drivers
+v0xc4f34d5e0_0 .net *"_ivl_7", 0 0, L_0xc4f3b08c0;  1 drivers
+v0xc4f34d680_0 .net *"_ivl_9", 15 0, L_0xc4ef53700;  1 drivers
+L_0xc4e87af50 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f34d720_0 .net/s "acc_in", 31 0, L_0xc4e87af50;  1 drivers
+v0xc4f34d7c0_0 .net/s "acc_out", 31 0, L_0xc4f3af2a0;  alias, 1 drivers
+v0xc4f34d860_0 .net/s "product", 15 0, L_0xc4ef53660;  1 drivers
+v0xc4f34d900_0 .net/s "product_ext", 31 0, L_0xc4f3af200;  1 drivers
+v0xc4f34d9a0_0 .net/s "w", 7 0, L_0xc4f3b0a00;  1 drivers
+v0xc4f34da40_0 .net/s "x", 7 0, L_0xc4f3b0960;  1 drivers
+L_0xc4f3af0c0 .extend/s 16, L_0xc4f3b0960;
+L_0xc4f3af160 .extend/s 16, L_0xc4f3b0a00;
+L_0xc4ef53660 .arith/mult 16, L_0xc4f3af0c0, L_0xc4f3af160;
+L_0xc4f3b08c0 .part L_0xc4ef53660, 15, 1;
+L_0xc4ef53700 .repeat 16, 16, L_0xc4f3b08c0;
+L_0xc4f3af200 .concat [ 16 16 0 0], L_0xc4ef53660, L_0xc4ef53700;
+L_0xc4f3af2a0 .arith/sum 32, L_0xc4e87af50, L_0xc4f3af200;
+S_0xc4f34a400 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334d00 .param/l "i" 1 5 20, +C4<0111>;
+S_0xc4f34a580 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f34a400;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f340840 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f340880 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f3408c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f34dae0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3af340;  1 drivers
+v0xc4f34db80_0 .net/s *"_ivl_2", 15 0, L_0xc4f3af3e0;  1 drivers
+v0xc4f34dc20_0 .net *"_ivl_7", 0 0, L_0xc4f3b0aa0;  1 drivers
+v0xc4f34dcc0_0 .net *"_ivl_9", 15 0, L_0xc4ef53840;  1 drivers
+L_0xc4e87af98 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f34dd60_0 .net/s "acc_in", 31 0, L_0xc4e87af98;  1 drivers
+v0xc4f34de00_0 .net/s "acc_out", 31 0, L_0xc4f3af520;  alias, 1 drivers
+v0xc4f34dea0_0 .net/s "product", 15 0, L_0xc4ef537a0;  1 drivers
+v0xc4f34df40_0 .net/s "product_ext", 31 0, L_0xc4f3af480;  1 drivers
+v0xc4f34dfe0_0 .net/s "w", 7 0, L_0xc4f3b0be0;  1 drivers
+v0xc4f34e080_0 .net/s "x", 7 0, L_0xc4f3b0b40;  1 drivers
+L_0xc4f3af340 .extend/s 16, L_0xc4f3b0b40;
+L_0xc4f3af3e0 .extend/s 16, L_0xc4f3b0be0;
+L_0xc4ef537a0 .arith/mult 16, L_0xc4f3af340, L_0xc4f3af3e0;
+L_0xc4f3b0aa0 .part L_0xc4ef537a0, 15, 1;
+L_0xc4ef53840 .repeat 16, 16, L_0xc4f3b0aa0;
+L_0xc4f3af480 .concat [ 16 16 0 0], L_0xc4ef537a0, L_0xc4ef53840;
+L_0xc4f3af520 .arith/sum 32, L_0xc4e87af98, L_0xc4f3af480;
+S_0xc4f34a700 .scope generate, "GEN_MAC[8]" "GEN_MAC[8]" 5 20, 5 20 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334c00 .param/l "i" 1 5 20, +C4<01000>;
+S_0xc4f34a880 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f34a700;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f340900 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f340940 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f340980 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f34e120_0 .net/s *"_ivl_0", 15 0, L_0xc4f3af5c0;  1 drivers
+v0xc4f34e1c0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3af660;  1 drivers
+v0xc4f34e260_0 .net *"_ivl_7", 0 0, L_0xc4f3b0c80;  1 drivers
+v0xc4f34e300_0 .net *"_ivl_9", 15 0, L_0xc4ef53980;  1 drivers
+L_0xc4e87afe0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f34e3a0_0 .net/s "acc_in", 31 0, L_0xc4e87afe0;  1 drivers
+v0xc4f34e440_0 .net/s "acc_out", 31 0, L_0xc4f3af7a0;  alias, 1 drivers
+v0xc4f34e4e0_0 .net/s "product", 15 0, L_0xc4ef538e0;  1 drivers
+v0xc4f34e580_0 .net/s "product_ext", 31 0, L_0xc4f3af700;  1 drivers
+v0xc4f34e620_0 .net/s "w", 7 0, L_0xc4f3b0dc0;  1 drivers
+v0xc4f34e6c0_0 .net/s "x", 7 0, L_0xc4f3b0d20;  1 drivers
+L_0xc4f3af5c0 .extend/s 16, L_0xc4f3b0d20;
+L_0xc4f3af660 .extend/s 16, L_0xc4f3b0dc0;
+L_0xc4ef538e0 .arith/mult 16, L_0xc4f3af5c0, L_0xc4f3af660;
+L_0xc4f3b0c80 .part L_0xc4ef538e0, 15, 1;
+L_0xc4ef53980 .repeat 16, 16, L_0xc4f3b0c80;
+L_0xc4f3af700 .concat [ 16 16 0 0], L_0xc4ef538e0, L_0xc4ef53980;
+L_0xc4f3af7a0 .arith/sum 32, L_0xc4e87afe0, L_0xc4f3af700;
+S_0xc4f34aa00 .scope generate, "GEN_MAC[9]" "GEN_MAC[9]" 5 20, 5 20 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334d40 .param/l "i" 1 5 20, +C4<01001>;
+S_0xc4f34ab80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f34aa00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f3409c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f340a00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f340a40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f34e760_0 .net/s *"_ivl_0", 15 0, L_0xc4f3af840;  1 drivers
+v0xc4f34e800_0 .net/s *"_ivl_2", 15 0, L_0xc4f3af8e0;  1 drivers
+v0xc4f34e8a0_0 .net *"_ivl_7", 0 0, L_0xc4f3b0e60;  1 drivers
+v0xc4f34e940_0 .net *"_ivl_9", 15 0, L_0xc4ef53b60;  1 drivers
+L_0xc4e87b028 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f34e9e0_0 .net/s "acc_in", 31 0, L_0xc4e87b028;  1 drivers
+v0xc4f34ea80_0 .net/s "acc_out", 31 0, L_0xc4f3afa20;  alias, 1 drivers
+v0xc4f34eb20_0 .net/s "product", 15 0, L_0xc4ef53ac0;  1 drivers
+v0xc4f34ebc0_0 .net/s "product_ext", 31 0, L_0xc4f3af980;  1 drivers
+v0xc4f34ec60_0 .net/s "w", 7 0, L_0xc4f3b0fa0;  1 drivers
+v0xc4f34ed00_0 .net/s "x", 7 0, L_0xc4f3b0f00;  1 drivers
+L_0xc4f3af840 .extend/s 16, L_0xc4f3b0f00;
+L_0xc4f3af8e0 .extend/s 16, L_0xc4f3b0fa0;
+L_0xc4ef53ac0 .arith/mult 16, L_0xc4f3af840, L_0xc4f3af8e0;
+L_0xc4f3b0e60 .part L_0xc4ef53ac0, 15, 1;
+L_0xc4ef53b60 .repeat 16, 16, L_0xc4f3b0e60;
+L_0xc4f3af980 .concat [ 16 16 0 0], L_0xc4ef53ac0, L_0xc4ef53b60;
+L_0xc4f3afa20 .arith/sum 32, L_0xc4e87b028, L_0xc4f3af980;
+S_0xc4f34ad00 .scope generate, "GEN_MAC[10]" "GEN_MAC[10]" 5 20, 5 20 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334d80 .param/l "i" 1 5 20, +C4<01010>;
+S_0xc4f34ae80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f34ad00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f340a80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f340ac0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f340b00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f34eda0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3afac0;  1 drivers
+v0xc4f34ee40_0 .net/s *"_ivl_2", 15 0, L_0xc4f3afb60;  1 drivers
+v0xc4f34eee0_0 .net *"_ivl_7", 0 0, L_0xc4f3b1040;  1 drivers
+v0xc4f34ef80_0 .net *"_ivl_9", 15 0, L_0xc4ef53ca0;  1 drivers
+L_0xc4e87b070 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f34f020_0 .net/s "acc_in", 31 0, L_0xc4e87b070;  1 drivers
+v0xc4f34f0c0_0 .net/s "acc_out", 31 0, L_0xc4f3afca0;  alias, 1 drivers
+v0xc4f34f160_0 .net/s "product", 15 0, L_0xc4ef53c00;  1 drivers
+v0xc4f34f200_0 .net/s "product_ext", 31 0, L_0xc4f3afc00;  1 drivers
+v0xc4f34f2a0_0 .net/s "w", 7 0, L_0xc4f3b1180;  1 drivers
+v0xc4f34f340_0 .net/s "x", 7 0, L_0xc4f3b10e0;  1 drivers
+L_0xc4f3afac0 .extend/s 16, L_0xc4f3b10e0;
+L_0xc4f3afb60 .extend/s 16, L_0xc4f3b1180;
+L_0xc4ef53c00 .arith/mult 16, L_0xc4f3afac0, L_0xc4f3afb60;
+L_0xc4f3b1040 .part L_0xc4ef53c00, 15, 1;
+L_0xc4ef53ca0 .repeat 16, 16, L_0xc4f3b1040;
+L_0xc4f3afc00 .concat [ 16 16 0 0], L_0xc4ef53c00, L_0xc4ef53ca0;
+L_0xc4f3afca0 .arith/sum 32, L_0xc4e87b070, L_0xc4f3afc00;
+S_0xc4f34b000 .scope generate, "GEN_MAC[11]" "GEN_MAC[11]" 5 20, 5 20 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334dc0 .param/l "i" 1 5 20, +C4<01011>;
+S_0xc4f34b180 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f34b000;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f340b40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f340b80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f340bc0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f34f3e0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3afd40;  1 drivers
+v0xc4f34f480_0 .net/s *"_ivl_2", 15 0, L_0xc4f3afde0;  1 drivers
+v0xc4f34f520_0 .net *"_ivl_7", 0 0, L_0xc4f3b1220;  1 drivers
+v0xc4f34f5c0_0 .net *"_ivl_9", 15 0, L_0xc4ef53d40;  1 drivers
+L_0xc4e87b0b8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f34f660_0 .net/s "acc_in", 31 0, L_0xc4e87b0b8;  1 drivers
+v0xc4f34f700_0 .net/s "acc_out", 31 0, L_0xc4f3aff20;  alias, 1 drivers
+v0xc4f34f7a0_0 .net/s "product", 15 0, L_0xc4ef53a20;  1 drivers
+v0xc4f34f840_0 .net/s "product_ext", 31 0, L_0xc4f3afe80;  1 drivers
+v0xc4f34f8e0_0 .net/s "w", 7 0, L_0xc4f3b1360;  1 drivers
+v0xc4f34f980_0 .net/s "x", 7 0, L_0xc4f3b12c0;  1 drivers
+L_0xc4f3afd40 .extend/s 16, L_0xc4f3b12c0;
+L_0xc4f3afde0 .extend/s 16, L_0xc4f3b1360;
+L_0xc4ef53a20 .arith/mult 16, L_0xc4f3afd40, L_0xc4f3afde0;
+L_0xc4f3b1220 .part L_0xc4ef53a20, 15, 1;
+L_0xc4ef53d40 .repeat 16, 16, L_0xc4f3b1220;
+L_0xc4f3afe80 .concat [ 16 16 0 0], L_0xc4ef53a20, L_0xc4ef53d40;
+L_0xc4f3aff20 .arith/sum 32, L_0xc4e87b0b8, L_0xc4f3afe80;
+S_0xc4f34b300 .scope generate, "GEN_MAC[12]" "GEN_MAC[12]" 5 20, 5 20 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334e00 .param/l "i" 1 5 20, +C4<01100>;
+S_0xc4f34b480 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f34b300;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f340c00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f340c40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f340c80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f34fa20_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b4000;  1 drivers
+v0xc4f34fac0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b40a0;  1 drivers
+v0xc4f34fb60_0 .net *"_ivl_7", 0 0, L_0xc4f3b1400;  1 drivers
+v0xc4f34fc00_0 .net *"_ivl_9", 15 0, L_0xc4ef53e80;  1 drivers
+L_0xc4e87b100 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f34fca0_0 .net/s "acc_in", 31 0, L_0xc4e87b100;  1 drivers
+v0xc4f34fd40_0 .net/s "acc_out", 31 0, L_0xc4f3b41e0;  alias, 1 drivers
+v0xc4f34fde0_0 .net/s "product", 15 0, L_0xc4ef53de0;  1 drivers
+v0xc4f34fe80_0 .net/s "product_ext", 31 0, L_0xc4f3b4140;  1 drivers
+v0xc4f34ff20_0 .net/s "w", 7 0, L_0xc4f3b1540;  1 drivers
+v0xc4f350000_0 .net/s "x", 7 0, L_0xc4f3b14a0;  1 drivers
+L_0xc4f3b4000 .extend/s 16, L_0xc4f3b14a0;
+L_0xc4f3b40a0 .extend/s 16, L_0xc4f3b1540;
+L_0xc4ef53de0 .arith/mult 16, L_0xc4f3b4000, L_0xc4f3b40a0;
+L_0xc4f3b1400 .part L_0xc4ef53de0, 15, 1;
+L_0xc4ef53e80 .repeat 16, 16, L_0xc4f3b1400;
+L_0xc4f3b4140 .concat [ 16 16 0 0], L_0xc4ef53de0, L_0xc4ef53e80;
+L_0xc4f3b41e0 .arith/sum 32, L_0xc4e87b100, L_0xc4f3b4140;
+S_0xc4f34b600 .scope generate, "GEN_MAC[13]" "GEN_MAC[13]" 5 20, 5 20 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334e40 .param/l "i" 1 5 20, +C4<01101>;
+S_0xc4f34b780 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f34b600;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f340cc0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f340d00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f340d40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f3500a0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b4280;  1 drivers
+v0xc4f350140_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b4320;  1 drivers
+v0xc4f3501e0_0 .net *"_ivl_7", 0 0, L_0xc4f3b15e0;  1 drivers
+v0xc4f350280_0 .net *"_ivl_9", 15 0, L_0xc4ef5c000;  1 drivers
+L_0xc4e87b148 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f350320_0 .net/s "acc_in", 31 0, L_0xc4e87b148;  1 drivers
+v0xc4f3503c0_0 .net/s "acc_out", 31 0, L_0xc4f3b4460;  alias, 1 drivers
+v0xc4f350460_0 .net/s "product", 15 0, L_0xc4ef53f20;  1 drivers
+v0xc4f350500_0 .net/s "product_ext", 31 0, L_0xc4f3b43c0;  1 drivers
+v0xc4f3505a0_0 .net/s "w", 7 0, L_0xc4f3b1720;  1 drivers
+v0xc4f350640_0 .net/s "x", 7 0, L_0xc4f3b1680;  1 drivers
+L_0xc4f3b4280 .extend/s 16, L_0xc4f3b1680;
+L_0xc4f3b4320 .extend/s 16, L_0xc4f3b1720;
+L_0xc4ef53f20 .arith/mult 16, L_0xc4f3b4280, L_0xc4f3b4320;
+L_0xc4f3b15e0 .part L_0xc4ef53f20, 15, 1;
+L_0xc4ef5c000 .repeat 16, 16, L_0xc4f3b15e0;
+L_0xc4f3b43c0 .concat [ 16 16 0 0], L_0xc4ef53f20, L_0xc4ef5c000;
+L_0xc4f3b4460 .arith/sum 32, L_0xc4e87b148, L_0xc4f3b43c0;
+S_0xc4f34b900 .scope generate, "GEN_MAC[14]" "GEN_MAC[14]" 5 20, 5 20 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334e80 .param/l "i" 1 5 20, +C4<01110>;
+S_0xc4f34ba80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f34b900;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f340d80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f340dc0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f340e00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f3506e0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b4500;  1 drivers
+v0xc4f350780_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b45a0;  1 drivers
+v0xc4f350820_0 .net *"_ivl_7", 0 0, L_0xc4f3b17c0;  1 drivers
+v0xc4f3508c0_0 .net *"_ivl_9", 15 0, L_0xc4ef5c140;  1 drivers
+L_0xc4e87b190 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f350960_0 .net/s "acc_in", 31 0, L_0xc4e87b190;  1 drivers
+v0xc4f350a00_0 .net/s "acc_out", 31 0, L_0xc4f3b46e0;  alias, 1 drivers
+v0xc4f350aa0_0 .net/s "product", 15 0, L_0xc4ef5c0a0;  1 drivers
+v0xc4f350b40_0 .net/s "product_ext", 31 0, L_0xc4f3b4640;  1 drivers
+v0xc4f350be0_0 .net/s "w", 7 0, L_0xc4f3b1900;  1 drivers
+v0xc4f350c80_0 .net/s "x", 7 0, L_0xc4f3b1860;  1 drivers
+L_0xc4f3b4500 .extend/s 16, L_0xc4f3b1860;
+L_0xc4f3b45a0 .extend/s 16, L_0xc4f3b1900;
+L_0xc4ef5c0a0 .arith/mult 16, L_0xc4f3b4500, L_0xc4f3b45a0;
+L_0xc4f3b17c0 .part L_0xc4ef5c0a0, 15, 1;
+L_0xc4ef5c140 .repeat 16, 16, L_0xc4f3b17c0;
+L_0xc4f3b4640 .concat [ 16 16 0 0], L_0xc4ef5c0a0, L_0xc4ef5c140;
+L_0xc4f3b46e0 .arith/sum 32, L_0xc4e87b190, L_0xc4f3b4640;
+S_0xc4f34bc00 .scope generate, "GEN_MAC[15]" "GEN_MAC[15]" 5 20, 5 20 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334ec0 .param/l "i" 1 5 20, +C4<01111>;
+S_0xc4f34bd80 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f34bc00;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f340e40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f340e80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f340ec0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f350d20_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b4780;  1 drivers
+v0xc4f350dc0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b4820;  1 drivers
+v0xc4f350e60_0 .net *"_ivl_7", 0 0, L_0xc4f3b19a0;  1 drivers
+v0xc4f350f00_0 .net *"_ivl_9", 15 0, L_0xc4ef5c280;  1 drivers
+L_0xc4e87b1d8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f350fa0_0 .net/s "acc_in", 31 0, L_0xc4e87b1d8;  1 drivers
+v0xc4f351040_0 .net/s "acc_out", 31 0, L_0xc4f3b4960;  alias, 1 drivers
+v0xc4f3510e0_0 .net/s "product", 15 0, L_0xc4ef5c1e0;  1 drivers
+v0xc4f351180_0 .net/s "product_ext", 31 0, L_0xc4f3b48c0;  1 drivers
+v0xc4f351220_0 .net/s "w", 7 0, L_0xc4f3b1ae0;  1 drivers
+v0xc4f3512c0_0 .net/s "x", 7 0, L_0xc4f3b1a40;  1 drivers
+L_0xc4f3b4780 .extend/s 16, L_0xc4f3b1a40;
+L_0xc4f3b4820 .extend/s 16, L_0xc4f3b1ae0;
+L_0xc4ef5c1e0 .arith/mult 16, L_0xc4f3b4780, L_0xc4f3b4820;
+L_0xc4f3b19a0 .part L_0xc4ef5c1e0, 15, 1;
+L_0xc4ef5c280 .repeat 16, 16, L_0xc4f3b19a0;
+L_0xc4f3b48c0 .concat [ 16 16 0 0], L_0xc4ef5c1e0, L_0xc4ef5c280;
+L_0xc4f3b4960 .arith/sum 32, L_0xc4e87b1d8, L_0xc4f3b48c0;
+S_0xc4f354000 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334f00 .param/l "i" 1 5 80, +C4<00>;
+L_0xc4f3a8700 .functor BUFZ 32, L_0xc4f3ae3a0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f354180 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334f40 .param/l "i" 1 5 80, +C4<01>;
+L_0xc4f3a8770 .functor BUFZ 32, L_0xc4f3ae620, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f354300 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334f80 .param/l "i" 1 5 80, +C4<010>;
+L_0xc4f3a87e0 .functor BUFZ 32, L_0xc4f3ae8a0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f354480 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f334fc0 .param/l "i" 1 5 80, +C4<011>;
+L_0xc4f3a8850 .functor BUFZ 32, L_0xc4f3aeb20, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f354600 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f335000 .param/l "i" 1 5 80, +C4<0100>;
+L_0xc4f3a88c0 .functor BUFZ 32, L_0xc4f3aeda0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f354780 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f335040 .param/l "i" 1 5 80, +C4<0101>;
+L_0xc4f3a8930 .functor BUFZ 32, L_0xc4f3af020, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f354900 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f335080 .param/l "i" 1 5 80, +C4<0110>;
+L_0xc4f3a89a0 .functor BUFZ 32, L_0xc4f3af2a0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f354a80 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f3350c0 .param/l "i" 1 5 80, +C4<0111>;
+L_0xc4f3a8a10 .functor BUFZ 32, L_0xc4f3af520, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f354c00 .scope generate, "GEN_TREE_INPUT[8]" "GEN_TREE_INPUT[8]" 5 80, 5 80 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f335100 .param/l "i" 1 5 80, +C4<01000>;
+L_0xc4f3a8a80 .functor BUFZ 32, L_0xc4f3af7a0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f354d80 .scope generate, "GEN_TREE_INPUT[9]" "GEN_TREE_INPUT[9]" 5 80, 5 80 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f335140 .param/l "i" 1 5 80, +C4<01001>;
+L_0xc4f3a8af0 .functor BUFZ 32, L_0xc4f3afa20, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f354f00 .scope generate, "GEN_TREE_INPUT[10]" "GEN_TREE_INPUT[10]" 5 80, 5 80 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f335180 .param/l "i" 1 5 80, +C4<01010>;
+L_0xc4f3a8b60 .functor BUFZ 32, L_0xc4f3afca0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f355080 .scope generate, "GEN_TREE_INPUT[11]" "GEN_TREE_INPUT[11]" 5 80, 5 80 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f3351c0 .param/l "i" 1 5 80, +C4<01011>;
+L_0xc4f3a8bd0 .functor BUFZ 32, L_0xc4f3aff20, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f355200 .scope generate, "GEN_TREE_INPUT[12]" "GEN_TREE_INPUT[12]" 5 80, 5 80 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f335200 .param/l "i" 1 5 80, +C4<01100>;
+L_0xc4f3a8c40 .functor BUFZ 32, L_0xc4f3b41e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f355380 .scope generate, "GEN_TREE_INPUT[13]" "GEN_TREE_INPUT[13]" 5 80, 5 80 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f335240 .param/l "i" 1 5 80, +C4<01101>;
+L_0xc4f3a8cb0 .functor BUFZ 32, L_0xc4f3b4460, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f355500 .scope generate, "GEN_TREE_INPUT[14]" "GEN_TREE_INPUT[14]" 5 80, 5 80 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f335280 .param/l "i" 1 5 80, +C4<01110>;
+L_0xc4f3a8d20 .functor BUFZ 32, L_0xc4f3b46e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f355680 .scope generate, "GEN_TREE_INPUT[15]" "GEN_TREE_INPUT[15]" 5 80, 5 80 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f3352c0 .param/l "i" 1 5 80, +C4<01111>;
+L_0xc4f3a8d90 .functor BUFZ 32, L_0xc4f3b4960, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f355800 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f335300 .param/l "level" 1 5 92, +C4<00>;
+S_0xc4f355980 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f355800;
+ .timescale 0 0;
+P_0xc4f335340 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3b4a00 .arith/sum 32, L_0xc4f3a8700, L_0xc4f3a8770;
+S_0xc4f355b00 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f355800;
+ .timescale 0 0;
+P_0xc4f335380 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3b4aa0 .arith/sum 32, L_0xc4f3a87e0, L_0xc4f3a8850;
+S_0xc4f355c80 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xc4f355800;
+ .timescale 0 0;
+P_0xc4f3353c0 .param/l "node" 1 5 94, +C4<010>;
+L_0xc4f3b4b40 .arith/sum 32, L_0xc4f3a88c0, L_0xc4f3a8930;
+S_0xc4f355e00 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xc4f355800;
+ .timescale 0 0;
+P_0xc4f335400 .param/l "node" 1 5 94, +C4<011>;
+L_0xc4f3b4be0 .arith/sum 32, L_0xc4f3a89a0, L_0xc4f3a8a10;
+S_0xc4f355f80 .scope generate, "GEN_TREE_NODE[4]" "GEN_TREE_NODE[4]" 5 94, 5 94 0, S_0xc4f355800;
+ .timescale 0 0;
+P_0xc4f335480 .param/l "node" 1 5 94, +C4<0100>;
+L_0xc4f3b4c80 .arith/sum 32, L_0xc4f3a8a80, L_0xc4f3a8af0;
+S_0xc4f356100 .scope generate, "GEN_TREE_NODE[5]" "GEN_TREE_NODE[5]" 5 94, 5 94 0, S_0xc4f355800;
+ .timescale 0 0;
+P_0xc4f3354c0 .param/l "node" 1 5 94, +C4<0101>;
+L_0xc4f3b4d20 .arith/sum 32, L_0xc4f3a8b60, L_0xc4f3a8bd0;
+S_0xc4f356280 .scope generate, "GEN_TREE_NODE[6]" "GEN_TREE_NODE[6]" 5 94, 5 94 0, S_0xc4f355800;
+ .timescale 0 0;
+P_0xc4f335500 .param/l "node" 1 5 94, +C4<0110>;
+L_0xc4f3b4dc0 .arith/sum 32, L_0xc4f3a8c40, L_0xc4f3a8cb0;
+S_0xc4f356400 .scope generate, "GEN_TREE_NODE[7]" "GEN_TREE_NODE[7]" 5 94, 5 94 0, S_0xc4f355800;
+ .timescale 0 0;
+P_0xc4f335540 .param/l "node" 1 5 94, +C4<0111>;
+L_0xc4f3b4e60 .arith/sum 32, L_0xc4f3a8d20, L_0xc4f3a8d90;
+S_0xc4f356580 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f335580 .param/l "level" 1 5 92, +C4<01>;
+S_0xc4f356700 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f356580;
+ .timescale 0 0;
+P_0xc4f3355c0 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3b4f00 .arith/sum 32, L_0xc4f3b4a00, L_0xc4f3b4aa0;
+S_0xc4f356880 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f356580;
+ .timescale 0 0;
+P_0xc4f335600 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3b4fa0 .arith/sum 32, L_0xc4f3b4b40, L_0xc4f3b4be0;
+S_0xc4f356a00 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xc4f356580;
+ .timescale 0 0;
+P_0xc4f335640 .param/l "node" 1 5 94, +C4<010>;
+L_0xc4f3b5040 .arith/sum 32, L_0xc4f3b4c80, L_0xc4f3b4d20;
+S_0xc4f356b80 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xc4f356580;
+ .timescale 0 0;
+P_0xc4f335680 .param/l "node" 1 5 94, +C4<011>;
+L_0xc4f3b50e0 .arith/sum 32, L_0xc4f3b4dc0, L_0xc4f3b4e60;
+S_0xc4f356d00 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f3356c0 .param/l "level" 1 5 92, +C4<010>;
+S_0xc4f356e80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f356d00;
+ .timescale 0 0;
+P_0xc4f335700 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3b5180 .arith/sum 32, L_0xc4f3b4f00, L_0xc4f3b4fa0;
+S_0xc4f357000 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f356d00;
+ .timescale 0 0;
+P_0xc4f335740 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3b5220 .arith/sum 32, L_0xc4f3b5040, L_0xc4f3b50e0;
+S_0xc4f357180 .scope generate, "GEN_TREE_LEVEL[3]" "GEN_TREE_LEVEL[3]" 5 92, 5 92 0, S_0xc4f348d80;
+ .timescale 0 0;
+P_0xc4f335780 .param/l "level" 1 5 92, +C4<011>;
+S_0xc4f357300 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f357180;
+ .timescale 0 0;
+P_0xc4f3357c0 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3b52c0 .arith/sum 32, L_0xc4f3b5180, L_0xc4f3b5220;
+S_0xc4f357480 .scope module, "u_d" "neuron_parallel" 12 141, 4 1 0, S_0x102d15030;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "start";
+    .port_info 3 /INPUT 512 "x_bus";
+    .port_info 4 /INPUT 512 "w_bus";
+    .port_info 5 /INPUT 8 "bias";
+    .port_info 6 /OUTPUT 8 "y";
+    .port_info 7 /OUTPUT 1 "busy";
+    .port_info 8 /OUTPUT 1 "done";
+P_0xc4ef2c300 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000100000>;
+P_0xc4ef2c340 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000001000>;
+P_0xc4ef2c380 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000000010>;
+P_0xc4ef2c3c0 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000001>;
+P_0xc4ef2c400 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000001000000>;
+P_0xc4ef2c440 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000100000>;
+v0xc4f373660_0 .net *"_ivl_0", 31 0, L_0xc4f3b5540;  1 drivers
+v0xc4f373700_0 .net *"_ivl_11", 31 0, L_0xc4ef5c460;  1 drivers
+v0xc4f3737a0_0 .net *"_ivl_14", 31 0, L_0xc4f3b55e0;  1 drivers
+L_0xc4e87b2f8 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f373840_0 .net *"_ivl_17", 30 0, L_0xc4e87b2f8;  1 drivers
+L_0xc4e87b340 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3738e0_0 .net/2u *"_ivl_18", 31 0, L_0xc4e87b340;  1 drivers
+v0xc4f373980_0 .net *"_ivl_21", 31 0, L_0xc4ef5c500;  1 drivers
+L_0xc4e87b388 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f373a20_0 .net/2u *"_ivl_22", 31 0, L_0xc4e87b388;  1 drivers
+v0xc4f373ac0_0 .net *"_ivl_25", 31 0, L_0xc4ef5c5a0;  1 drivers
+v0xc4f373b60_0 .net *"_ivl_29", 0 0, L_0xc4f3c19a0;  1 drivers
+L_0xc4e87b220 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f373c00_0 .net *"_ivl_3", 30 0, L_0xc4e87b220;  1 drivers
+v0xc4f373ca0_0 .net *"_ivl_31", 23 0, L_0xc4ef5ee40;  1 drivers
+L_0xc4e87b268 .functor BUFT 1, C4<00000000000000000000000000100000>, C4<0>, C4<0>, C4<0>;
+v0xc4f373d40_0 .net/2u *"_ivl_4", 31 0, L_0xc4e87b268;  1 drivers
+v0xc4f373de0_0 .net *"_ivl_7", 31 0, L_0xc4ef5c3c0;  1 drivers
+L_0xc4e87b2b0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f373e80_0 .net/2u *"_ivl_8", 31 0, L_0xc4e87b2b0;  1 drivers
+v0xc4f373f20_0 .var/s "acc", 31 0;
+v0xc4f380000_0 .net/s "acc_next", 31 0, L_0xc4f3bfa20;  1 drivers
+v0xc4f3800a0_0 .net/s "bias", 7 0, v0xc4f385400_0;  1 drivers
+v0xc4f380140_0 .net/s "bias_ext", 31 0, L_0xc4f3bfac0;  1 drivers
+v0xc4f3801e0_0 .var "busy", 0 0;
+v0xc4f380280_0 .net "clk", 0 0, v0xc4f385860_0;  alias, 1 drivers
+v0xc4f380320_0 .var "done", 0 0;
+v0xc4f3803c0_0 .net/s "final_acc", 31 0, L_0xc4f3bfb60;  1 drivers
+v0xc4f380460_0 .var "group_index", 0 0;
+v0xc4f380500_0 .net "rst", 0 0, v0xc4f385ea0_0;  alias, 1 drivers
+v0xc4f3805a0_0 .net "start", 0 0, v0xc4f386120_0;  1 drivers
+v0xc4f380640_0 .net/s "w_bus", 511 0, v0xc4f3864e0_0;  1 drivers
+v0xc4f3806e0_0 .net/s "w_group", 255 0, L_0xc4f3b1cc0;  1 drivers
+v0xc4f380780_0 .net/s "x_bus", 511 0, v0xc4f386800_0;  1 drivers
+v0xc4f380820_0 .net/s "x_group", 255 0, L_0xc4f3b1c20;  1 drivers
+v0xc4f3808c0_0 .var/s "y", 7 0;
+L_0xc4f3b5540 .concat [ 1 31 0 0], v0xc4f380460_0, L_0xc4e87b220;
+L_0xc4ef5c3c0 .arith/mult 32, L_0xc4f3b5540, L_0xc4e87b268;
+L_0xc4ef5c460 .arith/mult 32, L_0xc4ef5c3c0, L_0xc4e87b2b0;
+L_0xc4f3b1c20 .part/v v0xc4f386800_0, L_0xc4ef5c460, 256;
+L_0xc4f3b55e0 .concat [ 1 31 0 0], v0xc4f380460_0, L_0xc4e87b2f8;
+L_0xc4ef5c500 .arith/mult 32, L_0xc4f3b55e0, L_0xc4e87b340;
+L_0xc4ef5c5a0 .arith/mult 32, L_0xc4ef5c500, L_0xc4e87b388;
+L_0xc4f3b1cc0 .part/v v0xc4f3864e0_0, L_0xc4ef5c5a0, 256;
+L_0xc4f3c19a0 .part v0xc4f385400_0, 7, 1;
+L_0xc4ef5ee40 .repeat 24, 24, L_0xc4f3c19a0;
+L_0xc4f3bfac0 .concat [ 8 24 0 0], v0xc4f385400_0, L_0xc4ef5ee40;
+L_0xc4f3bfb60 .arith/sum 32, L_0xc4f3bfa20, L_0xc4f3bfac0;
+S_0xc4f357600 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xc4f357480;
+ .timescale 0 0;
+    .port_info 0 /INPUT 256 "x_bus";
+    .port_info 1 /INPUT 256 "w_bus";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4ef0e600 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000100000>;
+P_0xc4ef0e640 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000001000>;
+P_0xc4ef0e680 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000100000>;
+P_0xc4ef0e6c0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000101>;
+v0xc4f3732a0_0 .net/s "acc_in", 31 0, v0xc4f373f20_0;  1 drivers
+v0xc4f373340_0 .net/s "acc_out", 31 0, L_0xc4f3bfa20;  alias, 1 drivers
+v0xc4f3733e0 .array "products", 31 0;
+v0xc4f3733e0_0 .net/s v0xc4f3733e0 0, 31 0, L_0xc4f3b5860; 1 drivers
+v0xc4f3733e0_1 .net/s v0xc4f3733e0 1, 31 0, L_0xc4f3b5ae0; 1 drivers
+v0xc4f3733e0_2 .net/s v0xc4f3733e0 2, 31 0, L_0xc4f3b5d60; 1 drivers
+v0xc4f3733e0_3 .net/s v0xc4f3733e0 3, 31 0, L_0xc4f3b5fe0; 1 drivers
+v0xc4f3733e0_4 .net/s v0xc4f3733e0 4, 31 0, L_0xc4f3b6260; 1 drivers
+v0xc4f3733e0_5 .net/s v0xc4f3733e0 5, 31 0, L_0xc4f3b64e0; 1 drivers
+v0xc4f3733e0_6 .net/s v0xc4f3733e0 6, 31 0, L_0xc4f3b6760; 1 drivers
+v0xc4f3733e0_7 .net/s v0xc4f3733e0 7, 31 0, L_0xc4f3b69e0; 1 drivers
+v0xc4f3733e0_8 .net/s v0xc4f3733e0 8, 31 0, L_0xc4f3b6c60; 1 drivers
+v0xc4f3733e0_9 .net/s v0xc4f3733e0 9, 31 0, L_0xc4f3b6ee0; 1 drivers
+v0xc4f3733e0_10 .net/s v0xc4f3733e0 10, 31 0, L_0xc4f3b7160; 1 drivers
+v0xc4f3733e0_11 .net/s v0xc4f3733e0 11, 31 0, L_0xc4f3b73e0; 1 drivers
+v0xc4f3733e0_12 .net/s v0xc4f3733e0 12, 31 0, L_0xc4f3b7660; 1 drivers
+v0xc4f3733e0_13 .net/s v0xc4f3733e0 13, 31 0, L_0xc4f3b78e0; 1 drivers
+v0xc4f3733e0_14 .net/s v0xc4f3733e0 14, 31 0, L_0xc4f3b7b60; 1 drivers
+v0xc4f3733e0_15 .net/s v0xc4f3733e0 15, 31 0, L_0xc4f3b7de0; 1 drivers
+v0xc4f3733e0_16 .net/s v0xc4f3733e0 16, 31 0, L_0xc4f3bc0a0; 1 drivers
+v0xc4f3733e0_17 .net/s v0xc4f3733e0 17, 31 0, L_0xc4f3bc320; 1 drivers
+v0xc4f3733e0_18 .net/s v0xc4f3733e0 18, 31 0, L_0xc4f3bc5a0; 1 drivers
+v0xc4f3733e0_19 .net/s v0xc4f3733e0 19, 31 0, L_0xc4f3bc820; 1 drivers
+v0xc4f3733e0_20 .net/s v0xc4f3733e0 20, 31 0, L_0xc4f3bcaa0; 1 drivers
+v0xc4f3733e0_21 .net/s v0xc4f3733e0 21, 31 0, L_0xc4f3bcd20; 1 drivers
+v0xc4f3733e0_22 .net/s v0xc4f3733e0 22, 31 0, L_0xc4f3bcfa0; 1 drivers
+v0xc4f3733e0_23 .net/s v0xc4f3733e0 23, 31 0, L_0xc4f3bd220; 1 drivers
+v0xc4f3733e0_24 .net/s v0xc4f3733e0 24, 31 0, L_0xc4f3bd4a0; 1 drivers
+v0xc4f3733e0_25 .net/s v0xc4f3733e0 25, 31 0, L_0xc4f3bd720; 1 drivers
+v0xc4f3733e0_26 .net/s v0xc4f3733e0 26, 31 0, L_0xc4f3bd9a0; 1 drivers
+v0xc4f3733e0_27 .net/s v0xc4f3733e0 27, 31 0, L_0xc4f3bdc20; 1 drivers
+v0xc4f3733e0_28 .net/s v0xc4f3733e0 28, 31 0, L_0xc4f3bdea0; 1 drivers
+v0xc4f3733e0_29 .net/s v0xc4f3733e0 29, 31 0, L_0xc4f3be120; 1 drivers
+v0xc4f3733e0_30 .net/s v0xc4f3733e0 30, 31 0, L_0xc4f3be3a0; 1 drivers
+v0xc4f3733e0_31 .net/s v0xc4f3733e0 31, 31 0, L_0xc4f3be620; 1 drivers
+v0xc4f373480 .array "tree", 191 0;
+v0xc4f373480_0 .net/s v0xc4f373480 0, 31 0, L_0xc4f3a8e00; 1 drivers
+v0xc4f373480_1 .net/s v0xc4f373480 1, 31 0, L_0xc4f3a8e70; 1 drivers
+v0xc4f373480_2 .net/s v0xc4f373480 2, 31 0, L_0xc4f3a8ee0; 1 drivers
+v0xc4f373480_3 .net/s v0xc4f373480 3, 31 0, L_0xc4f3a8f50; 1 drivers
+v0xc4f373480_4 .net/s v0xc4f373480 4, 31 0, L_0xc4f3a8fc0; 1 drivers
+v0xc4f373480_5 .net/s v0xc4f373480 5, 31 0, L_0xc4f3a9030; 1 drivers
+v0xc4f373480_6 .net/s v0xc4f373480 6, 31 0, L_0xc4f3a90a0; 1 drivers
+v0xc4f373480_7 .net/s v0xc4f373480 7, 31 0, L_0xc4f3a9110; 1 drivers
+v0xc4f373480_8 .net/s v0xc4f373480 8, 31 0, L_0xc4f3a9180; 1 drivers
+v0xc4f373480_9 .net/s v0xc4f373480 9, 31 0, L_0xc4f3a91f0; 1 drivers
+v0xc4f373480_10 .net/s v0xc4f373480 10, 31 0, L_0xc4f3a9260; 1 drivers
+v0xc4f373480_11 .net/s v0xc4f373480 11, 31 0, L_0xc4f3a92d0; 1 drivers
+v0xc4f373480_12 .net/s v0xc4f373480 12, 31 0, L_0xc4f3a9340; 1 drivers
+v0xc4f373480_13 .net/s v0xc4f373480 13, 31 0, L_0xc4f3a93b0; 1 drivers
+v0xc4f373480_14 .net/s v0xc4f373480 14, 31 0, L_0xc4f3a9420; 1 drivers
+v0xc4f373480_15 .net/s v0xc4f373480 15, 31 0, L_0xc4f3a9490; 1 drivers
+v0xc4f373480_16 .net/s v0xc4f373480 16, 31 0, L_0xc4f3a9500; 1 drivers
+v0xc4f373480_17 .net/s v0xc4f373480 17, 31 0, L_0xc4f3a9570; 1 drivers
+v0xc4f373480_18 .net/s v0xc4f373480 18, 31 0, L_0xc4f3a95e0; 1 drivers
+v0xc4f373480_19 .net/s v0xc4f373480 19, 31 0, L_0xc4f3a9650; 1 drivers
+v0xc4f373480_20 .net/s v0xc4f373480 20, 31 0, L_0xc4f3a96c0; 1 drivers
+v0xc4f373480_21 .net/s v0xc4f373480 21, 31 0, L_0xc4f3a9730; 1 drivers
+v0xc4f373480_22 .net/s v0xc4f373480 22, 31 0, L_0xc4f3a97a0; 1 drivers
+v0xc4f373480_23 .net/s v0xc4f373480 23, 31 0, L_0xc4f3a9810; 1 drivers
+v0xc4f373480_24 .net/s v0xc4f373480 24, 31 0, L_0xc4f3a9880; 1 drivers
+v0xc4f373480_25 .net/s v0xc4f373480 25, 31 0, L_0xc4f3a98f0; 1 drivers
+v0xc4f373480_26 .net/s v0xc4f373480 26, 31 0, L_0xc4f3a9960; 1 drivers
+v0xc4f373480_27 .net/s v0xc4f373480 27, 31 0, L_0xc4f3a99d0; 1 drivers
+v0xc4f373480_28 .net/s v0xc4f373480 28, 31 0, L_0xc4f3a9a40; 1 drivers
+v0xc4f373480_29 .net/s v0xc4f373480 29, 31 0, L_0xc4f3a9ab0; 1 drivers
+v0xc4f373480_30 .net/s v0xc4f373480 30, 31 0, L_0xc4f3a9b20; 1 drivers
+v0xc4f373480_31 .net/s v0xc4f373480 31, 31 0, L_0xc4f3a9b90; 1 drivers
+v0xc4f373480_32 .net/s v0xc4f373480 32, 31 0, L_0xc4f3be6c0; 1 drivers
+v0xc4f373480_33 .net/s v0xc4f373480 33, 31 0, L_0xc4f3be760; 1 drivers
+v0xc4f373480_34 .net/s v0xc4f373480 34, 31 0, L_0xc4f3be800; 1 drivers
+v0xc4f373480_35 .net/s v0xc4f373480 35, 31 0, L_0xc4f3be8a0; 1 drivers
+v0xc4f373480_36 .net/s v0xc4f373480 36, 31 0, L_0xc4f3be940; 1 drivers
+v0xc4f373480_37 .net/s v0xc4f373480 37, 31 0, L_0xc4f3be9e0; 1 drivers
+v0xc4f373480_38 .net/s v0xc4f373480 38, 31 0, L_0xc4f3bea80; 1 drivers
+v0xc4f373480_39 .net/s v0xc4f373480 39, 31 0, L_0xc4f3beb20; 1 drivers
+v0xc4f373480_40 .net/s v0xc4f373480 40, 31 0, L_0xc4f3bebc0; 1 drivers
+v0xc4f373480_41 .net/s v0xc4f373480 41, 31 0, L_0xc4f3bec60; 1 drivers
+v0xc4f373480_42 .net/s v0xc4f373480 42, 31 0, L_0xc4f3bed00; 1 drivers
+v0xc4f373480_43 .net/s v0xc4f373480 43, 31 0, L_0xc4f3beda0; 1 drivers
+v0xc4f373480_44 .net/s v0xc4f373480 44, 31 0, L_0xc4f3bee40; 1 drivers
+v0xc4f373480_45 .net/s v0xc4f373480 45, 31 0, L_0xc4f3beee0; 1 drivers
+v0xc4f373480_46 .net/s v0xc4f373480 46, 31 0, L_0xc4f3bef80; 1 drivers
+v0xc4f373480_47 .net/s v0xc4f373480 47, 31 0, L_0xc4f3bf020; 1 drivers
+o0xc4e869540 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_48 .net/s v0xc4f373480 48, 31 0, o0xc4e869540; 0 drivers
+o0xc4e869570 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_49 .net/s v0xc4f373480 49, 31 0, o0xc4e869570; 0 drivers
+o0xc4e8695a0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_50 .net/s v0xc4f373480 50, 31 0, o0xc4e8695a0; 0 drivers
+o0xc4e8695d0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_51 .net/s v0xc4f373480 51, 31 0, o0xc4e8695d0; 0 drivers
+o0xc4e869600 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_52 .net/s v0xc4f373480 52, 31 0, o0xc4e869600; 0 drivers
+o0xc4e869630 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_53 .net/s v0xc4f373480 53, 31 0, o0xc4e869630; 0 drivers
+o0xc4e869660 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_54 .net/s v0xc4f373480 54, 31 0, o0xc4e869660; 0 drivers
+o0xc4e869690 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_55 .net/s v0xc4f373480 55, 31 0, o0xc4e869690; 0 drivers
+o0xc4e8696c0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_56 .net/s v0xc4f373480 56, 31 0, o0xc4e8696c0; 0 drivers
+o0xc4e8696f0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_57 .net/s v0xc4f373480 57, 31 0, o0xc4e8696f0; 0 drivers
+o0xc4e869720 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_58 .net/s v0xc4f373480 58, 31 0, o0xc4e869720; 0 drivers
+o0xc4e869750 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_59 .net/s v0xc4f373480 59, 31 0, o0xc4e869750; 0 drivers
+o0xc4e869780 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_60 .net/s v0xc4f373480 60, 31 0, o0xc4e869780; 0 drivers
+o0xc4e8697b0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_61 .net/s v0xc4f373480 61, 31 0, o0xc4e8697b0; 0 drivers
+o0xc4e8697e0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_62 .net/s v0xc4f373480 62, 31 0, o0xc4e8697e0; 0 drivers
+o0xc4e869810 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_63 .net/s v0xc4f373480 63, 31 0, o0xc4e869810; 0 drivers
+v0xc4f373480_64 .net/s v0xc4f373480 64, 31 0, L_0xc4f3bf0c0; 1 drivers
+v0xc4f373480_65 .net/s v0xc4f373480 65, 31 0, L_0xc4f3bf160; 1 drivers
+v0xc4f373480_66 .net/s v0xc4f373480 66, 31 0, L_0xc4f3bf200; 1 drivers
+v0xc4f373480_67 .net/s v0xc4f373480 67, 31 0, L_0xc4f3bf2a0; 1 drivers
+v0xc4f373480_68 .net/s v0xc4f373480 68, 31 0, L_0xc4f3bf340; 1 drivers
+v0xc4f373480_69 .net/s v0xc4f373480 69, 31 0, L_0xc4f3bf3e0; 1 drivers
+v0xc4f373480_70 .net/s v0xc4f373480 70, 31 0, L_0xc4f3bf480; 1 drivers
+v0xc4f373480_71 .net/s v0xc4f373480 71, 31 0, L_0xc4f3bf520; 1 drivers
+o0xc4e8699c0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_72 .net/s v0xc4f373480 72, 31 0, o0xc4e8699c0; 0 drivers
+o0xc4e8699f0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_73 .net/s v0xc4f373480 73, 31 0, o0xc4e8699f0; 0 drivers
+o0xc4e869a20 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_74 .net/s v0xc4f373480 74, 31 0, o0xc4e869a20; 0 drivers
+o0xc4e869a50 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_75 .net/s v0xc4f373480 75, 31 0, o0xc4e869a50; 0 drivers
+o0xc4e869a80 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_76 .net/s v0xc4f373480 76, 31 0, o0xc4e869a80; 0 drivers
+o0xc4e869ab0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_77 .net/s v0xc4f373480 77, 31 0, o0xc4e869ab0; 0 drivers
+o0xc4e869ae0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_78 .net/s v0xc4f373480 78, 31 0, o0xc4e869ae0; 0 drivers
+o0xc4e869b10 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_79 .net/s v0xc4f373480 79, 31 0, o0xc4e869b10; 0 drivers
+o0xc4e869b40 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_80 .net/s v0xc4f373480 80, 31 0, o0xc4e869b40; 0 drivers
+o0xc4e869b70 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_81 .net/s v0xc4f373480 81, 31 0, o0xc4e869b70; 0 drivers
+o0xc4e869ba0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_82 .net/s v0xc4f373480 82, 31 0, o0xc4e869ba0; 0 drivers
+o0xc4e869bd0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_83 .net/s v0xc4f373480 83, 31 0, o0xc4e869bd0; 0 drivers
+o0xc4e869c00 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_84 .net/s v0xc4f373480 84, 31 0, o0xc4e869c00; 0 drivers
+o0xc4e869c30 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_85 .net/s v0xc4f373480 85, 31 0, o0xc4e869c30; 0 drivers
+o0xc4e869c60 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_86 .net/s v0xc4f373480 86, 31 0, o0xc4e869c60; 0 drivers
+o0xc4e869c90 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_87 .net/s v0xc4f373480 87, 31 0, o0xc4e869c90; 0 drivers
+o0xc4e869cc0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_88 .net/s v0xc4f373480 88, 31 0, o0xc4e869cc0; 0 drivers
+o0xc4e869cf0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_89 .net/s v0xc4f373480 89, 31 0, o0xc4e869cf0; 0 drivers
+o0xc4e869d20 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_90 .net/s v0xc4f373480 90, 31 0, o0xc4e869d20; 0 drivers
+o0xc4e869d50 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_91 .net/s v0xc4f373480 91, 31 0, o0xc4e869d50; 0 drivers
+o0xc4e869d80 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_92 .net/s v0xc4f373480 92, 31 0, o0xc4e869d80; 0 drivers
+o0xc4e869db0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_93 .net/s v0xc4f373480 93, 31 0, o0xc4e869db0; 0 drivers
+o0xc4e869de0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_94 .net/s v0xc4f373480 94, 31 0, o0xc4e869de0; 0 drivers
+o0xc4e869e10 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_95 .net/s v0xc4f373480 95, 31 0, o0xc4e869e10; 0 drivers
+v0xc4f373480_96 .net/s v0xc4f373480 96, 31 0, L_0xc4f3bf5c0; 1 drivers
+v0xc4f373480_97 .net/s v0xc4f373480 97, 31 0, L_0xc4f3bf660; 1 drivers
+v0xc4f373480_98 .net/s v0xc4f373480 98, 31 0, L_0xc4f3bf700; 1 drivers
+v0xc4f373480_99 .net/s v0xc4f373480 99, 31 0, L_0xc4f3bf7a0; 1 drivers
+o0xc4e869f00 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_100 .net/s v0xc4f373480 100, 31 0, o0xc4e869f00; 0 drivers
+o0xc4e869f30 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_101 .net/s v0xc4f373480 101, 31 0, o0xc4e869f30; 0 drivers
+o0xc4e869f60 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_102 .net/s v0xc4f373480 102, 31 0, o0xc4e869f60; 0 drivers
+o0xc4e869f90 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_103 .net/s v0xc4f373480 103, 31 0, o0xc4e869f90; 0 drivers
+o0xc4e869fc0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_104 .net/s v0xc4f373480 104, 31 0, o0xc4e869fc0; 0 drivers
+o0xc4e869ff0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_105 .net/s v0xc4f373480 105, 31 0, o0xc4e869ff0; 0 drivers
+o0xc4e86a020 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_106 .net/s v0xc4f373480 106, 31 0, o0xc4e86a020; 0 drivers
+o0xc4e86a050 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_107 .net/s v0xc4f373480 107, 31 0, o0xc4e86a050; 0 drivers
+o0xc4e86a080 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_108 .net/s v0xc4f373480 108, 31 0, o0xc4e86a080; 0 drivers
+o0xc4e86a0b0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_109 .net/s v0xc4f373480 109, 31 0, o0xc4e86a0b0; 0 drivers
+o0xc4e86a0e0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_110 .net/s v0xc4f373480 110, 31 0, o0xc4e86a0e0; 0 drivers
+o0xc4e86a110 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_111 .net/s v0xc4f373480 111, 31 0, o0xc4e86a110; 0 drivers
+o0xc4e86a140 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_112 .net/s v0xc4f373480 112, 31 0, o0xc4e86a140; 0 drivers
+o0xc4e86a170 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_113 .net/s v0xc4f373480 113, 31 0, o0xc4e86a170; 0 drivers
+o0xc4e86a1a0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_114 .net/s v0xc4f373480 114, 31 0, o0xc4e86a1a0; 0 drivers
+o0xc4e86a1d0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_115 .net/s v0xc4f373480 115, 31 0, o0xc4e86a1d0; 0 drivers
+o0xc4e86a200 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_116 .net/s v0xc4f373480 116, 31 0, o0xc4e86a200; 0 drivers
+o0xc4e86a230 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_117 .net/s v0xc4f373480 117, 31 0, o0xc4e86a230; 0 drivers
+o0xc4e86a260 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_118 .net/s v0xc4f373480 118, 31 0, o0xc4e86a260; 0 drivers
+o0xc4e86a290 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_119 .net/s v0xc4f373480 119, 31 0, o0xc4e86a290; 0 drivers
+o0xc4e86a2c0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_120 .net/s v0xc4f373480 120, 31 0, o0xc4e86a2c0; 0 drivers
+o0xc4e86a2f0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_121 .net/s v0xc4f373480 121, 31 0, o0xc4e86a2f0; 0 drivers
+o0xc4e86a320 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_122 .net/s v0xc4f373480 122, 31 0, o0xc4e86a320; 0 drivers
+o0xc4e86a350 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_123 .net/s v0xc4f373480 123, 31 0, o0xc4e86a350; 0 drivers
+o0xc4e86a380 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_124 .net/s v0xc4f373480 124, 31 0, o0xc4e86a380; 0 drivers
+o0xc4e86a3b0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_125 .net/s v0xc4f373480 125, 31 0, o0xc4e86a3b0; 0 drivers
+o0xc4e86a3e0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_126 .net/s v0xc4f373480 126, 31 0, o0xc4e86a3e0; 0 drivers
+o0xc4e86a410 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_127 .net/s v0xc4f373480 127, 31 0, o0xc4e86a410; 0 drivers
+v0xc4f373480_128 .net/s v0xc4f373480 128, 31 0, L_0xc4f3bf840; 1 drivers
+v0xc4f373480_129 .net/s v0xc4f373480 129, 31 0, L_0xc4f3bf8e0; 1 drivers
+o0xc4e86a4a0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_130 .net/s v0xc4f373480 130, 31 0, o0xc4e86a4a0; 0 drivers
+o0xc4e86a4d0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_131 .net/s v0xc4f373480 131, 31 0, o0xc4e86a4d0; 0 drivers
+o0xc4e86a500 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_132 .net/s v0xc4f373480 132, 31 0, o0xc4e86a500; 0 drivers
+o0xc4e86a530 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_133 .net/s v0xc4f373480 133, 31 0, o0xc4e86a530; 0 drivers
+o0xc4e86a560 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_134 .net/s v0xc4f373480 134, 31 0, o0xc4e86a560; 0 drivers
+o0xc4e86a590 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_135 .net/s v0xc4f373480 135, 31 0, o0xc4e86a590; 0 drivers
+o0xc4e86a5c0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_136 .net/s v0xc4f373480 136, 31 0, o0xc4e86a5c0; 0 drivers
+o0xc4e86a5f0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_137 .net/s v0xc4f373480 137, 31 0, o0xc4e86a5f0; 0 drivers
+o0xc4e86a620 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_138 .net/s v0xc4f373480 138, 31 0, o0xc4e86a620; 0 drivers
+o0xc4e86a650 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_139 .net/s v0xc4f373480 139, 31 0, o0xc4e86a650; 0 drivers
+o0xc4e86a680 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_140 .net/s v0xc4f373480 140, 31 0, o0xc4e86a680; 0 drivers
+o0xc4e86a6b0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_141 .net/s v0xc4f373480 141, 31 0, o0xc4e86a6b0; 0 drivers
+o0xc4e86a6e0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_142 .net/s v0xc4f373480 142, 31 0, o0xc4e86a6e0; 0 drivers
+o0xc4e86a710 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_143 .net/s v0xc4f373480 143, 31 0, o0xc4e86a710; 0 drivers
+o0xc4e86a740 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_144 .net/s v0xc4f373480 144, 31 0, o0xc4e86a740; 0 drivers
+o0xc4e86a770 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_145 .net/s v0xc4f373480 145, 31 0, o0xc4e86a770; 0 drivers
+o0xc4e86a7a0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_146 .net/s v0xc4f373480 146, 31 0, o0xc4e86a7a0; 0 drivers
+o0xc4e86a7d0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_147 .net/s v0xc4f373480 147, 31 0, o0xc4e86a7d0; 0 drivers
+o0xc4e86a800 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_148 .net/s v0xc4f373480 148, 31 0, o0xc4e86a800; 0 drivers
+o0xc4e86a830 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_149 .net/s v0xc4f373480 149, 31 0, o0xc4e86a830; 0 drivers
+o0xc4e86a860 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_150 .net/s v0xc4f373480 150, 31 0, o0xc4e86a860; 0 drivers
+o0xc4e86a890 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_151 .net/s v0xc4f373480 151, 31 0, o0xc4e86a890; 0 drivers
+o0xc4e86a8c0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_152 .net/s v0xc4f373480 152, 31 0, o0xc4e86a8c0; 0 drivers
+o0xc4e86a8f0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_153 .net/s v0xc4f373480 153, 31 0, o0xc4e86a8f0; 0 drivers
+o0xc4e86a920 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_154 .net/s v0xc4f373480 154, 31 0, o0xc4e86a920; 0 drivers
+o0xc4e86a950 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_155 .net/s v0xc4f373480 155, 31 0, o0xc4e86a950; 0 drivers
+o0xc4e86a980 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_156 .net/s v0xc4f373480 156, 31 0, o0xc4e86a980; 0 drivers
+o0xc4e86a9b0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_157 .net/s v0xc4f373480 157, 31 0, o0xc4e86a9b0; 0 drivers
+o0xc4e86a9e0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_158 .net/s v0xc4f373480 158, 31 0, o0xc4e86a9e0; 0 drivers
+o0xc4e86aa10 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_159 .net/s v0xc4f373480 159, 31 0, o0xc4e86aa10; 0 drivers
+v0xc4f373480_160 .net/s v0xc4f373480 160, 31 0, L_0xc4f3bf980; 1 drivers
+o0xc4e86aa70 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_161 .net/s v0xc4f373480 161, 31 0, o0xc4e86aa70; 0 drivers
+o0xc4e86aaa0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_162 .net/s v0xc4f373480 162, 31 0, o0xc4e86aaa0; 0 drivers
+o0xc4e86aad0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_163 .net/s v0xc4f373480 163, 31 0, o0xc4e86aad0; 0 drivers
+o0xc4e86ab00 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_164 .net/s v0xc4f373480 164, 31 0, o0xc4e86ab00; 0 drivers
+o0xc4e86ab30 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_165 .net/s v0xc4f373480 165, 31 0, o0xc4e86ab30; 0 drivers
+o0xc4e86ab60 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_166 .net/s v0xc4f373480 166, 31 0, o0xc4e86ab60; 0 drivers
+o0xc4e86ab90 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_167 .net/s v0xc4f373480 167, 31 0, o0xc4e86ab90; 0 drivers
+o0xc4e86abc0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_168 .net/s v0xc4f373480 168, 31 0, o0xc4e86abc0; 0 drivers
+o0xc4e86abf0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_169 .net/s v0xc4f373480 169, 31 0, o0xc4e86abf0; 0 drivers
+o0xc4e86ac20 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_170 .net/s v0xc4f373480 170, 31 0, o0xc4e86ac20; 0 drivers
+o0xc4e86ac50 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_171 .net/s v0xc4f373480 171, 31 0, o0xc4e86ac50; 0 drivers
+o0xc4e86ac80 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_172 .net/s v0xc4f373480 172, 31 0, o0xc4e86ac80; 0 drivers
+o0xc4e86acb0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_173 .net/s v0xc4f373480 173, 31 0, o0xc4e86acb0; 0 drivers
+o0xc4e86ace0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_174 .net/s v0xc4f373480 174, 31 0, o0xc4e86ace0; 0 drivers
+o0xc4e86ad10 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_175 .net/s v0xc4f373480 175, 31 0, o0xc4e86ad10; 0 drivers
+o0xc4e86ad40 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_176 .net/s v0xc4f373480 176, 31 0, o0xc4e86ad40; 0 drivers
+o0xc4e86ad70 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_177 .net/s v0xc4f373480 177, 31 0, o0xc4e86ad70; 0 drivers
+o0xc4e86ada0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_178 .net/s v0xc4f373480 178, 31 0, o0xc4e86ada0; 0 drivers
+o0xc4e86add0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_179 .net/s v0xc4f373480 179, 31 0, o0xc4e86add0; 0 drivers
+o0xc4e86ae00 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_180 .net/s v0xc4f373480 180, 31 0, o0xc4e86ae00; 0 drivers
+o0xc4e86ae30 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_181 .net/s v0xc4f373480 181, 31 0, o0xc4e86ae30; 0 drivers
+o0xc4e86ae60 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_182 .net/s v0xc4f373480 182, 31 0, o0xc4e86ae60; 0 drivers
+o0xc4e86ae90 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_183 .net/s v0xc4f373480 183, 31 0, o0xc4e86ae90; 0 drivers
+o0xc4e86aec0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_184 .net/s v0xc4f373480 184, 31 0, o0xc4e86aec0; 0 drivers
+o0xc4e86aef0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_185 .net/s v0xc4f373480 185, 31 0, o0xc4e86aef0; 0 drivers
+o0xc4e86af20 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_186 .net/s v0xc4f373480 186, 31 0, o0xc4e86af20; 0 drivers
+o0xc4e86af50 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_187 .net/s v0xc4f373480 187, 31 0, o0xc4e86af50; 0 drivers
+o0xc4e86af80 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_188 .net/s v0xc4f373480 188, 31 0, o0xc4e86af80; 0 drivers
+o0xc4e86afb0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_189 .net/s v0xc4f373480 189, 31 0, o0xc4e86afb0; 0 drivers
+o0xc4e86afe0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_190 .net/s v0xc4f373480 190, 31 0, o0xc4e86afe0; 0 drivers
+o0xc4e86b010 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f373480_191 .net/s v0xc4f373480 191, 31 0, o0xc4e86b010; 0 drivers
+v0xc4f373520_0 .net/s "w_bus", 255 0, L_0xc4f3b1cc0;  alias, 1 drivers
+v0xc4f3735c0_0 .net/s "x_bus", 255 0, L_0xc4f3b1c20;  alias, 1 drivers
+L_0xc4f3b1e00 .part L_0xc4f3b1c20, 0, 8;
+L_0xc4f3b1ea0 .part L_0xc4f3b1cc0, 0, 8;
+L_0xc4f3b1fe0 .part L_0xc4f3b1c20, 8, 8;
+L_0xc4f3b2080 .part L_0xc4f3b1cc0, 8, 8;
+L_0xc4f3b21c0 .part L_0xc4f3b1c20, 16, 8;
+L_0xc4f3b2260 .part L_0xc4f3b1cc0, 16, 8;
+L_0xc4f3b23a0 .part L_0xc4f3b1c20, 24, 8;
+L_0xc4f3b2440 .part L_0xc4f3b1cc0, 24, 8;
+L_0xc4f3b2580 .part L_0xc4f3b1c20, 32, 8;
+L_0xc4f3b2620 .part L_0xc4f3b1cc0, 32, 8;
+L_0xc4f3b2760 .part L_0xc4f3b1c20, 40, 8;
+L_0xc4f3b2800 .part L_0xc4f3b1cc0, 40, 8;
+L_0xc4f3b2940 .part L_0xc4f3b1c20, 48, 8;
+L_0xc4f3b29e0 .part L_0xc4f3b1cc0, 48, 8;
+L_0xc4f3b2b20 .part L_0xc4f3b1c20, 56, 8;
+L_0xc4f3b2bc0 .part L_0xc4f3b1cc0, 56, 8;
+L_0xc4f3b2d00 .part L_0xc4f3b1c20, 64, 8;
+L_0xc4f3b2da0 .part L_0xc4f3b1cc0, 64, 8;
+L_0xc4f3b2ee0 .part L_0xc4f3b1c20, 72, 8;
+L_0xc4f3b2f80 .part L_0xc4f3b1cc0, 72, 8;
+L_0xc4f3b30c0 .part L_0xc4f3b1c20, 80, 8;
+L_0xc4f3b3160 .part L_0xc4f3b1cc0, 80, 8;
+L_0xc4f3b32a0 .part L_0xc4f3b1c20, 88, 8;
+L_0xc4f3b3340 .part L_0xc4f3b1cc0, 88, 8;
+L_0xc4f3b3480 .part L_0xc4f3b1c20, 96, 8;
+L_0xc4f3b3520 .part L_0xc4f3b1cc0, 96, 8;
+L_0xc4f3b3660 .part L_0xc4f3b1c20, 104, 8;
+L_0xc4f3b3700 .part L_0xc4f3b1cc0, 104, 8;
+L_0xc4f3b3840 .part L_0xc4f3b1c20, 112, 8;
+L_0xc4f3b38e0 .part L_0xc4f3b1cc0, 112, 8;
+L_0xc4f3b3a20 .part L_0xc4f3b1c20, 120, 8;
+L_0xc4f3b3ac0 .part L_0xc4f3b1cc0, 120, 8;
+L_0xc4f3b3c00 .part L_0xc4f3b1c20, 128, 8;
+L_0xc4f3b3ca0 .part L_0xc4f3b1cc0, 128, 8;
+L_0xc4f3b3de0 .part L_0xc4f3b1c20, 136, 8;
+L_0xc4f3b3e80 .part L_0xc4f3b1cc0, 136, 8;
+L_0xc4f3c0000 .part L_0xc4f3b1c20, 144, 8;
+L_0xc4f3c00a0 .part L_0xc4f3b1cc0, 144, 8;
+L_0xc4f3c01e0 .part L_0xc4f3b1c20, 152, 8;
+L_0xc4f3c0280 .part L_0xc4f3b1cc0, 152, 8;
+L_0xc4f3c03c0 .part L_0xc4f3b1c20, 160, 8;
+L_0xc4f3c0460 .part L_0xc4f3b1cc0, 160, 8;
+L_0xc4f3c05a0 .part L_0xc4f3b1c20, 168, 8;
+L_0xc4f3c0640 .part L_0xc4f3b1cc0, 168, 8;
+L_0xc4f3c0780 .part L_0xc4f3b1c20, 176, 8;
+L_0xc4f3c0820 .part L_0xc4f3b1cc0, 176, 8;
+L_0xc4f3c0960 .part L_0xc4f3b1c20, 184, 8;
+L_0xc4f3c0a00 .part L_0xc4f3b1cc0, 184, 8;
+L_0xc4f3c0b40 .part L_0xc4f3b1c20, 192, 8;
+L_0xc4f3c0be0 .part L_0xc4f3b1cc0, 192, 8;
+L_0xc4f3c0d20 .part L_0xc4f3b1c20, 200, 8;
+L_0xc4f3c0dc0 .part L_0xc4f3b1cc0, 200, 8;
+L_0xc4f3c0f00 .part L_0xc4f3b1c20, 208, 8;
+L_0xc4f3c0fa0 .part L_0xc4f3b1cc0, 208, 8;
+L_0xc4f3c10e0 .part L_0xc4f3b1c20, 216, 8;
+L_0xc4f3c1180 .part L_0xc4f3b1cc0, 216, 8;
+L_0xc4f3c12c0 .part L_0xc4f3b1c20, 224, 8;
+L_0xc4f3c1360 .part L_0xc4f3b1cc0, 224, 8;
+L_0xc4f3c14a0 .part L_0xc4f3b1c20, 232, 8;
+L_0xc4f3c1540 .part L_0xc4f3b1cc0, 232, 8;
+L_0xc4f3c1680 .part L_0xc4f3b1c20, 240, 8;
+L_0xc4f3c1720 .part L_0xc4f3b1cc0, 240, 8;
+L_0xc4f3c1860 .part L_0xc4f3b1c20, 248, 8;
+L_0xc4f3c1900 .part L_0xc4f3b1cc0, 248, 8;
+L_0xc4f3bfa20 .arith/sum 32, v0xc4f373f20_0, L_0xc4f3bf980;
+S_0xc4f357780 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335840 .param/l "i" 1 5 20, +C4<00>;
+S_0xc4f357900 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f357780;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f340f00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f340f40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f340f80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f3529e0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b5680;  1 drivers
+v0xc4f352a80_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b5720;  1 drivers
+v0xc4f352b20_0 .net *"_ivl_7", 0 0, L_0xc4f3b1d60;  1 drivers
+v0xc4f352bc0_0 .net *"_ivl_9", 15 0, L_0xc4ef5c6e0;  1 drivers
+L_0xc4e87b3d0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f352c60_0 .net/s "acc_in", 31 0, L_0xc4e87b3d0;  1 drivers
+v0xc4f352d00_0 .net/s "acc_out", 31 0, L_0xc4f3b5860;  alias, 1 drivers
+v0xc4f352da0_0 .net/s "product", 15 0, L_0xc4ef5c640;  1 drivers
+v0xc4f352e40_0 .net/s "product_ext", 31 0, L_0xc4f3b57c0;  1 drivers
+v0xc4f352ee0_0 .net/s "w", 7 0, L_0xc4f3b1ea0;  1 drivers
+v0xc4f352f80_0 .net/s "x", 7 0, L_0xc4f3b1e00;  1 drivers
+L_0xc4f3b5680 .extend/s 16, L_0xc4f3b1e00;
+L_0xc4f3b5720 .extend/s 16, L_0xc4f3b1ea0;
+L_0xc4ef5c640 .arith/mult 16, L_0xc4f3b5680, L_0xc4f3b5720;
+L_0xc4f3b1d60 .part L_0xc4ef5c640, 15, 1;
+L_0xc4ef5c6e0 .repeat 16, 16, L_0xc4f3b1d60;
+L_0xc4f3b57c0 .concat [ 16 16 0 0], L_0xc4ef5c640, L_0xc4ef5c6e0;
+L_0xc4f3b5860 .arith/sum 32, L_0xc4e87b3d0, L_0xc4f3b57c0;
+S_0xc4f357a80 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335880 .param/l "i" 1 5 20, +C4<01>;
+S_0xc4f357c00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f357a80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f340fc0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f341000 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f341040 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f353020_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b5900;  1 drivers
+v0xc4f3530c0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b59a0;  1 drivers
+v0xc4f353160_0 .net *"_ivl_7", 0 0, L_0xc4f3b1f40;  1 drivers
+v0xc4f353200_0 .net *"_ivl_9", 15 0, L_0xc4ef5c820;  1 drivers
+L_0xc4e87b418 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3532a0_0 .net/s "acc_in", 31 0, L_0xc4e87b418;  1 drivers
+v0xc4f353340_0 .net/s "acc_out", 31 0, L_0xc4f3b5ae0;  alias, 1 drivers
+v0xc4f3533e0_0 .net/s "product", 15 0, L_0xc4ef5c780;  1 drivers
+v0xc4f353480_0 .net/s "product_ext", 31 0, L_0xc4f3b5a40;  1 drivers
+v0xc4f353520_0 .net/s "w", 7 0, L_0xc4f3b2080;  1 drivers
+v0xc4f3535c0_0 .net/s "x", 7 0, L_0xc4f3b1fe0;  1 drivers
+L_0xc4f3b5900 .extend/s 16, L_0xc4f3b1fe0;
+L_0xc4f3b59a0 .extend/s 16, L_0xc4f3b2080;
+L_0xc4ef5c780 .arith/mult 16, L_0xc4f3b5900, L_0xc4f3b59a0;
+L_0xc4f3b1f40 .part L_0xc4ef5c780, 15, 1;
+L_0xc4ef5c820 .repeat 16, 16, L_0xc4f3b1f40;
+L_0xc4f3b5a40 .concat [ 16 16 0 0], L_0xc4ef5c780, L_0xc4ef5c820;
+L_0xc4f3b5ae0 .arith/sum 32, L_0xc4e87b418, L_0xc4f3b5a40;
+S_0xc4f357d80 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f3358c0 .param/l "i" 1 5 20, +C4<010>;
+S_0xc4f35c000 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f357d80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f341080 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f3410c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f341100 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f353660_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b5b80;  1 drivers
+v0xc4f353700_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b5c20;  1 drivers
+v0xc4f3537a0_0 .net *"_ivl_7", 0 0, L_0xc4f3b2120;  1 drivers
+v0xc4f353840_0 .net *"_ivl_9", 15 0, L_0xc4ef5c960;  1 drivers
+L_0xc4e87b460 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3538e0_0 .net/s "acc_in", 31 0, L_0xc4e87b460;  1 drivers
+v0xc4f353980_0 .net/s "acc_out", 31 0, L_0xc4f3b5d60;  alias, 1 drivers
+v0xc4f353a20_0 .net/s "product", 15 0, L_0xc4ef5c8c0;  1 drivers
+v0xc4f353ac0_0 .net/s "product_ext", 31 0, L_0xc4f3b5cc0;  1 drivers
+v0xc4f353b60_0 .net/s "w", 7 0, L_0xc4f3b2260;  1 drivers
+v0xc4f353c00_0 .net/s "x", 7 0, L_0xc4f3b21c0;  1 drivers
+L_0xc4f3b5b80 .extend/s 16, L_0xc4f3b21c0;
+L_0xc4f3b5c20 .extend/s 16, L_0xc4f3b2260;
+L_0xc4ef5c8c0 .arith/mult 16, L_0xc4f3b5b80, L_0xc4f3b5c20;
+L_0xc4f3b2120 .part L_0xc4ef5c8c0, 15, 1;
+L_0xc4ef5c960 .repeat 16, 16, L_0xc4f3b2120;
+L_0xc4f3b5cc0 .concat [ 16 16 0 0], L_0xc4ef5c8c0, L_0xc4ef5c960;
+L_0xc4f3b5d60 .arith/sum 32, L_0xc4e87b460, L_0xc4f3b5cc0;
+S_0xc4f35c180 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335900 .param/l "i" 1 5 20, +C4<011>;
+S_0xc4f35c300 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35c180;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f341140 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f341180 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f3411c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f353ca0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b5e00;  1 drivers
+v0xc4f353d40_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b5ea0;  1 drivers
+v0xc4f353de0_0 .net *"_ivl_7", 0 0, L_0xc4f3b2300;  1 drivers
+v0xc4f353e80_0 .net *"_ivl_9", 15 0, L_0xc4ef5caa0;  1 drivers
+L_0xc4e87b4a8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f353f20_0 .net/s "acc_in", 31 0, L_0xc4e87b4a8;  1 drivers
+v0xc4f360000_0 .net/s "acc_out", 31 0, L_0xc4f3b5fe0;  alias, 1 drivers
+v0xc4f3600a0_0 .net/s "product", 15 0, L_0xc4ef5ca00;  1 drivers
+v0xc4f360140_0 .net/s "product_ext", 31 0, L_0xc4f3b5f40;  1 drivers
+v0xc4f3601e0_0 .net/s "w", 7 0, L_0xc4f3b2440;  1 drivers
+v0xc4f360280_0 .net/s "x", 7 0, L_0xc4f3b23a0;  1 drivers
+L_0xc4f3b5e00 .extend/s 16, L_0xc4f3b23a0;
+L_0xc4f3b5ea0 .extend/s 16, L_0xc4f3b2440;
+L_0xc4ef5ca00 .arith/mult 16, L_0xc4f3b5e00, L_0xc4f3b5ea0;
+L_0xc4f3b2300 .part L_0xc4ef5ca00, 15, 1;
+L_0xc4ef5caa0 .repeat 16, 16, L_0xc4f3b2300;
+L_0xc4f3b5f40 .concat [ 16 16 0 0], L_0xc4ef5ca00, L_0xc4ef5caa0;
+L_0xc4f3b5fe0 .arith/sum 32, L_0xc4e87b4a8, L_0xc4f3b5f40;
+S_0xc4f35c480 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335980 .param/l "i" 1 5 20, +C4<0100>;
+S_0xc4f35c600 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35c480;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f341200 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f341240 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f341280 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f360320_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b6080;  1 drivers
+v0xc4f3603c0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b6120;  1 drivers
+v0xc4f360460_0 .net *"_ivl_7", 0 0, L_0xc4f3b24e0;  1 drivers
+v0xc4f360500_0 .net *"_ivl_9", 15 0, L_0xc4ef5cbe0;  1 drivers
+L_0xc4e87b4f0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3605a0_0 .net/s "acc_in", 31 0, L_0xc4e87b4f0;  1 drivers
+v0xc4f360640_0 .net/s "acc_out", 31 0, L_0xc4f3b6260;  alias, 1 drivers
+v0xc4f3606e0_0 .net/s "product", 15 0, L_0xc4ef5cb40;  1 drivers
+v0xc4f360780_0 .net/s "product_ext", 31 0, L_0xc4f3b61c0;  1 drivers
+v0xc4f360820_0 .net/s "w", 7 0, L_0xc4f3b2620;  1 drivers
+v0xc4f3608c0_0 .net/s "x", 7 0, L_0xc4f3b2580;  1 drivers
+L_0xc4f3b6080 .extend/s 16, L_0xc4f3b2580;
+L_0xc4f3b6120 .extend/s 16, L_0xc4f3b2620;
+L_0xc4ef5cb40 .arith/mult 16, L_0xc4f3b6080, L_0xc4f3b6120;
+L_0xc4f3b24e0 .part L_0xc4ef5cb40, 15, 1;
+L_0xc4ef5cbe0 .repeat 16, 16, L_0xc4f3b24e0;
+L_0xc4f3b61c0 .concat [ 16 16 0 0], L_0xc4ef5cb40, L_0xc4ef5cbe0;
+L_0xc4f3b6260 .arith/sum 32, L_0xc4e87b4f0, L_0xc4f3b61c0;
+S_0xc4f35c780 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f3359c0 .param/l "i" 1 5 20, +C4<0101>;
+S_0xc4f35c900 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35c780;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f3412c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f341300 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f341340 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f360960_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b6300;  1 drivers
+v0xc4f360a00_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b63a0;  1 drivers
+v0xc4f360aa0_0 .net *"_ivl_7", 0 0, L_0xc4f3b26c0;  1 drivers
+v0xc4f360b40_0 .net *"_ivl_9", 15 0, L_0xc4ef5cd20;  1 drivers
+L_0xc4e87b538 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f360be0_0 .net/s "acc_in", 31 0, L_0xc4e87b538;  1 drivers
+v0xc4f360c80_0 .net/s "acc_out", 31 0, L_0xc4f3b64e0;  alias, 1 drivers
+v0xc4f360d20_0 .net/s "product", 15 0, L_0xc4ef5cc80;  1 drivers
+v0xc4f360dc0_0 .net/s "product_ext", 31 0, L_0xc4f3b6440;  1 drivers
+v0xc4f360e60_0 .net/s "w", 7 0, L_0xc4f3b2800;  1 drivers
+v0xc4f360f00_0 .net/s "x", 7 0, L_0xc4f3b2760;  1 drivers
+L_0xc4f3b6300 .extend/s 16, L_0xc4f3b2760;
+L_0xc4f3b63a0 .extend/s 16, L_0xc4f3b2800;
+L_0xc4ef5cc80 .arith/mult 16, L_0xc4f3b6300, L_0xc4f3b63a0;
+L_0xc4f3b26c0 .part L_0xc4ef5cc80, 15, 1;
+L_0xc4ef5cd20 .repeat 16, 16, L_0xc4f3b26c0;
+L_0xc4f3b6440 .concat [ 16 16 0 0], L_0xc4ef5cc80, L_0xc4ef5cd20;
+L_0xc4f3b64e0 .arith/sum 32, L_0xc4e87b538, L_0xc4f3b6440;
+S_0xc4f35ca80 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335a00 .param/l "i" 1 5 20, +C4<0110>;
+S_0xc4f35cc00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35ca80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f341380 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f3413c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f341400 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f360fa0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b6580;  1 drivers
+v0xc4f361040_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b6620;  1 drivers
+v0xc4f3610e0_0 .net *"_ivl_7", 0 0, L_0xc4f3b28a0;  1 drivers
+v0xc4f361180_0 .net *"_ivl_9", 15 0, L_0xc4ef5ce60;  1 drivers
+L_0xc4e87b580 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f361220_0 .net/s "acc_in", 31 0, L_0xc4e87b580;  1 drivers
+v0xc4f3612c0_0 .net/s "acc_out", 31 0, L_0xc4f3b6760;  alias, 1 drivers
+v0xc4f361360_0 .net/s "product", 15 0, L_0xc4ef5cdc0;  1 drivers
+v0xc4f361400_0 .net/s "product_ext", 31 0, L_0xc4f3b66c0;  1 drivers
+v0xc4f3614a0_0 .net/s "w", 7 0, L_0xc4f3b29e0;  1 drivers
+v0xc4f361540_0 .net/s "x", 7 0, L_0xc4f3b2940;  1 drivers
+L_0xc4f3b6580 .extend/s 16, L_0xc4f3b2940;
+L_0xc4f3b6620 .extend/s 16, L_0xc4f3b29e0;
+L_0xc4ef5cdc0 .arith/mult 16, L_0xc4f3b6580, L_0xc4f3b6620;
+L_0xc4f3b28a0 .part L_0xc4ef5cdc0, 15, 1;
+L_0xc4ef5ce60 .repeat 16, 16, L_0xc4f3b28a0;
+L_0xc4f3b66c0 .concat [ 16 16 0 0], L_0xc4ef5cdc0, L_0xc4ef5ce60;
+L_0xc4f3b6760 .arith/sum 32, L_0xc4e87b580, L_0xc4f3b66c0;
+S_0xc4f35cd80 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335a40 .param/l "i" 1 5 20, +C4<0111>;
+S_0xc4f35cf00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35cd80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f341440 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f341480 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f3414c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f3615e0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b6800;  1 drivers
+v0xc4f361680_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b68a0;  1 drivers
+v0xc4f361720_0 .net *"_ivl_7", 0 0, L_0xc4f3b2a80;  1 drivers
+v0xc4f3617c0_0 .net *"_ivl_9", 15 0, L_0xc4ef5cfa0;  1 drivers
+L_0xc4e87b5c8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f361860_0 .net/s "acc_in", 31 0, L_0xc4e87b5c8;  1 drivers
+v0xc4f361900_0 .net/s "acc_out", 31 0, L_0xc4f3b69e0;  alias, 1 drivers
+v0xc4f3619a0_0 .net/s "product", 15 0, L_0xc4ef5cf00;  1 drivers
+v0xc4f361a40_0 .net/s "product_ext", 31 0, L_0xc4f3b6940;  1 drivers
+v0xc4f361ae0_0 .net/s "w", 7 0, L_0xc4f3b2bc0;  1 drivers
+v0xc4f361b80_0 .net/s "x", 7 0, L_0xc4f3b2b20;  1 drivers
+L_0xc4f3b6800 .extend/s 16, L_0xc4f3b2b20;
+L_0xc4f3b68a0 .extend/s 16, L_0xc4f3b2bc0;
+L_0xc4ef5cf00 .arith/mult 16, L_0xc4f3b6800, L_0xc4f3b68a0;
+L_0xc4f3b2a80 .part L_0xc4ef5cf00, 15, 1;
+L_0xc4ef5cfa0 .repeat 16, 16, L_0xc4f3b2a80;
+L_0xc4f3b6940 .concat [ 16 16 0 0], L_0xc4ef5cf00, L_0xc4ef5cfa0;
+L_0xc4f3b69e0 .arith/sum 32, L_0xc4e87b5c8, L_0xc4f3b6940;
+S_0xc4f35d080 .scope generate, "GEN_MAC[8]" "GEN_MAC[8]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335940 .param/l "i" 1 5 20, +C4<01000>;
+S_0xc4f35d200 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35d080;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f341500 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f341540 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f341580 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f361c20_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b6a80;  1 drivers
+v0xc4f361cc0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b6b20;  1 drivers
+v0xc4f361d60_0 .net *"_ivl_7", 0 0, L_0xc4f3b2c60;  1 drivers
+v0xc4f361e00_0 .net *"_ivl_9", 15 0, L_0xc4ef5d0e0;  1 drivers
+L_0xc4e87b610 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f361ea0_0 .net/s "acc_in", 31 0, L_0xc4e87b610;  1 drivers
+v0xc4f361f40_0 .net/s "acc_out", 31 0, L_0xc4f3b6c60;  alias, 1 drivers
+v0xc4f361fe0_0 .net/s "product", 15 0, L_0xc4ef5d040;  1 drivers
+v0xc4f362080_0 .net/s "product_ext", 31 0, L_0xc4f3b6bc0;  1 drivers
+v0xc4f362120_0 .net/s "w", 7 0, L_0xc4f3b2da0;  1 drivers
+v0xc4f3621c0_0 .net/s "x", 7 0, L_0xc4f3b2d00;  1 drivers
+L_0xc4f3b6a80 .extend/s 16, L_0xc4f3b2d00;
+L_0xc4f3b6b20 .extend/s 16, L_0xc4f3b2da0;
+L_0xc4ef5d040 .arith/mult 16, L_0xc4f3b6a80, L_0xc4f3b6b20;
+L_0xc4f3b2c60 .part L_0xc4ef5d040, 15, 1;
+L_0xc4ef5d0e0 .repeat 16, 16, L_0xc4f3b2c60;
+L_0xc4f3b6bc0 .concat [ 16 16 0 0], L_0xc4ef5d040, L_0xc4ef5d0e0;
+L_0xc4f3b6c60 .arith/sum 32, L_0xc4e87b610, L_0xc4f3b6bc0;
+S_0xc4f35d380 .scope generate, "GEN_MAC[9]" "GEN_MAC[9]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335a80 .param/l "i" 1 5 20, +C4<01001>;
+S_0xc4f35d500 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35d380;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f3415c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f341600 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f341640 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f362260_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b6d00;  1 drivers
+v0xc4f362300_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b6da0;  1 drivers
+v0xc4f3623a0_0 .net *"_ivl_7", 0 0, L_0xc4f3b2e40;  1 drivers
+v0xc4f362440_0 .net *"_ivl_9", 15 0, L_0xc4ef5d2c0;  1 drivers
+L_0xc4e87b658 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3624e0_0 .net/s "acc_in", 31 0, L_0xc4e87b658;  1 drivers
+v0xc4f362580_0 .net/s "acc_out", 31 0, L_0xc4f3b6ee0;  alias, 1 drivers
+v0xc4f362620_0 .net/s "product", 15 0, L_0xc4ef5d220;  1 drivers
+v0xc4f3626c0_0 .net/s "product_ext", 31 0, L_0xc4f3b6e40;  1 drivers
+v0xc4f362760_0 .net/s "w", 7 0, L_0xc4f3b2f80;  1 drivers
+v0xc4f362800_0 .net/s "x", 7 0, L_0xc4f3b2ee0;  1 drivers
+L_0xc4f3b6d00 .extend/s 16, L_0xc4f3b2ee0;
+L_0xc4f3b6da0 .extend/s 16, L_0xc4f3b2f80;
+L_0xc4ef5d220 .arith/mult 16, L_0xc4f3b6d00, L_0xc4f3b6da0;
+L_0xc4f3b2e40 .part L_0xc4ef5d220, 15, 1;
+L_0xc4ef5d2c0 .repeat 16, 16, L_0xc4f3b2e40;
+L_0xc4f3b6e40 .concat [ 16 16 0 0], L_0xc4ef5d220, L_0xc4ef5d2c0;
+L_0xc4f3b6ee0 .arith/sum 32, L_0xc4e87b658, L_0xc4f3b6e40;
+S_0xc4f35d680 .scope generate, "GEN_MAC[10]" "GEN_MAC[10]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335ac0 .param/l "i" 1 5 20, +C4<01010>;
+S_0xc4f35d800 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35d680;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f341680 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f3416c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f341700 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f3628a0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b6f80;  1 drivers
+v0xc4f362940_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b7020;  1 drivers
+v0xc4f3629e0_0 .net *"_ivl_7", 0 0, L_0xc4f3b3020;  1 drivers
+v0xc4f362a80_0 .net *"_ivl_9", 15 0, L_0xc4ef5d400;  1 drivers
+L_0xc4e87b6a0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f362b20_0 .net/s "acc_in", 31 0, L_0xc4e87b6a0;  1 drivers
+v0xc4f362bc0_0 .net/s "acc_out", 31 0, L_0xc4f3b7160;  alias, 1 drivers
+v0xc4f362c60_0 .net/s "product", 15 0, L_0xc4ef5d360;  1 drivers
+v0xc4f362d00_0 .net/s "product_ext", 31 0, L_0xc4f3b70c0;  1 drivers
+v0xc4f362da0_0 .net/s "w", 7 0, L_0xc4f3b3160;  1 drivers
+v0xc4f362e40_0 .net/s "x", 7 0, L_0xc4f3b30c0;  1 drivers
+L_0xc4f3b6f80 .extend/s 16, L_0xc4f3b30c0;
+L_0xc4f3b7020 .extend/s 16, L_0xc4f3b3160;
+L_0xc4ef5d360 .arith/mult 16, L_0xc4f3b6f80, L_0xc4f3b7020;
+L_0xc4f3b3020 .part L_0xc4ef5d360, 15, 1;
+L_0xc4ef5d400 .repeat 16, 16, L_0xc4f3b3020;
+L_0xc4f3b70c0 .concat [ 16 16 0 0], L_0xc4ef5d360, L_0xc4ef5d400;
+L_0xc4f3b7160 .arith/sum 32, L_0xc4e87b6a0, L_0xc4f3b70c0;
+S_0xc4f35d980 .scope generate, "GEN_MAC[11]" "GEN_MAC[11]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335b00 .param/l "i" 1 5 20, +C4<01011>;
+S_0xc4f35db00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35d980;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f341740 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f341780 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f3417c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f362ee0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b7200;  1 drivers
+v0xc4f362f80_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b72a0;  1 drivers
+v0xc4f363020_0 .net *"_ivl_7", 0 0, L_0xc4f3b3200;  1 drivers
+v0xc4f3630c0_0 .net *"_ivl_9", 15 0, L_0xc4ef5d4a0;  1 drivers
+L_0xc4e87b6e8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f363160_0 .net/s "acc_in", 31 0, L_0xc4e87b6e8;  1 drivers
+v0xc4f363200_0 .net/s "acc_out", 31 0, L_0xc4f3b73e0;  alias, 1 drivers
+v0xc4f3632a0_0 .net/s "product", 15 0, L_0xc4ef5d180;  1 drivers
+v0xc4f363340_0 .net/s "product_ext", 31 0, L_0xc4f3b7340;  1 drivers
+v0xc4f3633e0_0 .net/s "w", 7 0, L_0xc4f3b3340;  1 drivers
+v0xc4f363480_0 .net/s "x", 7 0, L_0xc4f3b32a0;  1 drivers
+L_0xc4f3b7200 .extend/s 16, L_0xc4f3b32a0;
+L_0xc4f3b72a0 .extend/s 16, L_0xc4f3b3340;
+L_0xc4ef5d180 .arith/mult 16, L_0xc4f3b7200, L_0xc4f3b72a0;
+L_0xc4f3b3200 .part L_0xc4ef5d180, 15, 1;
+L_0xc4ef5d4a0 .repeat 16, 16, L_0xc4f3b3200;
+L_0xc4f3b7340 .concat [ 16 16 0 0], L_0xc4ef5d180, L_0xc4ef5d4a0;
+L_0xc4f3b73e0 .arith/sum 32, L_0xc4e87b6e8, L_0xc4f3b7340;
+S_0xc4f35dc80 .scope generate, "GEN_MAC[12]" "GEN_MAC[12]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335b40 .param/l "i" 1 5 20, +C4<01100>;
+S_0xc4f35de00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35dc80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f341800 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f341840 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f341880 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f363520_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b7480;  1 drivers
+v0xc4f3635c0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b7520;  1 drivers
+v0xc4f363660_0 .net *"_ivl_7", 0 0, L_0xc4f3b33e0;  1 drivers
+v0xc4f363700_0 .net *"_ivl_9", 15 0, L_0xc4ef5d5e0;  1 drivers
+L_0xc4e87b730 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3637a0_0 .net/s "acc_in", 31 0, L_0xc4e87b730;  1 drivers
+v0xc4f363840_0 .net/s "acc_out", 31 0, L_0xc4f3b7660;  alias, 1 drivers
+v0xc4f3638e0_0 .net/s "product", 15 0, L_0xc4ef5d540;  1 drivers
+v0xc4f363980_0 .net/s "product_ext", 31 0, L_0xc4f3b75c0;  1 drivers
+v0xc4f363a20_0 .net/s "w", 7 0, L_0xc4f3b3520;  1 drivers
+v0xc4f363ac0_0 .net/s "x", 7 0, L_0xc4f3b3480;  1 drivers
+L_0xc4f3b7480 .extend/s 16, L_0xc4f3b3480;
+L_0xc4f3b7520 .extend/s 16, L_0xc4f3b3520;
+L_0xc4ef5d540 .arith/mult 16, L_0xc4f3b7480, L_0xc4f3b7520;
+L_0xc4f3b33e0 .part L_0xc4ef5d540, 15, 1;
+L_0xc4ef5d5e0 .repeat 16, 16, L_0xc4f3b33e0;
+L_0xc4f3b75c0 .concat [ 16 16 0 0], L_0xc4ef5d540, L_0xc4ef5d5e0;
+L_0xc4f3b7660 .arith/sum 32, L_0xc4e87b730, L_0xc4f3b75c0;
+S_0xc4f35df80 .scope generate, "GEN_MAC[13]" "GEN_MAC[13]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335b80 .param/l "i" 1 5 20, +C4<01101>;
+S_0xc4f35e100 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35df80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f3418c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f341900 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f341940 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f363b60_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b7700;  1 drivers
+v0xc4f363c00_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b77a0;  1 drivers
+v0xc4f363ca0_0 .net *"_ivl_7", 0 0, L_0xc4f3b35c0;  1 drivers
+v0xc4f363d40_0 .net *"_ivl_9", 15 0, L_0xc4ef5d720;  1 drivers
+L_0xc4e87b778 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f363de0_0 .net/s "acc_in", 31 0, L_0xc4e87b778;  1 drivers
+v0xc4f363e80_0 .net/s "acc_out", 31 0, L_0xc4f3b78e0;  alias, 1 drivers
+v0xc4f363f20_0 .net/s "product", 15 0, L_0xc4ef5d680;  1 drivers
+v0xc4f368000_0 .net/s "product_ext", 31 0, L_0xc4f3b7840;  1 drivers
+v0xc4f3680a0_0 .net/s "w", 7 0, L_0xc4f3b3700;  1 drivers
+v0xc4f368140_0 .net/s "x", 7 0, L_0xc4f3b3660;  1 drivers
+L_0xc4f3b7700 .extend/s 16, L_0xc4f3b3660;
+L_0xc4f3b77a0 .extend/s 16, L_0xc4f3b3700;
+L_0xc4ef5d680 .arith/mult 16, L_0xc4f3b7700, L_0xc4f3b77a0;
+L_0xc4f3b35c0 .part L_0xc4ef5d680, 15, 1;
+L_0xc4ef5d720 .repeat 16, 16, L_0xc4f3b35c0;
+L_0xc4f3b7840 .concat [ 16 16 0 0], L_0xc4ef5d680, L_0xc4ef5d720;
+L_0xc4f3b78e0 .arith/sum 32, L_0xc4e87b778, L_0xc4f3b7840;
+S_0xc4f35e280 .scope generate, "GEN_MAC[14]" "GEN_MAC[14]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335bc0 .param/l "i" 1 5 20, +C4<01110>;
+S_0xc4f35e400 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35e280;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f341980 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f3419c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f341a00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f3681e0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b7980;  1 drivers
+v0xc4f368280_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b7a20;  1 drivers
+v0xc4f368320_0 .net *"_ivl_7", 0 0, L_0xc4f3b37a0;  1 drivers
+v0xc4f3683c0_0 .net *"_ivl_9", 15 0, L_0xc4ef5d860;  1 drivers
+L_0xc4e87b7c0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f368460_0 .net/s "acc_in", 31 0, L_0xc4e87b7c0;  1 drivers
+v0xc4f368500_0 .net/s "acc_out", 31 0, L_0xc4f3b7b60;  alias, 1 drivers
+v0xc4f3685a0_0 .net/s "product", 15 0, L_0xc4ef5d7c0;  1 drivers
+v0xc4f368640_0 .net/s "product_ext", 31 0, L_0xc4f3b7ac0;  1 drivers
+v0xc4f3686e0_0 .net/s "w", 7 0, L_0xc4f3b38e0;  1 drivers
+v0xc4f368780_0 .net/s "x", 7 0, L_0xc4f3b3840;  1 drivers
+L_0xc4f3b7980 .extend/s 16, L_0xc4f3b3840;
+L_0xc4f3b7a20 .extend/s 16, L_0xc4f3b38e0;
+L_0xc4ef5d7c0 .arith/mult 16, L_0xc4f3b7980, L_0xc4f3b7a20;
+L_0xc4f3b37a0 .part L_0xc4ef5d7c0, 15, 1;
+L_0xc4ef5d860 .repeat 16, 16, L_0xc4f3b37a0;
+L_0xc4f3b7ac0 .concat [ 16 16 0 0], L_0xc4ef5d7c0, L_0xc4ef5d860;
+L_0xc4f3b7b60 .arith/sum 32, L_0xc4e87b7c0, L_0xc4f3b7ac0;
+S_0xc4f35e580 .scope generate, "GEN_MAC[15]" "GEN_MAC[15]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335c00 .param/l "i" 1 5 20, +C4<01111>;
+S_0xc4f35e700 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35e580;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f341a40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f341a80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f341ac0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f368820_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b7c00;  1 drivers
+v0xc4f3688c0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b7ca0;  1 drivers
+v0xc4f368960_0 .net *"_ivl_7", 0 0, L_0xc4f3b3980;  1 drivers
+v0xc4f368a00_0 .net *"_ivl_9", 15 0, L_0xc4ef5d9a0;  1 drivers
+L_0xc4e87b808 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f368aa0_0 .net/s "acc_in", 31 0, L_0xc4e87b808;  1 drivers
+v0xc4f368b40_0 .net/s "acc_out", 31 0, L_0xc4f3b7de0;  alias, 1 drivers
+v0xc4f368be0_0 .net/s "product", 15 0, L_0xc4ef5d900;  1 drivers
+v0xc4f368c80_0 .net/s "product_ext", 31 0, L_0xc4f3b7d40;  1 drivers
+v0xc4f368d20_0 .net/s "w", 7 0, L_0xc4f3b3ac0;  1 drivers
+v0xc4f368dc0_0 .net/s "x", 7 0, L_0xc4f3b3a20;  1 drivers
+L_0xc4f3b7c00 .extend/s 16, L_0xc4f3b3a20;
+L_0xc4f3b7ca0 .extend/s 16, L_0xc4f3b3ac0;
+L_0xc4ef5d900 .arith/mult 16, L_0xc4f3b7c00, L_0xc4f3b7ca0;
+L_0xc4f3b3980 .part L_0xc4ef5d900, 15, 1;
+L_0xc4ef5d9a0 .repeat 16, 16, L_0xc4f3b3980;
+L_0xc4f3b7d40 .concat [ 16 16 0 0], L_0xc4ef5d900, L_0xc4ef5d9a0;
+L_0xc4f3b7de0 .arith/sum 32, L_0xc4e87b808, L_0xc4f3b7d40;
+S_0xc4f35e880 .scope generate, "GEN_MAC[16]" "GEN_MAC[16]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335c40 .param/l "i" 1 5 20, +C4<010000>;
+S_0xc4f35ea00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35e880;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f341b00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f341b40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f341b80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f368e60_0 .net/s *"_ivl_0", 15 0, L_0xc4f3b7e80;  1 drivers
+v0xc4f368f00_0 .net/s *"_ivl_2", 15 0, L_0xc4f3b7f20;  1 drivers
+v0xc4f368fa0_0 .net *"_ivl_7", 0 0, L_0xc4f3b3b60;  1 drivers
+v0xc4f369040_0 .net *"_ivl_9", 15 0, L_0xc4ef5dae0;  1 drivers
+L_0xc4e87b850 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3690e0_0 .net/s "acc_in", 31 0, L_0xc4e87b850;  1 drivers
+v0xc4f369180_0 .net/s "acc_out", 31 0, L_0xc4f3bc0a0;  alias, 1 drivers
+v0xc4f369220_0 .net/s "product", 15 0, L_0xc4ef5da40;  1 drivers
+v0xc4f3692c0_0 .net/s "product_ext", 31 0, L_0xc4f3bc000;  1 drivers
+v0xc4f369360_0 .net/s "w", 7 0, L_0xc4f3b3ca0;  1 drivers
+v0xc4f369400_0 .net/s "x", 7 0, L_0xc4f3b3c00;  1 drivers
+L_0xc4f3b7e80 .extend/s 16, L_0xc4f3b3c00;
+L_0xc4f3b7f20 .extend/s 16, L_0xc4f3b3ca0;
+L_0xc4ef5da40 .arith/mult 16, L_0xc4f3b7e80, L_0xc4f3b7f20;
+L_0xc4f3b3b60 .part L_0xc4ef5da40, 15, 1;
+L_0xc4ef5dae0 .repeat 16, 16, L_0xc4f3b3b60;
+L_0xc4f3bc000 .concat [ 16 16 0 0], L_0xc4ef5da40, L_0xc4ef5dae0;
+L_0xc4f3bc0a0 .arith/sum 32, L_0xc4e87b850, L_0xc4f3bc000;
+S_0xc4f35eb80 .scope generate, "GEN_MAC[17]" "GEN_MAC[17]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335c80 .param/l "i" 1 5 20, +C4<010001>;
+S_0xc4f35ed00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35eb80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f341bc0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f341c00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f341c40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f3694a0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3bc140;  1 drivers
+v0xc4f369540_0 .net/s *"_ivl_2", 15 0, L_0xc4f3bc1e0;  1 drivers
+v0xc4f3695e0_0 .net *"_ivl_7", 0 0, L_0xc4f3b3d40;  1 drivers
+v0xc4f369680_0 .net *"_ivl_9", 15 0, L_0xc4ef5dc20;  1 drivers
+L_0xc4e87b898 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f369720_0 .net/s "acc_in", 31 0, L_0xc4e87b898;  1 drivers
+v0xc4f3697c0_0 .net/s "acc_out", 31 0, L_0xc4f3bc320;  alias, 1 drivers
+v0xc4f369860_0 .net/s "product", 15 0, L_0xc4ef5db80;  1 drivers
+v0xc4f369900_0 .net/s "product_ext", 31 0, L_0xc4f3bc280;  1 drivers
+v0xc4f3699a0_0 .net/s "w", 7 0, L_0xc4f3b3e80;  1 drivers
+v0xc4f369a40_0 .net/s "x", 7 0, L_0xc4f3b3de0;  1 drivers
+L_0xc4f3bc140 .extend/s 16, L_0xc4f3b3de0;
+L_0xc4f3bc1e0 .extend/s 16, L_0xc4f3b3e80;
+L_0xc4ef5db80 .arith/mult 16, L_0xc4f3bc140, L_0xc4f3bc1e0;
+L_0xc4f3b3d40 .part L_0xc4ef5db80, 15, 1;
+L_0xc4ef5dc20 .repeat 16, 16, L_0xc4f3b3d40;
+L_0xc4f3bc280 .concat [ 16 16 0 0], L_0xc4ef5db80, L_0xc4ef5dc20;
+L_0xc4f3bc320 .arith/sum 32, L_0xc4e87b898, L_0xc4f3bc280;
+S_0xc4f35ee80 .scope generate, "GEN_MAC[18]" "GEN_MAC[18]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335cc0 .param/l "i" 1 5 20, +C4<010010>;
+S_0xc4f35f000 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35ee80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f341c80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f341cc0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f341d00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f369ae0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3bc3c0;  1 drivers
+v0xc4f369b80_0 .net/s *"_ivl_2", 15 0, L_0xc4f3bc460;  1 drivers
+v0xc4f369c20_0 .net *"_ivl_7", 0 0, L_0xc4f3b3f20;  1 drivers
+v0xc4f369cc0_0 .net *"_ivl_9", 15 0, L_0xc4ef5dd60;  1 drivers
+L_0xc4e87b8e0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f369d60_0 .net/s "acc_in", 31 0, L_0xc4e87b8e0;  1 drivers
+v0xc4f369e00_0 .net/s "acc_out", 31 0, L_0xc4f3bc5a0;  alias, 1 drivers
+v0xc4f369ea0_0 .net/s "product", 15 0, L_0xc4ef5dcc0;  1 drivers
+v0xc4f369f40_0 .net/s "product_ext", 31 0, L_0xc4f3bc500;  1 drivers
+v0xc4f369fe0_0 .net/s "w", 7 0, L_0xc4f3c00a0;  1 drivers
+v0xc4f36a080_0 .net/s "x", 7 0, L_0xc4f3c0000;  1 drivers
+L_0xc4f3bc3c0 .extend/s 16, L_0xc4f3c0000;
+L_0xc4f3bc460 .extend/s 16, L_0xc4f3c00a0;
+L_0xc4ef5dcc0 .arith/mult 16, L_0xc4f3bc3c0, L_0xc4f3bc460;
+L_0xc4f3b3f20 .part L_0xc4ef5dcc0, 15, 1;
+L_0xc4ef5dd60 .repeat 16, 16, L_0xc4f3b3f20;
+L_0xc4f3bc500 .concat [ 16 16 0 0], L_0xc4ef5dcc0, L_0xc4ef5dd60;
+L_0xc4f3bc5a0 .arith/sum 32, L_0xc4e87b8e0, L_0xc4f3bc500;
+S_0xc4f35f180 .scope generate, "GEN_MAC[19]" "GEN_MAC[19]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335d00 .param/l "i" 1 5 20, +C4<010011>;
+S_0xc4f35f300 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35f180;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f341d40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f341d80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f341dc0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f36a120_0 .net/s *"_ivl_0", 15 0, L_0xc4f3bc640;  1 drivers
+v0xc4f36a1c0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3bc6e0;  1 drivers
+v0xc4f36a260_0 .net *"_ivl_7", 0 0, L_0xc4f3c0140;  1 drivers
+v0xc4f36a300_0 .net *"_ivl_9", 15 0, L_0xc4ef5dea0;  1 drivers
+L_0xc4e87b928 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f36a3a0_0 .net/s "acc_in", 31 0, L_0xc4e87b928;  1 drivers
+v0xc4f36a440_0 .net/s "acc_out", 31 0, L_0xc4f3bc820;  alias, 1 drivers
+v0xc4f36a4e0_0 .net/s "product", 15 0, L_0xc4ef5de00;  1 drivers
+v0xc4f36a580_0 .net/s "product_ext", 31 0, L_0xc4f3bc780;  1 drivers
+v0xc4f36a620_0 .net/s "w", 7 0, L_0xc4f3c0280;  1 drivers
+v0xc4f36a6c0_0 .net/s "x", 7 0, L_0xc4f3c01e0;  1 drivers
+L_0xc4f3bc640 .extend/s 16, L_0xc4f3c01e0;
+L_0xc4f3bc6e0 .extend/s 16, L_0xc4f3c0280;
+L_0xc4ef5de00 .arith/mult 16, L_0xc4f3bc640, L_0xc4f3bc6e0;
+L_0xc4f3c0140 .part L_0xc4ef5de00, 15, 1;
+L_0xc4ef5dea0 .repeat 16, 16, L_0xc4f3c0140;
+L_0xc4f3bc780 .concat [ 16 16 0 0], L_0xc4ef5de00, L_0xc4ef5dea0;
+L_0xc4f3bc820 .arith/sum 32, L_0xc4e87b928, L_0xc4f3bc780;
+S_0xc4f35f480 .scope generate, "GEN_MAC[20]" "GEN_MAC[20]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335d40 .param/l "i" 1 5 20, +C4<010100>;
+S_0xc4f35f600 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35f480;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f341e00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f341e40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f341e80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f36a760_0 .net/s *"_ivl_0", 15 0, L_0xc4f3bc8c0;  1 drivers
+v0xc4f36a800_0 .net/s *"_ivl_2", 15 0, L_0xc4f3bc960;  1 drivers
+v0xc4f36a8a0_0 .net *"_ivl_7", 0 0, L_0xc4f3c0320;  1 drivers
+v0xc4f36a940_0 .net *"_ivl_9", 15 0, L_0xc4ef5dfe0;  1 drivers
+L_0xc4e87b970 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f36a9e0_0 .net/s "acc_in", 31 0, L_0xc4e87b970;  1 drivers
+v0xc4f36aa80_0 .net/s "acc_out", 31 0, L_0xc4f3bcaa0;  alias, 1 drivers
+v0xc4f36ab20_0 .net/s "product", 15 0, L_0xc4ef5df40;  1 drivers
+v0xc4f36abc0_0 .net/s "product_ext", 31 0, L_0xc4f3bca00;  1 drivers
+v0xc4f36ac60_0 .net/s "w", 7 0, L_0xc4f3c0460;  1 drivers
+v0xc4f36ad00_0 .net/s "x", 7 0, L_0xc4f3c03c0;  1 drivers
+L_0xc4f3bc8c0 .extend/s 16, L_0xc4f3c03c0;
+L_0xc4f3bc960 .extend/s 16, L_0xc4f3c0460;
+L_0xc4ef5df40 .arith/mult 16, L_0xc4f3bc8c0, L_0xc4f3bc960;
+L_0xc4f3c0320 .part L_0xc4ef5df40, 15, 1;
+L_0xc4ef5dfe0 .repeat 16, 16, L_0xc4f3c0320;
+L_0xc4f3bca00 .concat [ 16 16 0 0], L_0xc4ef5df40, L_0xc4ef5dfe0;
+L_0xc4f3bcaa0 .arith/sum 32, L_0xc4e87b970, L_0xc4f3bca00;
+S_0xc4f35f780 .scope generate, "GEN_MAC[21]" "GEN_MAC[21]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335d80 .param/l "i" 1 5 20, +C4<010101>;
+S_0xc4f35f900 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35f780;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f341ec0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f341f00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f341f40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f36ada0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3bcb40;  1 drivers
+v0xc4f36ae40_0 .net/s *"_ivl_2", 15 0, L_0xc4f3bcbe0;  1 drivers
+v0xc4f36aee0_0 .net *"_ivl_7", 0 0, L_0xc4f3c0500;  1 drivers
+v0xc4f36af80_0 .net *"_ivl_9", 15 0, L_0xc4ef5e120;  1 drivers
+L_0xc4e87b9b8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f36b020_0 .net/s "acc_in", 31 0, L_0xc4e87b9b8;  1 drivers
+v0xc4f36b0c0_0 .net/s "acc_out", 31 0, L_0xc4f3bcd20;  alias, 1 drivers
+v0xc4f36b160_0 .net/s "product", 15 0, L_0xc4ef5e080;  1 drivers
+v0xc4f36b200_0 .net/s "product_ext", 31 0, L_0xc4f3bcc80;  1 drivers
+v0xc4f36b2a0_0 .net/s "w", 7 0, L_0xc4f3c0640;  1 drivers
+v0xc4f36b340_0 .net/s "x", 7 0, L_0xc4f3c05a0;  1 drivers
+L_0xc4f3bcb40 .extend/s 16, L_0xc4f3c05a0;
+L_0xc4f3bcbe0 .extend/s 16, L_0xc4f3c0640;
+L_0xc4ef5e080 .arith/mult 16, L_0xc4f3bcb40, L_0xc4f3bcbe0;
+L_0xc4f3c0500 .part L_0xc4ef5e080, 15, 1;
+L_0xc4ef5e120 .repeat 16, 16, L_0xc4f3c0500;
+L_0xc4f3bcc80 .concat [ 16 16 0 0], L_0xc4ef5e080, L_0xc4ef5e120;
+L_0xc4f3bcd20 .arith/sum 32, L_0xc4e87b9b8, L_0xc4f3bcc80;
+S_0xc4f35fa80 .scope generate, "GEN_MAC[22]" "GEN_MAC[22]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335dc0 .param/l "i" 1 5 20, +C4<010110>;
+S_0xc4f35fc00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35fa80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f341f80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f341fc0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f342000 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f36b3e0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3bcdc0;  1 drivers
+v0xc4f36b480_0 .net/s *"_ivl_2", 15 0, L_0xc4f3bce60;  1 drivers
+v0xc4f36b520_0 .net *"_ivl_7", 0 0, L_0xc4f3c06e0;  1 drivers
+v0xc4f36b5c0_0 .net *"_ivl_9", 15 0, L_0xc4ef5e260;  1 drivers
+L_0xc4e87ba00 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f36b660_0 .net/s "acc_in", 31 0, L_0xc4e87ba00;  1 drivers
+v0xc4f36b700_0 .net/s "acc_out", 31 0, L_0xc4f3bcfa0;  alias, 1 drivers
+v0xc4f36b7a0_0 .net/s "product", 15 0, L_0xc4ef5e1c0;  1 drivers
+v0xc4f36b840_0 .net/s "product_ext", 31 0, L_0xc4f3bcf00;  1 drivers
+v0xc4f36b8e0_0 .net/s "w", 7 0, L_0xc4f3c0820;  1 drivers
+v0xc4f36b980_0 .net/s "x", 7 0, L_0xc4f3c0780;  1 drivers
+L_0xc4f3bcdc0 .extend/s 16, L_0xc4f3c0780;
+L_0xc4f3bce60 .extend/s 16, L_0xc4f3c0820;
+L_0xc4ef5e1c0 .arith/mult 16, L_0xc4f3bcdc0, L_0xc4f3bce60;
+L_0xc4f3c06e0 .part L_0xc4ef5e1c0, 15, 1;
+L_0xc4ef5e260 .repeat 16, 16, L_0xc4f3c06e0;
+L_0xc4f3bcf00 .concat [ 16 16 0 0], L_0xc4ef5e1c0, L_0xc4ef5e260;
+L_0xc4f3bcfa0 .arith/sum 32, L_0xc4e87ba00, L_0xc4f3bcf00;
+S_0xc4f35fd80 .scope generate, "GEN_MAC[23]" "GEN_MAC[23]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335e00 .param/l "i" 1 5 20, +C4<010111>;
+S_0xc4f36c000 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f35fd80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f342040 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f342080 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f3420c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f36ba20_0 .net/s *"_ivl_0", 15 0, L_0xc4f3bd040;  1 drivers
+v0xc4f36bac0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3bd0e0;  1 drivers
+v0xc4f36bb60_0 .net *"_ivl_7", 0 0, L_0xc4f3c08c0;  1 drivers
+v0xc4f36bc00_0 .net *"_ivl_9", 15 0, L_0xc4ef5e3a0;  1 drivers
+L_0xc4e87ba48 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f36bca0_0 .net/s "acc_in", 31 0, L_0xc4e87ba48;  1 drivers
+v0xc4f36bd40_0 .net/s "acc_out", 31 0, L_0xc4f3bd220;  alias, 1 drivers
+v0xc4f36bde0_0 .net/s "product", 15 0, L_0xc4ef5e300;  1 drivers
+v0xc4f36be80_0 .net/s "product_ext", 31 0, L_0xc4f3bd180;  1 drivers
+v0xc4f36bf20_0 .net/s "w", 7 0, L_0xc4f3c0a00;  1 drivers
+v0xc4f370000_0 .net/s "x", 7 0, L_0xc4f3c0960;  1 drivers
+L_0xc4f3bd040 .extend/s 16, L_0xc4f3c0960;
+L_0xc4f3bd0e0 .extend/s 16, L_0xc4f3c0a00;
+L_0xc4ef5e300 .arith/mult 16, L_0xc4f3bd040, L_0xc4f3bd0e0;
+L_0xc4f3c08c0 .part L_0xc4ef5e300, 15, 1;
+L_0xc4ef5e3a0 .repeat 16, 16, L_0xc4f3c08c0;
+L_0xc4f3bd180 .concat [ 16 16 0 0], L_0xc4ef5e300, L_0xc4ef5e3a0;
+L_0xc4f3bd220 .arith/sum 32, L_0xc4e87ba48, L_0xc4f3bd180;
+S_0xc4f36c180 .scope generate, "GEN_MAC[24]" "GEN_MAC[24]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335e40 .param/l "i" 1 5 20, +C4<011000>;
+S_0xc4f36c300 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f36c180;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f342100 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f342140 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f342180 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f3700a0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3bd2c0;  1 drivers
+v0xc4f370140_0 .net/s *"_ivl_2", 15 0, L_0xc4f3bd360;  1 drivers
+v0xc4f3701e0_0 .net *"_ivl_7", 0 0, L_0xc4f3c0aa0;  1 drivers
+v0xc4f370280_0 .net *"_ivl_9", 15 0, L_0xc4ef5e4e0;  1 drivers
+L_0xc4e87ba90 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f370320_0 .net/s "acc_in", 31 0, L_0xc4e87ba90;  1 drivers
+v0xc4f3703c0_0 .net/s "acc_out", 31 0, L_0xc4f3bd4a0;  alias, 1 drivers
+v0xc4f370460_0 .net/s "product", 15 0, L_0xc4ef5e440;  1 drivers
+v0xc4f370500_0 .net/s "product_ext", 31 0, L_0xc4f3bd400;  1 drivers
+v0xc4f3705a0_0 .net/s "w", 7 0, L_0xc4f3c0be0;  1 drivers
+v0xc4f370640_0 .net/s "x", 7 0, L_0xc4f3c0b40;  1 drivers
+L_0xc4f3bd2c0 .extend/s 16, L_0xc4f3c0b40;
+L_0xc4f3bd360 .extend/s 16, L_0xc4f3c0be0;
+L_0xc4ef5e440 .arith/mult 16, L_0xc4f3bd2c0, L_0xc4f3bd360;
+L_0xc4f3c0aa0 .part L_0xc4ef5e440, 15, 1;
+L_0xc4ef5e4e0 .repeat 16, 16, L_0xc4f3c0aa0;
+L_0xc4f3bd400 .concat [ 16 16 0 0], L_0xc4ef5e440, L_0xc4ef5e4e0;
+L_0xc4f3bd4a0 .arith/sum 32, L_0xc4e87ba90, L_0xc4f3bd400;
+S_0xc4f36c480 .scope generate, "GEN_MAC[25]" "GEN_MAC[25]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335e80 .param/l "i" 1 5 20, +C4<011001>;
+S_0xc4f36c600 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f36c480;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f3421c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f342200 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f342240 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f3706e0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3bd540;  1 drivers
+v0xc4f370780_0 .net/s *"_ivl_2", 15 0, L_0xc4f3bd5e0;  1 drivers
+v0xc4f370820_0 .net *"_ivl_7", 0 0, L_0xc4f3c0c80;  1 drivers
+v0xc4f3708c0_0 .net *"_ivl_9", 15 0, L_0xc4ef5e620;  1 drivers
+L_0xc4e87bad8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f370960_0 .net/s "acc_in", 31 0, L_0xc4e87bad8;  1 drivers
+v0xc4f370a00_0 .net/s "acc_out", 31 0, L_0xc4f3bd720;  alias, 1 drivers
+v0xc4f370aa0_0 .net/s "product", 15 0, L_0xc4ef5e580;  1 drivers
+v0xc4f370b40_0 .net/s "product_ext", 31 0, L_0xc4f3bd680;  1 drivers
+v0xc4f370be0_0 .net/s "w", 7 0, L_0xc4f3c0dc0;  1 drivers
+v0xc4f370c80_0 .net/s "x", 7 0, L_0xc4f3c0d20;  1 drivers
+L_0xc4f3bd540 .extend/s 16, L_0xc4f3c0d20;
+L_0xc4f3bd5e0 .extend/s 16, L_0xc4f3c0dc0;
+L_0xc4ef5e580 .arith/mult 16, L_0xc4f3bd540, L_0xc4f3bd5e0;
+L_0xc4f3c0c80 .part L_0xc4ef5e580, 15, 1;
+L_0xc4ef5e620 .repeat 16, 16, L_0xc4f3c0c80;
+L_0xc4f3bd680 .concat [ 16 16 0 0], L_0xc4ef5e580, L_0xc4ef5e620;
+L_0xc4f3bd720 .arith/sum 32, L_0xc4e87bad8, L_0xc4f3bd680;
+S_0xc4f36c780 .scope generate, "GEN_MAC[26]" "GEN_MAC[26]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335ec0 .param/l "i" 1 5 20, +C4<011010>;
+S_0xc4f36c900 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f36c780;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f342280 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f3422c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f342300 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f370d20_0 .net/s *"_ivl_0", 15 0, L_0xc4f3bd7c0;  1 drivers
+v0xc4f370dc0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3bd860;  1 drivers
+v0xc4f370e60_0 .net *"_ivl_7", 0 0, L_0xc4f3c0e60;  1 drivers
+v0xc4f370f00_0 .net *"_ivl_9", 15 0, L_0xc4ef5e760;  1 drivers
+L_0xc4e87bb20 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f370fa0_0 .net/s "acc_in", 31 0, L_0xc4e87bb20;  1 drivers
+v0xc4f371040_0 .net/s "acc_out", 31 0, L_0xc4f3bd9a0;  alias, 1 drivers
+v0xc4f3710e0_0 .net/s "product", 15 0, L_0xc4ef5e6c0;  1 drivers
+v0xc4f371180_0 .net/s "product_ext", 31 0, L_0xc4f3bd900;  1 drivers
+v0xc4f371220_0 .net/s "w", 7 0, L_0xc4f3c0fa0;  1 drivers
+v0xc4f3712c0_0 .net/s "x", 7 0, L_0xc4f3c0f00;  1 drivers
+L_0xc4f3bd7c0 .extend/s 16, L_0xc4f3c0f00;
+L_0xc4f3bd860 .extend/s 16, L_0xc4f3c0fa0;
+L_0xc4ef5e6c0 .arith/mult 16, L_0xc4f3bd7c0, L_0xc4f3bd860;
+L_0xc4f3c0e60 .part L_0xc4ef5e6c0, 15, 1;
+L_0xc4ef5e760 .repeat 16, 16, L_0xc4f3c0e60;
+L_0xc4f3bd900 .concat [ 16 16 0 0], L_0xc4ef5e6c0, L_0xc4ef5e760;
+L_0xc4f3bd9a0 .arith/sum 32, L_0xc4e87bb20, L_0xc4f3bd900;
+S_0xc4f36ca80 .scope generate, "GEN_MAC[27]" "GEN_MAC[27]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335f00 .param/l "i" 1 5 20, +C4<011011>;
+S_0xc4f36cc00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f36ca80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f342340 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f342380 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f3423c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f371360_0 .net/s *"_ivl_0", 15 0, L_0xc4f3bda40;  1 drivers
+v0xc4f371400_0 .net/s *"_ivl_2", 15 0, L_0xc4f3bdae0;  1 drivers
+v0xc4f3714a0_0 .net *"_ivl_7", 0 0, L_0xc4f3c1040;  1 drivers
+v0xc4f371540_0 .net *"_ivl_9", 15 0, L_0xc4ef5e8a0;  1 drivers
+L_0xc4e87bb68 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3715e0_0 .net/s "acc_in", 31 0, L_0xc4e87bb68;  1 drivers
+v0xc4f371680_0 .net/s "acc_out", 31 0, L_0xc4f3bdc20;  alias, 1 drivers
+v0xc4f371720_0 .net/s "product", 15 0, L_0xc4ef5e800;  1 drivers
+v0xc4f3717c0_0 .net/s "product_ext", 31 0, L_0xc4f3bdb80;  1 drivers
+v0xc4f371860_0 .net/s "w", 7 0, L_0xc4f3c1180;  1 drivers
+v0xc4f371900_0 .net/s "x", 7 0, L_0xc4f3c10e0;  1 drivers
+L_0xc4f3bda40 .extend/s 16, L_0xc4f3c10e0;
+L_0xc4f3bdae0 .extend/s 16, L_0xc4f3c1180;
+L_0xc4ef5e800 .arith/mult 16, L_0xc4f3bda40, L_0xc4f3bdae0;
+L_0xc4f3c1040 .part L_0xc4ef5e800, 15, 1;
+L_0xc4ef5e8a0 .repeat 16, 16, L_0xc4f3c1040;
+L_0xc4f3bdb80 .concat [ 16 16 0 0], L_0xc4ef5e800, L_0xc4ef5e8a0;
+L_0xc4f3bdc20 .arith/sum 32, L_0xc4e87bb68, L_0xc4f3bdb80;
+S_0xc4f36cd80 .scope generate, "GEN_MAC[28]" "GEN_MAC[28]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335f40 .param/l "i" 1 5 20, +C4<011100>;
+S_0xc4f36cf00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f36cd80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f342400 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f342440 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f342480 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f3719a0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3bdcc0;  1 drivers
+v0xc4f371a40_0 .net/s *"_ivl_2", 15 0, L_0xc4f3bdd60;  1 drivers
+v0xc4f371ae0_0 .net *"_ivl_7", 0 0, L_0xc4f3c1220;  1 drivers
+v0xc4f371b80_0 .net *"_ivl_9", 15 0, L_0xc4ef5e9e0;  1 drivers
+L_0xc4e87bbb0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f371c20_0 .net/s "acc_in", 31 0, L_0xc4e87bbb0;  1 drivers
+v0xc4f371cc0_0 .net/s "acc_out", 31 0, L_0xc4f3bdea0;  alias, 1 drivers
+v0xc4f371d60_0 .net/s "product", 15 0, L_0xc4ef5e940;  1 drivers
+v0xc4f371e00_0 .net/s "product_ext", 31 0, L_0xc4f3bde00;  1 drivers
+v0xc4f371ea0_0 .net/s "w", 7 0, L_0xc4f3c1360;  1 drivers
+v0xc4f371f40_0 .net/s "x", 7 0, L_0xc4f3c12c0;  1 drivers
+L_0xc4f3bdcc0 .extend/s 16, L_0xc4f3c12c0;
+L_0xc4f3bdd60 .extend/s 16, L_0xc4f3c1360;
+L_0xc4ef5e940 .arith/mult 16, L_0xc4f3bdcc0, L_0xc4f3bdd60;
+L_0xc4f3c1220 .part L_0xc4ef5e940, 15, 1;
+L_0xc4ef5e9e0 .repeat 16, 16, L_0xc4f3c1220;
+L_0xc4f3bde00 .concat [ 16 16 0 0], L_0xc4ef5e940, L_0xc4ef5e9e0;
+L_0xc4f3bdea0 .arith/sum 32, L_0xc4e87bbb0, L_0xc4f3bde00;
+S_0xc4f36d080 .scope generate, "GEN_MAC[29]" "GEN_MAC[29]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335f80 .param/l "i" 1 5 20, +C4<011101>;
+S_0xc4f36d200 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f36d080;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f3424c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f342500 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f342540 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f371fe0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3bdf40;  1 drivers
+v0xc4f372080_0 .net/s *"_ivl_2", 15 0, L_0xc4f3bdfe0;  1 drivers
+v0xc4f372120_0 .net *"_ivl_7", 0 0, L_0xc4f3c1400;  1 drivers
+v0xc4f3721c0_0 .net *"_ivl_9", 15 0, L_0xc4ef5eb20;  1 drivers
+L_0xc4e87bbf8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f372260_0 .net/s "acc_in", 31 0, L_0xc4e87bbf8;  1 drivers
+v0xc4f372300_0 .net/s "acc_out", 31 0, L_0xc4f3be120;  alias, 1 drivers
+v0xc4f3723a0_0 .net/s "product", 15 0, L_0xc4ef5ea80;  1 drivers
+v0xc4f372440_0 .net/s "product_ext", 31 0, L_0xc4f3be080;  1 drivers
+v0xc4f3724e0_0 .net/s "w", 7 0, L_0xc4f3c1540;  1 drivers
+v0xc4f372580_0 .net/s "x", 7 0, L_0xc4f3c14a0;  1 drivers
+L_0xc4f3bdf40 .extend/s 16, L_0xc4f3c14a0;
+L_0xc4f3bdfe0 .extend/s 16, L_0xc4f3c1540;
+L_0xc4ef5ea80 .arith/mult 16, L_0xc4f3bdf40, L_0xc4f3bdfe0;
+L_0xc4f3c1400 .part L_0xc4ef5ea80, 15, 1;
+L_0xc4ef5eb20 .repeat 16, 16, L_0xc4f3c1400;
+L_0xc4f3be080 .concat [ 16 16 0 0], L_0xc4ef5ea80, L_0xc4ef5eb20;
+L_0xc4f3be120 .arith/sum 32, L_0xc4e87bbf8, L_0xc4f3be080;
+S_0xc4f36d380 .scope generate, "GEN_MAC[30]" "GEN_MAC[30]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f335fc0 .param/l "i" 1 5 20, +C4<011110>;
+S_0xc4f36d500 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f36d380;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f342580 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f3425c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f342600 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f372620_0 .net/s *"_ivl_0", 15 0, L_0xc4f3be1c0;  1 drivers
+v0xc4f3726c0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3be260;  1 drivers
+v0xc4f372760_0 .net *"_ivl_7", 0 0, L_0xc4f3c15e0;  1 drivers
+v0xc4f372800_0 .net *"_ivl_9", 15 0, L_0xc4ef5ec60;  1 drivers
+L_0xc4e87bc40 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3728a0_0 .net/s "acc_in", 31 0, L_0xc4e87bc40;  1 drivers
+v0xc4f372940_0 .net/s "acc_out", 31 0, L_0xc4f3be3a0;  alias, 1 drivers
+v0xc4f3729e0_0 .net/s "product", 15 0, L_0xc4ef5ebc0;  1 drivers
+v0xc4f372a80_0 .net/s "product_ext", 31 0, L_0xc4f3be300;  1 drivers
+v0xc4f372b20_0 .net/s "w", 7 0, L_0xc4f3c1720;  1 drivers
+v0xc4f372bc0_0 .net/s "x", 7 0, L_0xc4f3c1680;  1 drivers
+L_0xc4f3be1c0 .extend/s 16, L_0xc4f3c1680;
+L_0xc4f3be260 .extend/s 16, L_0xc4f3c1720;
+L_0xc4ef5ebc0 .arith/mult 16, L_0xc4f3be1c0, L_0xc4f3be260;
+L_0xc4f3c15e0 .part L_0xc4ef5ebc0, 15, 1;
+L_0xc4ef5ec60 .repeat 16, 16, L_0xc4f3c15e0;
+L_0xc4f3be300 .concat [ 16 16 0 0], L_0xc4ef5ebc0, L_0xc4ef5ec60;
+L_0xc4f3be3a0 .arith/sum 32, L_0xc4e87bc40, L_0xc4f3be300;
+S_0xc4f36d680 .scope generate, "GEN_MAC[31]" "GEN_MAC[31]" 5 20, 5 20 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336000 .param/l "i" 1 5 20, +C4<011111>;
+S_0xc4f36d800 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f36d680;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f342640 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f342680 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f3426c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f372c60_0 .net/s *"_ivl_0", 15 0, L_0xc4f3be440;  1 drivers
+v0xc4f372d00_0 .net/s *"_ivl_2", 15 0, L_0xc4f3be4e0;  1 drivers
+v0xc4f372da0_0 .net *"_ivl_7", 0 0, L_0xc4f3c17c0;  1 drivers
+v0xc4f372e40_0 .net *"_ivl_9", 15 0, L_0xc4ef5eda0;  1 drivers
+L_0xc4e87bc88 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f372ee0_0 .net/s "acc_in", 31 0, L_0xc4e87bc88;  1 drivers
+v0xc4f372f80_0 .net/s "acc_out", 31 0, L_0xc4f3be620;  alias, 1 drivers
+v0xc4f373020_0 .net/s "product", 15 0, L_0xc4ef5ed00;  1 drivers
+v0xc4f3730c0_0 .net/s "product_ext", 31 0, L_0xc4f3be580;  1 drivers
+v0xc4f373160_0 .net/s "w", 7 0, L_0xc4f3c1900;  1 drivers
+v0xc4f373200_0 .net/s "x", 7 0, L_0xc4f3c1860;  1 drivers
+L_0xc4f3be440 .extend/s 16, L_0xc4f3c1860;
+L_0xc4f3be4e0 .extend/s 16, L_0xc4f3c1900;
+L_0xc4ef5ed00 .arith/mult 16, L_0xc4f3be440, L_0xc4f3be4e0;
+L_0xc4f3c17c0 .part L_0xc4ef5ed00, 15, 1;
+L_0xc4ef5eda0 .repeat 16, 16, L_0xc4f3c17c0;
+L_0xc4f3be580 .concat [ 16 16 0 0], L_0xc4ef5ed00, L_0xc4ef5eda0;
+L_0xc4f3be620 .arith/sum 32, L_0xc4e87bc88, L_0xc4f3be580;
+S_0xc4f36d980 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336040 .param/l "i" 1 5 80, +C4<00>;
+L_0xc4f3a8e00 .functor BUFZ 32, L_0xc4f3b5860, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36db00 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336080 .param/l "i" 1 5 80, +C4<01>;
+L_0xc4f3a8e70 .functor BUFZ 32, L_0xc4f3b5ae0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36dc80 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f3360c0 .param/l "i" 1 5 80, +C4<010>;
+L_0xc4f3a8ee0 .functor BUFZ 32, L_0xc4f3b5d60, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36de00 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336100 .param/l "i" 1 5 80, +C4<011>;
+L_0xc4f3a8f50 .functor BUFZ 32, L_0xc4f3b5fe0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36df80 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336140 .param/l "i" 1 5 80, +C4<0100>;
+L_0xc4f3a8fc0 .functor BUFZ 32, L_0xc4f3b6260, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36e100 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336180 .param/l "i" 1 5 80, +C4<0101>;
+L_0xc4f3a9030 .functor BUFZ 32, L_0xc4f3b64e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36e280 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f3361c0 .param/l "i" 1 5 80, +C4<0110>;
+L_0xc4f3a90a0 .functor BUFZ 32, L_0xc4f3b6760, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36e400 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336200 .param/l "i" 1 5 80, +C4<0111>;
+L_0xc4f3a9110 .functor BUFZ 32, L_0xc4f3b69e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36e580 .scope generate, "GEN_TREE_INPUT[8]" "GEN_TREE_INPUT[8]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336240 .param/l "i" 1 5 80, +C4<01000>;
+L_0xc4f3a9180 .functor BUFZ 32, L_0xc4f3b6c60, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36e700 .scope generate, "GEN_TREE_INPUT[9]" "GEN_TREE_INPUT[9]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336280 .param/l "i" 1 5 80, +C4<01001>;
+L_0xc4f3a91f0 .functor BUFZ 32, L_0xc4f3b6ee0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36e880 .scope generate, "GEN_TREE_INPUT[10]" "GEN_TREE_INPUT[10]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f3362c0 .param/l "i" 1 5 80, +C4<01010>;
+L_0xc4f3a9260 .functor BUFZ 32, L_0xc4f3b7160, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36ea00 .scope generate, "GEN_TREE_INPUT[11]" "GEN_TREE_INPUT[11]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336300 .param/l "i" 1 5 80, +C4<01011>;
+L_0xc4f3a92d0 .functor BUFZ 32, L_0xc4f3b73e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36eb80 .scope generate, "GEN_TREE_INPUT[12]" "GEN_TREE_INPUT[12]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336340 .param/l "i" 1 5 80, +C4<01100>;
+L_0xc4f3a9340 .functor BUFZ 32, L_0xc4f3b7660, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36ed00 .scope generate, "GEN_TREE_INPUT[13]" "GEN_TREE_INPUT[13]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336380 .param/l "i" 1 5 80, +C4<01101>;
+L_0xc4f3a93b0 .functor BUFZ 32, L_0xc4f3b78e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36ee80 .scope generate, "GEN_TREE_INPUT[14]" "GEN_TREE_INPUT[14]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f3363c0 .param/l "i" 1 5 80, +C4<01110>;
+L_0xc4f3a9420 .functor BUFZ 32, L_0xc4f3b7b60, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36f000 .scope generate, "GEN_TREE_INPUT[15]" "GEN_TREE_INPUT[15]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336400 .param/l "i" 1 5 80, +C4<01111>;
+L_0xc4f3a9490 .functor BUFZ 32, L_0xc4f3b7de0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36f180 .scope generate, "GEN_TREE_INPUT[16]" "GEN_TREE_INPUT[16]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336440 .param/l "i" 1 5 80, +C4<010000>;
+L_0xc4f3a9500 .functor BUFZ 32, L_0xc4f3bc0a0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36f300 .scope generate, "GEN_TREE_INPUT[17]" "GEN_TREE_INPUT[17]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336480 .param/l "i" 1 5 80, +C4<010001>;
+L_0xc4f3a9570 .functor BUFZ 32, L_0xc4f3bc320, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36f480 .scope generate, "GEN_TREE_INPUT[18]" "GEN_TREE_INPUT[18]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f3364c0 .param/l "i" 1 5 80, +C4<010010>;
+L_0xc4f3a95e0 .functor BUFZ 32, L_0xc4f3bc5a0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36f600 .scope generate, "GEN_TREE_INPUT[19]" "GEN_TREE_INPUT[19]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336500 .param/l "i" 1 5 80, +C4<010011>;
+L_0xc4f3a9650 .functor BUFZ 32, L_0xc4f3bc820, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36f780 .scope generate, "GEN_TREE_INPUT[20]" "GEN_TREE_INPUT[20]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336540 .param/l "i" 1 5 80, +C4<010100>;
+L_0xc4f3a96c0 .functor BUFZ 32, L_0xc4f3bcaa0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36f900 .scope generate, "GEN_TREE_INPUT[21]" "GEN_TREE_INPUT[21]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336580 .param/l "i" 1 5 80, +C4<010101>;
+L_0xc4f3a9730 .functor BUFZ 32, L_0xc4f3bcd20, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36fa80 .scope generate, "GEN_TREE_INPUT[22]" "GEN_TREE_INPUT[22]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f3365c0 .param/l "i" 1 5 80, +C4<010110>;
+L_0xc4f3a97a0 .functor BUFZ 32, L_0xc4f3bcfa0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36fc00 .scope generate, "GEN_TREE_INPUT[23]" "GEN_TREE_INPUT[23]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336600 .param/l "i" 1 5 80, +C4<010111>;
+L_0xc4f3a9810 .functor BUFZ 32, L_0xc4f3bd220, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f36fd80 .scope generate, "GEN_TREE_INPUT[24]" "GEN_TREE_INPUT[24]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336640 .param/l "i" 1 5 80, +C4<011000>;
+L_0xc4f3a9880 .functor BUFZ 32, L_0xc4f3bd4a0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f374000 .scope generate, "GEN_TREE_INPUT[25]" "GEN_TREE_INPUT[25]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336680 .param/l "i" 1 5 80, +C4<011001>;
+L_0xc4f3a98f0 .functor BUFZ 32, L_0xc4f3bd720, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f374180 .scope generate, "GEN_TREE_INPUT[26]" "GEN_TREE_INPUT[26]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f3366c0 .param/l "i" 1 5 80, +C4<011010>;
+L_0xc4f3a9960 .functor BUFZ 32, L_0xc4f3bd9a0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f374300 .scope generate, "GEN_TREE_INPUT[27]" "GEN_TREE_INPUT[27]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336700 .param/l "i" 1 5 80, +C4<011011>;
+L_0xc4f3a99d0 .functor BUFZ 32, L_0xc4f3bdc20, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f374480 .scope generate, "GEN_TREE_INPUT[28]" "GEN_TREE_INPUT[28]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336740 .param/l "i" 1 5 80, +C4<011100>;
+L_0xc4f3a9a40 .functor BUFZ 32, L_0xc4f3bdea0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f374600 .scope generate, "GEN_TREE_INPUT[29]" "GEN_TREE_INPUT[29]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336780 .param/l "i" 1 5 80, +C4<011101>;
+L_0xc4f3a9ab0 .functor BUFZ 32, L_0xc4f3be120, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f374780 .scope generate, "GEN_TREE_INPUT[30]" "GEN_TREE_INPUT[30]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f3367c0 .param/l "i" 1 5 80, +C4<011110>;
+L_0xc4f3a9b20 .functor BUFZ 32, L_0xc4f3be3a0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f374900 .scope generate, "GEN_TREE_INPUT[31]" "GEN_TREE_INPUT[31]" 5 80, 5 80 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336800 .param/l "i" 1 5 80, +C4<011111>;
+L_0xc4f3a9b90 .functor BUFZ 32, L_0xc4f3be620, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f374a80 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336840 .param/l "level" 1 5 92, +C4<00>;
+S_0xc4f374c00 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f374a80;
+ .timescale 0 0;
+P_0xc4f336880 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3be6c0 .arith/sum 32, L_0xc4f3a8e00, L_0xc4f3a8e70;
+S_0xc4f374d80 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f374a80;
+ .timescale 0 0;
+P_0xc4f3368c0 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3be760 .arith/sum 32, L_0xc4f3a8ee0, L_0xc4f3a8f50;
+S_0xc4f374f00 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xc4f374a80;
+ .timescale 0 0;
+P_0xc4f336900 .param/l "node" 1 5 94, +C4<010>;
+L_0xc4f3be800 .arith/sum 32, L_0xc4f3a8fc0, L_0xc4f3a9030;
+S_0xc4f375080 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xc4f374a80;
+ .timescale 0 0;
+P_0xc4f336940 .param/l "node" 1 5 94, +C4<011>;
+L_0xc4f3be8a0 .arith/sum 32, L_0xc4f3a90a0, L_0xc4f3a9110;
+S_0xc4f375200 .scope generate, "GEN_TREE_NODE[4]" "GEN_TREE_NODE[4]" 5 94, 5 94 0, S_0xc4f374a80;
+ .timescale 0 0;
+P_0xc4f3369c0 .param/l "node" 1 5 94, +C4<0100>;
+L_0xc4f3be940 .arith/sum 32, L_0xc4f3a9180, L_0xc4f3a91f0;
+S_0xc4f375380 .scope generate, "GEN_TREE_NODE[5]" "GEN_TREE_NODE[5]" 5 94, 5 94 0, S_0xc4f374a80;
+ .timescale 0 0;
+P_0xc4f336a00 .param/l "node" 1 5 94, +C4<0101>;
+L_0xc4f3be9e0 .arith/sum 32, L_0xc4f3a9260, L_0xc4f3a92d0;
+S_0xc4f375500 .scope generate, "GEN_TREE_NODE[6]" "GEN_TREE_NODE[6]" 5 94, 5 94 0, S_0xc4f374a80;
+ .timescale 0 0;
+P_0xc4f336a40 .param/l "node" 1 5 94, +C4<0110>;
+L_0xc4f3bea80 .arith/sum 32, L_0xc4f3a9340, L_0xc4f3a93b0;
+S_0xc4f375680 .scope generate, "GEN_TREE_NODE[7]" "GEN_TREE_NODE[7]" 5 94, 5 94 0, S_0xc4f374a80;
+ .timescale 0 0;
+P_0xc4f336a80 .param/l "node" 1 5 94, +C4<0111>;
+L_0xc4f3beb20 .arith/sum 32, L_0xc4f3a9420, L_0xc4f3a9490;
+S_0xc4f375800 .scope generate, "GEN_TREE_NODE[8]" "GEN_TREE_NODE[8]" 5 94, 5 94 0, S_0xc4f374a80;
+ .timescale 0 0;
+P_0xc4f336980 .param/l "node" 1 5 94, +C4<01000>;
+L_0xc4f3bebc0 .arith/sum 32, L_0xc4f3a9500, L_0xc4f3a9570;
+S_0xc4f375980 .scope generate, "GEN_TREE_NODE[9]" "GEN_TREE_NODE[9]" 5 94, 5 94 0, S_0xc4f374a80;
+ .timescale 0 0;
+P_0xc4f336ac0 .param/l "node" 1 5 94, +C4<01001>;
+L_0xc4f3bec60 .arith/sum 32, L_0xc4f3a95e0, L_0xc4f3a9650;
+S_0xc4f375b00 .scope generate, "GEN_TREE_NODE[10]" "GEN_TREE_NODE[10]" 5 94, 5 94 0, S_0xc4f374a80;
+ .timescale 0 0;
+P_0xc4f336b00 .param/l "node" 1 5 94, +C4<01010>;
+L_0xc4f3bed00 .arith/sum 32, L_0xc4f3a96c0, L_0xc4f3a9730;
+S_0xc4f375c80 .scope generate, "GEN_TREE_NODE[11]" "GEN_TREE_NODE[11]" 5 94, 5 94 0, S_0xc4f374a80;
+ .timescale 0 0;
+P_0xc4f336b40 .param/l "node" 1 5 94, +C4<01011>;
+L_0xc4f3beda0 .arith/sum 32, L_0xc4f3a97a0, L_0xc4f3a9810;
+S_0xc4f375e00 .scope generate, "GEN_TREE_NODE[12]" "GEN_TREE_NODE[12]" 5 94, 5 94 0, S_0xc4f374a80;
+ .timescale 0 0;
+P_0xc4f336b80 .param/l "node" 1 5 94, +C4<01100>;
+L_0xc4f3bee40 .arith/sum 32, L_0xc4f3a9880, L_0xc4f3a98f0;
+S_0xc4f375f80 .scope generate, "GEN_TREE_NODE[13]" "GEN_TREE_NODE[13]" 5 94, 5 94 0, S_0xc4f374a80;
+ .timescale 0 0;
+P_0xc4f336bc0 .param/l "node" 1 5 94, +C4<01101>;
+L_0xc4f3beee0 .arith/sum 32, L_0xc4f3a9960, L_0xc4f3a99d0;
+S_0xc4f376100 .scope generate, "GEN_TREE_NODE[14]" "GEN_TREE_NODE[14]" 5 94, 5 94 0, S_0xc4f374a80;
+ .timescale 0 0;
+P_0xc4f336c00 .param/l "node" 1 5 94, +C4<01110>;
+L_0xc4f3bef80 .arith/sum 32, L_0xc4f3a9a40, L_0xc4f3a9ab0;
+S_0xc4f376280 .scope generate, "GEN_TREE_NODE[15]" "GEN_TREE_NODE[15]" 5 94, 5 94 0, S_0xc4f374a80;
+ .timescale 0 0;
+P_0xc4f336c40 .param/l "node" 1 5 94, +C4<01111>;
+L_0xc4f3bf020 .arith/sum 32, L_0xc4f3a9b20, L_0xc4f3a9b90;
+S_0xc4f376400 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336c80 .param/l "level" 1 5 92, +C4<01>;
+S_0xc4f376580 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f376400;
+ .timescale 0 0;
+P_0xc4f336cc0 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3bf0c0 .arith/sum 32, L_0xc4f3be6c0, L_0xc4f3be760;
+S_0xc4f376700 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f376400;
+ .timescale 0 0;
+P_0xc4f336d00 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3bf160 .arith/sum 32, L_0xc4f3be800, L_0xc4f3be8a0;
+S_0xc4f376880 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xc4f376400;
+ .timescale 0 0;
+P_0xc4f336d40 .param/l "node" 1 5 94, +C4<010>;
+L_0xc4f3bf200 .arith/sum 32, L_0xc4f3be940, L_0xc4f3be9e0;
+S_0xc4f376a00 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xc4f376400;
+ .timescale 0 0;
+P_0xc4f336d80 .param/l "node" 1 5 94, +C4<011>;
+L_0xc4f3bf2a0 .arith/sum 32, L_0xc4f3bea80, L_0xc4f3beb20;
+S_0xc4f376b80 .scope generate, "GEN_TREE_NODE[4]" "GEN_TREE_NODE[4]" 5 94, 5 94 0, S_0xc4f376400;
+ .timescale 0 0;
+P_0xc4f336e00 .param/l "node" 1 5 94, +C4<0100>;
+L_0xc4f3bf340 .arith/sum 32, L_0xc4f3bebc0, L_0xc4f3bec60;
+S_0xc4f376d00 .scope generate, "GEN_TREE_NODE[5]" "GEN_TREE_NODE[5]" 5 94, 5 94 0, S_0xc4f376400;
+ .timescale 0 0;
+P_0xc4f336e40 .param/l "node" 1 5 94, +C4<0101>;
+L_0xc4f3bf3e0 .arith/sum 32, L_0xc4f3bed00, L_0xc4f3beda0;
+S_0xc4f376e80 .scope generate, "GEN_TREE_NODE[6]" "GEN_TREE_NODE[6]" 5 94, 5 94 0, S_0xc4f376400;
+ .timescale 0 0;
+P_0xc4f336e80 .param/l "node" 1 5 94, +C4<0110>;
+L_0xc4f3bf480 .arith/sum 32, L_0xc4f3bee40, L_0xc4f3beee0;
+S_0xc4f377000 .scope generate, "GEN_TREE_NODE[7]" "GEN_TREE_NODE[7]" 5 94, 5 94 0, S_0xc4f376400;
+ .timescale 0 0;
+P_0xc4f336ec0 .param/l "node" 1 5 94, +C4<0111>;
+L_0xc4f3bf520 .arith/sum 32, L_0xc4f3bef80, L_0xc4f3bf020;
+S_0xc4f377180 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f336f00 .param/l "level" 1 5 92, +C4<010>;
+S_0xc4f377300 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f377180;
+ .timescale 0 0;
+P_0xc4f336f40 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3bf5c0 .arith/sum 32, L_0xc4f3bf0c0, L_0xc4f3bf160;
+S_0xc4f377480 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f377180;
+ .timescale 0 0;
+P_0xc4f336f80 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3bf660 .arith/sum 32, L_0xc4f3bf200, L_0xc4f3bf2a0;
+S_0xc4f377600 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xc4f377180;
+ .timescale 0 0;
+P_0xc4f336fc0 .param/l "node" 1 5 94, +C4<010>;
+L_0xc4f3bf700 .arith/sum 32, L_0xc4f3bf340, L_0xc4f3bf3e0;
+S_0xc4f377780 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xc4f377180;
+ .timescale 0 0;
+P_0xc4f337000 .param/l "node" 1 5 94, +C4<011>;
+L_0xc4f3bf7a0 .arith/sum 32, L_0xc4f3bf480, L_0xc4f3bf520;
+S_0xc4f377900 .scope generate, "GEN_TREE_LEVEL[3]" "GEN_TREE_LEVEL[3]" 5 92, 5 92 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f337040 .param/l "level" 1 5 92, +C4<011>;
+S_0xc4f377a80 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f377900;
+ .timescale 0 0;
+P_0xc4f337080 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3bf840 .arith/sum 32, L_0xc4f3bf5c0, L_0xc4f3bf660;
+S_0xc4f377c00 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f377900;
+ .timescale 0 0;
+P_0xc4f3370c0 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3bf8e0 .arith/sum 32, L_0xc4f3bf700, L_0xc4f3bf7a0;
+S_0xc4f377d80 .scope generate, "GEN_TREE_LEVEL[4]" "GEN_TREE_LEVEL[4]" 5 92, 5 92 0, S_0xc4f357600;
+ .timescale 0 0;
+P_0xc4f337100 .param/l "level" 1 5 92, +C4<0100>;
+S_0xc4f378000 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f377d80;
+ .timescale 0 0;
+P_0xc4f337140 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3bf980 .arith/sum 32, L_0xc4f3bf840, L_0xc4f3bf8e0;
+S_0xc4f378180 .scope module, "u_e" "neuron_parallel" 12 171, 4 1 0, S_0x102d15030;
+ .timescale -9 -12;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 1 "start";
+    .port_info 3 /INPUT 32 "x_bus";
+    .port_info 4 /INPUT 32 "w_bus";
+    .port_info 5 /INPUT 8 "bias";
+    .port_info 6 /OUTPUT 8 "y";
+    .port_info 7 /OUTPUT 1 "busy";
+    .port_info 8 /OUTPUT 1 "done";
+P_0xc4ef2c480 .param/l "ACC_WIDTH" 0 4 5, +C4<00000000000000000000000000100000>;
+P_0xc4ef2c4c0 .param/l "DATA_WIDTH" 0 4 2, +C4<00000000000000000000000000001000>;
+P_0xc4ef2c500 .param/l "GROUPS" 1 4 20, +C4<00000000000000000000000000000000>;
+P_0xc4ef2c540 .param/l "GROUP_INDEX_WIDTH" 1 4 21, +C4<00000000000000000000000000000001>;
+P_0xc4ef2c580 .param/l "N_INPUTS" 0 4 3, +C4<00000000000000000000000000000100>;
+P_0xc4ef2c5c0 .param/l "PARALLEL" 0 4 4, +C4<00000000000000000000000000001000>;
+v0xc4f383f20_0 .net *"_ivl_0", 31 0, L_0xc4f3bfc00;  1 drivers
+v0xc4f384000_0 .net *"_ivl_11", 31 0, L_0xc4ef5ef80;  1 drivers
+v0xc4f3840a0_0 .net *"_ivl_14", 31 0, L_0xc4f3bfca0;  1 drivers
+L_0xc4e87bda8 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f384140_0 .net *"_ivl_17", 30 0, L_0xc4e87bda8;  1 drivers
+L_0xc4e87bdf0 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3841e0_0 .net/2u *"_ivl_18", 31 0, L_0xc4e87bdf0;  1 drivers
+v0xc4f384280_0 .net *"_ivl_21", 31 0, L_0xc4ef5f020;  1 drivers
+L_0xc4e87be38 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f384320_0 .net/2u *"_ivl_22", 31 0, L_0xc4e87be38;  1 drivers
+v0xc4f3843c0_0 .net *"_ivl_25", 31 0, L_0xc4ef5f0c0;  1 drivers
+v0xc4f384460_0 .net *"_ivl_29", 0 0, L_0xc4f3c2a80;  1 drivers
+L_0xc4e87bcd0 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f384500_0 .net *"_ivl_3", 30 0, L_0xc4e87bcd0;  1 drivers
+v0xc4f3845a0_0 .net *"_ivl_31", 23 0, L_0xc4ef5fc00;  1 drivers
+L_0xc4e87bd18 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f384640_0 .net/2u *"_ivl_4", 31 0, L_0xc4e87bd18;  1 drivers
+v0xc4f3846e0_0 .net *"_ivl_7", 31 0, L_0xc4ef5eee0;  1 drivers
+L_0xc4e87bd60 .functor BUFT 1, C4<00000000000000000000000000001000>, C4<0>, C4<0>, C4<0>;
+v0xc4f384780_0 .net/2u *"_ivl_8", 31 0, L_0xc4e87bd60;  1 drivers
+v0xc4f384820_0 .var/s "acc", 31 0;
+v0xc4f3848c0_0 .net/s "acc_next", 31 0, L_0xc4f3c55e0;  1 drivers
+v0xc4f384960_0 .net/s "bias", 7 0, v0xc4f3854a0_0;  1 drivers
+v0xc4f384a00_0 .net/s "bias_ext", 31 0, L_0xc4f3c5680;  1 drivers
+v0xc4f384aa0_0 .var "busy", 0 0;
+v0xc4f384b40_0 .net "clk", 0 0, v0xc4f385860_0;  alias, 1 drivers
+v0xc4f384be0_0 .var "done", 0 0;
+v0xc4f384c80_0 .net/s "final_acc", 31 0, L_0xc4f3c5720;  1 drivers
+v0xc4f384d20_0 .var "group_index", 0 0;
+v0xc4f384dc0_0 .net "rst", 0 0, v0xc4f385ea0_0;  alias, 1 drivers
+v0xc4f384e60_0 .net "start", 0 0, v0xc4f3861c0_0;  1 drivers
+v0xc4f384f00_0 .net/s "w_bus", 31 0, v0xc4f386580_0;  1 drivers
+v0xc4f384fa0_0 .net/s "w_group", 63 0, L_0xc4f3c1ae0;  1 drivers
+v0xc4f385040_0 .net/s "x_bus", 31 0, v0xc4f3868a0_0;  1 drivers
+v0xc4f3850e0_0 .net/s "x_group", 63 0, L_0xc4f3c1a40;  1 drivers
+v0xc4f385180_0 .var/s "y", 7 0;
+L_0xc4f3bfc00 .concat [ 1 31 0 0], v0xc4f384d20_0, L_0xc4e87bcd0;
+L_0xc4ef5eee0 .arith/mult 32, L_0xc4f3bfc00, L_0xc4e87bd18;
+L_0xc4ef5ef80 .arith/mult 32, L_0xc4ef5eee0, L_0xc4e87bd60;
+L_0xc4f3c1a40 .part/v v0xc4f3868a0_0, L_0xc4ef5ef80, 64;
+L_0xc4f3bfca0 .concat [ 1 31 0 0], v0xc4f384d20_0, L_0xc4e87bda8;
+L_0xc4ef5f020 .arith/mult 32, L_0xc4f3bfca0, L_0xc4e87bdf0;
+L_0xc4ef5f0c0 .arith/mult 32, L_0xc4ef5f020, L_0xc4e87be38;
+L_0xc4f3c1ae0 .part/v v0xc4f386580_0, L_0xc4ef5f0c0, 64;
+L_0xc4f3c2a80 .part v0xc4f3854a0_0, 7, 1;
+L_0xc4ef5fc00 .repeat 24, 24, L_0xc4f3c2a80;
+L_0xc4f3c5680 .concat [ 8 24 0 0], v0xc4f3854a0_0, L_0xc4ef5fc00;
+L_0xc4f3c5720 .arith/sum 32, L_0xc4f3c55e0, L_0xc4f3c5680;
+S_0xc4f378300 .scope module, "u_mac8" "mac8" 4 52, 5 1 0, S_0xc4f378180;
+ .timescale 0 0;
+    .port_info 0 /INPUT 64 "x_bus";
+    .port_info 1 /INPUT 64 "w_bus";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4ef0e800 .param/l "ACC_WIDTH" 0 5 3, +C4<00000000000000000000000000100000>;
+P_0xc4ef0e840 .param/l "DATA_WIDTH" 0 5 2, +C4<00000000000000000000000000001000>;
+P_0xc4ef0e880 .param/l "PARALLEL" 0 5 4, +C4<00000000000000000000000000001000>;
+P_0xc4ef0e8c0 .param/l "TREE_LEVELS" 1 5 70, +C4<00000000000000000000000000000011>;
+v0xc4f383b60_0 .net/s "acc_in", 31 0, v0xc4f384820_0;  1 drivers
+v0xc4f383c00_0 .net/s "acc_out", 31 0, L_0xc4f3c55e0;  alias, 1 drivers
+v0xc4f383ca0 .array "products", 7 0;
+v0xc4f383ca0_0 .net/s v0xc4f383ca0 0, 31 0, L_0xc4f3bff20; 1 drivers
+v0xc4f383ca0_1 .net/s v0xc4f383ca0 1, 31 0, L_0xc4f3c41e0; 1 drivers
+v0xc4f383ca0_2 .net/s v0xc4f383ca0 2, 31 0, L_0xc4f3c4460; 1 drivers
+v0xc4f383ca0_3 .net/s v0xc4f383ca0 3, 31 0, L_0xc4f3c46e0; 1 drivers
+v0xc4f383ca0_4 .net/s v0xc4f383ca0 4, 31 0, L_0xc4f3c4960; 1 drivers
+v0xc4f383ca0_5 .net/s v0xc4f383ca0 5, 31 0, L_0xc4f3c4be0; 1 drivers
+v0xc4f383ca0_6 .net/s v0xc4f383ca0 6, 31 0, L_0xc4f3c4e60; 1 drivers
+v0xc4f383ca0_7 .net/s v0xc4f383ca0 7, 31 0, L_0xc4f3c50e0; 1 drivers
+v0xc4f383d40 .array "tree", 31 0;
+v0xc4f383d40_0 .net/s v0xc4f383d40 0, 31 0, L_0xc4f3a9c00; 1 drivers
+v0xc4f383d40_1 .net/s v0xc4f383d40 1, 31 0, L_0xc4f3a9c70; 1 drivers
+v0xc4f383d40_2 .net/s v0xc4f383d40 2, 31 0, L_0xc4f3a9ce0; 1 drivers
+v0xc4f383d40_3 .net/s v0xc4f383d40 3, 31 0, L_0xc4f3a9d50; 1 drivers
+v0xc4f383d40_4 .net/s v0xc4f383d40 4, 31 0, L_0xc4f3a9dc0; 1 drivers
+v0xc4f383d40_5 .net/s v0xc4f383d40 5, 31 0, L_0xc4f3a9e30; 1 drivers
+v0xc4f383d40_6 .net/s v0xc4f383d40 6, 31 0, L_0xc4f3a9ea0; 1 drivers
+v0xc4f383d40_7 .net/s v0xc4f383d40 7, 31 0, L_0xc4f3a9f10; 1 drivers
+v0xc4f383d40_8 .net/s v0xc4f383d40 8, 31 0, L_0xc4f3c5180; 1 drivers
+v0xc4f383d40_9 .net/s v0xc4f383d40 9, 31 0, L_0xc4f3c5220; 1 drivers
+v0xc4f383d40_10 .net/s v0xc4f383d40 10, 31 0, L_0xc4f3c52c0; 1 drivers
+v0xc4f383d40_11 .net/s v0xc4f383d40 11, 31 0, L_0xc4f3c5360; 1 drivers
+o0xc4e86cf30 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f383d40_12 .net/s v0xc4f383d40 12, 31 0, o0xc4e86cf30; 0 drivers
+o0xc4e86cf60 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f383d40_13 .net/s v0xc4f383d40 13, 31 0, o0xc4e86cf60; 0 drivers
+o0xc4e86cf90 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f383d40_14 .net/s v0xc4f383d40 14, 31 0, o0xc4e86cf90; 0 drivers
+o0xc4e86cfc0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f383d40_15 .net/s v0xc4f383d40 15, 31 0, o0xc4e86cfc0; 0 drivers
+v0xc4f383d40_16 .net/s v0xc4f383d40 16, 31 0, L_0xc4f3c5400; 1 drivers
+v0xc4f383d40_17 .net/s v0xc4f383d40 17, 31 0, L_0xc4f3c54a0; 1 drivers
+o0xc4e86d050 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f383d40_18 .net/s v0xc4f383d40 18, 31 0, o0xc4e86d050; 0 drivers
+o0xc4e86d080 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f383d40_19 .net/s v0xc4f383d40 19, 31 0, o0xc4e86d080; 0 drivers
+o0xc4e86d0b0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f383d40_20 .net/s v0xc4f383d40 20, 31 0, o0xc4e86d0b0; 0 drivers
+o0xc4e86d0e0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f383d40_21 .net/s v0xc4f383d40 21, 31 0, o0xc4e86d0e0; 0 drivers
+o0xc4e86d110 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f383d40_22 .net/s v0xc4f383d40 22, 31 0, o0xc4e86d110; 0 drivers
+o0xc4e86d140 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f383d40_23 .net/s v0xc4f383d40 23, 31 0, o0xc4e86d140; 0 drivers
+v0xc4f383d40_24 .net/s v0xc4f383d40 24, 31 0, L_0xc4f3c5540; 1 drivers
+o0xc4e86d1a0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f383d40_25 .net/s v0xc4f383d40 25, 31 0, o0xc4e86d1a0; 0 drivers
+o0xc4e86d1d0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f383d40_26 .net/s v0xc4f383d40 26, 31 0, o0xc4e86d1d0; 0 drivers
+o0xc4e86d200 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f383d40_27 .net/s v0xc4f383d40 27, 31 0, o0xc4e86d200; 0 drivers
+o0xc4e86d230 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f383d40_28 .net/s v0xc4f383d40 28, 31 0, o0xc4e86d230; 0 drivers
+o0xc4e86d260 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f383d40_29 .net/s v0xc4f383d40 29, 31 0, o0xc4e86d260; 0 drivers
+o0xc4e86d290 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f383d40_30 .net/s v0xc4f383d40 30, 31 0, o0xc4e86d290; 0 drivers
+o0xc4e86d2c0 .functor BUFZ 32, c4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
+v0xc4f383d40_31 .net/s v0xc4f383d40 31, 31 0, o0xc4e86d2c0; 0 drivers
+v0xc4f383de0_0 .net/s "w_bus", 63 0, L_0xc4f3c1ae0;  alias, 1 drivers
+v0xc4f383e80_0 .net/s "x_bus", 63 0, L_0xc4f3c1a40;  alias, 1 drivers
+L_0xc4f3c1c20 .part L_0xc4f3c1a40, 0, 8;
+L_0xc4f3c1cc0 .part L_0xc4f3c1ae0, 0, 8;
+L_0xc4f3c1e00 .part L_0xc4f3c1a40, 8, 8;
+L_0xc4f3c1ea0 .part L_0xc4f3c1ae0, 8, 8;
+L_0xc4f3c1fe0 .part L_0xc4f3c1a40, 16, 8;
+L_0xc4f3c2080 .part L_0xc4f3c1ae0, 16, 8;
+L_0xc4f3c21c0 .part L_0xc4f3c1a40, 24, 8;
+L_0xc4f3c2260 .part L_0xc4f3c1ae0, 24, 8;
+L_0xc4f3c23a0 .part L_0xc4f3c1a40, 32, 8;
+L_0xc4f3c2440 .part L_0xc4f3c1ae0, 32, 8;
+L_0xc4f3c2580 .part L_0xc4f3c1a40, 40, 8;
+L_0xc4f3c2620 .part L_0xc4f3c1ae0, 40, 8;
+L_0xc4f3c2760 .part L_0xc4f3c1a40, 48, 8;
+L_0xc4f3c2800 .part L_0xc4f3c1ae0, 48, 8;
+L_0xc4f3c2940 .part L_0xc4f3c1a40, 56, 8;
+L_0xc4f3c29e0 .part L_0xc4f3c1ae0, 56, 8;
+L_0xc4f3c55e0 .arith/sum 32, v0xc4f384820_0, L_0xc4f3c5540;
+S_0xc4f378480 .scope generate, "GEN_MAC[0]" "GEN_MAC[0]" 5 20, 5 20 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f337200 .param/l "i" 1 5 20, +C4<00>;
+S_0xc4f378600 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f378480;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f342700 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f342740 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f342780 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f380960_0 .net/s *"_ivl_0", 15 0, L_0xc4f3bfd40;  1 drivers
+v0xc4f380a00_0 .net/s *"_ivl_2", 15 0, L_0xc4f3bfde0;  1 drivers
+v0xc4f380aa0_0 .net *"_ivl_7", 0 0, L_0xc4f3c1b80;  1 drivers
+v0xc4f380b40_0 .net *"_ivl_9", 15 0, L_0xc4ef5f200;  1 drivers
+L_0xc4e87be80 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f380be0_0 .net/s "acc_in", 31 0, L_0xc4e87be80;  1 drivers
+v0xc4f380c80_0 .net/s "acc_out", 31 0, L_0xc4f3bff20;  alias, 1 drivers
+v0xc4f380d20_0 .net/s "product", 15 0, L_0xc4ef5f160;  1 drivers
+v0xc4f380dc0_0 .net/s "product_ext", 31 0, L_0xc4f3bfe80;  1 drivers
+v0xc4f380e60_0 .net/s "w", 7 0, L_0xc4f3c1cc0;  1 drivers
+v0xc4f380f00_0 .net/s "x", 7 0, L_0xc4f3c1c20;  1 drivers
+L_0xc4f3bfd40 .extend/s 16, L_0xc4f3c1c20;
+L_0xc4f3bfde0 .extend/s 16, L_0xc4f3c1cc0;
+L_0xc4ef5f160 .arith/mult 16, L_0xc4f3bfd40, L_0xc4f3bfde0;
+L_0xc4f3c1b80 .part L_0xc4ef5f160, 15, 1;
+L_0xc4ef5f200 .repeat 16, 16, L_0xc4f3c1b80;
+L_0xc4f3bfe80 .concat [ 16 16 0 0], L_0xc4ef5f160, L_0xc4ef5f200;
+L_0xc4f3bff20 .arith/sum 32, L_0xc4e87be80, L_0xc4f3bfe80;
+S_0xc4f378780 .scope generate, "GEN_MAC[1]" "GEN_MAC[1]" 5 20, 5 20 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f337240 .param/l "i" 1 5 20, +C4<01>;
+S_0xc4f378900 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f378780;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f3427c0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f342800 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f342840 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f380fa0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3c4000;  1 drivers
+v0xc4f381040_0 .net/s *"_ivl_2", 15 0, L_0xc4f3c40a0;  1 drivers
+v0xc4f3810e0_0 .net *"_ivl_7", 0 0, L_0xc4f3c1d60;  1 drivers
+v0xc4f381180_0 .net *"_ivl_9", 15 0, L_0xc4ef5f340;  1 drivers
+L_0xc4e87bec8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f381220_0 .net/s "acc_in", 31 0, L_0xc4e87bec8;  1 drivers
+v0xc4f3812c0_0 .net/s "acc_out", 31 0, L_0xc4f3c41e0;  alias, 1 drivers
+v0xc4f381360_0 .net/s "product", 15 0, L_0xc4ef5f2a0;  1 drivers
+v0xc4f381400_0 .net/s "product_ext", 31 0, L_0xc4f3c4140;  1 drivers
+v0xc4f3814a0_0 .net/s "w", 7 0, L_0xc4f3c1ea0;  1 drivers
+v0xc4f381540_0 .net/s "x", 7 0, L_0xc4f3c1e00;  1 drivers
+L_0xc4f3c4000 .extend/s 16, L_0xc4f3c1e00;
+L_0xc4f3c40a0 .extend/s 16, L_0xc4f3c1ea0;
+L_0xc4ef5f2a0 .arith/mult 16, L_0xc4f3c4000, L_0xc4f3c40a0;
+L_0xc4f3c1d60 .part L_0xc4ef5f2a0, 15, 1;
+L_0xc4ef5f340 .repeat 16, 16, L_0xc4f3c1d60;
+L_0xc4f3c4140 .concat [ 16 16 0 0], L_0xc4ef5f2a0, L_0xc4ef5f340;
+L_0xc4f3c41e0 .arith/sum 32, L_0xc4e87bec8, L_0xc4f3c4140;
+S_0xc4f378a80 .scope generate, "GEN_MAC[2]" "GEN_MAC[2]" 5 20, 5 20 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f337280 .param/l "i" 1 5 20, +C4<010>;
+S_0xc4f378c00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f378a80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f342880 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f3428c0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f342900 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f3815e0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3c4280;  1 drivers
+v0xc4f381680_0 .net/s *"_ivl_2", 15 0, L_0xc4f3c4320;  1 drivers
+v0xc4f381720_0 .net *"_ivl_7", 0 0, L_0xc4f3c1f40;  1 drivers
+v0xc4f3817c0_0 .net *"_ivl_9", 15 0, L_0xc4ef5f480;  1 drivers
+L_0xc4e87bf10 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f381860_0 .net/s "acc_in", 31 0, L_0xc4e87bf10;  1 drivers
+v0xc4f381900_0 .net/s "acc_out", 31 0, L_0xc4f3c4460;  alias, 1 drivers
+v0xc4f3819a0_0 .net/s "product", 15 0, L_0xc4ef5f3e0;  1 drivers
+v0xc4f381a40_0 .net/s "product_ext", 31 0, L_0xc4f3c43c0;  1 drivers
+v0xc4f381ae0_0 .net/s "w", 7 0, L_0xc4f3c2080;  1 drivers
+v0xc4f381b80_0 .net/s "x", 7 0, L_0xc4f3c1fe0;  1 drivers
+L_0xc4f3c4280 .extend/s 16, L_0xc4f3c1fe0;
+L_0xc4f3c4320 .extend/s 16, L_0xc4f3c2080;
+L_0xc4ef5f3e0 .arith/mult 16, L_0xc4f3c4280, L_0xc4f3c4320;
+L_0xc4f3c1f40 .part L_0xc4ef5f3e0, 15, 1;
+L_0xc4ef5f480 .repeat 16, 16, L_0xc4f3c1f40;
+L_0xc4f3c43c0 .concat [ 16 16 0 0], L_0xc4ef5f3e0, L_0xc4ef5f480;
+L_0xc4f3c4460 .arith/sum 32, L_0xc4e87bf10, L_0xc4f3c43c0;
+S_0xc4f378d80 .scope generate, "GEN_MAC[3]" "GEN_MAC[3]" 5 20, 5 20 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f3372c0 .param/l "i" 1 5 20, +C4<011>;
+S_0xc4f378f00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f378d80;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f342940 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f342980 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f3429c0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f381c20_0 .net/s *"_ivl_0", 15 0, L_0xc4f3c4500;  1 drivers
+v0xc4f381cc0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3c45a0;  1 drivers
+v0xc4f381d60_0 .net *"_ivl_7", 0 0, L_0xc4f3c2120;  1 drivers
+v0xc4f381e00_0 .net *"_ivl_9", 15 0, L_0xc4ef5f5c0;  1 drivers
+L_0xc4e87bf58 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f381ea0_0 .net/s "acc_in", 31 0, L_0xc4e87bf58;  1 drivers
+v0xc4f381f40_0 .net/s "acc_out", 31 0, L_0xc4f3c46e0;  alias, 1 drivers
+v0xc4f381fe0_0 .net/s "product", 15 0, L_0xc4ef5f520;  1 drivers
+v0xc4f382080_0 .net/s "product_ext", 31 0, L_0xc4f3c4640;  1 drivers
+v0xc4f382120_0 .net/s "w", 7 0, L_0xc4f3c2260;  1 drivers
+v0xc4f3821c0_0 .net/s "x", 7 0, L_0xc4f3c21c0;  1 drivers
+L_0xc4f3c4500 .extend/s 16, L_0xc4f3c21c0;
+L_0xc4f3c45a0 .extend/s 16, L_0xc4f3c2260;
+L_0xc4ef5f520 .arith/mult 16, L_0xc4f3c4500, L_0xc4f3c45a0;
+L_0xc4f3c2120 .part L_0xc4ef5f520, 15, 1;
+L_0xc4ef5f5c0 .repeat 16, 16, L_0xc4f3c2120;
+L_0xc4f3c4640 .concat [ 16 16 0 0], L_0xc4ef5f520, L_0xc4ef5f5c0;
+L_0xc4f3c46e0 .arith/sum 32, L_0xc4e87bf58, L_0xc4f3c4640;
+S_0xc4f379080 .scope generate, "GEN_MAC[4]" "GEN_MAC[4]" 5 20, 5 20 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f337340 .param/l "i" 1 5 20, +C4<0100>;
+S_0xc4f379200 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f379080;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f342a00 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f342a40 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f342a80 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f382260_0 .net/s *"_ivl_0", 15 0, L_0xc4f3c4780;  1 drivers
+v0xc4f382300_0 .net/s *"_ivl_2", 15 0, L_0xc4f3c4820;  1 drivers
+v0xc4f3823a0_0 .net *"_ivl_7", 0 0, L_0xc4f3c2300;  1 drivers
+v0xc4f382440_0 .net *"_ivl_9", 15 0, L_0xc4ef5f700;  1 drivers
+L_0xc4e87bfa0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3824e0_0 .net/s "acc_in", 31 0, L_0xc4e87bfa0;  1 drivers
+v0xc4f382580_0 .net/s "acc_out", 31 0, L_0xc4f3c4960;  alias, 1 drivers
+v0xc4f382620_0 .net/s "product", 15 0, L_0xc4ef5f660;  1 drivers
+v0xc4f3826c0_0 .net/s "product_ext", 31 0, L_0xc4f3c48c0;  1 drivers
+v0xc4f382760_0 .net/s "w", 7 0, L_0xc4f3c2440;  1 drivers
+v0xc4f382800_0 .net/s "x", 7 0, L_0xc4f3c23a0;  1 drivers
+L_0xc4f3c4780 .extend/s 16, L_0xc4f3c23a0;
+L_0xc4f3c4820 .extend/s 16, L_0xc4f3c2440;
+L_0xc4ef5f660 .arith/mult 16, L_0xc4f3c4780, L_0xc4f3c4820;
+L_0xc4f3c2300 .part L_0xc4ef5f660, 15, 1;
+L_0xc4ef5f700 .repeat 16, 16, L_0xc4f3c2300;
+L_0xc4f3c48c0 .concat [ 16 16 0 0], L_0xc4ef5f660, L_0xc4ef5f700;
+L_0xc4f3c4960 .arith/sum 32, L_0xc4e87bfa0, L_0xc4f3c48c0;
+S_0xc4f379380 .scope generate, "GEN_MAC[5]" "GEN_MAC[5]" 5 20, 5 20 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f337380 .param/l "i" 1 5 20, +C4<0101>;
+S_0xc4f379500 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f379380;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f342ac0 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f342b00 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f342b40 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f3828a0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3c4a00;  1 drivers
+v0xc4f382940_0 .net/s *"_ivl_2", 15 0, L_0xc4f3c4aa0;  1 drivers
+v0xc4f3829e0_0 .net *"_ivl_7", 0 0, L_0xc4f3c24e0;  1 drivers
+v0xc4f382a80_0 .net *"_ivl_9", 15 0, L_0xc4ef5f840;  1 drivers
+L_0xc4e87bfe8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f382b20_0 .net/s "acc_in", 31 0, L_0xc4e87bfe8;  1 drivers
+v0xc4f382bc0_0 .net/s "acc_out", 31 0, L_0xc4f3c4be0;  alias, 1 drivers
+v0xc4f382c60_0 .net/s "product", 15 0, L_0xc4ef5f7a0;  1 drivers
+v0xc4f382d00_0 .net/s "product_ext", 31 0, L_0xc4f3c4b40;  1 drivers
+v0xc4f382da0_0 .net/s "w", 7 0, L_0xc4f3c2620;  1 drivers
+v0xc4f382e40_0 .net/s "x", 7 0, L_0xc4f3c2580;  1 drivers
+L_0xc4f3c4a00 .extend/s 16, L_0xc4f3c2580;
+L_0xc4f3c4aa0 .extend/s 16, L_0xc4f3c2620;
+L_0xc4ef5f7a0 .arith/mult 16, L_0xc4f3c4a00, L_0xc4f3c4aa0;
+L_0xc4f3c24e0 .part L_0xc4ef5f7a0, 15, 1;
+L_0xc4ef5f840 .repeat 16, 16, L_0xc4f3c24e0;
+L_0xc4f3c4b40 .concat [ 16 16 0 0], L_0xc4ef5f7a0, L_0xc4ef5f840;
+L_0xc4f3c4be0 .arith/sum 32, L_0xc4e87bfe8, L_0xc4f3c4b40;
+S_0xc4f379680 .scope generate, "GEN_MAC[6]" "GEN_MAC[6]" 5 20, 5 20 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f3373c0 .param/l "i" 1 5 20, +C4<0110>;
+S_0xc4f379800 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f379680;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f342b80 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f342bc0 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f342c00 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f382ee0_0 .net/s *"_ivl_0", 15 0, L_0xc4f3c4c80;  1 drivers
+v0xc4f382f80_0 .net/s *"_ivl_2", 15 0, L_0xc4f3c4d20;  1 drivers
+v0xc4f383020_0 .net *"_ivl_7", 0 0, L_0xc4f3c26c0;  1 drivers
+v0xc4f3830c0_0 .net *"_ivl_9", 15 0, L_0xc4ef5f980;  1 drivers
+L_0xc4e87c030 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f383160_0 .net/s "acc_in", 31 0, L_0xc4e87c030;  1 drivers
+v0xc4f383200_0 .net/s "acc_out", 31 0, L_0xc4f3c4e60;  alias, 1 drivers
+v0xc4f3832a0_0 .net/s "product", 15 0, L_0xc4ef5f8e0;  1 drivers
+v0xc4f383340_0 .net/s "product_ext", 31 0, L_0xc4f3c4dc0;  1 drivers
+v0xc4f3833e0_0 .net/s "w", 7 0, L_0xc4f3c2800;  1 drivers
+v0xc4f383480_0 .net/s "x", 7 0, L_0xc4f3c2760;  1 drivers
+L_0xc4f3c4c80 .extend/s 16, L_0xc4f3c2760;
+L_0xc4f3c4d20 .extend/s 16, L_0xc4f3c2800;
+L_0xc4ef5f8e0 .arith/mult 16, L_0xc4f3c4c80, L_0xc4f3c4d20;
+L_0xc4f3c26c0 .part L_0xc4ef5f8e0, 15, 1;
+L_0xc4ef5f980 .repeat 16, 16, L_0xc4f3c26c0;
+L_0xc4f3c4dc0 .concat [ 16 16 0 0], L_0xc4ef5f8e0, L_0xc4ef5f980;
+L_0xc4f3c4e60 .arith/sum 32, L_0xc4e87c030, L_0xc4f3c4dc0;
+S_0xc4f379980 .scope generate, "GEN_MAC[7]" "GEN_MAC[7]" 5 20, 5 20 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f337400 .param/l "i" 1 5 20, +C4<0111>;
+S_0xc4f379b00 .scope module, "u_mac" "mac_unit" 5 25, 6 1 0, S_0xc4f379980;
+ .timescale 0 0;
+    .port_info 0 /INPUT 8 "x";
+    .port_info 1 /INPUT 8 "w";
+    .port_info 2 /INPUT 32 "acc_in";
+    .port_info 3 /OUTPUT 32 "acc_out";
+P_0xc4f342c40 .param/l "ACC_WIDTH" 0 6 3, +C4<00000000000000000000000000100000>;
+P_0xc4f342c80 .param/l "DATA_WIDTH" 0 6 2, +C4<00000000000000000000000000001000>;
+P_0xc4f342cc0 .param/l "PROD_WIDTH" 1 6 11, +C4<0000000000000000000000000000000000000000000000000000000000010000>;
+v0xc4f383520_0 .net/s *"_ivl_0", 15 0, L_0xc4f3c4f00;  1 drivers
+v0xc4f3835c0_0 .net/s *"_ivl_2", 15 0, L_0xc4f3c4fa0;  1 drivers
+v0xc4f383660_0 .net *"_ivl_7", 0 0, L_0xc4f3c28a0;  1 drivers
+v0xc4f383700_0 .net *"_ivl_9", 15 0, L_0xc4ef5fac0;  1 drivers
+L_0xc4e87c078 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0xc4f3837a0_0 .net/s "acc_in", 31 0, L_0xc4e87c078;  1 drivers
+v0xc4f383840_0 .net/s "acc_out", 31 0, L_0xc4f3c50e0;  alias, 1 drivers
+v0xc4f3838e0_0 .net/s "product", 15 0, L_0xc4ef5fa20;  1 drivers
+v0xc4f383980_0 .net/s "product_ext", 31 0, L_0xc4f3c5040;  1 drivers
+v0xc4f383a20_0 .net/s "w", 7 0, L_0xc4f3c29e0;  1 drivers
+v0xc4f383ac0_0 .net/s "x", 7 0, L_0xc4f3c2940;  1 drivers
+L_0xc4f3c4f00 .extend/s 16, L_0xc4f3c2940;
+L_0xc4f3c4fa0 .extend/s 16, L_0xc4f3c29e0;
+L_0xc4ef5fa20 .arith/mult 16, L_0xc4f3c4f00, L_0xc4f3c4fa0;
+L_0xc4f3c28a0 .part L_0xc4ef5fa20, 15, 1;
+L_0xc4ef5fac0 .repeat 16, 16, L_0xc4f3c28a0;
+L_0xc4f3c5040 .concat [ 16 16 0 0], L_0xc4ef5fa20, L_0xc4ef5fac0;
+L_0xc4f3c50e0 .arith/sum 32, L_0xc4e87c078, L_0xc4f3c5040;
+S_0xc4f379c80 .scope generate, "GEN_TREE_INPUT[0]" "GEN_TREE_INPUT[0]" 5 80, 5 80 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f337300 .param/l "i" 1 5 80, +C4<00>;
+L_0xc4f3a9c00 .functor BUFZ 32, L_0xc4f3bff20, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f379e00 .scope generate, "GEN_TREE_INPUT[1]" "GEN_TREE_INPUT[1]" 5 80, 5 80 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f337440 .param/l "i" 1 5 80, +C4<01>;
+L_0xc4f3a9c70 .functor BUFZ 32, L_0xc4f3c41e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f379f80 .scope generate, "GEN_TREE_INPUT[2]" "GEN_TREE_INPUT[2]" 5 80, 5 80 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f337480 .param/l "i" 1 5 80, +C4<010>;
+L_0xc4f3a9ce0 .functor BUFZ 32, L_0xc4f3c4460, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f37a100 .scope generate, "GEN_TREE_INPUT[3]" "GEN_TREE_INPUT[3]" 5 80, 5 80 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f3374c0 .param/l "i" 1 5 80, +C4<011>;
+L_0xc4f3a9d50 .functor BUFZ 32, L_0xc4f3c46e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f37a280 .scope generate, "GEN_TREE_INPUT[4]" "GEN_TREE_INPUT[4]" 5 80, 5 80 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f337500 .param/l "i" 1 5 80, +C4<0100>;
+L_0xc4f3a9dc0 .functor BUFZ 32, L_0xc4f3c4960, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f37a400 .scope generate, "GEN_TREE_INPUT[5]" "GEN_TREE_INPUT[5]" 5 80, 5 80 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f337540 .param/l "i" 1 5 80, +C4<0101>;
+L_0xc4f3a9e30 .functor BUFZ 32, L_0xc4f3c4be0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f37a580 .scope generate, "GEN_TREE_INPUT[6]" "GEN_TREE_INPUT[6]" 5 80, 5 80 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f337580 .param/l "i" 1 5 80, +C4<0110>;
+L_0xc4f3a9ea0 .functor BUFZ 32, L_0xc4f3c4e60, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f37a700 .scope generate, "GEN_TREE_INPUT[7]" "GEN_TREE_INPUT[7]" 5 80, 5 80 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f3375c0 .param/l "i" 1 5 80, +C4<0111>;
+L_0xc4f3a9f10 .functor BUFZ 32, L_0xc4f3c50e0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+S_0xc4f37a880 .scope generate, "GEN_TREE_LEVEL[0]" "GEN_TREE_LEVEL[0]" 5 92, 5 92 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f337600 .param/l "level" 1 5 92, +C4<00>;
+S_0xc4f37aa00 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f37a880;
+ .timescale 0 0;
+P_0xc4f337640 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3c5180 .arith/sum 32, L_0xc4f3a9c00, L_0xc4f3a9c70;
+S_0xc4f37ab80 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f37a880;
+ .timescale 0 0;
+P_0xc4f337680 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3c5220 .arith/sum 32, L_0xc4f3a9ce0, L_0xc4f3a9d50;
+S_0xc4f37ad00 .scope generate, "GEN_TREE_NODE[2]" "GEN_TREE_NODE[2]" 5 94, 5 94 0, S_0xc4f37a880;
+ .timescale 0 0;
+P_0xc4f3376c0 .param/l "node" 1 5 94, +C4<010>;
+L_0xc4f3c52c0 .arith/sum 32, L_0xc4f3a9dc0, L_0xc4f3a9e30;
+S_0xc4f37ae80 .scope generate, "GEN_TREE_NODE[3]" "GEN_TREE_NODE[3]" 5 94, 5 94 0, S_0xc4f37a880;
+ .timescale 0 0;
+P_0xc4f337700 .param/l "node" 1 5 94, +C4<011>;
+L_0xc4f3c5360 .arith/sum 32, L_0xc4f3a9ea0, L_0xc4f3a9f10;
+S_0xc4f37b000 .scope generate, "GEN_TREE_LEVEL[1]" "GEN_TREE_LEVEL[1]" 5 92, 5 92 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f337740 .param/l "level" 1 5 92, +C4<01>;
+S_0xc4f37b180 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f37b000;
+ .timescale 0 0;
+P_0xc4f337780 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3c5400 .arith/sum 32, L_0xc4f3c5180, L_0xc4f3c5220;
+S_0xc4f37b300 .scope generate, "GEN_TREE_NODE[1]" "GEN_TREE_NODE[1]" 5 94, 5 94 0, S_0xc4f37b000;
+ .timescale 0 0;
+P_0xc4f3377c0 .param/l "node" 1 5 94, +C4<01>;
+L_0xc4f3c54a0 .arith/sum 32, L_0xc4f3c52c0, L_0xc4f3c5360;
+S_0xc4f37b480 .scope generate, "GEN_TREE_LEVEL[2]" "GEN_TREE_LEVEL[2]" 5 92, 5 92 0, S_0xc4f378300;
+ .timescale 0 0;
+P_0xc4f337800 .param/l "level" 1 5 92, +C4<010>;
+S_0xc4f37b600 .scope generate, "GEN_TREE_NODE[0]" "GEN_TREE_NODE[0]" 5 94, 5 94 0, S_0xc4f37b480;
+ .timescale 0 0;
+P_0xc4f337840 .param/l "node" 1 5 94, +C4<00>;
+L_0xc4f3c5540 .arith/sum 32, L_0xc4f3c5400, L_0xc4f3c54a0;
+    .scope S_0x102d14700;
+T_0 ;
+    %wait E_0xc4eec7600;
+    %load/vec4 v0xc4f2cd5e0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_0.0, 8;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0xc4f2cd540_0, 0;
+    %pushi/vec4 0, 0, 40;
+    %assign/vec4 v0xc4f2cd040_0, 0;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f2cd9a0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2cd2c0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2cd400_0, 0;
+    %jmp T_0.1;
+T_0.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2cd400_0, 0;
+    %load/vec4 v0xc4f2cd680_0;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_0.4, 9;
+    %load/vec4 v0xc4f2cd2c0_0;
+    %nor/r;
+    %and;
+T_0.4;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_0.2, 8;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0xc4f2cd540_0, 0;
+    %pushi/vec4 0, 0, 40;
+    %assign/vec4 v0xc4f2cd040_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f2cd2c0_0, 0;
+    %jmp T_0.3;
+T_0.2 ;
+    %load/vec4 v0xc4f2cd2c0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_0.5, 8;
+    %load/vec4 v0xc4f2cd540_0;
+    %pad/u 32;
+    %cmpi/e 7, 0, 32;
+    %jmp/0xz  T_0.7, 4;
+    %load/vec4 v0xc4f2cd4a0_0;
+    %assign/vec4 v0xc4f2cd040_0, 0;
+    %load/vec4 v0xc4f2cd4a0_0;
+    %cmpi/s 0, 0, 40;
+    %flag_or 5, 4;
+    %jmp/0xz  T_0.9, 5;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f2cd9a0_0, 0;
+    %jmp T_0.10;
+T_0.9 ;
+    %load/vec4 v0xc4f2cd4a0_0;
+    %cmpi/s 127, 0, 40;
+    %flag_or 5, 4; GT is !LE
+    %flag_inv 5;
+    %jmp/0xz  T_0.11, 5;
+    %pushi/vec4 127, 0, 16;
+    %assign/vec4 v0xc4f2cd9a0_0, 0;
+    %jmp T_0.12;
+T_0.11 ;
+    %load/vec4 v0xc4f2cd4a0_0;
+    %parti/s 16, 0, 2;
+    %assign/vec4 v0xc4f2cd9a0_0, 0;
+T_0.12 ;
+T_0.10 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2cd2c0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f2cd400_0, 0;
+    %jmp T_0.8;
+T_0.7 ;
+    %load/vec4 v0xc4f2cd0e0_0;
+    %assign/vec4 v0xc4f2cd040_0, 0;
+    %load/vec4 v0xc4f2cd540_0;
+    %addi 1, 0, 3;
+    %assign/vec4 v0xc4f2cd540_0, 0;
+T_0.8 ;
+T_0.5 ;
+T_0.3 ;
+T_0.1 ;
+    %jmp T_0;
+    .thread T_0;
+    .scope S_0xc4f2cab80;
+T_1 ;
+    %wait E_0xc4eec7600;
+    %load/vec4 v0xc4f2d9ea0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.0, 8;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0xc4f2d9e00_0, 0;
+    %pushi/vec4 0, 0, 40;
+    %assign/vec4 v0xc4f2d9900_0, 0;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f2da260_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2d9b80_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2d9cc0_0, 0;
+    %jmp T_1.1;
+T_1.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2d9cc0_0, 0;
+    %load/vec4 v0xc4f2d9f40_0;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_1.4, 9;
+    %load/vec4 v0xc4f2d9b80_0;
+    %nor/r;
+    %and;
+T_1.4;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.2, 8;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0xc4f2d9e00_0, 0;
+    %pushi/vec4 0, 0, 40;
+    %assign/vec4 v0xc4f2d9900_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f2d9b80_0, 0;
+    %jmp T_1.3;
+T_1.2 ;
+    %load/vec4 v0xc4f2d9b80_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_1.5, 8;
+    %load/vec4 v0xc4f2d9e00_0;
+    %pad/u 32;
+    %cmpi/e 7, 0, 32;
+    %jmp/0xz  T_1.7, 4;
+    %load/vec4 v0xc4f2d9d60_0;
+    %assign/vec4 v0xc4f2d9900_0, 0;
+    %load/vec4 v0xc4f2d9d60_0;
+    %cmpi/s 0, 0, 40;
+    %flag_or 5, 4;
+    %jmp/0xz  T_1.9, 5;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f2da260_0, 0;
+    %jmp T_1.10;
+T_1.9 ;
+    %load/vec4 v0xc4f2d9d60_0;
+    %cmpi/s 127, 0, 40;
+    %flag_or 5, 4; GT is !LE
+    %flag_inv 5;
+    %jmp/0xz  T_1.11, 5;
+    %pushi/vec4 127, 0, 16;
+    %assign/vec4 v0xc4f2da260_0, 0;
+    %jmp T_1.12;
+T_1.11 ;
+    %load/vec4 v0xc4f2d9d60_0;
+    %parti/s 16, 0, 2;
+    %assign/vec4 v0xc4f2da260_0, 0;
+T_1.12 ;
+T_1.10 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2d9b80_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f2d9cc0_0, 0;
+    %jmp T_1.8;
+T_1.7 ;
+    %load/vec4 v0xc4f2d99a0_0;
+    %assign/vec4 v0xc4f2d9900_0, 0;
+    %load/vec4 v0xc4f2d9e00_0;
+    %addi 1, 0, 3;
+    %assign/vec4 v0xc4f2d9e00_0, 0;
+T_1.8 ;
+T_1.5 ;
+T_1.3 ;
+T_1.1 ;
+    %jmp T_1;
+    .thread T_1;
+    .scope S_0xc4f2d6400;
+T_2 ;
+    %wait E_0xc4eec7600;
+    %load/vec4 v0xc4f2e2760_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_2.0, 8;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0xc4f2e26c0_0, 0;
+    %pushi/vec4 0, 0, 40;
+    %assign/vec4 v0xc4f2e21c0_0, 0;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f2e2b20_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2e2440_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2e2580_0, 0;
+    %jmp T_2.1;
+T_2.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2e2580_0, 0;
+    %load/vec4 v0xc4f2e2800_0;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_2.4, 9;
+    %load/vec4 v0xc4f2e2440_0;
+    %nor/r;
+    %and;
+T_2.4;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_2.2, 8;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0xc4f2e26c0_0, 0;
+    %pushi/vec4 0, 0, 40;
+    %assign/vec4 v0xc4f2e21c0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f2e2440_0, 0;
+    %jmp T_2.3;
+T_2.2 ;
+    %load/vec4 v0xc4f2e2440_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_2.5, 8;
+    %load/vec4 v0xc4f2e26c0_0;
+    %pad/u 32;
+    %cmpi/e 7, 0, 32;
+    %jmp/0xz  T_2.7, 4;
+    %load/vec4 v0xc4f2e2620_0;
+    %assign/vec4 v0xc4f2e21c0_0, 0;
+    %load/vec4 v0xc4f2e2620_0;
+    %cmpi/s 0, 0, 40;
+    %flag_or 5, 4;
+    %jmp/0xz  T_2.9, 5;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f2e2b20_0, 0;
+    %jmp T_2.10;
+T_2.9 ;
+    %load/vec4 v0xc4f2e2620_0;
+    %cmpi/s 127, 0, 40;
+    %flag_or 5, 4; GT is !LE
+    %flag_inv 5;
+    %jmp/0xz  T_2.11, 5;
+    %pushi/vec4 127, 0, 16;
+    %assign/vec4 v0xc4f2e2b20_0, 0;
+    %jmp T_2.12;
+T_2.11 ;
+    %load/vec4 v0xc4f2e2620_0;
+    %parti/s 16, 0, 2;
+    %assign/vec4 v0xc4f2e2b20_0, 0;
+T_2.12 ;
+T_2.10 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2e2440_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f2e2580_0, 0;
+    %jmp T_2.8;
+T_2.7 ;
+    %load/vec4 v0xc4f2e2260_0;
+    %assign/vec4 v0xc4f2e21c0_0, 0;
+    %load/vec4 v0xc4f2e26c0_0;
+    %addi 1, 0, 3;
+    %assign/vec4 v0xc4f2e26c0_0, 0;
+T_2.8 ;
+T_2.5 ;
+T_2.3 ;
+T_2.1 ;
+    %jmp T_2;
+    .thread T_2;
+    .scope S_0xc4f2e5c80;
+T_3 ;
+    %wait E_0xc4eec7600;
+    %load/vec4 v0xc4f2eb020_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_3.0, 8;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0xc4f2eaf80_0, 0;
+    %pushi/vec4 0, 0, 40;
+    %assign/vec4 v0xc4f2eaa80_0, 0;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f2eb3e0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2ead00_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2eae40_0, 0;
+    %jmp T_3.1;
+T_3.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2eae40_0, 0;
+    %load/vec4 v0xc4f2eb0c0_0;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_3.4, 9;
+    %load/vec4 v0xc4f2ead00_0;
+    %nor/r;
+    %and;
+T_3.4;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_3.2, 8;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0xc4f2eaf80_0, 0;
+    %pushi/vec4 0, 0, 40;
+    %assign/vec4 v0xc4f2eaa80_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f2ead00_0, 0;
+    %jmp T_3.3;
+T_3.2 ;
+    %load/vec4 v0xc4f2ead00_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_3.5, 8;
+    %load/vec4 v0xc4f2eaf80_0;
+    %pad/u 32;
+    %cmpi/e 7, 0, 32;
+    %jmp/0xz  T_3.7, 4;
+    %load/vec4 v0xc4f2eaee0_0;
+    %assign/vec4 v0xc4f2eaa80_0, 0;
+    %load/vec4 v0xc4f2eaee0_0;
+    %cmpi/s 0, 0, 40;
+    %flag_or 5, 4;
+    %jmp/0xz  T_3.9, 5;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f2eb3e0_0, 0;
+    %jmp T_3.10;
+T_3.9 ;
+    %load/vec4 v0xc4f2eaee0_0;
+    %cmpi/s 127, 0, 40;
+    %flag_or 5, 4; GT is !LE
+    %flag_inv 5;
+    %jmp/0xz  T_3.11, 5;
+    %pushi/vec4 127, 0, 16;
+    %assign/vec4 v0xc4f2eb3e0_0, 0;
+    %jmp T_3.12;
+T_3.11 ;
+    %load/vec4 v0xc4f2eaee0_0;
+    %parti/s 16, 0, 2;
+    %assign/vec4 v0xc4f2eb3e0_0, 0;
+T_3.12 ;
+T_3.10 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2ead00_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f2eae40_0, 0;
+    %jmp T_3.8;
+T_3.7 ;
+    %load/vec4 v0xc4f2eab20_0;
+    %assign/vec4 v0xc4f2eaa80_0, 0;
+    %load/vec4 v0xc4f2eaf80_0;
+    %addi 1, 0, 3;
+    %assign/vec4 v0xc4f2eaf80_0, 0;
+T_3.8 ;
+T_3.5 ;
+T_3.3 ;
+T_3.1 ;
+    %jmp T_3;
+    .thread T_3;
+    .scope S_0xc4f2ed500;
+T_4 ;
+    %wait E_0xc4eec7600;
+    %load/vec4 v0xc4f2f38e0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_4.0, 8;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0xc4f2f3840_0, 0;
+    %pushi/vec4 0, 0, 40;
+    %assign/vec4 v0xc4f2f3340_0, 0;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f2f3ca0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2f35c0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2f3700_0, 0;
+    %jmp T_4.1;
+T_4.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2f3700_0, 0;
+    %load/vec4 v0xc4f2f3980_0;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_4.4, 9;
+    %load/vec4 v0xc4f2f35c0_0;
+    %nor/r;
+    %and;
+T_4.4;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_4.2, 8;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0xc4f2f3840_0, 0;
+    %pushi/vec4 0, 0, 40;
+    %assign/vec4 v0xc4f2f3340_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f2f35c0_0, 0;
+    %jmp T_4.3;
+T_4.2 ;
+    %load/vec4 v0xc4f2f35c0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_4.5, 8;
+    %load/vec4 v0xc4f2f3840_0;
+    %pad/u 32;
+    %cmpi/e 7, 0, 32;
+    %jmp/0xz  T_4.7, 4;
+    %load/vec4 v0xc4f2f37a0_0;
+    %assign/vec4 v0xc4f2f3340_0, 0;
+    %load/vec4 v0xc4f2f37a0_0;
+    %cmpi/s 0, 0, 40;
+    %flag_or 5, 4;
+    %jmp/0xz  T_4.9, 5;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f2f3ca0_0, 0;
+    %jmp T_4.10;
+T_4.9 ;
+    %load/vec4 v0xc4f2f37a0_0;
+    %cmpi/s 127, 0, 40;
+    %flag_or 5, 4; GT is !LE
+    %flag_inv 5;
+    %jmp/0xz  T_4.11, 5;
+    %pushi/vec4 127, 0, 16;
+    %assign/vec4 v0xc4f2f3ca0_0, 0;
+    %jmp T_4.12;
+T_4.11 ;
+    %load/vec4 v0xc4f2f37a0_0;
+    %parti/s 16, 0, 2;
+    %assign/vec4 v0xc4f2f3ca0_0, 0;
+T_4.12 ;
+T_4.10 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2f35c0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f2f3700_0, 0;
+    %jmp T_4.8;
+T_4.7 ;
+    %load/vec4 v0xc4f2f33e0_0;
+    %assign/vec4 v0xc4f2f3340_0, 0;
+    %load/vec4 v0xc4f2f3840_0;
+    %addi 1, 0, 3;
+    %assign/vec4 v0xc4f2f3840_0, 0;
+T_4.8 ;
+T_4.5 ;
+T_4.3 ;
+T_4.1 ;
+    %jmp T_4;
+    .thread T_4;
+    .scope S_0xc4f2f8d80;
+T_5 ;
+    %wait E_0xc4eec7600;
+    %load/vec4 v0xc4f3041e0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_5.0, 8;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0xc4f304140_0, 0;
+    %pushi/vec4 0, 0, 40;
+    %assign/vec4 v0xc4f2ffc00_0, 0;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f3045a0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2ffe80_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f304000_0, 0;
+    %jmp T_5.1;
+T_5.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f304000_0, 0;
+    %load/vec4 v0xc4f304280_0;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_5.4, 9;
+    %load/vec4 v0xc4f2ffe80_0;
+    %nor/r;
+    %and;
+T_5.4;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_5.2, 8;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0xc4f304140_0, 0;
+    %pushi/vec4 0, 0, 40;
+    %assign/vec4 v0xc4f2ffc00_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f2ffe80_0, 0;
+    %jmp T_5.3;
+T_5.2 ;
+    %load/vec4 v0xc4f2ffe80_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_5.5, 8;
+    %load/vec4 v0xc4f304140_0;
+    %pad/u 32;
+    %cmpi/e 7, 0, 32;
+    %jmp/0xz  T_5.7, 4;
+    %load/vec4 v0xc4f3040a0_0;
+    %assign/vec4 v0xc4f2ffc00_0, 0;
+    %load/vec4 v0xc4f3040a0_0;
+    %cmpi/s 0, 0, 40;
+    %flag_or 5, 4;
+    %jmp/0xz  T_5.9, 5;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f3045a0_0, 0;
+    %jmp T_5.10;
+T_5.9 ;
+    %load/vec4 v0xc4f3040a0_0;
+    %cmpi/s 127, 0, 40;
+    %flag_or 5, 4; GT is !LE
+    %flag_inv 5;
+    %jmp/0xz  T_5.11, 5;
+    %pushi/vec4 127, 0, 16;
+    %assign/vec4 v0xc4f3045a0_0, 0;
+    %jmp T_5.12;
+T_5.11 ;
+    %load/vec4 v0xc4f3040a0_0;
+    %parti/s 16, 0, 2;
+    %assign/vec4 v0xc4f3045a0_0, 0;
+T_5.12 ;
+T_5.10 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f2ffe80_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f304000_0, 0;
+    %jmp T_5.8;
+T_5.7 ;
+    %load/vec4 v0xc4f2ffca0_0;
+    %assign/vec4 v0xc4f2ffc00_0, 0;
+    %load/vec4 v0xc4f304140_0;
+    %addi 1, 0, 3;
+    %assign/vec4 v0xc4f304140_0, 0;
+T_5.8 ;
+T_5.5 ;
+T_5.3 ;
+T_5.1 ;
+    %jmp T_5;
+    .thread T_5;
+    .scope S_0xc4f300600;
+T_6 ;
+    %wait E_0xc4eec7600;
+    %load/vec4 v0xc4f308aa0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_6.0, 8;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0xc4f308a00_0, 0;
+    %pushi/vec4 0, 0, 40;
+    %assign/vec4 v0xc4f308500_0, 0;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f308e60_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f308780_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3088c0_0, 0;
+    %jmp T_6.1;
+T_6.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3088c0_0, 0;
+    %load/vec4 v0xc4f308b40_0;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_6.4, 9;
+    %load/vec4 v0xc4f308780_0;
+    %nor/r;
+    %and;
+T_6.4;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_6.2, 8;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0xc4f308a00_0, 0;
+    %pushi/vec4 0, 0, 40;
+    %assign/vec4 v0xc4f308500_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f308780_0, 0;
+    %jmp T_6.3;
+T_6.2 ;
+    %load/vec4 v0xc4f308780_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_6.5, 8;
+    %load/vec4 v0xc4f308a00_0;
+    %pad/u 32;
+    %cmpi/e 7, 0, 32;
+    %jmp/0xz  T_6.7, 4;
+    %load/vec4 v0xc4f308960_0;
+    %assign/vec4 v0xc4f308500_0, 0;
+    %load/vec4 v0xc4f308960_0;
+    %cmpi/s 0, 0, 40;
+    %flag_or 5, 4;
+    %jmp/0xz  T_6.9, 5;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f308e60_0, 0;
+    %jmp T_6.10;
+T_6.9 ;
+    %load/vec4 v0xc4f308960_0;
+    %cmpi/s 127, 0, 40;
+    %flag_or 5, 4; GT is !LE
+    %flag_inv 5;
+    %jmp/0xz  T_6.11, 5;
+    %pushi/vec4 127, 0, 16;
+    %assign/vec4 v0xc4f308e60_0, 0;
+    %jmp T_6.12;
+T_6.11 ;
+    %load/vec4 v0xc4f308960_0;
+    %parti/s 16, 0, 2;
+    %assign/vec4 v0xc4f308e60_0, 0;
+T_6.12 ;
+T_6.10 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f308780_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f3088c0_0, 0;
+    %jmp T_6.8;
+T_6.7 ;
+    %load/vec4 v0xc4f3085a0_0;
+    %assign/vec4 v0xc4f308500_0, 0;
+    %load/vec4 v0xc4f308a00_0;
+    %addi 1, 0, 3;
+    %assign/vec4 v0xc4f308a00_0, 0;
+T_6.8 ;
+T_6.5 ;
+T_6.3 ;
+T_6.1 ;
+    %jmp T_6;
+    .thread T_6;
+    .scope S_0xc4f303d80;
+T_7 ;
+    %wait E_0xc4eec7600;
+    %load/vec4 v0xc4f315360_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_7.0, 8;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0xc4f3152c0_0, 0;
+    %pushi/vec4 0, 0, 40;
+    %assign/vec4 v0xc4f314dc0_0, 0;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f315720_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f315040_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f315180_0, 0;
+    %jmp T_7.1;
+T_7.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f315180_0, 0;
+    %load/vec4 v0xc4f315400_0;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_7.4, 9;
+    %load/vec4 v0xc4f315040_0;
+    %nor/r;
+    %and;
+T_7.4;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_7.2, 8;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0xc4f3152c0_0, 0;
+    %pushi/vec4 0, 0, 40;
+    %assign/vec4 v0xc4f314dc0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f315040_0, 0;
+    %jmp T_7.3;
+T_7.2 ;
+    %load/vec4 v0xc4f315040_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_7.5, 8;
+    %load/vec4 v0xc4f3152c0_0;
+    %pad/u 32;
+    %cmpi/e 7, 0, 32;
+    %jmp/0xz  T_7.7, 4;
+    %load/vec4 v0xc4f315220_0;
+    %assign/vec4 v0xc4f314dc0_0, 0;
+    %load/vec4 v0xc4f315220_0;
+    %cmpi/s 0, 0, 40;
+    %flag_or 5, 4;
+    %jmp/0xz  T_7.9, 5;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f315720_0, 0;
+    %jmp T_7.10;
+T_7.9 ;
+    %load/vec4 v0xc4f315220_0;
+    %cmpi/s 127, 0, 40;
+    %flag_or 5, 4; GT is !LE
+    %flag_inv 5;
+    %jmp/0xz  T_7.11, 5;
+    %pushi/vec4 127, 0, 16;
+    %assign/vec4 v0xc4f315720_0, 0;
+    %jmp T_7.12;
+T_7.11 ;
+    %load/vec4 v0xc4f315220_0;
+    %parti/s 16, 0, 2;
+    %assign/vec4 v0xc4f315720_0, 0;
+T_7.12 ;
+T_7.10 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f315040_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f315180_0, 0;
+    %jmp T_7.8;
+T_7.7 ;
+    %load/vec4 v0xc4f314e60_0;
+    %assign/vec4 v0xc4f314dc0_0, 0;
+    %load/vec4 v0xc4f3152c0_0;
+    %addi 1, 0, 3;
+    %assign/vec4 v0xc4f3152c0_0, 0;
+T_7.8 ;
+T_7.5 ;
+T_7.3 ;
+T_7.1 ;
+    %jmp T_7;
+    .thread T_7;
+    .scope S_0x102d16ff0;
+T_8 ;
+    %wait E_0xc4ef18800;
+    %load/vec4 v0xc4f316760_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_8.0, 8;
+    %pushi/vec4 0, 0, 2;
+    %assign/vec4 v0xc4f316800_0, 0;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f316580_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f316620_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f316120_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f3163a0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f316300_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3164e0_0, 0;
+    %pushi/vec4 0, 0, 22;
+    %assign/vec4 v0xc4f316080_0, 0;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f316440_0, 0;
+    %jmp T_8.1;
+T_8.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f316620_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f316300_0, 0;
+    %load/vec4 v0xc4f316800_0;
+    %dup/vec4;
+    %pushi/vec4 0, 0, 2;
+    %cmp/u;
+    %jmp/1 T_8.2, 6;
+    %dup/vec4;
+    %pushi/vec4 1, 0, 2;
+    %cmp/u;
+    %jmp/1 T_8.3, 6;
+    %pushi/vec4 0, 0, 2;
+    %assign/vec4 v0xc4f316800_0, 0;
+    %jmp T_8.5;
+T_8.2 ;
+    %load/vec4 v0xc4f3166c0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_8.6, 8;
+    %load/vec4 v0xc4f3169e0_0;
+    %assign/vec4 v0xc4f3164e0_0, 0;
+    %load/vec4 v0xc4f315ea0_0;
+    %assign/vec4 v0xc4f316080_0, 0;
+    %load/vec4 v0xc4f316940_0;
+    %assign/vec4 v0xc4f316440_0, 0;
+    %load/vec4 v0xc4f315fe0_0;
+    %assign/vec4 v0xc4f316120_0, 0;
+    %load/vec4 v0xc4f3168a0_0;
+    %assign/vec4 v0xc4f3163a0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f316300_0, 0;
+    %pushi/vec4 1, 0, 2;
+    %assign/vec4 v0xc4f316800_0, 0;
+T_8.6 ;
+    %jmp T_8.5;
+T_8.3 ;
+    %load/vec4 v0xc4f316260_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_8.8, 8;
+    %load/vec4 v0xc4f3164e0_0;
+    %nor/r;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_8.10, 8;
+    %load/vec4 v0xc4f3161c0_0;
+    %assign/vec4 v0xc4f316580_0, 0;
+T_8.10 ;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f316620_0, 0;
+    %pushi/vec4 0, 0, 2;
+    %assign/vec4 v0xc4f316800_0, 0;
+T_8.8 ;
+    %jmp T_8.5;
+T_8.5 ;
+    %pop/vec4 1;
+T_8.1 ;
+    %jmp T_8;
+    .thread T_8;
+    .scope S_0x102d24bb0;
+T_9 ;
+    %wait E_0xc4ef18840;
+    %load/vec4 v0xc4f317200_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_9.0, 8;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f317020_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3170c0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f316b20_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f316f80_0, 0;
+    %pushi/vec4 0, 0, 22;
+    %assign/vec4 v0xc4f316e40_0, 0;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f316ee0_0, 0;
+    %pushi/vec4 0, 0, 32;
+    %assign/vec4 v0xc4f316c60_0, 0;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0xc4f316d00_0, 0, 32;
+T_9.2 ; Top of for-loop
+    %load/vec4 v0xc4f316d00_0;
+    %cmpi/s 4096, 0, 32;
+	  %jmp/0xz T_9.3, 5;
+    %pushi/vec4 0, 0, 16;
+    %ix/getv/s 3, v0xc4f316d00_0;
+    %ix/load 4, 0, 0; Constant delay
+    %assign/vec4/a/d v0xc4f316da0, 0, 4;
+T_9.4 ; for-loop step statement
+    %load/vec4 v0xc4f316d00_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f316d00_0, 0, 32;
+    %jmp T_9.2;
+T_9.3 ; for-loop exit label
+    %jmp T_9.1;
+T_9.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3170c0_0, 0;
+    %load/vec4 v0xc4f316b20_0;
+    %nor/r;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_9.5, 8;
+    %load/vec4 v0xc4f317160_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_9.7, 8;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f316b20_0, 0;
+    %load/vec4 v0xc4f317340_0;
+    %assign/vec4 v0xc4f316f80_0, 0;
+    %load/vec4 v0xc4f316a80_0;
+    %assign/vec4 v0xc4f316e40_0, 0;
+    %load/vec4 v0xc4f3172a0_0;
+    %assign/vec4 v0xc4f316ee0_0, 0;
+    %pushi/vec4 2, 0, 32;
+    %assign/vec4 v0xc4f316c60_0, 0;
+T_9.7 ;
+    %jmp T_9.6;
+T_9.5 ;
+    %load/vec4 v0xc4f316c60_0;
+    %cmpi/s 0, 0, 32;
+    %flag_or 5, 4; GT is !LE
+    %flag_inv 5;
+    %jmp/0xz  T_9.9, 5;
+    %load/vec4 v0xc4f316c60_0;
+    %subi 1, 0, 32;
+    %assign/vec4 v0xc4f316c60_0, 0;
+    %jmp T_9.10;
+T_9.9 ;
+    %load/vec4 v0xc4f316f80_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_9.11, 8;
+    %load/vec4 v0xc4f316e40_0;
+    %pad/u 32;
+    %cmpi/u 4096, 0, 32;
+    %jmp/0xz  T_9.13, 5;
+    %load/vec4 v0xc4f316ee0_0;
+    %ix/getv 3, v0xc4f316e40_0;
+    %ix/load 4, 0, 0; Constant delay
+    %assign/vec4/a/d v0xc4f316da0, 0, 4;
+T_9.13 ;
+    %jmp T_9.12;
+T_9.11 ;
+    %load/vec4 v0xc4f316e40_0;
+    %pad/u 32;
+    %cmpi/u 4096, 0, 32;
+    %jmp/0xz  T_9.15, 5;
+    %ix/getv 4, v0xc4f316e40_0;
+    %load/vec4a v0xc4f316da0, 4;
+    %assign/vec4 v0xc4f317020_0, 0;
+    %jmp T_9.16;
+T_9.15 ;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f317020_0, 0;
+T_9.16 ;
+T_9.12 ;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f3170c0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f316b20_0, 0;
+T_9.10 ;
+T_9.6 ;
+T_9.1 ;
+    %jmp T_9;
+    .thread T_9;
+    .scope S_0xc4f31e580;
+T_10 ;
+    %wait E_0xc4ef188c0;
+    %load/vec4 v0xc4f3224e0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_10.0, 8;
+    %pushi/vec4 0, 0, 2;
+    %assign/vec4 v0xc4f322580_0, 0;
+    %pushi/vec4 0, 0, 22;
+    %assign/vec4 v0xc4f321cc0_0, 0;
+    %pushi/vec4 0, 0, 8;
+    %assign/vec4 v0xc4f322300_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3223a0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f322080_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f322260_0, 0;
+    %pushi/vec4 0, 0, 22;
+    %assign/vec4 v0xc4f321e00_0, 0;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f3221c0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f321ea0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f322120_0, 0;
+    %jmp T_10.1;
+T_10.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3223a0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f322080_0, 0;
+    %load/vec4 v0xc4f322580_0;
+    %dup/vec4;
+    %pushi/vec4 0, 0, 2;
+    %cmp/u;
+    %jmp/1 T_10.2, 6;
+    %dup/vec4;
+    %pushi/vec4 1, 0, 2;
+    %cmp/u;
+    %jmp/1 T_10.3, 6;
+    %pushi/vec4 0, 0, 2;
+    %assign/vec4 v0xc4f322580_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f322080_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f321ea0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f322120_0, 0;
+    %jmp T_10.5;
+T_10.2 ;
+    %load/vec4 v0xc4f322440_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_10.6, 8;
+    %load/vec4 v0xc4f321c20_0;
+    %assign/vec4 v0xc4f321cc0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f322080_0, 0;
+    %load/vec4 v0xc4f3226c0_0;
+    %assign/vec4 v0xc4f322260_0, 0;
+    %load/vec4 v0xc4f321c20_0;
+    %ix/load 4, 1, 0;
+    %flag_set/imm 4, 0;
+    %shiftr 4;
+    %assign/vec4 v0xc4f321e00_0, 0;
+    %load/vec4 v0xc4f321c20_0;
+    %parti/s 1, 0, 2;
+    %cmpi/e 0, 0, 1;
+    %jmp/0xz  T_10.8, 4;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f321ea0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f322120_0, 0;
+    %pushi/vec4 0, 0, 8;
+    %load/vec4 v0xc4f322620_0;
+    %concat/vec4; draw_concat_vec4
+    %assign/vec4 v0xc4f3221c0_0, 0;
+    %jmp T_10.9;
+T_10.8 ;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f321ea0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f322120_0, 0;
+    %load/vec4 v0xc4f322620_0;
+    %concati/vec4 0, 0, 8;
+    %assign/vec4 v0xc4f3221c0_0, 0;
+T_10.9 ;
+    %pushi/vec4 1, 0, 2;
+    %assign/vec4 v0xc4f322580_0, 0;
+T_10.6 ;
+    %jmp T_10.5;
+T_10.3 ;
+    %load/vec4 v0xc4f321fe0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_10.10, 8;
+    %load/vec4 v0xc4f321cc0_0;
+    %parti/s 1, 0, 2;
+    %cmpi/e 0, 0, 1;
+    %jmp/0xz  T_10.12, 4;
+    %load/vec4 v0xc4f321f40_0;
+    %parti/s 8, 0, 2;
+    %assign/vec4 v0xc4f322300_0, 0;
+    %jmp T_10.13;
+T_10.12 ;
+    %load/vec4 v0xc4f321f40_0;
+    %parti/s 8, 8, 5;
+    %assign/vec4 v0xc4f322300_0, 0;
+T_10.13 ;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f3223a0_0, 0;
+    %pushi/vec4 0, 0, 2;
+    %assign/vec4 v0xc4f322580_0, 0;
+T_10.10 ;
+    %jmp T_10.5;
+T_10.5 ;
+    %pop/vec4 1;
+T_10.1 ;
+    %jmp T_10;
+    .thread T_10;
+    .scope S_0xc4f31e700;
+T_11 ;
+    %wait E_0xc4ef188c0;
+    %load/vec4 v0xc4f326bc0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_11.0, 8;
+    %pushi/vec4 0, 0, 2;
+    %assign/vec4 v0xc4f326b20_0, 0;
+    %pushi/vec4 0, 0, 32;
+    %assign/vec4 v0xc4f326620_0, 0;
+    %pushi/vec4 0, 0, 8;
+    %assign/vec4 v0xc4f326f80_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3268a0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3269e0_0, 0;
+    %jmp T_11.1;
+T_11.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3269e0_0, 0;
+    %load/vec4 v0xc4f326c60_0;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_11.4, 9;
+    %load/vec4 v0xc4f3268a0_0;
+    %nor/r;
+    %and;
+T_11.4;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_11.2, 8;
+    %pushi/vec4 0, 0, 2;
+    %assign/vec4 v0xc4f326b20_0, 0;
+    %pushi/vec4 0, 0, 32;
+    %assign/vec4 v0xc4f326620_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f3268a0_0, 0;
+    %jmp T_11.3;
+T_11.2 ;
+    %load/vec4 v0xc4f3268a0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_11.5, 8;
+    %load/vec4 v0xc4f326b20_0;
+    %pad/u 32;
+    %cmpi/e 3, 0, 32;
+    %jmp/0xz  T_11.7, 4;
+    %load/vec4 v0xc4f326a80_0;
+    %assign/vec4 v0xc4f326620_0, 0;
+    %load/vec4 v0xc4f326a80_0;
+    %cmpi/s 0, 0, 32;
+    %flag_or 5, 4;
+    %jmp/0xz  T_11.9, 5;
+    %pushi/vec4 0, 0, 8;
+    %assign/vec4 v0xc4f326f80_0, 0;
+    %jmp T_11.10;
+T_11.9 ;
+    %load/vec4 v0xc4f326a80_0;
+    %cmpi/s 127, 0, 32;
+    %flag_or 5, 4; GT is !LE
+    %flag_inv 5;
+    %jmp/0xz  T_11.11, 5;
+    %pushi/vec4 127, 0, 8;
+    %assign/vec4 v0xc4f326f80_0, 0;
+    %jmp T_11.12;
+T_11.11 ;
+    %load/vec4 v0xc4f326a80_0;
+    %parti/s 8, 0, 2;
+    %assign/vec4 v0xc4f326f80_0, 0;
+T_11.12 ;
+T_11.10 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3268a0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f3269e0_0, 0;
+    %jmp T_11.8;
+T_11.7 ;
+    %load/vec4 v0xc4f3266c0_0;
+    %assign/vec4 v0xc4f326620_0, 0;
+    %load/vec4 v0xc4f326b20_0;
+    %addi 1, 0, 2;
+    %assign/vec4 v0xc4f326b20_0, 0;
+T_11.8 ;
+T_11.5 ;
+T_11.3 ;
+T_11.1 ;
+    %jmp T_11;
+    .thread T_11;
+    .scope S_0x102d16640;
+T_12 ;
+    %wait E_0xc4ef188c0;
+    %load/vec4 v0xc4f32c5a0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_12.0, 8;
+    %pushi/vec4 0, 0, 4;
+    %assign/vec4 v0xc4f32c6e0_0, 0;
+    %pushi/vec4 0, 0, 6;
+    %assign/vec4 v0xc4f327e80_0, 0;
+    %pushi/vec4 0, 0, 8;
+    %assign/vec4 v0xc4f327c00_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f327980_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f327ac0_0, 0;
+    %pushi/vec4 0, 0, 22;
+    %assign/vec4 v0xc4f327340_0, 0;
+    %pushi/vec4 0, 0, 8;
+    %assign/vec4 v0xc4f327a20_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32c460_0, 0;
+    %pushi/vec4 0, 0, 8;
+    %assign/vec4 v0xc4f32cb40_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f327ca0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f327de0_0, 0;
+    %jmp T_12.1;
+T_12.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f327980_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32c460_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f327de0_0, 0;
+    %load/vec4 v0xc4f32c6e0_0;
+    %dup/vec4;
+    %pushi/vec4 0, 0, 4;
+    %cmp/u;
+    %jmp/1 T_12.2, 6;
+    %dup/vec4;
+    %pushi/vec4 1, 0, 4;
+    %cmp/u;
+    %jmp/1 T_12.3, 6;
+    %dup/vec4;
+    %pushi/vec4 2, 0, 4;
+    %cmp/u;
+    %jmp/1 T_12.4, 6;
+    %dup/vec4;
+    %pushi/vec4 3, 0, 4;
+    %cmp/u;
+    %jmp/1 T_12.5, 6;
+    %dup/vec4;
+    %pushi/vec4 4, 0, 4;
+    %cmp/u;
+    %jmp/1 T_12.6, 6;
+    %dup/vec4;
+    %pushi/vec4 5, 0, 4;
+    %cmp/u;
+    %jmp/1 T_12.7, 6;
+    %pushi/vec4 0, 0, 4;
+    %assign/vec4 v0xc4f32c6e0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f327ca0_0, 0;
+    %jmp T_12.9;
+T_12.2 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f327ca0_0, 0;
+    %load/vec4 v0xc4f32c640_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_12.10, 8;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f327ca0_0, 0;
+    %pushi/vec4 0, 0, 6;
+    %assign/vec4 v0xc4f327e80_0, 0;
+    %load/vec4 v0xc4f32c960_0;
+    %assign/vec4 v0xc4f327340_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f327ac0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f327980_0, 0;
+    %pushi/vec4 1, 0, 4;
+    %assign/vec4 v0xc4f32c6e0_0, 0;
+T_12.10 ;
+    %jmp T_12.9;
+T_12.3 ;
+    %load/vec4 v0xc4f3278e0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_12.12, 8;
+    %load/vec4 v0xc4f327840_0;
+    %load/vec4 v0xc4f327e80_0;
+    %pad/u 7;
+    %ix/vec4 3;
+    %ix/load 4, 0, 0; Constant delay
+    %assign/vec4/a/d v0xc4f32caa0, 0, 4;
+    %load/vec4 v0xc4f327e80_0;
+    %pad/u 32;
+    %cmpi/e 31, 0, 32;
+    %jmp/0xz  T_12.14, 4;
+    %pushi/vec4 0, 0, 6;
+    %assign/vec4 v0xc4f327e80_0, 0;
+    %load/vec4 v0xc4f32c780_0;
+    %assign/vec4 v0xc4f327340_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f327ac0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f327980_0, 0;
+    %pushi/vec4 2, 0, 4;
+    %assign/vec4 v0xc4f32c6e0_0, 0;
+    %jmp T_12.15;
+T_12.14 ;
+    %load/vec4 v0xc4f327e80_0;
+    %addi 1, 0, 6;
+    %assign/vec4 v0xc4f327e80_0, 0;
+    %load/vec4 v0xc4f32c960_0;
+    %load/vec4 v0xc4f327e80_0;
+    %pad/u 22;
+    %add;
+    %addi 1, 0, 22;
+    %assign/vec4 v0xc4f327340_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f327980_0, 0;
+T_12.15 ;
+T_12.12 ;
+    %jmp T_12.9;
+T_12.4 ;
+    %load/vec4 v0xc4f3278e0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_12.16, 8;
+    %load/vec4 v0xc4f327840_0;
+    %load/vec4 v0xc4f327e80_0;
+    %pad/u 7;
+    %ix/vec4 3;
+    %ix/load 4, 0, 0; Constant delay
+    %assign/vec4/a/d v0xc4f32c8c0, 0, 4;
+    %load/vec4 v0xc4f327e80_0;
+    %pad/u 32;
+    %cmpi/e 31, 0, 32;
+    %jmp/0xz  T_12.18, 4;
+    %load/vec4 v0xc4f327b60_0;
+    %assign/vec4 v0xc4f327340_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f327ac0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f327980_0, 0;
+    %pushi/vec4 3, 0, 4;
+    %assign/vec4 v0xc4f32c6e0_0, 0;
+    %jmp T_12.19;
+T_12.18 ;
+    %load/vec4 v0xc4f327e80_0;
+    %addi 1, 0, 6;
+    %assign/vec4 v0xc4f327e80_0, 0;
+    %load/vec4 v0xc4f32c780_0;
+    %load/vec4 v0xc4f327e80_0;
+    %pad/u 22;
+    %add;
+    %addi 1, 0, 22;
+    %assign/vec4 v0xc4f327340_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f327980_0, 0;
+T_12.19 ;
+T_12.16 ;
+    %jmp T_12.9;
+T_12.5 ;
+    %load/vec4 v0xc4f3278e0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_12.20, 8;
+    %load/vec4 v0xc4f327840_0;
+    %assign/vec4 v0xc4f327c00_0, 0;
+    %pushi/vec4 4, 0, 4;
+    %assign/vec4 v0xc4f32c6e0_0, 0;
+T_12.20 ;
+    %jmp T_12.9;
+T_12.6 ;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32c460_0, 0;
+    %pushi/vec4 5, 0, 4;
+    %assign/vec4 v0xc4f32c6e0_0, 0;
+    %jmp T_12.9;
+T_12.7 ;
+    %load/vec4 v0xc4f32c3c0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_12.22, 8;
+    %load/vec4 v0xc4f32c500_0;
+    %assign/vec4 v0xc4f32cb40_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f327ca0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f327de0_0, 0;
+    %pushi/vec4 0, 0, 4;
+    %assign/vec4 v0xc4f32c6e0_0, 0;
+T_12.22 ;
+    %jmp T_12.9;
+T_12.9 ;
+    %pop/vec4 1;
+T_12.1 ;
+    %jmp T_12;
+    .thread T_12;
+    .scope S_0x102d167c0;
+T_13 ;
+    %wait E_0xc4ef18b40;
+    %load/vec4 v0xc4f32da40_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_13.0, 8;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0xc4f32dae0_0, 0;
+    %pushi/vec4 0, 0, 14;
+    %assign/vec4 v0xc4f32cdc0_0, 0;
+    %pushi/vec4 0, 0, 22;
+    %assign/vec4 v0xc4f32cc80_0, 0;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f32dc20_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32dcc0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32cfa0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32db80_0, 0;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f32d180_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32d220_0, 0;
+    %pushi/vec4 0, 0, 22;
+    %assign/vec4 v0xc4f32d540_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d5e0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d7c0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d900_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d720_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d860_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d9a0_0, 0;
+    %pushi/vec4 0, 0, 16;
+    %assign/vec4 v0xc4f32cf00_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32ce60_0, 0;
+    %jmp T_13.1;
+T_13.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32d220_0, 0;
+    %load/vec4 v0xc4f32dae0_0;
+    %dup/vec4;
+    %pushi/vec4 0, 0, 3;
+    %cmp/u;
+    %jmp/1 T_13.2, 6;
+    %dup/vec4;
+    %pushi/vec4 1, 0, 3;
+    %cmp/u;
+    %jmp/1 T_13.3, 6;
+    %dup/vec4;
+    %pushi/vec4 2, 0, 3;
+    %cmp/u;
+    %jmp/1 T_13.4, 6;
+    %dup/vec4;
+    %pushi/vec4 3, 0, 3;
+    %cmp/u;
+    %jmp/1 T_13.5, 6;
+    %dup/vec4;
+    %pushi/vec4 4, 0, 3;
+    %cmp/u;
+    %jmp/1 T_13.6, 6;
+    %pushi/vec4 0, 0, 3;
+    %assign/vec4 v0xc4f32dae0_0, 0;
+    %pushi/vec4 0, 0, 14;
+    %assign/vec4 v0xc4f32cdc0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d5e0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d7c0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d900_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d720_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d860_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d9a0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32ce60_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32cfa0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32db80_0, 0;
+    %jmp T_13.8;
+T_13.2 ;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d5e0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d7c0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d900_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d720_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d860_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d9a0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32ce60_0, 0;
+    %load/vec4 v0xc4f32cdc0_0;
+    %pad/u 32;
+    %cmpi/e 11999, 0, 32;
+    %jmp/0xz  T_13.9, 4;
+    %pushi/vec4 0, 0, 14;
+    %assign/vec4 v0xc4f32cdc0_0, 0;
+    %pushi/vec4 1, 0, 3;
+    %assign/vec4 v0xc4f32dae0_0, 0;
+    %jmp T_13.10;
+T_13.9 ;
+    %load/vec4 v0xc4f32cdc0_0;
+    %addi 1, 0, 14;
+    %assign/vec4 v0xc4f32cdc0_0, 0;
+T_13.10 ;
+    %jmp T_13.8;
+T_13.3 ;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d5e0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d7c0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d900_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d720_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d860_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d9a0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32ce60_0, 0;
+    %load/vec4 v0xc4f32d2c0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_13.11, 8;
+    %load/vec4 v0xc4f32d040_0;
+    %assign/vec4 v0xc4f32cc80_0, 0;
+    %load/vec4 v0xc4f32d400_0;
+    %assign/vec4 v0xc4f32dc20_0, 0;
+    %load/vec4 v0xc4f32d4a0_0;
+    %assign/vec4 v0xc4f32dcc0_0, 0;
+    %load/vec4 v0xc4f32d0e0_0;
+    %assign/vec4 v0xc4f32cfa0_0, 0;
+    %load/vec4 v0xc4f32d360_0;
+    %assign/vec4 v0xc4f32db80_0, 0;
+    %load/vec4 v0xc4f32d040_0;
+    %assign/vec4 v0xc4f32d540_0, 0;
+    %load/vec4 v0xc4f32d0e0_0;
+    %assign/vec4 v0xc4f32d720_0, 0;
+    %load/vec4 v0xc4f32d360_0;
+    %assign/vec4 v0xc4f32d860_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32d5e0_0, 0;
+    %pushi/vec4 0, 0, 14;
+    %assign/vec4 v0xc4f32cdc0_0, 0;
+    %load/vec4 v0xc4f32d4a0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_13.13, 8;
+    %load/vec4 v0xc4f32d400_0;
+    %assign/vec4 v0xc4f32cf00_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32ce60_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32d900_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d7c0_0, 0;
+    %pushi/vec4 3, 0, 3;
+    %assign/vec4 v0xc4f32dae0_0, 0;
+    %jmp T_13.14;
+T_13.13 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32ce60_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d900_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32d7c0_0, 0;
+    %pushi/vec4 2, 0, 3;
+    %assign/vec4 v0xc4f32dae0_0, 0;
+T_13.14 ;
+T_13.11 ;
+    %jmp T_13.8;
+T_13.4 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32d5e0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32d7c0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d900_0, 0;
+    %load/vec4 v0xc4f32cfa0_0;
+    %assign/vec4 v0xc4f32d720_0, 0;
+    %load/vec4 v0xc4f32db80_0;
+    %assign/vec4 v0xc4f32d860_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d9a0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32ce60_0, 0;
+    %load/vec4 v0xc4f32cdc0_0;
+    %pad/u 32;
+    %cmpi/e 5, 0, 32;
+    %jmp/0xz  T_13.15, 4;
+    %load/vec4 v0xc4f32d680_0;
+    %assign/vec4 v0xc4f32d180_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d220_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d5e0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d7c0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d720_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d860_0, 0;
+    %pushi/vec4 0, 0, 14;
+    %assign/vec4 v0xc4f32cdc0_0, 0;
+    %pushi/vec4 1, 0, 3;
+    %assign/vec4 v0xc4f32dae0_0, 0;
+    %jmp T_13.16;
+T_13.15 ;
+    %load/vec4 v0xc4f32cdc0_0;
+    %addi 1, 0, 14;
+    %assign/vec4 v0xc4f32cdc0_0, 0;
+T_13.16 ;
+    %jmp T_13.8;
+T_13.5 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32d5e0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d7c0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32d900_0, 0;
+    %load/vec4 v0xc4f32cfa0_0;
+    %assign/vec4 v0xc4f32d720_0, 0;
+    %load/vec4 v0xc4f32db80_0;
+    %assign/vec4 v0xc4f32d860_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d9a0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32ce60_0, 0;
+    %load/vec4 v0xc4f32cdc0_0;
+    %pad/u 32;
+    %cmpi/e 5, 0, 32;
+    %jmp/0xz  T_13.17, 4;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d900_0, 0;
+    %pushi/vec4 0, 0, 14;
+    %assign/vec4 v0xc4f32cdc0_0, 0;
+    %pushi/vec4 4, 0, 3;
+    %assign/vec4 v0xc4f32dae0_0, 0;
+    %jmp T_13.18;
+T_13.17 ;
+    %load/vec4 v0xc4f32cdc0_0;
+    %addi 1, 0, 14;
+    %assign/vec4 v0xc4f32cdc0_0, 0;
+T_13.18 ;
+    %jmp T_13.8;
+T_13.6 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32d5e0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d7c0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d900_0, 0;
+    %load/vec4 v0xc4f32cfa0_0;
+    %assign/vec4 v0xc4f32d720_0, 0;
+    %load/vec4 v0xc4f32db80_0;
+    %assign/vec4 v0xc4f32d860_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d9a0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f32ce60_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d5e0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d720_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d860_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f32d220_0, 0;
+    %pushi/vec4 1, 0, 3;
+    %assign/vec4 v0xc4f32dae0_0, 0;
+    %jmp T_13.8;
+T_13.8 ;
+    %pop/vec4 1;
+T_13.1 ;
+    %jmp T_13;
+    .thread T_13;
+    .scope S_0xc4f329e00;
+T_14 ;
+    %wait E_0xc4ef18b80;
+    %load/vec4 v0xc4f3321c0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_14.0, 8;
+    %pushi/vec4 0, 0, 2;
+    %assign/vec4 v0xc4f332120_0, 0;
+    %pushi/vec4 0, 0, 32;
+    %assign/vec4 v0xc4f331c20_0, 0;
+    %pushi/vec4 0, 0, 8;
+    %assign/vec4 v0xc4f332580_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f331ea0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f331fe0_0, 0;
+    %jmp T_14.1;
+T_14.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f331fe0_0, 0;
+    %load/vec4 v0xc4f332260_0;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_14.4, 9;
+    %load/vec4 v0xc4f331ea0_0;
+    %nor/r;
+    %and;
+T_14.4;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_14.2, 8;
+    %pushi/vec4 0, 0, 2;
+    %assign/vec4 v0xc4f332120_0, 0;
+    %pushi/vec4 0, 0, 32;
+    %assign/vec4 v0xc4f331c20_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f331ea0_0, 0;
+    %jmp T_14.3;
+T_14.2 ;
+    %load/vec4 v0xc4f331ea0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_14.5, 8;
+    %load/vec4 v0xc4f332120_0;
+    %pad/u 32;
+    %cmpi/e 3, 0, 32;
+    %jmp/0xz  T_14.7, 4;
+    %load/vec4 v0xc4f332080_0;
+    %assign/vec4 v0xc4f331c20_0, 0;
+    %load/vec4 v0xc4f332080_0;
+    %cmpi/s 0, 0, 32;
+    %flag_or 5, 4;
+    %jmp/0xz  T_14.9, 5;
+    %pushi/vec4 0, 0, 8;
+    %assign/vec4 v0xc4f332580_0, 0;
+    %jmp T_14.10;
+T_14.9 ;
+    %load/vec4 v0xc4f332080_0;
+    %cmpi/s 127, 0, 32;
+    %flag_or 5, 4; GT is !LE
+    %flag_inv 5;
+    %jmp/0xz  T_14.11, 5;
+    %pushi/vec4 127, 0, 8;
+    %assign/vec4 v0xc4f332580_0, 0;
+    %jmp T_14.12;
+T_14.11 ;
+    %load/vec4 v0xc4f332080_0;
+    %parti/s 8, 0, 2;
+    %assign/vec4 v0xc4f332580_0, 0;
+T_14.12 ;
+T_14.10 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f331ea0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f331fe0_0, 0;
+    %jmp T_14.8;
+T_14.7 ;
+    %load/vec4 v0xc4f331cc0_0;
+    %assign/vec4 v0xc4f331c20_0, 0;
+    %load/vec4 v0xc4f332120_0;
+    %addi 1, 0, 2;
+    %assign/vec4 v0xc4f332120_0, 0;
+T_14.8 ;
+T_14.5 ;
+T_14.3 ;
+T_14.1 ;
+    %jmp T_14;
+    .thread T_14;
+    .scope S_0xc4f339500;
+T_15 ;
+    %wait E_0xc4ef18b80;
+    %load/vec4 v0xc4f346a80_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_15.0, 8;
+    %pushi/vec4 0, 0, 2;
+    %assign/vec4 v0xc4f3469e0_0, 0;
+    %pushi/vec4 0, 0, 32;
+    %assign/vec4 v0xc4f3464e0_0, 0;
+    %pushi/vec4 0, 0, 8;
+    %assign/vec4 v0xc4f346e40_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f346760_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3468a0_0, 0;
+    %jmp T_15.1;
+T_15.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3468a0_0, 0;
+    %load/vec4 v0xc4f346b20_0;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_15.4, 9;
+    %load/vec4 v0xc4f346760_0;
+    %nor/r;
+    %and;
+T_15.4;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_15.2, 8;
+    %pushi/vec4 0, 0, 2;
+    %assign/vec4 v0xc4f3469e0_0, 0;
+    %pushi/vec4 0, 0, 32;
+    %assign/vec4 v0xc4f3464e0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f346760_0, 0;
+    %jmp T_15.3;
+T_15.2 ;
+    %load/vec4 v0xc4f346760_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_15.5, 8;
+    %load/vec4 v0xc4f3469e0_0;
+    %pad/u 32;
+    %cmpi/e 2, 0, 32;
+    %jmp/0xz  T_15.7, 4;
+    %load/vec4 v0xc4f346940_0;
+    %assign/vec4 v0xc4f3464e0_0, 0;
+    %load/vec4 v0xc4f346940_0;
+    %cmpi/s 0, 0, 32;
+    %flag_or 5, 4;
+    %jmp/0xz  T_15.9, 5;
+    %pushi/vec4 0, 0, 8;
+    %assign/vec4 v0xc4f346e40_0, 0;
+    %jmp T_15.10;
+T_15.9 ;
+    %load/vec4 v0xc4f346940_0;
+    %cmpi/s 127, 0, 32;
+    %flag_or 5, 4; GT is !LE
+    %flag_inv 5;
+    %jmp/0xz  T_15.11, 5;
+    %pushi/vec4 127, 0, 8;
+    %assign/vec4 v0xc4f346e40_0, 0;
+    %jmp T_15.12;
+T_15.11 ;
+    %load/vec4 v0xc4f346940_0;
+    %parti/s 8, 0, 2;
+    %assign/vec4 v0xc4f346e40_0, 0;
+T_15.12 ;
+T_15.10 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f346760_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f3468a0_0, 0;
+    %jmp T_15.8;
+T_15.7 ;
+    %load/vec4 v0xc4f346580_0;
+    %assign/vec4 v0xc4f3464e0_0, 0;
+    %load/vec4 v0xc4f3469e0_0;
+    %addi 1, 0, 2;
+    %assign/vec4 v0xc4f3469e0_0, 0;
+T_15.8 ;
+T_15.5 ;
+T_15.3 ;
+T_15.1 ;
+    %jmp T_15;
+    .thread T_15;
+    .scope S_0xc4f348c00;
+T_16 ;
+    %wait E_0xc4ef18b80;
+    %load/vec4 v0xc4f352580_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_16.0, 8;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3524e0_0, 0;
+    %pushi/vec4 0, 0, 32;
+    %assign/vec4 v0xc4f351fe0_0, 0;
+    %pushi/vec4 0, 0, 8;
+    %assign/vec4 v0xc4f352940_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f352260_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3523a0_0, 0;
+    %jmp T_16.1;
+T_16.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3523a0_0, 0;
+    %load/vec4 v0xc4f352620_0;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_16.4, 9;
+    %load/vec4 v0xc4f352260_0;
+    %nor/r;
+    %and;
+T_16.4;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_16.2, 8;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3524e0_0, 0;
+    %pushi/vec4 0, 0, 32;
+    %assign/vec4 v0xc4f351fe0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f352260_0, 0;
+    %jmp T_16.3;
+T_16.2 ;
+    %load/vec4 v0xc4f352260_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_16.5, 8;
+    %load/vec4 v0xc4f3524e0_0;
+    %pad/u 32;
+    %cmpi/e 0, 0, 32;
+    %jmp/0xz  T_16.7, 4;
+    %load/vec4 v0xc4f352440_0;
+    %assign/vec4 v0xc4f351fe0_0, 0;
+    %load/vec4 v0xc4f352440_0;
+    %cmpi/s 0, 0, 32;
+    %flag_or 5, 4;
+    %jmp/0xz  T_16.9, 5;
+    %pushi/vec4 0, 0, 8;
+    %assign/vec4 v0xc4f352940_0, 0;
+    %jmp T_16.10;
+T_16.9 ;
+    %load/vec4 v0xc4f352440_0;
+    %cmpi/s 127, 0, 32;
+    %flag_or 5, 4; GT is !LE
+    %flag_inv 5;
+    %jmp/0xz  T_16.11, 5;
+    %pushi/vec4 127, 0, 8;
+    %assign/vec4 v0xc4f352940_0, 0;
+    %jmp T_16.12;
+T_16.11 ;
+    %load/vec4 v0xc4f352440_0;
+    %parti/s 8, 0, 2;
+    %assign/vec4 v0xc4f352940_0, 0;
+T_16.12 ;
+T_16.10 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f352260_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f3523a0_0, 0;
+    %jmp T_16.8;
+T_16.7 ;
+    %load/vec4 v0xc4f352080_0;
+    %assign/vec4 v0xc4f351fe0_0, 0;
+    %load/vec4 v0xc4f3524e0_0;
+    %addi 1, 0, 1;
+    %assign/vec4 v0xc4f3524e0_0, 0;
+T_16.8 ;
+T_16.5 ;
+T_16.3 ;
+T_16.1 ;
+    %jmp T_16;
+    .thread T_16;
+    .scope S_0xc4f357480;
+T_17 ;
+    %wait E_0xc4ef18b80;
+    %load/vec4 v0xc4f380500_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_17.0, 8;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f380460_0, 0;
+    %pushi/vec4 0, 0, 32;
+    %assign/vec4 v0xc4f373f20_0, 0;
+    %pushi/vec4 0, 0, 8;
+    %assign/vec4 v0xc4f3808c0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3801e0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f380320_0, 0;
+    %jmp T_17.1;
+T_17.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f380320_0, 0;
+    %load/vec4 v0xc4f3805a0_0;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_17.4, 9;
+    %load/vec4 v0xc4f3801e0_0;
+    %nor/r;
+    %and;
+T_17.4;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_17.2, 8;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f380460_0, 0;
+    %pushi/vec4 0, 0, 32;
+    %assign/vec4 v0xc4f373f20_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f3801e0_0, 0;
+    %jmp T_17.3;
+T_17.2 ;
+    %load/vec4 v0xc4f3801e0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_17.5, 8;
+    %load/vec4 v0xc4f380460_0;
+    %pad/u 32;
+    %cmpi/e 1, 0, 32;
+    %jmp/0xz  T_17.7, 4;
+    %load/vec4 v0xc4f3803c0_0;
+    %assign/vec4 v0xc4f373f20_0, 0;
+    %load/vec4 v0xc4f3803c0_0;
+    %cmpi/s 0, 0, 32;
+    %flag_or 5, 4;
+    %jmp/0xz  T_17.9, 5;
+    %pushi/vec4 0, 0, 8;
+    %assign/vec4 v0xc4f3808c0_0, 0;
+    %jmp T_17.10;
+T_17.9 ;
+    %load/vec4 v0xc4f3803c0_0;
+    %cmpi/s 127, 0, 32;
+    %flag_or 5, 4; GT is !LE
+    %flag_inv 5;
+    %jmp/0xz  T_17.11, 5;
+    %pushi/vec4 127, 0, 8;
+    %assign/vec4 v0xc4f3808c0_0, 0;
+    %jmp T_17.12;
+T_17.11 ;
+    %load/vec4 v0xc4f3803c0_0;
+    %parti/s 8, 0, 2;
+    %assign/vec4 v0xc4f3808c0_0, 0;
+T_17.12 ;
+T_17.10 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3801e0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f380320_0, 0;
+    %jmp T_17.8;
+T_17.7 ;
+    %load/vec4 v0xc4f380000_0;
+    %assign/vec4 v0xc4f373f20_0, 0;
+    %load/vec4 v0xc4f380460_0;
+    %addi 1, 0, 1;
+    %assign/vec4 v0xc4f380460_0, 0;
+T_17.8 ;
+T_17.5 ;
+T_17.3 ;
+T_17.1 ;
+    %jmp T_17;
+    .thread T_17;
+    .scope S_0xc4f378180;
+T_18 ;
+    %wait E_0xc4ef18b80;
+    %load/vec4 v0xc4f384dc0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_18.0, 8;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f384d20_0, 0;
+    %pushi/vec4 0, 0, 32;
+    %assign/vec4 v0xc4f384820_0, 0;
+    %pushi/vec4 0, 0, 8;
+    %assign/vec4 v0xc4f385180_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f384aa0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f384be0_0, 0;
+    %jmp T_18.1;
+T_18.0 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f384be0_0, 0;
+    %load/vec4 v0xc4f384e60_0;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_18.4, 9;
+    %load/vec4 v0xc4f384aa0_0;
+    %nor/r;
+    %and;
+T_18.4;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_18.2, 8;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f384d20_0, 0;
+    %pushi/vec4 0, 0, 32;
+    %assign/vec4 v0xc4f384820_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f384aa0_0, 0;
+    %jmp T_18.3;
+T_18.2 ;
+    %load/vec4 v0xc4f384aa0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_18.5, 8;
+    %load/vec4 v0xc4f384d20_0;
+    %pad/u 32;
+    %cmpi/e 4294967295, 0, 32;
+    %jmp/0xz  T_18.7, 4;
+    %load/vec4 v0xc4f384c80_0;
+    %assign/vec4 v0xc4f384820_0, 0;
+    %load/vec4 v0xc4f384c80_0;
+    %cmpi/s 0, 0, 32;
+    %flag_or 5, 4;
+    %jmp/0xz  T_18.9, 5;
+    %pushi/vec4 0, 0, 8;
+    %assign/vec4 v0xc4f385180_0, 0;
+    %jmp T_18.10;
+T_18.9 ;
+    %load/vec4 v0xc4f384c80_0;
+    %cmpi/s 127, 0, 32;
+    %flag_or 5, 4; GT is !LE
+    %flag_inv 5;
+    %jmp/0xz  T_18.11, 5;
+    %pushi/vec4 127, 0, 8;
+    %assign/vec4 v0xc4f385180_0, 0;
+    %jmp T_18.12;
+T_18.11 ;
+    %load/vec4 v0xc4f384c80_0;
+    %parti/s 8, 0, 2;
+    %assign/vec4 v0xc4f385180_0, 0;
+T_18.12 ;
+T_18.10 ;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f384aa0_0, 0;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f384be0_0, 0;
+    %jmp T_18.8;
+T_18.7 ;
+    %load/vec4 v0xc4f3848c0_0;
+    %assign/vec4 v0xc4f384820_0, 0;
+    %load/vec4 v0xc4f384d20_0;
+    %addi 1, 0, 1;
+    %assign/vec4 v0xc4f384d20_0, 0;
+T_18.8 ;
+T_18.5 ;
+T_18.3 ;
+T_18.1 ;
+    %jmp T_18;
+    .thread T_18;
+    .scope S_0x102d15030;
+T_19 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xc4f385860_0, 0, 1;
+T_19.0 ;
+    %delay 5000, 0;
+    %load/vec4 v0xc4f385860_0;
+    %inv;
+    %store/vec4 v0xc4f385860_0, 0, 1;
+    %jmp T_19.0;
+T_19.1 ;
+    %end;
+    .thread T_19;
+    .scope S_0x102d15030;
+T_20 ;
+    %vpi_call/w 12 187 "$dumpfile", "sim/parameter_sweep.vcd" {0 0 0};
+    %vpi_call/w 12 188 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x102d15030 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0xc4f385ea0_0, 0, 1;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0xc4f385cc0_0, 0, 32;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0xc4f385d60_0, 0, 32;
+    %pushi/vec4 500, 0, 32;
+    %store/vec4 v0xc4f385e00_0, 0, 32;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xc4f385f40_0, 0, 1;
+    %pushi/vec4 0, 0, 256;
+    %store/vec4 v0xc4f386620_0, 0, 256;
+    %pushi/vec4 0, 0, 256;
+    %store/vec4 v0xc4f386300_0, 0, 256;
+    %pushi/vec4 0, 0, 8;
+    %store/vec4 v0xc4f385220_0, 0, 8;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xc4f385fe0_0, 0, 1;
+    %pushi/vec4 0, 0, 240;
+    %store/vec4 v0xc4f3866c0_0, 0, 240;
+    %pushi/vec4 0, 0, 240;
+    %store/vec4 v0xc4f3863a0_0, 0, 240;
+    %pushi/vec4 0, 0, 8;
+    %store/vec4 v0xc4f3852c0_0, 0, 8;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xc4f386080_0, 0, 1;
+    %pushi/vec4 0, 0, 160;
+    %store/vec4 v0xc4f386760_0, 0, 160;
+    %pushi/vec4 0, 0, 160;
+    %store/vec4 v0xc4f386440_0, 0, 160;
+    %pushi/vec4 0, 0, 8;
+    %store/vec4 v0xc4f385360_0, 0, 8;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xc4f386120_0, 0, 1;
+    %pushi/vec4 0, 0, 512;
+    %store/vec4 v0xc4f386800_0, 0, 512;
+    %pushi/vec4 0, 0, 512;
+    %store/vec4 v0xc4f3864e0_0, 0, 512;
+    %pushi/vec4 0, 0, 8;
+    %store/vec4 v0xc4f385400_0, 0, 8;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xc4f3861c0_0, 0, 1;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0xc4f3868a0_0, 0, 32;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0xc4f386580_0, 0, 32;
+    %pushi/vec4 0, 0, 8;
+    %store/vec4 v0xc4f3854a0_0, 0, 8;
+    %pushi/vec4 2, 0, 32;
+T_20.0 %dup/vec4;
+    %cmpi/s 0, 0, 32;
+    %jmp/1xz T_20.1, 5;
+    %jmp/1 T_20.1, 4;
+    %subi 1, 0, 32;
+    %wait E_0xc4ef18b80;
+    %jmp T_20.0;
+T_20.1 ;
+    %pop/vec4 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xc4f385ea0_0, 0, 1;
+    %vpi_call/w 12 204 "$display", "\000" {0 0 0};
+    %vpi_call/w 12 205 "$display", "========================================" {0 0 0};
+    %vpi_call/w 12 206 "$display", "PHASE 2 - PARAMETER SWEEP" {0 0 0};
+    %vpi_call/w 12 207 "$display", "========================================" {0 0 0};
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+T_20.2 ; Top of for-loop
+    %load/vec4 v0xc4f385900_0;
+    %cmpi/s 32, 0, 32;
+	  %jmp/0xz T_20.3, 5;
+    %pushi/vec4 1, 0, 8;
+    %load/vec4 v0xc4f385900_0;
+    %muli 8, 0, 32;
+    %ix/vec4/s 4;
+    %store/vec4 v0xc4f386620_0, 4, 8;
+    %pushi/vec4 1, 0, 8;
+    %load/vec4 v0xc4f385900_0;
+    %muli 8, 0, 32;
+    %ix/vec4/s 4;
+    %store/vec4 v0xc4f386300_0, 4, 8;
+T_20.4 ; for-loop step statement
+    %load/vec4 v0xc4f385900_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+    %jmp T_20.2;
+T_20.3 ; for-loop exit label
+    %pushi/vec4 0, 0, 8;
+    %store/vec4 v0xc4f385220_0, 0, 8;
+    %wait E_0xc4ef18b80;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f385f40_0, 0;
+    %wait E_0xc4ef18b80;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f385f40_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xc4f386260_0, 0, 1;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+T_20.5 ;
+    %load/vec4 v0xc4f3859a0_0;
+    %nor/r;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_20.7, 9;
+    %load/vec4 v0xc4f386260_0;
+    %nor/r;
+    %and;
+T_20.7;
+    %flag_set/vec4 8;
+    %jmp/0xz T_20.6, 8;
+    %wait E_0xc4ef18b80;
+    %load/vec4 v0xc4f385900_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+    %load/vec4 v0xc4f385e00_0;
+    %load/vec4 v0xc4f385900_0;
+    %cmp/s;
+    %jmp/0xz  T_20.8, 5;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0xc4f386260_0, 0, 1;
+T_20.8 ;
+    %jmp T_20.5;
+T_20.6 ;
+    %wait E_0xc4ef18b80;
+    %vpi_call/w 12 231 "$display", "\000" {0 0 0};
+    %vpi_call/w 12 232 "$display", "CONFIG A: N_INPUTS=%0d PARALLEL=%0d (exact, GROUPS=%0d)", P_0xc4f2bc080, P_0xc4f2bc0c0, 32'sb00000000000000000000000000000100 {0 0 0};
+    %load/vec4 v0xc4f386260_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_20.10, 8;
+    %vpi_call/w 12 235 "$display", "  RESULT: TIMEOUT (did not assert done within %0d cycles)", v0xc4f385e00_0 {0 0 0};
+    %load/vec4 v0xc4f385cc0_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385cc0_0, 0, 32;
+    %jmp T_20.11;
+T_20.10 ;
+    %vpi_call/w 12 238 "$display", "  y = %0d   expected = 32", v0xc4f386940_0 {0 0 0};
+    %load/vec4 v0xc4f386940_0;
+    %cmpi/ne 32, 0, 8;
+    %jmp/0xz  T_20.12, 6;
+    %vpi_call/w 12 240 "$display", "  FAIL" {0 0 0};
+    %load/vec4 v0xc4f385cc0_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385cc0_0, 0, 32;
+    %jmp T_20.13;
+T_20.12 ;
+    %vpi_call/w 12 243 "$display", "  PASS" {0 0 0};
+T_20.13 ;
+T_20.11 ;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+T_20.14 ; Top of for-loop
+    %load/vec4 v0xc4f385900_0;
+    %cmpi/s 30, 0, 32;
+	  %jmp/0xz T_20.15, 5;
+    %pushi/vec4 1, 0, 8;
+    %load/vec4 v0xc4f385900_0;
+    %muli 8, 0, 32;
+    %ix/vec4/s 4;
+    %store/vec4 v0xc4f3866c0_0, 4, 8;
+    %pushi/vec4 1, 0, 8;
+    %load/vec4 v0xc4f385900_0;
+    %muli 8, 0, 32;
+    %ix/vec4/s 4;
+    %store/vec4 v0xc4f3863a0_0, 4, 8;
+T_20.16 ; for-loop step statement
+    %load/vec4 v0xc4f385900_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+    %jmp T_20.14;
+T_20.15 ; for-loop exit label
+    %pushi/vec4 0, 0, 8;
+    %store/vec4 v0xc4f3852c0_0, 0, 8;
+    %wait E_0xc4ef18b80;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f385fe0_0, 0;
+    %wait E_0xc4ef18b80;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f385fe0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xc4f386260_0, 0, 1;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+T_20.17 ;
+    %load/vec4 v0xc4f385a40_0;
+    %nor/r;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_20.19, 9;
+    %load/vec4 v0xc4f386260_0;
+    %nor/r;
+    %and;
+T_20.19;
+    %flag_set/vec4 8;
+    %jmp/0xz T_20.18, 8;
+    %wait E_0xc4ef18b80;
+    %load/vec4 v0xc4f385900_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+    %load/vec4 v0xc4f385e00_0;
+    %load/vec4 v0xc4f385900_0;
+    %cmp/s;
+    %jmp/0xz  T_20.20, 5;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0xc4f386260_0, 0, 1;
+T_20.20 ;
+    %jmp T_20.17;
+T_20.18 ;
+    %wait E_0xc4ef18b80;
+    %vpi_call/w 12 274 "$display", "\000" {0 0 0};
+    %vpi_call/w 12 275 "$display", "CONFIG B: N_INPUTS=%0d PARALLEL=%0d (NON-exact, GROUPS=%0d, %0d inputs actually read)", P_0xc4f2bc180, P_0xc4f2bc1c0, 32'sb00000000000000000000000000000011, 32'sb00000000000000000000000000011000 {0 0 0};
+    %load/vec4 v0xc4f386260_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_20.22, 8;
+    %vpi_call/w 12 279 "$display", "  RESULT: TIMEOUT (did not assert done within %0d cycles)", v0xc4f385e00_0 {0 0 0};
+    %load/vec4 v0xc4f385cc0_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385cc0_0, 0, 32;
+    %jmp T_20.23;
+T_20.22 ;
+    %vpi_call/w 12 282 "$display", "  y = %0d   RTL-truncated expected = 24   full-sum (NOT met) = 30", v0xc4f3869e0_0 {0 0 0};
+    %load/vec4 v0xc4f3869e0_0;
+    %cmpi/ne 24, 0, 8;
+    %jmp/0xz  T_20.24, 6;
+    %vpi_call/w 12 284 "$display", "  FAIL (unexpected value for current RTL behavior)" {0 0 0};
+    %load/vec4 v0xc4f385cc0_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385cc0_0, 0, 32;
+    %jmp T_20.25;
+T_20.24 ;
+    %vpi_call/w 12 287 "$display", "  PASS (matches current RTL truncation behavior)" {0 0 0};
+T_20.25 ;
+    %load/vec4 v0xc4f3869e0_0;
+    %cmpi/ne 30, 0, 8;
+    %jmp/0xz  T_20.26, 6;
+    %vpi_call/w 12 290 "$display", "  FINDING: last %0d input(s) are silently ignored (GROUPS = N_INPUTS/PARALLEL truncates)", 32'sb00000000000000000000000000000110 {0 0 0};
+    %load/vec4 v0xc4f385d60_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385d60_0, 0, 32;
+T_20.26 ;
+T_20.23 ;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+T_20.28 ; Top of for-loop
+    %load/vec4 v0xc4f385900_0;
+    %cmpi/s 20, 0, 32;
+	  %jmp/0xz T_20.29, 5;
+    %pushi/vec4 1, 0, 8;
+    %load/vec4 v0xc4f385900_0;
+    %muli 8, 0, 32;
+    %ix/vec4/s 4;
+    %store/vec4 v0xc4f386760_0, 4, 8;
+    %pushi/vec4 1, 0, 8;
+    %load/vec4 v0xc4f385900_0;
+    %muli 8, 0, 32;
+    %ix/vec4/s 4;
+    %store/vec4 v0xc4f386440_0, 4, 8;
+T_20.30 ; for-loop step statement
+    %load/vec4 v0xc4f385900_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+    %jmp T_20.28;
+T_20.29 ; for-loop exit label
+    %pushi/vec4 0, 0, 8;
+    %store/vec4 v0xc4f385360_0, 0, 8;
+    %wait E_0xc4ef18b80;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f386080_0, 0;
+    %wait E_0xc4ef18b80;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f386080_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xc4f386260_0, 0, 1;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+T_20.31 ;
+    %load/vec4 v0xc4f385ae0_0;
+    %nor/r;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_20.33, 9;
+    %load/vec4 v0xc4f386260_0;
+    %nor/r;
+    %and;
+T_20.33;
+    %flag_set/vec4 8;
+    %jmp/0xz T_20.32, 8;
+    %wait E_0xc4ef18b80;
+    %load/vec4 v0xc4f385900_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+    %load/vec4 v0xc4f385e00_0;
+    %load/vec4 v0xc4f385900_0;
+    %cmp/s;
+    %jmp/0xz  T_20.34, 5;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0xc4f386260_0, 0, 1;
+T_20.34 ;
+    %jmp T_20.31;
+T_20.32 ;
+    %wait E_0xc4ef18b80;
+    %vpi_call/w 12 318 "$display", "\000" {0 0 0};
+    %vpi_call/w 12 319 "$display", "CONFIG C: N_INPUTS=%0d PARALLEL=%0d (NON-exact, GROUPS=%0d, %0d inputs actually read)", P_0xc4f2bc280, P_0xc4f2bc2c0, 32'sb00000000000000000000000000000001, 32'sb00000000000000000000000000010000 {0 0 0};
+    %load/vec4 v0xc4f386260_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_20.36, 8;
+    %vpi_call/w 12 323 "$display", "  RESULT: TIMEOUT (did not assert done within %0d cycles)", v0xc4f385e00_0 {0 0 0};
+    %load/vec4 v0xc4f385cc0_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385cc0_0, 0, 32;
+    %jmp T_20.37;
+T_20.36 ;
+    %vpi_call/w 12 326 "$display", "  y = %0d   RTL-truncated expected = 16   full-sum (NOT met) = 20", v0xc4f386a80_0 {0 0 0};
+    %load/vec4 v0xc4f386a80_0;
+    %cmpi/ne 16, 0, 8;
+    %jmp/0xz  T_20.38, 6;
+    %vpi_call/w 12 328 "$display", "  FAIL (unexpected value for current RTL behavior)" {0 0 0};
+    %load/vec4 v0xc4f385cc0_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385cc0_0, 0, 32;
+    %jmp T_20.39;
+T_20.38 ;
+    %vpi_call/w 12 331 "$display", "  PASS (matches current RTL truncation behavior)" {0 0 0};
+T_20.39 ;
+    %load/vec4 v0xc4f386a80_0;
+    %cmpi/ne 20, 0, 8;
+    %jmp/0xz  T_20.40, 6;
+    %vpi_call/w 12 334 "$display", "  FINDING: last %0d input(s) are silently ignored (GROUPS = N_INPUTS/PARALLEL truncates)", 32'sb00000000000000000000000000000100 {0 0 0};
+    %load/vec4 v0xc4f385d60_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385d60_0, 0, 32;
+T_20.40 ;
+T_20.37 ;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+T_20.42 ; Top of for-loop
+    %load/vec4 v0xc4f385900_0;
+    %cmpi/s 64, 0, 32;
+	  %jmp/0xz T_20.43, 5;
+    %pushi/vec4 1, 0, 8;
+    %load/vec4 v0xc4f385900_0;
+    %muli 8, 0, 32;
+    %ix/vec4/s 4;
+    %store/vec4 v0xc4f386800_0, 4, 8;
+    %pushi/vec4 1, 0, 8;
+    %load/vec4 v0xc4f385900_0;
+    %muli 8, 0, 32;
+    %ix/vec4/s 4;
+    %store/vec4 v0xc4f3864e0_0, 4, 8;
+T_20.44 ; for-loop step statement
+    %load/vec4 v0xc4f385900_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+    %jmp T_20.42;
+T_20.43 ; for-loop exit label
+    %pushi/vec4 0, 0, 8;
+    %store/vec4 v0xc4f385400_0, 0, 8;
+    %wait E_0xc4ef18b80;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f386120_0, 0;
+    %wait E_0xc4ef18b80;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f386120_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xc4f386260_0, 0, 1;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+T_20.45 ;
+    %load/vec4 v0xc4f385b80_0;
+    %nor/r;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_20.47, 9;
+    %load/vec4 v0xc4f386260_0;
+    %nor/r;
+    %and;
+T_20.47;
+    %flag_set/vec4 8;
+    %jmp/0xz T_20.46, 8;
+    %wait E_0xc4ef18b80;
+    %load/vec4 v0xc4f385900_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+    %load/vec4 v0xc4f385e00_0;
+    %load/vec4 v0xc4f385900_0;
+    %cmp/s;
+    %jmp/0xz  T_20.48, 5;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0xc4f386260_0, 0, 1;
+T_20.48 ;
+    %jmp T_20.45;
+T_20.46 ;
+    %wait E_0xc4ef18b80;
+    %vpi_call/w 12 362 "$display", "\000" {0 0 0};
+    %vpi_call/w 12 363 "$display", "CONFIG D: N_INPUTS=%0d PARALLEL=%0d (exact, GROUPS=%0d)", P_0xc4f2bc380, P_0xc4f2bc3c0, 32'sb00000000000000000000000000000010 {0 0 0};
+    %load/vec4 v0xc4f386260_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_20.50, 8;
+    %vpi_call/w 12 366 "$display", "  RESULT: TIMEOUT (did not assert done within %0d cycles)", v0xc4f385e00_0 {0 0 0};
+    %load/vec4 v0xc4f385cc0_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385cc0_0, 0, 32;
+    %jmp T_20.51;
+T_20.50 ;
+    %vpi_call/w 12 369 "$display", "  y = %0d   expected = 64", v0xc4f386b20_0 {0 0 0};
+    %load/vec4 v0xc4f386b20_0;
+    %cmpi/ne 64, 0, 8;
+    %jmp/0xz  T_20.52, 6;
+    %vpi_call/w 12 371 "$display", "  FAIL" {0 0 0};
+    %load/vec4 v0xc4f385cc0_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385cc0_0, 0, 32;
+    %jmp T_20.53;
+T_20.52 ;
+    %vpi_call/w 12 374 "$display", "  PASS" {0 0 0};
+T_20.53 ;
+T_20.51 ;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+T_20.54 ; Top of for-loop
+    %load/vec4 v0xc4f385900_0;
+    %cmpi/s 4, 0, 32;
+	  %jmp/0xz T_20.55, 5;
+    %pushi/vec4 1, 0, 8;
+    %load/vec4 v0xc4f385900_0;
+    %muli 8, 0, 32;
+    %ix/vec4/s 4;
+    %store/vec4 v0xc4f3868a0_0, 4, 8;
+    %pushi/vec4 1, 0, 8;
+    %load/vec4 v0xc4f385900_0;
+    %muli 8, 0, 32;
+    %ix/vec4/s 4;
+    %store/vec4 v0xc4f386580_0, 4, 8;
+T_20.56 ; for-loop step statement
+    %load/vec4 v0xc4f385900_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+    %jmp T_20.54;
+T_20.55 ; for-loop exit label
+    %pushi/vec4 0, 0, 8;
+    %store/vec4 v0xc4f3854a0_0, 0, 8;
+    %wait E_0xc4ef18b80;
+    %pushi/vec4 1, 0, 1;
+    %assign/vec4 v0xc4f3861c0_0, 0;
+    %wait E_0xc4ef18b80;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v0xc4f3861c0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0xc4f386260_0, 0, 1;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+T_20.57 ;
+    %load/vec4 v0xc4f385c20_0;
+    %nor/r;
+    %flag_set/vec4 9;
+    %flag_get/vec4 9;
+    %jmp/0 T_20.59, 9;
+    %load/vec4 v0xc4f386260_0;
+    %nor/r;
+    %and;
+T_20.59;
+    %flag_set/vec4 8;
+    %jmp/0xz T_20.58, 8;
+    %wait E_0xc4ef18b80;
+    %load/vec4 v0xc4f385900_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385900_0, 0, 32;
+    %load/vec4 v0xc4f385e00_0;
+    %load/vec4 v0xc4f385900_0;
+    %cmp/s;
+    %jmp/0xz  T_20.60, 5;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0xc4f386260_0, 0, 1;
+T_20.60 ;
+    %jmp T_20.57;
+T_20.58 ;
+    %wait E_0xc4ef18b80;
+    %vpi_call/w 12 401 "$display", "\000" {0 0 0};
+    %vpi_call/w 12 402 "$display", "CONFIG E: N_INPUTS=%0d PARALLEL=%0d (DEGENERATE, GROUPS=%0d)", P_0xc4f2bc480, P_0xc4f2bc4c0, 32'sb00000000000000000000000000000000 {0 0 0};
+    %load/vec4 v0xc4f386260_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_20.62, 8;
+    %vpi_call/w 12 405 "$display", "  RESULT: TIMEOUT as expected (done never asserted within %0d cycles)", v0xc4f385e00_0 {0 0 0};
+    %vpi_call/w 12 406 "$display", "  FINDING: PARALLEL > N_INPUTS (GROUPS=0) hangs neuron_parallel forever -- design constraint, not currently guarded in RTL" {0 0 0};
+    %load/vec4 v0xc4f385d60_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385d60_0, 0, 32;
+    %jmp T_20.63;
+T_20.62 ;
+    %vpi_call/w 12 409 "$display", "  RESULT: completed with y=%0d (unexpected -- previously assumed to hang)", v0xc4f386bc0_0 {0 0 0};
+    %load/vec4 v0xc4f385cc0_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0xc4f385cc0_0, 0, 32;
+T_20.63 ;
+    %vpi_call/w 12 413 "$display", "\000" {0 0 0};
+    %vpi_call/w 12 414 "$display", "========================================" {0 0 0};
+    %vpi_call/w 12 415 "$display", "PARAMETER SWEEP SUMMARY" {0 0 0};
+    %vpi_call/w 12 416 "$display", "  errors   = %0d", v0xc4f385cc0_0 {0 0 0};
+    %vpi_call/w 12 417 "$display", "  findings = %0d (documented limitations, not bench failures)", v0xc4f385d60_0 {0 0 0};
+    %load/vec4 v0xc4f385cc0_0;
+    %cmpi/e 0, 0, 32;
+    %jmp/0xz  T_20.64, 4;
+    %vpi_call/w 12 419 "$display", "PARAMETER SWEEP: PASSED (all configs behaved as characterized)" {0 0 0};
+    %jmp T_20.65;
+T_20.64 ;
+    %vpi_call/w 12 421 "$display", "PARAMETER SWEEP: FAILED" {0 0 0};
+T_20.65 ;
+    %vpi_call/w 12 422 "$display", "========================================" {0 0 0};
+    %vpi_call/w 12 423 "$display", "\000" {0 0 0};
+    %vpi_call/w 12 425 "$finish" {0 0 0};
+    %end;
+    .thread T_20;
+# The file index is used to find the file name in the following table.
+:file_names 13;
+    "N/A";
+    "<interactive>";
+    "-";
+    "rtl/layer.v";
+    "rtl/neuron_parallel.v";
+    "rtl/mac8.v";
+    "rtl/mac_unit.v";
+    "rtl/memory_interface.v";
+    "rtl/memory_model.v";
+    "rtl/neuron_memory.v";
+    "rtl/int8_memory_access.v";
+    "rtl/psram_controller.v";
+    "sim/parameter_sweep_tb.v";
diff --git a/sim/parameter_sweep_tb.v b/sim/parameter_sweep_tb.v
new file mode 100644
index 0000000..01f0442
--- /dev/null
+++ b/sim/parameter_sweep_tb.v
@@ -0,0 +1,428 @@
+`timescale 1ns/1ps
+
+// ================================================================
+// PHASE 2 - PARAMETER SWEEP
+//
+// Roadmap requirement (docs/FPGA-NeuralNetwork-Engine.md, Phase 2):
+// validate multiple combinations of N_INPUTS / N_NEURONS / PARALLEL,
+// including configurations where N_INPUTS is NOT an exact multiple
+// of PARALLEL.
+//
+// neuron_parallel.v computes:
+//     localparam GROUPS = N_INPUTS / PARALLEL;
+// which is an INTEGER division. When N_INPUTS is not an exact
+// multiple of PARALLEL, the remainder inputs are silently never
+// read by the accumulator (GEN_TREE only ever selects the first
+// GROUPS*PARALLEL inputs). This bench characterizes that behavior
+// instead of assuming it does not exist, and uses a cycle-count
+// watchdog (never a blocking `wait`) so a config that never
+// asserts `done` is reported instead of hanging the simulation.
+// ================================================================
+
+module tb;
+
+    reg clk;
+    reg rst;
+
+    initial begin
+        clk = 0;
+        forever #5 clk = ~clk;
+    end
+
+    integer errors;
+    integer findings;
+
+    // ============================================================
+    // CONFIG A - baseline, exact multiple (sanity check)
+    // N_INPUTS=32 PARALLEL=8 -> GROUPS=4
+    // ============================================================
+
+    localparam A_DATA_WIDTH = 8;
+    localparam A_N_INPUTS   = 32;
+    localparam A_PARALLEL   = 8;
+    localparam A_ACC_WIDTH  = 32;
+
+    reg start_a;
+    reg signed [A_DATA_WIDTH*A_N_INPUTS-1:0] x_bus_a;
+    reg signed [A_DATA_WIDTH*A_N_INPUTS-1:0] w_bus_a;
+    reg signed [A_DATA_WIDTH-1:0] bias_a;
+    wire signed [A_DATA_WIDTH-1:0] y_a;
+    wire busy_a, done_a;
+
+    neuron_parallel #(
+        .DATA_WIDTH(A_DATA_WIDTH),
+        .N_INPUTS(A_N_INPUTS),
+        .PARALLEL(A_PARALLEL),
+        .ACC_WIDTH(A_ACC_WIDTH)
+    ) u_a (
+        .clk(clk), .rst(rst), .start(start_a),
+        .x_bus(x_bus_a), .w_bus(w_bus_a), .bias(bias_a),
+        .y(y_a), .busy(busy_a), .done(done_a)
+    );
+
+    // ============================================================
+    // CONFIG B - non-exact multiple
+    // N_INPUTS=30 PARALLEL=8 -> GROUPS=3 (24 inputs actually summed)
+    // ============================================================
+
+    localparam B_DATA_WIDTH = 8;
+    localparam B_N_INPUTS   = 30;
+    localparam B_PARALLEL   = 8;
+    localparam B_ACC_WIDTH  = 32;
+
+    reg start_b;
+    reg signed [B_DATA_WIDTH*B_N_INPUTS-1:0] x_bus_b;
+    reg signed [B_DATA_WIDTH*B_N_INPUTS-1:0] w_bus_b;
+    reg signed [B_DATA_WIDTH-1:0] bias_b;
+    wire signed [B_DATA_WIDTH-1:0] y_b;
+    wire busy_b, done_b;
+
+    neuron_parallel #(
+        .DATA_WIDTH(B_DATA_WIDTH),
+        .N_INPUTS(B_N_INPUTS),
+        .PARALLEL(B_PARALLEL),
+        .ACC_WIDTH(B_ACC_WIDTH)
+    ) u_b (
+        .clk(clk), .rst(rst), .start(start_b),
+        .x_bus(x_bus_b), .w_bus(w_bus_b), .bias(bias_b),
+        .y(y_b), .busy(busy_b), .done(done_b)
+    );
+
+    // ============================================================
+    // CONFIG C - non-exact multiple, different PARALLEL
+    // N_INPUTS=20 PARALLEL=16 -> GROUPS=1 (16 inputs actually summed)
+    // ============================================================
+
+    localparam C_DATA_WIDTH = 8;
+    localparam C_N_INPUTS   = 20;
+    localparam C_PARALLEL   = 16;
+    localparam C_ACC_WIDTH  = 32;
+
+    reg start_c;
+    reg signed [C_DATA_WIDTH*C_N_INPUTS-1:0] x_bus_c;
+    reg signed [C_DATA_WIDTH*C_N_INPUTS-1:0] w_bus_c;
+    reg signed [C_DATA_WIDTH-1:0] bias_c;
+    wire signed [C_DATA_WIDTH-1:0] y_c;
+    wire busy_c, done_c;
+
+    neuron_parallel #(
+        .DATA_WIDTH(C_DATA_WIDTH),
+        .N_INPUTS(C_N_INPUTS),
+        .PARALLEL(C_PARALLEL),
+        .ACC_WIDTH(C_ACC_WIDTH)
+    ) u_c (
+        .clk(clk), .rst(rst), .start(start_c),
+        .x_bus(x_bus_c), .w_bus(w_bus_c), .bias(bias_c),
+        .y(y_c), .busy(busy_c), .done(done_c)
+    );
+
+    // ============================================================
+    // CONFIG D - exact multiple, wide parallelism (sanity check)
+    // N_INPUTS=64 PARALLEL=32 -> GROUPS=2
+    // ============================================================
+
+    localparam D_DATA_WIDTH = 8;
+    localparam D_N_INPUTS   = 64;
+    localparam D_PARALLEL   = 32;
+    localparam D_ACC_WIDTH  = 32;
+
+    reg start_d;
+    reg signed [D_DATA_WIDTH*D_N_INPUTS-1:0] x_bus_d;
+    reg signed [D_DATA_WIDTH*D_N_INPUTS-1:0] w_bus_d;
+    reg signed [D_DATA_WIDTH-1:0] bias_d;
+    wire signed [D_DATA_WIDTH-1:0] y_d;
+    wire busy_d, done_d;
+
+    neuron_parallel #(
+        .DATA_WIDTH(D_DATA_WIDTH),
+        .N_INPUTS(D_N_INPUTS),
+        .PARALLEL(D_PARALLEL),
+        .ACC_WIDTH(D_ACC_WIDTH)
+    ) u_d (
+        .clk(clk), .rst(rst), .start(start_d),
+        .x_bus(x_bus_d), .w_bus(w_bus_d), .bias(bias_d),
+        .y(y_d), .busy(busy_d), .done(done_d)
+    );
+
+    // ============================================================
+    // CONFIG E - degenerate: PARALLEL > N_INPUTS
+    // N_INPUTS=4 PARALLEL=8 -> GROUPS=0
+    // Watchdog-guarded: expected to NOT complete (documents the
+    // constraint "PARALLEL must not exceed N_INPUTS").
+    // ============================================================
+
+    localparam E_DATA_WIDTH = 8;
+    localparam E_N_INPUTS   = 4;
+    localparam E_PARALLEL   = 8;
+    localparam E_ACC_WIDTH  = 32;
+
+    reg start_e;
+    reg signed [E_DATA_WIDTH*E_N_INPUTS-1:0] x_bus_e;
+    reg signed [E_DATA_WIDTH*E_N_INPUTS-1:0] w_bus_e;
+    reg signed [E_DATA_WIDTH-1:0] bias_e;
+    wire signed [E_DATA_WIDTH-1:0] y_e;
+    wire busy_e, done_e;
+
+    neuron_parallel #(
+        .DATA_WIDTH(E_DATA_WIDTH),
+        .N_INPUTS(E_N_INPUTS),
+        .PARALLEL(E_PARALLEL),
+        .ACC_WIDTH(E_ACC_WIDTH)
+    ) u_e (
+        .clk(clk), .rst(rst), .start(start_e),
+        .x_bus(x_bus_e), .w_bus(w_bus_e), .bias(bias_e),
+        .y(y_e), .busy(busy_e), .done(done_e)
+    );
+
+    // ============================================================
+    // MAIN
+    // ============================================================
+
+    integer max_cycles;
+    integer count;
+    reg timed_out;
+
+    initial begin
+
+        $dumpfile("sim/parameter_sweep.vcd");
+        $dumpvars(0, tb);
+
+        rst = 1;
+        errors = 0;
+        findings = 0;
+        max_cycles = 500;
+
+        start_a = 0; x_bus_a = 0; w_bus_a = 0; bias_a = 0;
+        start_b = 0; x_bus_b = 0; w_bus_b = 0; bias_b = 0;
+        start_c = 0; x_bus_c = 0; w_bus_c = 0; bias_c = 0;
+        start_d = 0; x_bus_d = 0; w_bus_d = 0; bias_d = 0;
+        start_e = 0; x_bus_e = 0; w_bus_e = 0; bias_e = 0;
+
+        repeat (2) @(posedge clk);
+        rst = 0;
+
+        $display("");
+        $display("========================================");
+        $display("PHASE 2 - PARAMETER SWEEP");
+        $display("========================================");
+
+        // --------------------------------------------------------
+        // CONFIG A: all x=1, all w=1, bias=0
+        // full sum = 32, exact multiple -> expect 32
+        // --------------------------------------------------------
+        for (count = 0; count < A_N_INPUTS; count = count + 1) begin
+            x_bus_a[count*A_DATA_WIDTH +: A_DATA_WIDTH] = 8'sd1;
+            w_bus_a[count*A_DATA_WIDTH +: A_DATA_WIDTH] = 8'sd1;
+        end
+        bias_a = 0;
+
+        @(posedge clk); start_a <= 1'b1;
+        @(posedge clk); start_a <= 1'b0;
+
+        timed_out = 1'b0;
+        count = 0;
+        while (!done_a && !timed_out) begin
+            @(posedge clk);
+            count = count + 1;
+            if (count > max_cycles) timed_out = 1'b1;
+        end
+        @(posedge clk);
+
+        $display("");
+        $display("CONFIG A: N_INPUTS=%0d PARALLEL=%0d (exact, GROUPS=%0d)",
+                  A_N_INPUTS, A_PARALLEL, A_N_INPUTS/A_PARALLEL);
+        if (timed_out) begin
+            $display("  RESULT: TIMEOUT (did not assert done within %0d cycles)", max_cycles);
+            errors = errors + 1;
+        end else begin
+            $display("  y = %0d   expected = 32", y_a);
+            if (y_a !== 8'sd32) begin
+                $display("  FAIL");
+                errors = errors + 1;
+            end else begin
+                $display("  PASS");
+            end
+        end
+
+        // --------------------------------------------------------
+        // CONFIG B: all x=1, all w=1, bias=0
+        // N_INPUTS=30, PARALLEL=8 -> GROUPS=3 -> only first 24
+        // inputs are actually summed by the current RTL.
+        // full-sum expectation would be 30; RTL-truncated
+        // expectation is 24. We check against the RTL-truncated
+        // value and flag the mismatch vs. the full sum as a
+        // documented finding (not a failure of this bench).
+        // --------------------------------------------------------
+        for (count = 0; count < B_N_INPUTS; count = count + 1) begin
+            x_bus_b[count*B_DATA_WIDTH +: B_DATA_WIDTH] = 8'sd1;
+            w_bus_b[count*B_DATA_WIDTH +: B_DATA_WIDTH] = 8'sd1;
+        end
+        bias_b = 0;
+
+        @(posedge clk); start_b <= 1'b1;
+        @(posedge clk); start_b <= 1'b0;
+
+        timed_out = 1'b0;
+        count = 0;
+        while (!done_b && !timed_out) begin
+            @(posedge clk);
+            count = count + 1;
+            if (count > max_cycles) timed_out = 1'b1;
+        end
+        @(posedge clk);
+
+        $display("");
+        $display("CONFIG B: N_INPUTS=%0d PARALLEL=%0d (NON-exact, GROUPS=%0d, %0d inputs actually read)",
+                  B_N_INPUTS, B_PARALLEL, B_N_INPUTS/B_PARALLEL,
+                  (B_N_INPUTS/B_PARALLEL)*B_PARALLEL);
+        if (timed_out) begin
+            $display("  RESULT: TIMEOUT (did not assert done within %0d cycles)", max_cycles);
+            errors = errors + 1;
+        end else begin
+            $display("  y = %0d   RTL-truncated expected = 24   full-sum (NOT met) = 30", y_b);
+            if (y_b !== 8'sd24) begin
+                $display("  FAIL (unexpected value for current RTL behavior)");
+                errors = errors + 1;
+            end else begin
+                $display("  PASS (matches current RTL truncation behavior)");
+            end
+            if (y_b !== B_N_INPUTS[7:0]) begin
+                $display("  FINDING: last %0d input(s) are silently ignored (GROUPS = N_INPUTS/PARALLEL truncates)",
+                          B_N_INPUTS - (B_N_INPUTS/B_PARALLEL)*B_PARALLEL);
+                findings = findings + 1;
+            end
+        end
+
+        // --------------------------------------------------------
+        // CONFIG C: same characterization, different sizes
+        // N_INPUTS=20, PARALLEL=16 -> GROUPS=1 -> only first 16 read
+        // --------------------------------------------------------
+        for (count = 0; count < C_N_INPUTS; count = count + 1) begin
+            x_bus_c[count*C_DATA_WIDTH +: C_DATA_WIDTH] = 8'sd1;
+            w_bus_c[count*C_DATA_WIDTH +: C_DATA_WIDTH] = 8'sd1;
+        end
+        bias_c = 0;
+
+        @(posedge clk); start_c <= 1'b1;
+        @(posedge clk); start_c <= 1'b0;
+
+        timed_out = 1'b0;
+        count = 0;
+        while (!done_c && !timed_out) begin
+            @(posedge clk);
+            count = count + 1;
+            if (count > max_cycles) timed_out = 1'b1;
+        end
+        @(posedge clk);
+
+        $display("");
+        $display("CONFIG C: N_INPUTS=%0d PARALLEL=%0d (NON-exact, GROUPS=%0d, %0d inputs actually read)",
+                  C_N_INPUTS, C_PARALLEL, C_N_INPUTS/C_PARALLEL,
+                  (C_N_INPUTS/C_PARALLEL)*C_PARALLEL);
+        if (timed_out) begin
+            $display("  RESULT: TIMEOUT (did not assert done within %0d cycles)", max_cycles);
+            errors = errors + 1;
+        end else begin
+            $display("  y = %0d   RTL-truncated expected = 16   full-sum (NOT met) = 20", y_c);
+            if (y_c !== 8'sd16) begin
+                $display("  FAIL (unexpected value for current RTL behavior)");
+                errors = errors + 1;
+            end else begin
+                $display("  PASS (matches current RTL truncation behavior)");
+            end
+            if (y_c !== C_N_INPUTS[7:0]) begin
+                $display("  FINDING: last %0d input(s) are silently ignored (GROUPS = N_INPUTS/PARALLEL truncates)",
+                          C_N_INPUTS - (C_N_INPUTS/C_PARALLEL)*C_PARALLEL);
+                findings = findings + 1;
+            end
+        end
+
+        // --------------------------------------------------------
+        // CONFIG D: all x=1, all w=1, bias=0
+        // full sum = 64, exact multiple -> expect 64
+        // --------------------------------------------------------
+        for (count = 0; count < D_N_INPUTS; count = count + 1) begin
+            x_bus_d[count*D_DATA_WIDTH +: D_DATA_WIDTH] = 8'sd1;
+            w_bus_d[count*D_DATA_WIDTH +: D_DATA_WIDTH] = 8'sd1;
+        end
+        bias_d = 0;
+
+        @(posedge clk); start_d <= 1'b1;
+        @(posedge clk); start_d <= 1'b0;
+
+        timed_out = 1'b0;
+        count = 0;
+        while (!done_d && !timed_out) begin
+            @(posedge clk);
+            count = count + 1;
+            if (count > max_cycles) timed_out = 1'b1;
+        end
+        @(posedge clk);
+
+        $display("");
+        $display("CONFIG D: N_INPUTS=%0d PARALLEL=%0d (exact, GROUPS=%0d)",
+                  D_N_INPUTS, D_PARALLEL, D_N_INPUTS/D_PARALLEL);
+        if (timed_out) begin
+            $display("  RESULT: TIMEOUT (did not assert done within %0d cycles)", max_cycles);
+            errors = errors + 1;
+        end else begin
+            $display("  y = %0d   expected = 64", y_d);
+            if (y_d !== 8'sd64) begin
+                $display("  FAIL");
+                errors = errors + 1;
+            end else begin
+                $display("  PASS");
+            end
+        end
+
+        // --------------------------------------------------------
+        // CONFIG E: degenerate PARALLEL > N_INPUTS -> GROUPS=0
+        // We EXPECT this to time out. If it ever completes, that
+        // is itself worth flagging (behavior changed).
+        // --------------------------------------------------------
+        for (count = 0; count < E_N_INPUTS; count = count + 1) begin
+            x_bus_e[count*E_DATA_WIDTH +: E_DATA_WIDTH] = 8'sd1;
+            w_bus_e[count*E_DATA_WIDTH +: E_DATA_WIDTH] = 8'sd1;
+        end
+        bias_e = 0;
+
+        @(posedge clk); start_e <= 1'b1;
+        @(posedge clk); start_e <= 1'b0;
+
+        timed_out = 1'b0;
+        count = 0;
+        while (!done_e && !timed_out) begin
+            @(posedge clk);
+            count = count + 1;
+            if (count > max_cycles) timed_out = 1'b1;
+        end
+        @(posedge clk);
+
+        $display("");
+        $display("CONFIG E: N_INPUTS=%0d PARALLEL=%0d (DEGENERATE, GROUPS=%0d)",
+                  E_N_INPUTS, E_PARALLEL, E_N_INPUTS/E_PARALLEL);
+        if (timed_out) begin
+            $display("  RESULT: TIMEOUT as expected (done never asserted within %0d cycles)", max_cycles);
+            $display("  FINDING: PARALLEL > N_INPUTS (GROUPS=0) hangs neuron_parallel forever -- design constraint, not currently guarded in RTL");
+            findings = findings + 1;
+        end else begin
+            $display("  RESULT: completed with y=%0d (unexpected -- previously assumed to hang)", y_e);
+            errors = errors + 1;
+        end
+
+        $display("");
+        $display("========================================");
+        $display("PARAMETER SWEEP SUMMARY");
+        $display("  errors   = %0d", errors);
+        $display("  findings = %0d (documented limitations, not bench failures)", findings);
+        if (errors == 0)
+            $display("PARAMETER SWEEP: PASSED (all configs behaved as characterized)");
+        else
+            $display("PARAMETER SWEEP: FAILED");
+        $display("========================================");
+        $display("");
+
+        $finish;
+    end
+
+endmodule