feat: real functional xsim verification of N=16 hybrid systolic system (EXP-0092)

tb_n16_system_ddr3.v, adapted from tb_n2_system_ddr3.v's own real DDR3-
model methodology (real mig_7series_0_mig, real 2-chip ddr3_model.sv,
real Vivado xsim). Submits 32 positions across all 4 groups of
n16_system_ddr3_top.v's own real neural_director_grouped.v + 4x
systolic_group.v + 20-way arbiter. 32/32 PASS, 0 errors.

This confirms EXP-0091's synthesis-only result (0 errors, 128
DSP48E1/53.33%) reflected real functional correctness, not just
connectivity -- the grouped Director's octet dispatch, the new
arbiter's slot map, and the shared-weight-broadcast barrier all work
correctly wired together at full N=16 scale.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

hardware/v2/logs/experiments.log

@@ -6240,3 +6240,74 @@ across all 4 groups and verify all 16 real results) before trusting
 this design at all -- synthesis succeeding proves connectivity, not
 correctness. (2) real, full P&R (place_design + route_design) for a
 real timing signoff, only after (1) passes.
+
+EXP-0092 -- real functional xsim of the N=16 hybrid systolic system:
+32/32 PASS against real DDR3 (2026-09-21, self-directed next_action
+from EXP-0091, continuing the user's own "Ok procedi ad implementare
+quel che manca" directive)
+
+CONTEXT: EXP-0091's own synthesis-only result (0 errors, 128 DSP48E1/
+53.33%) proved n16_system_ddr3_top.v's real CONNECTIVITY, explicitly
+NOT functional correctness -- the same class of bus-slicing/arbiter-
+offset bug already found and fixed twice this session (tb_systolic_
+group.v's arbiter offset, EXP-0089; the testbench-submission-doubling
+race, EXP-0090) could still be lurking undetected in this top-level's
+own new 21-way arbiter slot map, unverified until now.
+
+METHOD: new `hardware/v3/sim/tb_n16_system_ddr3.v`, directly adapted
+from tb_n2_system_ddr3.v's own real, proven harness -- SAME real 2-chip
+32-bit DDR3 model (WireDelay + ddr3_model.sv x2), SAME real
+mig_7series_0_mig with SIM_BYPASS_INIT_CAL="FAST", SAME pre_active-
+muxed direct preload path, SAME weight_byte/input_byte golden
+functions -- with neural_director_grouped.v + a real 20-way
+sdram_arbiter_n.v (4 groups' own weight-fetch + 16 PEs' own
+activation-fetch/writeback; no host_mem_bridge.v slot needed here,
+same as tb_n2_system_ddr3.v never instantiates spi_host_bridge_v3.v
+either) + 4x systolic_group.v replacing neural_director_packed.v + 2x
+packed_slot.v. Real, scoped test: ONE shared layer (w_base=0) across
+all 32 positions (simplest real addressing that still exercises every
+one of the 4 groups x 4 PEs x 2 lanes exactly once), each position's
+own golden result computed the same way tb_n2_system_ddr3.v's own
+golden_result() already does (independent of which group actually
+processed it -- checked purely by node_id/value pair, not by
+dispatch order, so the check is valid regardless of the Director's
+own real group-assignment order).
+
+Run via real Vivado xsim (xvlog/xelab/xsim by hand, mirroring EXP-0087/
+0088's own real methodology -- NOT the Icarus-with-stub-primitives
+elaboration-only check EXP-0091 itself used, which cannot instantiate
+the real MIG/DDR3 simulation models at all), same real 68-file MIG
+`user_design/rtl` tree + `ddr3_model.sv` + `wiredly.v` + `glbl.v` file
+set as sim_1's own tb_n2_system_ddr3.v run, RTL set swapped for the
+grouped/systolic modules.
+
+REAL RESULT: xvlog and xelab both clean (0 errors; only the same
+pre-existing MIG-internal `PRESENT_DATA_*` scalar-indexing warnings
+already seen in every prior real xsim of this MIG IP, not new). Real
+xsim run: init_calib_complete reached, both real weight and activation
+preloads completed, all 32 positions submitted and dispatched across
+all 4 real groups, **32/32 PASS, 0 errors, 0 FAIL**, `$finish` at
+190718033500 fs (190718.0335 ns) -- real wall-clock run time ~5m44s.
+Every one of the 4 groups' own 4 PEs' own 2 lanes (a/b) produced the
+exact real golden result, confirming: the grouped Director's own octet
+dispatch and per-PE x_base/result_addr/node_id assignment (EXP-0090,
+previously only unit-tested in isolation) really works wired into the
+full system; the 20-way arbiter's own slot map (4 group weight-fetch +
+16 PE activation/writeback slots, `PE_BASE = N_GROUPS + gg*4`) really
+routes every group's and every PE's own real DDR3 traffic to the
+correct address without cross-talk; and the shared-weight-broadcast
+barrier inside systolic_group.v (EXP-0089, previously only tested with
+1 group in isolation) really scales correctly to 4 concurrent group
+instances contending for the same real DDR3 channel.
+
+DECISION: the N=16 hybrid systolic system's real RTL is now functionally
+verified, not just synthesis-clean. This is the last real gate before
+trusting a P&R timing number -- proceed to real, full P&R (place_design
++ route_design) next.
+
+next_action: real, full P&R (place_design + route_design) for
+n16_system_ddr3_top.v against the real XC7A100T-CSG324-2 part, for a
+real timing signoff (WNS/WHS), per this project's own standing "real,
+measured numbers only" discipline -- EXP-0091's own 128 DSP48E1/53.33%
+utilization projection still needs a real post-route confirmation, and
+timing has not been checked at all yet for this larger top-level.