feat: real functional xsim verification of N=16 hybrid systolic system (EXP-0092)

tb_n16_system_ddr3.v, adapted from tb_n2_system_ddr3.v's own real DDR3-
model methodology (real mig_7series_0_mig, real 2-chip ddr3_model.sv,
real Vivado xsim). Submits 32 positions across all 4 groups of
n16_system_ddr3_top.v's own real neural_director_grouped.v + 4x
systolic_group.v + 20-way arbiter. 32/32 PASS, 0 errors.

This confirms EXP-0091's synthesis-only result (0 errors, 128
DSP48E1/53.33%) reflected real functional correctness, not just
connectivity -- the grouped Director's octet dispatch, the new
arbiter's slot map, and the shared-weight-broadcast barrier all work
correctly wired together at full N=16 scale.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

docs/ARCHITECTURE_ANALYSIS.md

@@ -659,7 +659,7 @@ specifically to document where/how it breaks rather than to succeed):
 
 ---
 
-### 5.6 [Steps 1–3 DONE, EXP-0089/0090/0091] Hybrid systolic scaling: 4 groups × 4-PE weight-stationary chains
+### 5.6 [Steps 1–4 DONE, EXP-0089/0090/0091/0092] Hybrid systolic scaling: 4 groups × 4-PE weight-stationary chains
 
 Captured from a 2026-09-20 brainstorming session as a purely exploratory
 idea; the same day, per the user's own explicit reprioritization, the real
@@ -693,15 +693,25 @@ systolic shift register) was resolved with the user directly (not guessed).
   result: 0 Errors, 128 DSP48E1/240 (53.33%)** — an exact real match to
   this section's own original DSP projection, now confirmed by real
   synthesis rather than estimated.
+- **Real functional verification (EXP-0092)**: `tb_n16_system_ddr3.v`,
+  directly adapted from `tb_n2_system_ddr3.v`'s own real DDR3-model
+  methodology (same real 2-chip 32-bit DDR3 model, same real
+  `mig_7series_0_mig`, real Vivado xsim — not the Icarus-with-stub-
+  primitives check EXP-0091 itself used, which cannot instantiate the
+  real MIG/DDR3 models at all). One shared layer across 32 positions,
+  filling all 4 groups × 4 PEs × 2 lanes exactly once. **Real result:
+  32/32 PASS, 0 errors**, `$finish` at 190718.0335ns — confirms the
+  grouped Director's octet dispatch, the new 21-way→20-way (test-scope,
+  no host slot needed) arbiter's slot map, and the shared-weight-
+  broadcast barrier all really work wired together at full N=16 scale,
+  not just in isolated unit tests.
 
-**Not yet done, real and disclosed**: this top-level has only been
-checked for **synthesis-level connectivity**, NOT yet for **functional
-correctness** (a real xsim test against the real DDR3 model, exercising
-all 4 groups, is the next real step — the same class of bus-slicing bug
-already found and fixed twice this session in similar flattened-bus
-contexts could still be lurking here undetected by synthesis alone) and
-NOT yet for **real timing** (no place_design/route_design run yet) — see
-EXP-0091's own `next_action`.
+**Not yet done, real and disclosed**: **real timing** — no
+place_design/route_design run yet against the real XC7A100T-CSG324-2
+part. EXP-0091's own 128 DSP48E1/240 (53.33%) is a real synthesis-only
+utilization number, not yet post-route-confirmed, and WNS/WHS have not
+been measured at all for this larger top-level — see EXP-0092's own
+`next_action`.
 
 **The problem it targets**: plain N=16 independent cores (§5.5's own
 "documentary, expected to break" framing) means 16 independent DDR3