feat(v2): M10 Optimization - data-driven findings, completes the V2 roadmap
Final milestone of docs/v2-description.md's §33 roadmap, scoped exactly to its own mandate: optimize only on data already gathered in M1-M9, across the pipeline/P_IN/processor-count/scheduling/memory axes - no speculative new features. Three concrete, data-driven results: 1. N_SLOTS=8 (numero processor axis): real synthesis + nextpnr-ecp5 P&R for dataflow_core at N_SLOTS=8, extending M7's N_SLOTS=2/4 sweep to the real DSP ceiling DEC-0005 predicted. 92.63 MHz POST-P&R, PASS at 80MHz, DSP 64/72 (88.9%). DEC-0012 recommends N_SLOTS=8 as the practical ceiling for P_IN=8 on the LFE5U-45F-8BG381. 2. ACC_WIDTH 24 vs 32 (pipeline axis): a real 6-seed nextpnr-ecp5 placement sweep (reusing already-synthesized netlists, no new synthesis needed) resolves EXP-0002's single-seed inconclusiveness. ACC_WIDTH=24 wins on both mean Fmax (+6.2%, 180.71 vs 170.12 MHz) and seed-to-seed variance (~3.4x tighter), on top of its already-known resource advantage. DEC-0013 recommends ACC_WIDTH=24 as the new default. 3. Stall %/utilization (scheduling/memory axes): testbench-only cycle counters added to tb_neural_multiprocessor.v (no RTL touched) close DEC-0011's deferred measurement gap with real data - shared PSRAM port 81.7% utilized, slot 0 95.2%, slot 1 65.2%, no conclusive evidence of harmful fixed-priority starvation at this scale. The 10-milestone V2 roadmap (docs/v2-description.md §33) is now complete end-to-end: real Verilator simulation, real Yosys synthesis, real nextpnr-ecp5 place & route for every milestone, fully logged (EXP-0001..EXP-0013, DEC-0001..DEC-0013, ERR-0001..ERR-0008) with no invented results (§30) and V1 kept frozen and untouched throughout (§1/§34). Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
Claude Sonnet 5
@@ -166,3 +166,35 @@ Osservazioni (tutte da dati reali sopra, nessun numero inventato):
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- BRAM=0 per V2 riflette una scelta di scope esplicita (M3 non ancora
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collegato, DEC-0009), non un vantaggio architetturale reale -- un
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confronto onesto lo nota piuttosto che nasconderlo.
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[2026-09-05] M10 -- Optimization, closing M9's deferred gaps with real
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data (§32/DEC-0011 follow-up)
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Stall %/utilization (EXP-0013, real SIMULATED data, N_SLOTS=2, 3-node
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DAG scenario, replacing M9's "NOT MEASURED" placeholder for V2 -- V1's
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own equivalent instrumentation was not built this session, still NOT
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MEASURED for V1):
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| Metric | V2 (SIMULATED, real) |
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|------------------------------------|------------------------|
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| shared PSRAM port utilization | 81.7% (18.3% idle) |
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| slot 0 (memory_manager) utilization| 95.2% |
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| slot 1 (memory_manager) utilization| 65.2% |
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N_SLOTS sweep, extended to the real DSP ceiling (EXP-0008/EXP-0011):
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| N_SLOTS | Fmax (POST-P&R) | DSP used/total |
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|-----------|-------------------|------------------|
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| 2 | 165.15 MHz | 16/72 (22%) |
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| 4 | 133.19 MHz | 32/72 (44%) |
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| 8 | 92.63 MHz | 64/72 (89%) |
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All three PASS at 80MHz; N_SLOTS=8 recommended as the practical
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ceiling for P_IN=8 on this chip (DEC-0012).
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ACC_WIDTH 6-seed real placement sweep (EXP-0012, resolves EXP-0002's
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single-seed inconclusiveness):
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| ACC_WIDTH | mean Fmax | min | max | stdev |
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|-------------|-------------|-------|-------|---------|
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| 32 | 170.12 MHz | 145.73| 183.96| 14.16 |
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| 24 | 180.71 MHz | 175.16| 185.49| 4.21 |
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ACC_WIDTH=24 recommended as the new default (DEC-0013): higher mean
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Fmax, much tighter variance, fewer resources, same bit-exact
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correctness.
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@@ -649,3 +649,129 @@ than M9 scope creep.
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STATUS:
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ACCEPTED
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DEC-0012
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DATE: 2026-09-05
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DECISION:
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For the LFE5U-45F-8BG381 target at P_IN=8, N_SLOTS=8 is the
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recommended practical ceiling for dataflow_core's processor count (the
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"numero processor" axis of M10). Beyond N_SLOTS=8, DSP usage would
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exceed the chip's 72 total MULT18X18D (N_SLOTS=8 already uses 64/72 =
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88.9%; N_SLOTS=9 would need 72/72 = 100%, leaving zero margin for any
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other DSP use and very likely failing placement given routing
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congestion already visibly eating into Fmax margin well before that
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point).
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WHY:
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Real P&R data across the full N_SLOTS sweep now run (EXP-0003 at the
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neural_processor_array level for M2, EXP-0008/EXP-0011 at the
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dataflow_core level for M7/M10) shows TWO real, independent trends
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converging on the same conclusion: (1) DSP usage scales exactly
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linearly at 8 per slot (matches P_IN=8), hitting 88.9% at N_SLOTS=8 --
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consistent with DEC-0005's original finding that DSP, not LUT/FF, is
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the first resource to saturate; (2) Fmax falls monotonically and
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non-linearly as N_SLOTS grows (165.15 -> 133.19 -> 92.63 MHz for
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N_SLOTS=2/4/8), meaning routing congestion around the shared
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neural_director/dependency_manager hub is ALREADY compounding with DSP
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pressure well before the hard resource ceiling is reached. N_SLOTS=8
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is therefore not merely "the largest N_SLOTS that fits" but close to
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where BOTH constraints (DSP budget and real routing congestion)
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become simultaneously binding -- a genuinely data-driven ceiling, not
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an assumed one.
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EVIDENCE:
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timing.log/synthesis.log EXP-0008 (N_SLOTS=2: 165.15 MHz, 16/72 DSP;
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N_SLOTS=4: 133.19 MHz, 32/72 DSP) and EXP-0011 (N_SLOTS=8: 92.63 MHz,
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PASS at 80MHz but with a much thinner margin, 64/72 DSP) -- all real
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nextpnr-ecp5 place&route measurements via harness_dataflow_core.v.
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ALTERNATIVES:
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1. Recommend a smaller N_SLOTS (e.g. 4) for a larger Fmax safety
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margin. Rejected as a BLANKET recommendation: whether 133.19 MHz's
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larger margin over 133.19 vs 92.63 MHz's thinner one actually
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matters depends on the target application's own real timing needs,
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which M9's benchmark did not fix to a specific number beyond
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"PASS at 80MHz" -- both configurations real-measure as passing.
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N_SLOTS=8 remains the data-driven CEILING; choosing a smaller
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N_SLOTS for a specific deployment is a downstream product decision,
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not something this session can make on the target's behalf.
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2. Reduce P_IN below 8 to allow more slots within the same DSP budget
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(e.g. P_IN=4, N_SLOTS=16 -> still 64 DSP). Rejected as untested:
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no real data exists yet on Fmax/throughput for P_IN=4 slots at any
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N_SLOTS -- this is a real, open experiment for a FUTURE session,
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not something to recommend without having actually measured it
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(§30).
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RESULT:
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N_SLOTS=8 (P_IN=8) is the data-driven practical ceiling on the
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LFE5U-45F-8BG381 for dataflow_core/neural_multiprocessor. Smaller
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N_SLOTS values remain valid, real-measured configurations trading
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Fmax margin for less concurrency; a P_IN<8 exploration for even higher
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N_SLOTS is explicitly flagged as untested future work, not assumed.
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STATUS:
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ACCEPTED
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DEC-0013
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DATE: 2026-09-05
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DECISION:
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ACC_WIDTH=24 is the recommended default for neural_processor.v's
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accumulator width (the "pipeline" axis of M10), replacing EXP-0002's
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original single-seed, inconclusive finding.
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WHY:
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A 6-seed real placement sweep (EXP-0012: default seed plus 5 explicit
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--seed values, same two already-synthesized netlists, real
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nextpnr-ecp5 P&R only -- no re-synthesis needed) shows ACC_WIDTH=24
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has a HIGHER mean Fmax (180.71 vs 170.12 MHz, +6.2%) AND a much
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tighter seed-to-seed spread (stdev 4.21 vs 14.16 MHz) than
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ACC_WIDTH=32. EXP-0002's original single-seed result (176.21 <
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183.12 MHz, suggesting ACC=24 was WORSE) is now understood as
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placement-seed noise, not a real trend -- exactly the kind of mistake
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a single-seed measurement risks, which is why §30/§31 call for
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experimentally exploring configurations rather than trusting one
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placement run. Combined with EXP-0001/EXP-0002's already-known
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resource advantage (ACC_WIDTH=24: LUT=49/FF=509/CCU2C=88 vs
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ACC_WIDTH=32: LUT=55/FF=533/CCU2C=96 -- fewer of every resource) and
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both being bit-exact-correct against the same 7-test regression
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(EXP-0001/EXP-0002), ACC_WIDTH=24 dominates ACC_WIDTH=32 on every real
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axis measured for a plain INT8 perceptron whose products/partial sums
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never need more than 24 bits of headroom for P_IN=8 (8 x int8 x int8
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products, worst case magnitude fits well under 2^24).
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EVIDENCE:
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timing.log EXP-0012 (6-seed Fmax data for both configs, computed
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mean/min/max/stdev); synthesis.log EXP-0001/EXP-0002 (resource
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counts, already logged); simulation.log EXP-0001/EXP-0002 (both
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configs bit-exact-correct against V1, 7/7 PASS).
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ALTERNATIVES:
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1. Keep ACC_WIDTH=32 as the default (matches V1's own mac_unit.v
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accumulator width, "when in doubt, match the frozen baseline").
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Rejected: real multi-seed data now shows ACC_WIDTH=24 is strictly
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better on Fmax, resource usage, AND correctness for this specific
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P_IN=8 INT8 configuration -- there is no real axis left on which
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ACC_WIDTH=32 wins for THIS workload. V1 itself is a separate, frozen
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baseline (§1/§34) and is not required to match V2's own internal
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width choices.
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2. Run more than 6 seeds per config for a tighter confidence interval.
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Deferred, not rejected: 6 seeds already show a clear, consistent
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direction (ACC=24 wins on both mean and variance) -- diminishing
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returns for this decision's purposes; a future session could extend
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the sweep if ACC_WIDTH ever becomes a live bottleneck again.
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RESULT:
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ACC_WIDTH default changed to 24 going forward for any NEW V2 module
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instantiating neural_processor.v at P_IN=8 (no existing committed
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module needs to be edited retroactively purely for this -- M1-M9's own
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modules already default to ACC_WIDTH=32 via their own parameter
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defaults and remain correct either way, since both widths are
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bit-exact verified; this is a recommendation for future configuration
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choices, not a mandate to re-synthesize already-logged results).
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STATUS:
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ACCEPTED
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@@ -252,3 +252,35 @@ decision: vedi decisions.log DEC-0011 (stall %/utilization non
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rimandata a M10 dove diventa direttamente utile).
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next_action: M10 -- Optimization, sulla base dei dati reali raccolti
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in M1-M9.
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[2026-09-05] M10 -- Optimization (finale della roadmap V2, §33)
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reason: roadmap M10 -- ottimizzare SOLO sulla base dei dati reali
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raccolti in M1-M9, sugli assi: pipeline, P_IN, numero processor,
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buffer, FIFO, scheduling, prefetch, routing, memoria.
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result: tre azioni concrete, tutte basate su dati reali gia' raccolti
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o su nuove misure reali mirate a colmare lacune gia' documentate:
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(1) N_SLOTS=8 sintetizzato e P&R reale (92.63 MHz, PASS @80MHz,
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DSP 64/72=88.9%) -- conferma e completa il limite gia' previsto da
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DEC-0005, formalizzato come DEC-0012 (N_SLOTS=8 tetto pratico per
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P_IN=8 su questo chip). (2) Sweep reale a 6 seed di piazzamento per
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ACC_WIDTH 24 vs 32 (riusando i netlist gia' sintetizzati) -- risolve
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l'inconcludenza a singolo seed di EXP-0002: ACC_WIDTH=24 vince sia
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in Fmax medio (+6.2%) che in varianza (~3.4x piu' stretta),
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formalizzato come DEC-0013 (ACC_WIDTH=24 nuovo default
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raccomandato). (3) Strumentazione di conteggio cicli aggiunta al
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testbench M8 (nessun RTL toccato) -- chiude la lacuna di
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DEC-0011 con dati reali SIMULATED: porta PSRAM condivisa
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utilizzata all'81.7%, slot0 al 95.2%, slot1 al 65.2% (nessuna prova
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conclusiva di starvation dannosa su un test cosi' piccolo).
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errors: nessuno.
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decision: vedi decisions.log DEC-0012 e DEC-0013.
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next_action: nessuna prevista dal mandato (§33 termina a M10) -- la
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roadmap V2 a 10 milestone e' ora completa end-to-end, da M1 (singolo
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neural_processor) a M9 (benchmark completo V1 vs V2) a M10 (risultati
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di ottimizzazione basati sui dati). Elementi ancora aperti restano
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tutti esplicitamente rimandati dalle proprie DEC entry (non
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dimenticanze): riuso slot in dependency_manager (DEC-0008),
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fairness dell'arbitro sotto contesa piu' estesa (DEC-0010), sweep
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P_IN<8 per N_SLOTS ancora piu' alto (DEC-0012 alternativa #2), riuso
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dei buffer M3 come cache condivisa (DEC-0009), strumentazione
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stall%/utilization anche lato V1 (DEC-0011).
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@@ -463,3 +463,53 @@ next_action: M10 -- Optimization, using the REAL data gathered in M1-
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fairness question (DEC-0010) -- plus building the stall %/
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utilization instrumentation DEC-0011 deferred, since M10 is exactly
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where that data becomes actionable.
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[2026-09-05] EXP-0011/EXP-0012/EXP-0013 -- M10 Optimization, only on
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data already gathered (docs/v2-description.md M10: "Solo sulla base
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dei dati: pipeline; P_IN; numero processor; buffer; FIFO; scheduling;
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prefetch; routing; memoria.")
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test/result summary (full detail in synthesis.log/timing.log/
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simulation.log/benchmark.log under the same EXP numbers):
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EXP-0011 ("numero processor" axis): dataflow_core N_SLOTS=8 real
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synthesis+P&R (via harness_dataflow_core.v) -- 92.63 MHz POST-P&R,
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PASS at 80MHz, DSP 64/72 (88.9%). Extends M7's N_SLOTS=2/4 sweep
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to the real ceiling DEC-0005 predicted. See decisions.log DEC-0012
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(N_SLOTS=8 recommended practical ceiling for P_IN=8).
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EXP-0012 ("pipeline" axis): ACC_WIDTH 24-vs-32, 6 real placement
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seeds each (reusing already-synthesized netlists, nextpnr-ecp5
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P&R only) -- ACC_WIDTH=24 wins on both mean Fmax (+6.2%) and
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variance (~3.4x tighter), resolving EXP-0002's single-seed
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inconclusiveness. See decisions.log DEC-0013 (ACC_WIDTH=24
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recommended new default).
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EXP-0013 ("scheduling"/"memoria" axes): testbench-only cycle-
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accounting instrumentation added to tb_neural_multiprocessor.v (no
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RTL touched) -- closes decisions.log DEC-0011's deferred stall %/
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utilization gap with real SIMULATED numbers (shared PSRAM port
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81.7% utilized, slot 0 95.2%, slot 1 65.2%, N_SLOTS=2 3-node DAG).
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No conclusive evidence of harmful fixed-priority starvation in
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this small a test (slot 0's higher utilization is at least partly
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explained by serving 2 sequential jobs vs slot 1's 1) --
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decisions.log DEC-0010's arbiter fairness question remains
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correctly deferred pending a larger, longer-running workload.
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simulator: Verilator 5.050 (--binary --timing) for EXP-0013; Yosys +
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real nextpnr-ecp5 for EXP-0011/EXP-0012 (no new simulation needed,
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reused already-verified netlists/functional results).
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PASS/FAIL: EXP-0013 4/4 PASS (unchanged from EXP-0009, instrumentation
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is additive-only). EXP-0011/EXP-0012 are synthesis/P&R measurements,
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not functional tests -- 0 synthesis problems, all P&R runs PASS at
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80MHz.
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errors: none this milestone.
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decision: see decisions.log DEC-0012 (N_SLOTS=8 ceiling) and DEC-0013
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(ACC_WIDTH=24 new default).
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next_action: none mandated by docs/v2-description.md's own roadmap
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(§33 ends at M10) -- the 10-milestone V2 roadmap is now complete
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end-to-end, from M1's single neural_processor through M9's full
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V1-vs-V2 benchmark to M10's data-driven optimization findings.
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Remaining open items (all explicitly deferred by their own DEC
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entries, not oversights): dependency_manager node-slot reclamation
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(DEC-0008), slot_mem_arbiter fairness under sustained/larger
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contention (DEC-0010, now informed by EXP-0013's small-scale data),
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a P_IN<4 sweep at higher N_SLOTS (DEC-0012's alternative #2), M3
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buffer reuse as a shared cache once real bandwidth pressure is
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measured (DEC-0009), and V1-side stall%/utilization instrumentation
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to complete the M9 table's V1 column (DEC-0011).
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@@ -95,3 +95,26 @@ PASS/FAIL: 4/4 PASS after fixing a real dropped-request bug in the
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regression: hardware/v2/sim/tb_memory_manager.v (M4) re-run unchanged
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(no M4 file touched) -- still 3/3 PASS, identical cycle counts
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(446/166/728), confirming slot_mem_arbiter.v is purely additive.
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[2026-09-05] EXP-0013 -- hardware/v2/sim/tb_neural_multiprocessor.v,
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M10 cycle-accounting instrumentation (closes decisions.log DEC-0011's
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deferred stall %/utilization gap with real data, testbench-only
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addition, no RTL touched)
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test: same EXP-0009 scenario (3-node DAG, N_SLOTS=2, real V1 PSRAM
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chain, real slot_mem_arbiter contention), instrumented with cycle
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counters (shared PSRAM port busy cycles via
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u_nmp.u_arbiter.owner!=0, each slot's memory_manager busy cycles via
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its own state!=MM_IDLE), measured from the first node registration
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to test completion.
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simulator: Verilator 5.050 (--binary --timing)
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PASS/FAIL: 4/4 PASS (unchanged from EXP-0009), plus real measured
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data: 684 total cycles measured; shared PSRAM port busy 559/684
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(81.7% utilization, 18.3% idle); slot 0 (memory_manager) busy
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651/684 (95.2%); slot 1 (memory_manager) busy 446/684 (65.2%).
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note: slot 0's higher utilization is at least partly explained by it
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serving TWO sequential jobs in this run (node0, then whichever slot
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frees first serves node2 -- likely slot 0, first-free/lowest-index)
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while slot 1 only ever serves node1 -- NOT conclusive evidence of
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harmful priority starvation on its own; see decisions.log DEC-0010's
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original fairness deferral, now informed by this real (if small)
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data point.
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@@ -76,3 +76,14 @@ $_TBUF_=16 (tri-state buffers for the bidirectional psram_dq bus,
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from V1's own unmodified psram_controller.v)
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CHECK: 0 problems (same 32 benign "multiple conflicting drivers for
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...neural_processor.\gi" warnings documented since EXP-0001).
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[2026-09-05] EXP-0011 -- dataflow_core N_SLOTS=8 (M10, "numero
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processor" axis, via harness_dataflow_core.v, extending M7's own
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N_SLOTS=2/4 sweep to the real DSP ceiling predicted by DEC-0005)
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LUT4=6439 CCU2C=996 TRELLIS_FF=9053 MULT18X18D=64 (64/72=88.9% of
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the LFE5U-45F's total DSP budget -- matches DEC-0005's M2-era
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prediction almost exactly, since dataflow_core's per-slot DSP cost
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is just neural_processor's own P_IN=8 DSP cost x N_SLOTS)
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DP16KD=0 (expected, DEC-0009). CHECK: 0 problems (same benign
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"multiple conflicting drivers" warnings as every other neural_processor
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instantiation since EXP-0001).
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@@ -70,3 +70,34 @@ configs still clear the 80MHz target with real margin.
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standalone synthesis, no harness needed), real nextpnr-ecp5 --45k
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--package CABGA381 --speed 8 --freq 80 --lpf-allow-unconstrained
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Fmax: 142.45 MHz -- PASS at 80MHz (real place&route measurement)
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[2026-09-05] EXP-0011 -- dataflow_core N_SLOTS=8 (via
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harness_dataflow_core.v), real nextpnr-ecp5 --45k --package CABGA381
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--speed 8 --freq 80 --lpf-allow-unconstrained
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Fmax: 92.63 MHz -- PASS at 80MHz (real place&route measurement), but
|
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with a much thinner margin than N_SLOTS=2 (165.15 MHz) or N_SLOTS=4
|
||||
(133.19 MHz) -- Fmax falls monotonically with N_SLOTS (165.15 ->
|
||||
133.19 -> 92.63 MHz for N_SLOTS=2/4/8) as routing congestion around
|
||||
the shared neural_director/dependency_manager hub grows, while DSP
|
||||
usage (88.9% at N_SLOTS=8) approaches its hard ceiling at the same
|
||||
time -- see decisions.log DEC-0012.
|
||||
|
||||
[2026-09-05] EXP-0012 -- ACC_WIDTH 24 vs 32 real placement-seed sweep
|
||||
(M10, "pipeline" axis, resolving EXP-0002's single-seed
|
||||
inconclusiveness), 5 additional real nextpnr-ecp5 seeds (1-5) plus the
|
||||
original default-seed run (EXP-0001/EXP-0002), same synthesized
|
||||
netlists (hardware/v2/synthesis/neural_processor_p8/top.json and
|
||||
neural_processor_p8_acc24/top.json), --45k --package CABGA381 --speed
|
||||
8 --freq 80 --lpf-allow-unconstrained
|
||||
ACC_WIDTH=32: seeds [default,1,2,3,4,5] -> [183.12, 164.85, 174.25,
|
||||
168.83, 183.96, 145.73] MHz. n=6, mean=170.12 MHz, min=145.73 MHz,
|
||||
max=183.96 MHz, stdev=14.16 MHz.
|
||||
ACC_WIDTH=24: seeds [default,1,2,3,4,5] -> [176.21, 183.72, 180.57,
|
||||
183.08, 185.49, 175.16] MHz. n=6, mean=180.71 MHz, min=175.16 MHz,
|
||||
max=185.49 MHz, stdev=4.21 MHz.
|
||||
Conclusion: over 6 real placement seeds, ACC_WIDTH=24 has a HIGHER
|
||||
mean Fmax (+10.6 MHz, +6.2%) AND a much lower seed-to-seed variance
|
||||
(stdev 4.21 vs 14.16 MHz, ~3.4x tighter) than ACC_WIDTH=32 --
|
||||
EXP-0002's single-seed result (176.21 < 183.12, i.e. ACC=24 looked
|
||||
WORSE) was placement-seed noise, not a real trend. See decisions.log
|
||||
DEC-0013.
|
||||
|
||||
Reference in New Issue
Block a user