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fix: ERR-0026 SDRAM tMRD datasheet-unit mismatch at 64MHz

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Real Alliance Memory AS4C4M16SA-6TIN datasheet (Rev 5.0, Table 17)
specifies tMRD as a fixed 2-tCK cycle count, not an ns value.
sdram_controller.v modeled it via ns_to_cycles(12), which rounded to
2 cycles by coincidence at every previously-tested frequency
(100/133/166MHz) but rounds to only 1 cycle at the real 64MHz board
target -- an under-provisioned one-time init sequence. Fixed by
hardcoding T_MRD=2, matching how CAS_LATENCY is already modeled.

Verified zero regression: full 9-config legacy sweep + a new
dedicated 64MHz config (461/461 PASS each), N=2/N=4 D-Stress
(identical cycle counts), board-level smoke test (11/11 PASS).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-06 18:27:36 +02:00
co-authored by Claude Sonnet 5
parent d6376e8f2a
commit 8890b0abc2
3 changed files with 80 additions and 1 deletions
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hardware/v2/logs/decisions.log
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@@ -2140,3 +2140,24 @@ and the new host-arb arbitration layer) -- this was deliberately not
attempted before now, since running the real toolchain against RTL
known to compute wrong answers would not have been a meaningful
result. That reason no longer applies.
DEC-0038
DATE: 2026-09-06
DECISION:
The SDRAM datasheet-parameter audit (PRE-PCB VERIFICATION FREEZE,
section 8) is CLOSED. Every timing parameter in hardware/v2/nms/rtl/
sdram_controller.v was cross-checked against the real Alliance Memory
AS4C4M16SA-6TIN datasheet (Rev 5.0, Table 17) at the real 64MHz target
frequency, not merely re-cited from a previous, uncross-checked
baseline. This found and closed ERR-0026 (T_MRD unit mismatch -- see
errors.log), the only genuine discrepancy found. tRCD, tRP, tRAS,
tWR, tMRD, tREFI are all now confirmed correct at 64MHz with zero
regression to the existing bit-exact regression suite. See
hardware/v2/docs/PRE_PCB_VERIFICATION.md for the full parameter-by-
parameter table (DATASHEET PARAMETER -> REQUIRED VALUE -> RTL VALUE ->
STATUS).
This REVISES CHIP_READINESS.md/OPEN_ITEMS.md's own prior "SDRAM
datasheet-parameter cross-check: OPEN (sim-level only)" status to
CLOSED.