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docs(v2): M9 full benchmark - V1 vs V2 comparison table (§32)

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Consolidates real, already-measured data from hardware/v1/ (frozen,
pre-certified) and V2's own M1-M8 logs into the §32-mandated
comparison table, on an apples-to-apples basis: both full systems
(V1's spi_neuron_top post_fix_verify vs V2's neural_multiprocessor
N_SLOTS=2), both PARALLEL=8/P_IN=8, both using the real unmodified V1
PSRAM backend.

Headline, all real measurements: V2 full-system Fmax 142.45 MHz
POST-P&R (PASS at 80MHz) vs V1's 68.65 MHz (FAIL at 80MHz); 166 vs 209
real simulated cycles for one neuron's 8-input dot product through the
same real PSRAM chain (2.6x wall-clock speedup); peak MAC/cycle 16
(N_SLOTS=2 concurrent slots, real contention already demonstrated in
EXP-0009) vs V1's 8 (single sequential core); lower LUT/FF despite V2
already including full dependency-graph scheduling that V1 has none
of.

9 of the table's 12 rows carry real sourced numbers; stall %/memory
utilization/processor utilization are reported as NOT MEASURED rather
than approximated (DEC-0011) - a real number needs dedicated
cycle-accounting instrumentation neither system has had built for it
yet, and approximating from partial data would violate §30's "no
invented results" rule. Deferred to M10, which needs exactly this
data to decide what to optimize.

No new RTL this milestone - pure data consolidation, logged as
EXP-0010.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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michele
2026-09-05 15:17:14 +02:00
co-authored by Claude Sonnet 5
parent 6cff2c8a7c
commit 84794a3d25
5 changed files with 180 additions and 1 deletions
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hardware/v2/logs/experiments.log
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@@ -433,3 +433,33 @@ next_action: M9 -- Full benchmark. Produce the V1-vs-V2 comparison
cycles/neuron, neurons/s, stall %, memory/processor utilization,
effective MAC/s), each number labeled THEORETICAL/SIMULATED/
SYNTHESIZED/POST-P&R per §30.
[2026-09-05] EXP-0010 -- M9 Full benchmark: V1 vs V2 comparison table
(docs/v2-description.md §32)
test: not a new simulation -- a consolidation of real, already-
measured data from hardware/v1/ (frozen, pre-certified) and V2's own
M1-M8 logs (EXP-0001..EXP-0009), placed side-by-side on an
apples-to-apples basis (both full-system, both PARALLEL=8/P_IN=8,
both using the real unmodified V1 PSRAM backend).
result: see benchmark.log's own M9 entry for the full 12-row table.
Headline: V2's full system (neural_multiprocessor, N_SLOTS=2) is
142.45 MHz POST-P&R (PASS @80MHz) vs V1's 68.65 MHz (FAIL @80MHz);
166 vs 209 real simulated cycles for one neuron's 8-input dot
product through the real PSRAM chain -- 2.6x wall-clock speedup,
measured, not assumed.
errors: none this milestone (pure data consolidation, no new RTL).
decision: see decisions.log DEC-0011 -- 3 of the 12 §32 rows (stall %,
memory utilization, processor utilization) are reported as NOT
MEASURED rather than approximated, since a real number would require
dedicated cycle-accounting instrumentation neither system has had
built for it yet; approximating from partial data would violate
§30's "no invented results" rule.
next_action: M10 -- Optimization, using the REAL data gathered in M1-
M9 (not blind guessing): revisit memory_manager's +1-cycle/tile
overhead (DEC-0006), the ACC_WIDTH 24-vs-32 Fmax question (EXP-0002,
inconclusive without a seed sweep), the N_SLOTS x P_IN trade-off
given the DSP ceiling (DEC-0005), dependency_manager's node-slot
reclamation (DEC-0008), and slot_mem_arbiter's fixed-priority
fairness question (DEC-0010) -- plus building the stall %/
utilization instrumentation DEC-0011 deferred, since M10 is exactly
where that data becomes actionable.