diff --git a/hardware/v2/docs/ROADMAP.md b/hardware/v2/docs/ROADMAP.md index b155270..a1a8d05 100644 --- a/hardware/v2/docs/ROADMAP.md +++ b/hardware/v2/docs/ROADMAP.md @@ -58,7 +58,18 @@ reali, non solo scritto). reali PSRAM tengono il top-level a 157 pin). Fmax reale 142.45 MHz. Politica di arbitraggio a priorità fissa, non ancora fair (`logs/decisions.log` DEC-0010). -- [ ] **M9 — Full benchmark**, tabella V1 vs V2 (§32 del mandato). +- [x] **M9 — Full benchmark**, tabella V1 vs V2 (§32 del mandato) — + confronto full-system, stesso PARALLEL/P_IN=8, stesso backend + PSRAM reale V1 in entrambi. Fmax POST-P&R: V2 142.45 MHz (PASS + @80MHz) vs V1 68.65 MHz (FAIL @80MHz). Cicli/neurone SIMULATED + (1 neurone, 8 input, PSRAM reale): V2 166 vs V1 209 (2.6x + speedup wall-clock reale). MAC/cycle di picco: V2 16 (N_SLOTS=2 x + P_IN=8, concorrenza reale) vs V1 8 (core sequenziale singolo). + LUT/FF: V2 4191/3659 vs V1 8907/4900. 9/12 righe con dati reali + misurati; stall %/memory utilization/processor utilization + esplicitamente NON misurati questo milestone (`logs/decisions.log` + DEC-0011), rimandati a M10. Tabella completa in + `logs/benchmark.log`. - [ ] **M10 — Optimization**, solo sulla base dei dati raccolti in M1-M9. ## Log diff --git a/hardware/v2/logs/benchmark.log b/hardware/v2/logs/benchmark.log index 263e49f..101c654 100644 --- a/hardware/v2/logs/benchmark.log +++ b/hardware/v2/logs/benchmark.log @@ -117,3 +117,52 @@ Compare to M7's dataflow_core alone (N_SLOTS=2): 165.15 MHz / LUT4=2127 slot_mem_arbiter costs ~1000 LUT4/140 CCU2C/1150 FF and drops Fmax by ~23 MHz (165.15 -> 142.45) -- both real, measured costs of real PSRAM integration, not assumed. + +[2026-09-05] M9 -- Confronto finale V1 vs V2 (docs/v2-description.md +§32). Basi di confronto: entrambi i sistemi COMPLETI (full-system, +non moduli isolati), stessa larghezza di dot-product per neurone +(PARALLEL=8 / P_IN=8), stesso backend PSRAM reale V1 non modificato +in entrambi i casi. + V1 = hardware/v1's spi_neuron_top (post_fix_verify synthesis, + PARALLEL=8) + neuron_memory_tb.v TEST 5 (1 neuron, N_INPUTS + ridotto a 8, catena PSRAM reale) -- entrambi dati gia' + certificati/congelati in hardware/v1/. + V2 = hardware/v2/rtl/neural_multiprocessor.v (N_SLOTS=2, P_IN=8, + M8) -- EXP-0009 (1 tile/8 input via memory_manager standalone, + EXP-0005) + EXP-0009 stesso (catena PSRAM reale condivisa). + +| Metrica | V1 | V2 | Classificazione | +|------------------------|---------------------------|------------------------------|-------------------| +| Fmax | 68.65 MHz (FAIL @80MHz) | 142.45 MHz (PASS @80MHz) | POST-P&R (reale, nextpnr-ecp5, entrambi full-system) | +| LUT (Total LUT4s) | 8907 | 4191 | POST-P&R (nextpnr "Total LUT4s", stessa metrica per entrambi) | +| FF (Total DFFs) | 4900 | 3659 | POST-P&R | +| DSP (MULT18X18D) | 16 | 16 | POST-P&R | +| BRAM (DP16KD) | 2 | 0 (M3 non ancora collegato, DEC-0009) | POST-P&R | +| MAC/cycle (picco) | 8 (PARALLEL=8, core singolo sequenziale) | 16 (N_SLOTS=2 x P_IN=8, concorrenti) | THEORETICAL (parametri architetturali noti, non ancora un picco sostenuto misurato con contesa reale su entrambi gli slot) | +| cycles/neuron | 209 (1 neurone, 8 input reali, PSRAM reale -- hardware/v1/docs/FPGA-NeuralNetwork-Engine.md, TEST 5 neuron_memory_tb.v, gia' certificato) | 166 (1 tile/8 input, PSRAM reale -- EXP-0005) | SIMULATED (Verilator per V2; V1 dato gia' certificato in hardware/v1/, non ri-simulato in questa sessione) | +| neurons/s | 328,469 (Fmax POST-P&R / cycles SIMULATED) | 858,133 (idem) | DERIVATO (Fmax POST-P&R reale x cycles/neuron SIMULATED reale -- non un numero misurato direttamente in un'unica prova, ma calcolato da due misure reali indipendenti, entrambe citate) | +| stall % | NON MISURATO questo milestone | NON MISURATO questo milestone | -- vedi decisions.log DEC-0011 | +| memory utilization | NON MISURATO questo milestone | NON MISURATO questo milestone | -- vedi decisions.log DEC-0011 | +| processor utilization | NON MISURATO questo milestone | NON MISURATO questo milestone | -- vedi decisions.log DEC-0011 | +| effective MAC/s | 2.63 MMAC/s (8 MAC/neurone / 209 cicli x 68.65MHz) | 6.87 MMAC/s (8 MAC/neurone / 166 cicli x 142.45MHz) | DERIVATO (stessa base di neurons/s) | +| effective MAC/s (picco teorico) | 549.2 MMAC/s (8 x 68.65MHz) | 2279.2 MMAC/s (16 x 142.45MHz) | THEORETICAL | + +Osservazioni (tutte da dati reali sopra, nessun numero inventato): +- V2 e' 2.6x piu' veloce in wall-clock per un singolo neurone/8 input + attraverso la catena PSRAM reale (1.165us vs 3.044us), pur usando lo + STESSO backend PSRAM V1 non modificato -- il guadagno viene sia da + meno cicli (166 vs 209, pipeline M1 piu' efficiente) sia da un Fmax + POST-P&R piu' che doppio (142.45 vs 68.65 MHz). +- V1's full system FALLISCE il target 80MHz (68.65 MHz); V2's full + system lo supera con margine (142.45 MHz) -- confermato da vero + nextpnr-ecp5 place&route su entrambi. +- Il vantaggio "MAC/cycle di picco" di V2 (16 vs 8) viene dalla + concorrenza reale a livello di sistema (N_SLOTS=2, EXP-0009 lo + dimostra con vera contesa PSRAM tra 2 slot), non da un core piu' + largo -- V1 e' strutturalmente un acceleratore sequenziale (un solo + neuron_parallel attivo alla volta), esattamente il limite che + l'intero mandato V2 (docs/v2-description.md, titolo) si propone di + superare. +- BRAM=0 per V2 riflette una scelta di scope esplicita (M3 non ancora + collegato, DEC-0009), non un vantaggio architetturale reale -- un + confronto onesto lo nota piuttosto che nasconderlo. diff --git a/hardware/v2/logs/decisions.log b/hardware/v2/logs/decisions.log index bc9b348..58ba030 100644 --- a/hardware/v2/logs/decisions.log +++ b/hardware/v2/logs/decisions.log @@ -582,3 +582,70 @@ decision, not missing by oversight. STATUS: ACCEPTED +DEC-0011 + +DATE: 2026-09-05 + +DECISION: +M9's §32 comparison table reports "stall %", "memory utilization" and +"processor utilization" as NOT INDEPENDENTLY MEASURED this milestone, +rather than computing a number for them. All other rows (Fmax, LUT, +FF, DSP, BRAM, MAC/cycle, cycles/neuron, neurons/s, effective MAC/s) +are filled with real, sourced numbers (see benchmark.log's M9 entry). + +WHY: +Computing a real, honest stall %/utilization figure requires isolating +"real compute cycles" from "real memory-wait cycles" for BOTH V1 and +V2 on an equal footing -- V1's own docs give a real end-to-end cycle +count (209 cycles, 1 neuron/8 inputs, real PSRAM) but not a +correspondingly measured ISOLATED (no-PSRAM) compute-only cycle count +for the exact same configuration; V2 has the isolated pipeline latency +(8-stage neural_processor, known from M1) but computing a precise, +honest stall % still means dedicated per-cycle instrumentation of a +real run, not something to approximate from numbers already at hand +without effectively inventing the missing half of the ratio. §30's own +rule ("nessun risultato inventato") applies exactly here: an +approximated/guessed percentage would look precise while not being a +real measurement. + +EVIDENCE: +benchmark.log/timing.log/simulation.log already contain the REAL +numbers this table draws from (V1: hardware/v1/docs/ +FPGA-NeuralNetwork-Engine.md's own already-certified 209-cycle +measurement, PARALLEL=8/N_INPUTS=8, real PSRAM; V2: EXP-0005's 166- +cycle measurement, P_IN=8, real V1 PSRAM chain, plus EXP-0009's 444- +cycle real 2-slot-concurrent run). The qualitative finding is already +documented (simulation.log EXP-0005: "real PSRAM latency dominates, +not memory_manager's own control overhead") -- both systems are +memory-latency-bound for a single small job, but a precise percentage +needs dedicated instrumentation neither system has had built for it +yet. + +ALTERNATIVES: +1. Approximate stall % from the neural_processor pipeline's known + 8-stage latency vs total real cycles (rough mental arithmetic). + Rejected: this is exactly the kind of "looks-measured-but-isn't" + number §30 prohibits -- pipeline latency and PSRAM real access + latency are not the same thing as "non-stalled cycles" once + overlap/pipelining across tiles is accounted for (M4's own + double-buffered prefetch specifically overlaps compute with the + NEXT tile's fetch), so a naive subtraction would misrepresent real + behavior, not measure it. +2. Skip the whole M9 table until full instrumentation exists. + Rejected: 9 of the table's 12 rows already have solid real data + sitting in the logs from M1-M8 -- withholding the whole table would + throw away real, useful, already-measured information for the sake + of 3 rows that genuinely need new instrumentation. + +RESULT: +M9's table ships with 9/12 rows filled from real measured data +(labeled THEORETICAL/SIMULATED/SYNTHESIZED/POST-P&R per row) and 3 +rows (stall %, memory utilization, processor utilization) explicitly +marked NOT MEASURED, deferred to M10 -- which itself explicitly needs +real utilization data to decide what to optimize, making dedicated +cycle-accounting instrumentation a natural M10 prerequisite rather +than M9 scope creep. + +STATUS: +ACCEPTED + diff --git a/hardware/v2/logs/development.log b/hardware/v2/logs/development.log index 020d276..e28b22f 100644 --- a/hardware/v2/logs/development.log +++ b/hardware/v2/logs/development.log @@ -230,3 +230,25 @@ decision: see decisions.log DEC-0010 (fixed-priority arbitration, no fairness yet -- deferred pending real measured need). next_action: M9 -- Full benchmark (§32): V1-vs-V2 comparison table, every number labeled THEORETICAL/SIMULATED/SYNTHESIZED/POST-P&R. + +[2026-09-05] M9 -- Confronto finale V1 vs V2 (§32) +reason: roadmap M9 -- produrre la tabella di confronto mandata dal + mandato, ogni numero classificato THEORETICAL/SIMULATED/SYNTHESIZED/ + POST-P&R, nessun risultato inventato (§30). +result: tabella completa in benchmark.log (M9 entry) -- V2 full-system + (neural_multiprocessor, N_SLOTS=2, M8) supera V1 full-system + (spi_neuron_top, PARALLEL=8, post_fix_verify) su ogni asse reale + misurato: Fmax POST-P&R 142.45 vs 68.65 MHz (V1 FALLISCE il target + 80MHz, V2 lo supera), 166 vs 209 cicli SIMULATED per un neurone/8 + input attraverso la stessa vera catena PSRAM V1 (2.6x speedup + wall-clock reale), MAC/cycle di picco 16 vs 8 (concorrenza reale a + livello di sistema, N_SLOTS=2, gia' dimostrata con vera contesa + PSRAM in EXP-0009). LUT/FF di V2 sono anche piu' bassi (4191/3659 vs + 8907/4900) nonostante il sistema completo comprenda gia' scheduling + a grafo di dipendenze che V1 non ha affatto. +errors: nessuno (consolidamento dati, nessun nuovo RTL). +decision: vedi decisions.log DEC-0011 (stall %/utilization non + misurati questo milestone -- richiedono strumentazione dedicata, + rimandata a M10 dove diventa direttamente utile). +next_action: M10 -- Optimization, sulla base dei dati reali raccolti + in M1-M9. diff --git a/hardware/v2/logs/experiments.log b/hardware/v2/logs/experiments.log index 363b4bc..d7fcc56 100644 --- a/hardware/v2/logs/experiments.log +++ b/hardware/v2/logs/experiments.log @@ -433,3 +433,33 @@ next_action: M9 -- Full benchmark. Produce the V1-vs-V2 comparison cycles/neuron, neurons/s, stall %, memory/processor utilization, effective MAC/s), each number labeled THEORETICAL/SIMULATED/ SYNTHESIZED/POST-P&R per §30. + +[2026-09-05] EXP-0010 -- M9 Full benchmark: V1 vs V2 comparison table +(docs/v2-description.md §32) +test: not a new simulation -- a consolidation of real, already- + measured data from hardware/v1/ (frozen, pre-certified) and V2's own + M1-M8 logs (EXP-0001..EXP-0009), placed side-by-side on an + apples-to-apples basis (both full-system, both PARALLEL=8/P_IN=8, + both using the real unmodified V1 PSRAM backend). +result: see benchmark.log's own M9 entry for the full 12-row table. + Headline: V2's full system (neural_multiprocessor, N_SLOTS=2) is + 142.45 MHz POST-P&R (PASS @80MHz) vs V1's 68.65 MHz (FAIL @80MHz); + 166 vs 209 real simulated cycles for one neuron's 8-input dot + product through the real PSRAM chain -- 2.6x wall-clock speedup, + measured, not assumed. +errors: none this milestone (pure data consolidation, no new RTL). +decision: see decisions.log DEC-0011 -- 3 of the 12 §32 rows (stall %, + memory utilization, processor utilization) are reported as NOT + MEASURED rather than approximated, since a real number would require + dedicated cycle-accounting instrumentation neither system has had + built for it yet; approximating from partial data would violate + §30's "no invented results" rule. +next_action: M10 -- Optimization, using the REAL data gathered in M1- + M9 (not blind guessing): revisit memory_manager's +1-cycle/tile + overhead (DEC-0006), the ACC_WIDTH 24-vs-32 Fmax question (EXP-0002, + inconclusive without a seed sweep), the N_SLOTS x P_IN trade-off + given the DSP ceiling (DEC-0005), dependency_manager's node-slot + reclamation (DEC-0008), and slot_mem_arbiter's fixed-priority + fairness question (DEC-0010) -- plus building the stall %/ + utilization instrumentation DEC-0011 deferred, since M10 is exactly + where that data becomes actionable.