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docs(v2): M9 full benchmark - V1 vs V2 comparison table (§32)

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Consolidates real, already-measured data from hardware/v1/ (frozen,
pre-certified) and V2's own M1-M8 logs into the §32-mandated
comparison table, on an apples-to-apples basis: both full systems
(V1's spi_neuron_top post_fix_verify vs V2's neural_multiprocessor
N_SLOTS=2), both PARALLEL=8/P_IN=8, both using the real unmodified V1
PSRAM backend.

Headline, all real measurements: V2 full-system Fmax 142.45 MHz
POST-P&R (PASS at 80MHz) vs V1's 68.65 MHz (FAIL at 80MHz); 166 vs 209
real simulated cycles for one neuron's 8-input dot product through the
same real PSRAM chain (2.6x wall-clock speedup); peak MAC/cycle 16
(N_SLOTS=2 concurrent slots, real contention already demonstrated in
EXP-0009) vs V1's 8 (single sequential core); lower LUT/FF despite V2
already including full dependency-graph scheduling that V1 has none
of.

9 of the table's 12 rows carry real sourced numbers; stall %/memory
utilization/processor utilization are reported as NOT MEASURED rather
than approximated (DEC-0011) - a real number needs dedicated
cycle-accounting instrumentation neither system has had built for it
yet, and approximating from partial data would violate §30's "no
invented results" rule. Deferred to M10, which needs exactly this
data to decide what to optimize.

No new RTL this milestone - pure data consolidation, logged as
EXP-0010.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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michele
2026-09-05 15:17:14 +02:00
co-authored by Claude Sonnet 5
parent 6cff2c8a7c
commit 84794a3d25
5 changed files with 180 additions and 1 deletions
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@@ -230,3 +230,25 @@ decision: see decisions.log DEC-0010 (fixed-priority arbitration, no
fairness yet -- deferred pending real measured need).
next_action: M9 -- Full benchmark (§32): V1-vs-V2 comparison table,
every number labeled THEORETICAL/SIMULATED/SYNTHESIZED/POST-P&R.
[2026-09-05] M9 -- Confronto finale V1 vs V2 (§32)
reason: roadmap M9 -- produrre la tabella di confronto mandata dal
mandato, ogni numero classificato THEORETICAL/SIMULATED/SYNTHESIZED/
POST-P&R, nessun risultato inventato (§30).
result: tabella completa in benchmark.log (M9 entry) -- V2 full-system
(neural_multiprocessor, N_SLOTS=2, M8) supera V1 full-system
(spi_neuron_top, PARALLEL=8, post_fix_verify) su ogni asse reale
misurato: Fmax POST-P&R 142.45 vs 68.65 MHz (V1 FALLISCE il target
80MHz, V2 lo supera), 166 vs 209 cicli SIMULATED per un neurone/8
input attraverso la stessa vera catena PSRAM V1 (2.6x speedup
wall-clock reale), MAC/cycle di picco 16 vs 8 (concorrenza reale a
livello di sistema, N_SLOTS=2, gia' dimostrata con vera contesa
PSRAM in EXP-0009). LUT/FF di V2 sono anche piu' bassi (4191/3659 vs
8907/4900) nonostante il sistema completo comprenda gia' scheduling
a grafo di dipendenze che V1 non ha affatto.
errors: nessuno (consolidamento dati, nessun nuovo RTL).
decision: vedi decisions.log DEC-0011 (stall %/utilization non
misurati questo milestone -- richiedono strumentazione dedicata,
rimandata a M10 dove diventa direttamente utile).
next_action: M10 -- Optimization, sulla base dei dati reali raccolti
in M1-M9.