docs(v2): M9 full benchmark - V1 vs V2 comparison table (§32)

Consolidates real, already-measured data from hardware/v1/ (frozen,
pre-certified) and V2's own M1-M8 logs into the §32-mandated
comparison table, on an apples-to-apples basis: both full systems
(V1's spi_neuron_top post_fix_verify vs V2's neural_multiprocessor
N_SLOTS=2), both PARALLEL=8/P_IN=8, both using the real unmodified V1
PSRAM backend.

Headline, all real measurements: V2 full-system Fmax 142.45 MHz
POST-P&R (PASS at 80MHz) vs V1's 68.65 MHz (FAIL at 80MHz); 166 vs 209
real simulated cycles for one neuron's 8-input dot product through the
same real PSRAM chain (2.6x wall-clock speedup); peak MAC/cycle 16
(N_SLOTS=2 concurrent slots, real contention already demonstrated in
EXP-0009) vs V1's 8 (single sequential core); lower LUT/FF despite V2
already including full dependency-graph scheduling that V1 has none
of.

9 of the table's 12 rows carry real sourced numbers; stall %/memory
utilization/processor utilization are reported as NOT MEASURED rather
than approximated (DEC-0011) - a real number needs dedicated
cycle-accounting instrumentation neither system has had built for it
yet, and approximating from partial data would violate §30's "no
invented results" rule. Deferred to M10, which needs exactly this
data to decide what to optimize.

No new RTL this milestone - pure data consolidation, logged as
EXP-0010.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/docs/ROADMAP.md

@@ -58,7 +58,18 @@ reali, non solo scritto).
       reali PSRAM tengono il top-level a 157 pin). Fmax reale 142.45
       MHz. Politica di arbitraggio a priorità fissa, non ancora fair
       (`logs/decisions.log` DEC-0010).
-- [ ] **M9 — Full benchmark**, tabella V1 vs V2 (§32 del mandato).
+- [x] **M9 — Full benchmark**, tabella V1 vs V2 (§32 del mandato) —
+      confronto full-system, stesso PARALLEL/P_IN=8, stesso backend
+      PSRAM reale V1 in entrambi. Fmax POST-P&R: V2 142.45 MHz (PASS
+      @80MHz) vs V1 68.65 MHz (FAIL @80MHz). Cicli/neurone SIMULATED
+      (1 neurone, 8 input, PSRAM reale): V2 166 vs V1 209 (2.6x
+      speedup wall-clock reale). MAC/cycle di picco: V2 16 (N_SLOTS=2 x
+      P_IN=8, concorrenza reale) vs V1 8 (core sequenziale singolo).
+      LUT/FF: V2 4191/3659 vs V1 8907/4900. 9/12 righe con dati reali
+      misurati; stall %/memory utilization/processor utilization
+      esplicitamente NON misurati questo milestone (`logs/decisions.log`
+      DEC-0011), rimandati a M10. Tabella completa in
+      `logs/benchmark.log`.
 - [ ] **M10 — Optimization**, solo sulla base dei dati raccolti in M1-M9.
 
 ## Log