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chore: remove root-level V1 duplicates, superseded by hardware/v1/ freeze

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hardware/v1/ was created (dc0b331) as a frozen snapshot of the V1
project that then lived at the repo root (rtl/, sim/, synth/, tools/,
docs/). Root received zero further commits to those files after the
freeze -- confirmed byte-identical to the hardware/v1/ copy for every
file removed here. Root was the "before", hardware/v1/ is the
curated, canonical "after".

Removed (all verified exact-hash duplicates of hardware/v1/ content):
  - rtl/ (20 files, 100% covered by hardware/v1/rtl/)
  - tools/{netasm,pinout,run_regression.py,flash_catalog,validation,
    fpga_benchmark.py} (19 files, 100% covered by hardware/v1/tools/;
    tools/neural_sim/ kept -- unique, post-freeze, no counterpart)
  - sim/*.v (47 testbenches, 100% covered by hardware/v1/sim/; the
    ~38 remaining sim/ entries are compiled binaries and .vcd
    waveform dumps, left as a separate cleanup decision)
  - synth/ecp5/{p2,p4,p8,post_fix_verify} (25 files, exact duplicates
    of hardware/v1/synthesis/; the other ~84 synth/ecp5/* experiment
    build directories are historical artifacts never carried into the
    freeze, left as a separate decision)
  - WORKLOG.md (duplicate of hardware/v1/docs/WORKLOG.md)
  - docs/{FPGA-Neural-Datapatch-Benchmark,FPGA-Neural-Hardware-Design,
    FPGA-NeuralNetwork-Engine}.md, docs/validation/*.md (18 files),
    docs/FPGA-Neural-Datasheet-{EN,IT}.pdf -- all exact duplicates of
    hardware/v1/docs/ content
  - hardware/v1/docs/DatasheetLatex/ (24 files) -- exact duplicate of
    hardware/v2/docs/datasheet/files/docs/datasheet/en/ (discovered
    during this audit; not the same DatasheetLatex already removed
    from hardware/v2/docs/ in an earlier commit)

Moved (genuine, unique, post-freeze V2 content -- not duplicated
anywhere, just living in the wrong/legacy root docs/ location):
  - docs/architecture/*.md -> hardware/v2/docs/architecture/
  - docs/pinouts.md, docs/FPGA_NEURAL_V2_DATASHEET.md,
    docs/FPGA_NEURAL_V2_SCHEMATIC.md,
    docs/FPGA-Neural-V2-Datasheet-EN.pdf -> hardware/v2/docs/

Left untouched (separate decisions, not part of this cleanup):
  - docs/FPGA-Neural-Flash-Subsystem-Verification.md, docs/
    v2-description.md -- orphaned root-only content, no duplicate
    found anywhere, but also not part of the reviewed plan
  - synth/ecp5/* experiment dirs and sim/*_sim + sim/*.vcd build
    artifacts -- not literal duplicates, flagged as candidates for a
    future, separate cleanup pass

Verified no functional breakage: grepped all remaining scripts/docs
for references to every removed path -- only prose/comment mentions
found, no executable imports or build-script paths broken.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-07 05:30:17 +02:00
co-authored by Claude Sonnet 5
parent e1cefd13db
commit 81a9619214
184 changed files with 0 additions and 1023781 deletions
Download Patch File Download Diff File Expand all files Collapse all files
synth/ecp5/p2/report.txt
-388
View File
@@ -1,388 +0,0 @@
Warning: IO 'y_bus[31]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[30]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[29]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[28]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[27]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[26]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[25]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[24]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[23]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[22]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[21]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[20]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[19]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[18]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[17]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[16]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[15]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[14]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[13]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[12]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[11]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[10]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[9]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[8]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[7]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[6]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[5]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[4]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[3]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[2]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[1]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[0]' is unconstrained in LPF and will be automatically placed
Warning: IO 'start' is unconstrained in LPF and will be automatically placed
Warning: IO 'rst' is unconstrained in LPF and will be automatically placed
Warning: IO 'done' is unconstrained in LPF and will be automatically placed
Warning: IO 'clk' is unconstrained in LPF and will be automatically placed
Warning: IO 'busy' is unconstrained in LPF and will be automatically placed
Info: Logic utilisation before packing:
Info: Total LUT4s: 481/43848 1%
Info: logic LUTs: 95/43848 0%
Info: carry LUTs: 386/43848 0%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 198/43848 0%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 191 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x83be9e7c
Info: Device utilisation:
Info: TRELLIS_IO: 37/ 245 15%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 8/ 72 11%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 198/ 43848 0%
Info: TRELLIS_COMB: 551/ 43848 1%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 129 cells, random placement wirelen = 25757.
Info: at initial placer iter 0, wirelen = 3145
Info: at initial placer iter 1, wirelen = 2698
Info: at initial placer iter 2, wirelen = 2587
Info: at initial placer iter 3, wirelen = 2563
Info: Running main analytical placer, max placement attempts per cell = 79003.
Info: at iteration #1, type ALL: wirelen solved = 2537, spread = 4133, legal = 5191; time = 0.01s
Info: at iteration #2, type ALL: wirelen solved = 2554, spread = 3904, legal = 4675; time = 0.00s
Info: at iteration #3, type ALL: wirelen solved = 2545, spread = 3704, legal = 4373; time = 0.00s
Info: at iteration #4, type ALL: wirelen solved = 2549, spread = 3862, legal = 4324; time = 0.00s
Info: at iteration #5, type ALL: wirelen solved = 2590, spread = 3707, legal = 4361; time = 0.00s
Info: at iteration #6, type ALL: wirelen solved = 2544, spread = 3885, legal = 4543; time = 0.00s
Info: at iteration #7, type ALL: wirelen solved = 2578, spread = 3986, legal = 4545; time = 0.00s
Info: at iteration #8, type ALL: wirelen solved = 2595, spread = 3719, legal = 4059; time = 0.00s
Info: at iteration #9, type ALL: wirelen solved = 2683, spread = 4065, legal = 4376; time = 0.00s
Info: at iteration #10, type ALL: wirelen solved = 2650, spread = 3696, legal = 3917; time = 0.00s
Info: at iteration #11, type ALL: wirelen solved = 2605, spread = 3682, legal = 4248; time = 0.00s
Info: at iteration #12, type ALL: wirelen solved = 2652, spread = 3920, legal = 4328; time = 0.00s
Info: at iteration #13, type ALL: wirelen solved = 2686, spread = 3988, legal = 4511; time = 0.00s
Info: at iteration #14, type ALL: wirelen solved = 2675, spread = 3787, legal = 4235; time = 0.00s
Info: at iteration #15, type ALL: wirelen solved = 2706, spread = 3567, legal = 4256; time = 0.00s
Info: HeAP Placer Time: 0.09s
Info: of which solving equations: 0.05s
Info: of which spreading cells: 0.01s
Info: of which strict legalisation: 0.01s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 124, wirelen = 3917
Info: at iteration #5: temp = 0.000000, timing cost = 93, wirelen = 2856
Info: at iteration #10: temp = 0.000000, timing cost = 103, wirelen = 2805
Info: at iteration #13: temp = 0.000000, timing cost = 103, wirelen = 2799
Info: SA placement time 0.16s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 98.23 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.59 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.53 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 2320, 2801) |****+
Info: [ 2801, 3282) |****+
Info: [ 3282, 3763) |
Info: [ 3763, 4244) |
Info: [ 4244, 4725) |
Info: [ 4725, 5206) |*******+
Info: [ 5206, 5687) |*********************+
Info: [ 5687, 6168) |*********+
Info: [ 6168, 6649) |***
Info: [ 6649, 7130) |*+
Info: [ 7130, 7611) |
Info: [ 7611, 8092) |****+
Info: [ 8092, 8573) |*****************+
Info: [ 8573, 9054) |********************+
Info: [ 9054, 9535) |****************************************+
Info: [ 9535, 10016) |************************************+
Info: [ 10016, 10497) |************************************************************
Info: [ 10497, 10978) |*********************************************************+
Info: [ 10978, 11459) |**********************************+
Info: [ 11459, 11940) |***+
Info: Checksum: 0x9ce6835b
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 1805 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 401 520 | 401 520 | 1232| 0.13 0.13|
Info: 2000 | 429 1378 | 28 858 | 263| 0.05 0.18|
Info: 2263 | 430 1606 | 1 228 | 0| 0.05 0.23|
Info: Routing complete.
Info: Router1 time 0.23s
Info: Checksum: 0xb5a832a6
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_layer.GEN_NEURON[3].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q.Q
Info: routing 0.87 1.27 Net u_layer.GEN_NEURON[3].u_neuron.w_group[10] (64,23) -> (65,22)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9.B2
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:58.43-58.50
Info: logic 3.07 4.33 Source u_layer.GEN_NEURON[3].u_neuron.u_mac8.GEN_MAC[1].u_mac.product_MULT18X18D_P9.P5
Info: routing 1.12 5.45 Net u_layer.GEN_NEURON[3].u_neuron.u_mac8.products[1][5] (65,22) -> (64,21)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_B1_CCU2C_S1$CCU2_COMB1.A
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13
Info: logic 0.35 5.81 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_B1_CCU2C_S1$CCU2_COMB1.FCO
Info: routing 0.00 5.81 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_3_B1_CCU2C_S1_COUT (64,21) -> (65,21)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 5.86 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_COMB0.FCO
Info: routing 0.00 5.86 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_FCI_INT (65,21) -> (65,21)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_COMB1.FCI
Info: logic 0.00 5.86 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1$CCU2_COMB1.FCO
Info: routing 0.00 5.86 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_4_B1_CCU2C_S1_COUT (65,21) -> (65,21)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 5.92 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_COMB0.FCO
Info: routing 0.00 5.92 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_FCI_INT (65,21) -> (65,21)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_COMB1.FCI
Info: logic 0.00 5.92 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1$CCU2_COMB1.FCO
Info: routing 0.00 5.92 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_5_B1_CCU2C_S1_COUT (65,21) -> (65,21)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 5.98 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1$CCU2_COMB0.FCO
Info: routing 0.00 5.98 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1$CCU2_FCI_INT (65,21) -> (65,21)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1$CCU2_COMB1.FCI
Info: logic 0.00 5.98 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1$CCU2_COMB1.FCO
Info: routing 0.00 5.98 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_6_B1_CCU2C_S1_COUT (65,21) -> (65,21)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 6.03 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1$CCU2_COMB0.FCO
Info: routing 0.00 6.03 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1$CCU2_FCI_INT (65,21) -> (65,21)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1$CCU2_COMB1.FCI
Info: logic 0.00 6.03 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1$CCU2_COMB1.FCO
Info: routing 0.00 6.03 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_7_B1_CCU2C_S1_COUT (65,21) -> (66,21)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 6.09 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1$CCU2_COMB0.FCO
Info: routing 0.00 6.09 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1$CCU2_FCI_INT (66,21) -> (66,21)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1$CCU2_COMB1.FCI
Info: logic 0.00 6.09 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1$CCU2_COMB1.FCO
Info: routing 0.00 6.09 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT (66,21) -> (66,21)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT_CCU2C_CIN$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.33 6.42 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT_CCU2C_CIN$CCU2_COMB0.F
Info: routing 0.89 7.31 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_8_B1_CCU2C_S1_COUT_CCU2C_CIN_S0 (66,21) -> (66,19)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9$CCU2_COMB1.B
Info: logic 0.35 7.66 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9$CCU2_COMB1.FCO
Info: routing 0.00 7.66 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_9_COUT (66,19) -> (66,19)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 7.72 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB0.FCO
Info: routing 0.00 7.72 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10$CCU2_FCI_INT (66,19) -> (66,19)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB1.FCI
Info: logic 0.00 7.72 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB1.FCO
Info: routing 0.00 7.72 Net u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_10_COUT (66,19) -> (66,19)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_11$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:115.9-115.38
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.33 8.05 Source u_layer.GEN_NEURON[3].u_neuron.acc_next_CCU2C_S1_11$CCU2_COMB0.F
Info: routing 0.87 8.92 Net u_layer.GEN_NEURON[3].u_neuron.acc_next[20] (66,19) -> (66,18)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.A
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42
Info: logic 0.35 9.27 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 9.27 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (66,18) -> (66,18)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 9.27 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 9.27 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (66,18) -> (67,18)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 9.33 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 9.33 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (67,18) -> (67,18)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 9.33 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 9.33 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (67,18) -> (67,18)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 9.39 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 9.39 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (67,18) -> (67,18)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 9.39 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 9.39 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (67,18) -> (67,18)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 9.44 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 9.44 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (67,18) -> (67,18)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 9.44 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 9.44 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT_CIN (67,18) -> (67,18)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 9.50 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 9.50 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (67,18) -> (67,18)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 9.50 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 9.50 Net $nextpnr_CCU2C_13$CIN (67,18) -> (68,18)
Info: Sink $nextpnr_CCU2C_13$CCU2_COMB0.FCI
Info: logic 0.33 9.82 Source $nextpnr_CCU2C_13$CCU2_COMB0.F
Info: routing 0.52 10.35 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z_D (68,18) -> (68,20)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.D
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.18 10.53 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_Z.F
Info: routing 0.55 11.08 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_D[2] (68,20) -> (67,20)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 11.26 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z.F
Info: routing 0.12 11.38 Net u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_DI[5] (67,20) -> (67,20)
Info: Sink u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_5.DI
Info: setup 0.00 11.38 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_5.DI
Info: 6.43 ns logic, 4.95 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source start$tr_io.O
Info: routing 3.44 3.44 Net start$TRELLIS_IO_IN (0,23) -> (70,21)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z_LUT4_Z.B
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:10.11-10.16
Info: logic 0.18 3.62 Source u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z_LUT4_Z.F
Info: routing 0.66 4.28 Net u_layer.GEN_NEURON[0].u_neuron.done_TRELLIS_FF_Q_DI_LUT4_D_1_Z[1] (70,21) -> (72,24)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_Z.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 4.46 Source u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z_D_LUT4_Z.F
Info: routing 0.60 5.07 Net u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z_D[3] (72,24) -> (72,24)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.25 Source u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR_LUT4_Z.F
Info: routing 0.47 5.71 Net u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q_LSR (72,24) -> (72,23)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q.LSR
Info: setup 0.29 6.00 Source u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q.LSR
Info: 0.83 ns logic, 5.17 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_layer.GEN_NEURON[3].u_neuron.y_TRELLIS_FF_Q_4.Q
Info: routing 4.37 4.76 Net y_bus[28]$TRELLIS_IO_OUT (66,20) -> (18,71)
Info: Sink y_bus[28]$tr_io.I
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.v:6.26-6.31
Info: 0.40 ns logic, 4.37 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 87.88 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.00 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.76 ns
Info: Slack histogram:
Info: legend: * represents 2 endpoint(s)
Info: + represents [1,2) endpoint(s)
Info: [ 1121, 1647) |***+
Info: [ 1647, 2173) |*+
Info: [ 2173, 2699) |
Info: [ 2699, 3225) |
Info: [ 3225, 3751) |
Info: [ 3751, 4277) |*****+
Info: [ 4277, 4803) |**************+
Info: [ 4803, 5329) |***+
Info: [ 5329, 5855) |***+
Info: [ 5855, 6381) |+
Info: [ 6381, 6907) |
Info: [ 6907, 7433) |***+
Info: [ 7433, 7959) |*******+
Info: [ 7959, 8485) |****+
Info: [ 8485, 9011) |********+
Info: [ 9011, 9537) |****************+
Info: [ 9537, 10063) |******************+
Info: [ 10063, 10589) |************************************************************
Info: [ 10589, 11115) |*************************************+
Info: [ 11115, 11641) |*************************+
37 warnings, 0 errors
Info: Program finished normally.
synth/ecp5/p2/synth.ys
-8
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@@ -1,8 +0,0 @@
read_verilog -sv /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.v
hierarchy -top top
synth_ecp5 -top top
write_json /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p2/top.json
synth/ecp5/p2/top.config
-10863
View File
File diff suppressed because it is too large Load Diff
synth/ecp5/p2/top.json
-44888
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File diff suppressed because one or more lines are too long
synth/ecp5/p2/top.lpf
View File
synth/ecp5/p2/top.v
-78
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@@ -1,78 +0,0 @@
module top (
input clk,
input rst,
input start,
output signed [31:0] y_bus,
output busy,
output done
);
localparam DATA_WIDTH = 8;
localparam N_INPUTS = 256;
localparam N_NEURONS = 4;
localparam PARALLEL = 2;
localparam ACC_WIDTH = 32;
reg signed [DATA_WIDTH*N_INPUTS-1:0] x_bus;
reg signed [DATA_WIDTH*N_INPUTS*N_NEURONS-1:0] weights_bus;
reg signed [DATA_WIDTH*N_NEURONS-1:0] bias_bus;
integer i;
initial begin
x_bus = 0;
weights_bus = 0;
bias_bus = 0;
// X = 1
for (i = 0; i < N_INPUTS; i = i + 1)
x_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd1;
// Neuron 0: first 32 weights = +1
for (i = 0; i < 32; i = i + 1)
weights_bus[
0*N_INPUTS*DATA_WIDTH +
i*DATA_WIDTH +:
DATA_WIDTH
] = 8'sd1;
// Neuron 1: all zero, bias = 10
bias_bus[1*DATA_WIDTH +: DATA_WIDTH] = 8'sd10;
// Neuron 2: all weights = -1
for (i = 0; i < N_INPUTS; i = i + 1)
weights_bus[
2*N_INPUTS*DATA_WIDTH +
i*DATA_WIDTH +:
DATA_WIDTH
] = -8'sd1;
// Neuron 3: first 32 weights = +4
for (i = 0; i < 32; i = i + 1)
weights_bus[
3*N_INPUTS*DATA_WIDTH +
i*DATA_WIDTH +:
DATA_WIDTH
] = 8'sd4;
end
layer #(
.DATA_WIDTH(DATA_WIDTH),
.N_INPUTS(N_INPUTS),
.N_NEURONS(N_NEURONS),
.PARALLEL(PARALLEL),
.ACC_WIDTH(ACC_WIDTH)
) u_layer (
.clk(clk),
.rst(rst),
.start(start),
.x_bus(x_bus),
.weights_bus(weights_bus),
.bias_bus(bias_bus),
.y_bus(y_bus),
.busy(busy),
.done(done)
);
endmodule
synth/ecp5/p2/yosys.log
View File
synth/ecp5/p4/report.txt
-391
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@@ -1,391 +0,0 @@
Warning: IO 'y_bus[31]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[30]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[29]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[28]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[27]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[26]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[25]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[24]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[23]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[22]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[21]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[20]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[19]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[18]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[17]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[16]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[15]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[14]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[13]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[12]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[11]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[10]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[9]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[8]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[7]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[6]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[5]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[4]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[3]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[2]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[1]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[0]' is unconstrained in LPF and will be automatically placed
Warning: IO 'start' is unconstrained in LPF and will be automatically placed
Warning: IO 'rst' is unconstrained in LPF and will be automatically placed
Warning: IO 'done' is unconstrained in LPF and will be automatically placed
Warning: IO 'clk' is unconstrained in LPF and will be automatically placed
Warning: IO 'busy' is unconstrained in LPF and will be automatically placed
Info: Logic utilisation before packing:
Info: Total LUT4s: 804/43848 1%
Info: logic LUTs: 356/43848 0%
Info: carry LUTs: 448/43848 1%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 194/43848 0%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 191 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x93c68254
Info: Device utilisation:
Info: TRELLIS_IO: 37/ 245 15%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 16/ 72 22%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 194/ 43848 0%
Info: TRELLIS_COMB: 890/ 43848 2%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 398 cells, random placement wirelen = 65706.
Info: at initial placer iter 0, wirelen = 3255
Info: at initial placer iter 1, wirelen = 2910
Info: at initial placer iter 2, wirelen = 2817
Info: at initial placer iter 3, wirelen = 2693
Info: Running main analytical placer, max placement attempts per cell = 161880.
Info: at iteration #1, type ALL: wirelen solved = 2654, spread = 6917, legal = 7559; time = 0.01s
Info: at iteration #2, type ALL: wirelen solved = 2701, spread = 7543, legal = 8208; time = 0.01s
Info: at iteration #3, type ALL: wirelen solved = 2730, spread = 8315, legal = 8393; time = 0.01s
Info: at iteration #4, type ALL: wirelen solved = 2702, spread = 6982, legal = 7415; time = 0.01s
Info: at iteration #5, type ALL: wirelen solved = 2846, spread = 6733, legal = 7431; time = 0.01s
Info: at iteration #6, type ALL: wirelen solved = 2766, spread = 7088, legal = 7527; time = 0.01s
Info: at iteration #7, type ALL: wirelen solved = 2848, spread = 7040, legal = 7862; time = 0.01s
Info: at iteration #8, type ALL: wirelen solved = 2953, spread = 6901, legal = 8121; time = 0.01s
Info: at iteration #9, type ALL: wirelen solved = 2945, spread = 6701, legal = 8004; time = 0.01s
Info: HeAP Placer Time: 0.10s
Info: of which solving equations: 0.06s
Info: of which spreading cells: 0.01s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 277, wirelen = 7415
Info: at iteration #5: temp = 0.000000, timing cost = 202, wirelen = 5008
Info: at iteration #10: temp = 0.000000, timing cost = 301, wirelen = 4801
Info: at iteration #15: temp = 0.000000, timing cost = 280, wirelen = 4741
Info: at iteration #20: temp = 0.000000, timing cost = 272, wirelen = 4694
Info: at iteration #20: temp = 0.000000, timing cost = 271, wirelen = 4699
Info: SA placement time 0.33s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 76.41 MHz (FAIL at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 6.72 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 7.09 ns
Info: Slack histogram:
Info: legend: * represents 2 endpoint(s)
Info: + represents [1,2) endpoint(s)
Info: [ -588, 38) |****+
Info: [ 38, 664) |*+
Info: [ 664, 1290) |
Info: [ 1290, 1916) |
Info: [ 1916, 2542) |**+
Info: [ 2542, 3168) |**************+
Info: [ 3168, 3794) |******+
Info: [ 3794, 4420) |+
Info: [ 4420, 5046) |*+
Info: [ 5046, 5672) |*+
Info: [ 5672, 6298) |
Info: [ 6298, 6924) |********+
Info: [ 6924, 7550) |*****+
Info: [ 7550, 8176) |*+
Info: [ 8176, 8802) |**+
Info: [ 8802, 9428) |************+
Info: [ 9428, 10054) |************************************************************
Info: [ 10054, 10680) |******************************************+
Info: [ 10680, 11306) |*************************************+
Info: [ 11306, 11932) |*******+
Info: Checksum: 0x87182704
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 2833 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 615 384 | 615 384 | 2543| 0.16 0.16|
Info: 2000 | 1342 657 | 727 273 | 2390| 0.18 0.34|
Info: 3000 | 2021 978 | 679 321 | 2204| 0.17 0.51|
Info: 4000 | 2356 1549 | 335 571 | 1570| 0.11 0.61|
Info: 5000 | 2415 2379 | 59 830 | 638| 0.06 0.67|
Info: 5643 | 2421 2956 | 6 577 | 0| 0.09 0.76|
Info: Routing complete.
Info: Router1 time 0.76s
Info: Checksum: 0xf9732732
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_layer.GEN_NEURON[0].u_neuron.u_mac8.w_bus_TRELLIS_FF_Q.Q
Info: routing 1.14 1.53 Net u_layer.GEN_NEURON[0].u_neuron.w_group[0] (31,23) -> (23,22)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9.B0
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:58.43-58.50
Info: logic 3.07 4.60 Source u_layer.GEN_NEURON[0].u_neuron.u_mac8.GEN_MAC[0].u_mac.product_MULT18X18D_P9.P2
Info: routing 1.52 6.12 Net u_layer.GEN_NEURON[0].u_neuron.u_mac8.products[0][2] (23,22) -> (31,20)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.B
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:73.9-73.13
Info: logic 0.35 6.47 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO
Info: routing 0.00 6.47 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (31,20) -> (31,20)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI
Info: logic 0.00 6.47 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO
Info: routing 0.00 6.47 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (31,20) -> (31,20)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 6.53 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCO
Info: routing 0.00 6.53 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_FCI_INT (31,20) -> (31,20)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCI
Info: logic 0.00 6.53 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB1.FCO
Info: routing 0.00 6.53 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_COUT (31,20) -> (32,20)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:101.21-102.44
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.33 6.86 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1$CCU2_COMB0.F
Info: routing 0.68 7.54 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0[2] (32,20) -> (34,20)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_A0_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.72 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_A0_LUT4_Z.F
Info: routing 1.09 8.81 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_A0 (34,20) -> (35,19)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB0.A
Info: logic 0.35 9.16 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB0.FCO
Info: routing 0.00 9.16 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13$CCU2_FCI_INT (35,19) -> (35,19)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB1.FCI
Info: logic 0.00 9.16 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB1.FCO
Info: routing 0.00 9.16 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_13_COUT (35,19) -> (35,19)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 9.22 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB0.FCO
Info: routing 0.00 9.22 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12$CCU2_FCI_INT (35,19) -> (35,19)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB1.FCI
Info: logic 0.00 9.22 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB1.FCO
Info: routing 0.00 9.22 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_12_COUT (35,19) -> (35,19)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 9.27 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB0.FCO
Info: routing 0.00 9.27 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10$CCU2_FCI_INT (35,19) -> (35,19)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB1.FCI
Info: logic 0.00 9.27 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB1.FCO
Info: routing 0.00 9.27 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_10_COUT (35,19) -> (35,19)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 9.33 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1$CCU2_COMB0.FCO
Info: routing 0.00 9.33 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1$CCU2_FCI_INT (35,19) -> (35,19)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1$CCU2_COMB1.FCI
Info: logic 0.00 9.33 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1$CCU2_COMB1.FCO
Info: routing 0.00 9.33 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_COUT (35,19) -> (36,19)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 9.38 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB0.FCO
Info: routing 0.00 9.38 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14$CCU2_FCI_INT (36,19) -> (36,19)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB1.FCI
Info: logic 0.00 9.38 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB1.FCO
Info: routing 0.00 9.38 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_14_COUT (36,19) -> (36,19)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 9.44 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB0.FCO
Info: routing 0.00 9.44 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1$CCU2_FCI_INT (36,19) -> (36,19)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB1.FCI
Info: logic 0.00 9.44 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB1.FCO
Info: routing 0.00 9.44 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_1_COUT (36,19) -> (36,19)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 9.50 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2$CCU2_COMB0.FCO
Info: routing 0.00 9.50 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2$CCU2_FCI_INT (36,19) -> (36,19)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2$CCU2_COMB1.FCI
Info: logic 0.00 9.50 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2$CCU2_COMB1.FCO
Info: routing 0.00 9.50 Net u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_2_COUT (36,19) -> (36,19)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_3$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.33 9.82 Source u_layer.GEN_NEURON[0].u_neuron.acc_next_CCU2C_S1_3$CCU2_COMB0.F
Info: routing 0.85 10.67 Net u_layer.GEN_NEURON[0].u_neuron.acc_next[20] (36,19) -> (36,18)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.A
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42
Info: logic 0.35 11.02 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 11.02 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (36,18) -> (36,18)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 11.02 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 11.02 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (36,18) -> (37,18)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 11.08 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 11.08 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (37,18) -> (37,18)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 11.08 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 11.08 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (37,18) -> (37,18)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 11.14 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 11.14 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (37,18) -> (37,18)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 11.14 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 11.14 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT_CIN (37,18) -> (37,18)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 11.19 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 11.19 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (37,18) -> (37,18)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 11.19 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 11.19 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT_CIN (37,18) -> (37,18)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCI
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 11.25 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB0.FCO
Info: routing 0.00 11.25 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT$CCU2_FCI_INT (37,18) -> (37,18)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCI
Info: logic 0.00 11.25 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D_CCU2C_COUT$CCU2_COMB1.FCO
Info: routing 0.00 11.25 Net $nextpnr_CCU2C_19$CIN (37,18) -> (38,18)
Info: Sink $nextpnr_CCU2C_19$CCU2_COMB0.FCI
Info: logic 0.33 11.58 Source $nextpnr_CCU2C_19$CCU2_COMB0.F
Info: routing 0.63 12.21 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z_D (38,18) -> (38,23)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z.D
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v:127.30-127.45
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.18 12.39 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C_LUT4_Z.F
Info: routing 0.64 13.03 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_C[1] (38,23) -> (36,23)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_4.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 13.21 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI_LUT4_Z_4.F
Info: routing 0.12 13.33 Net u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_DI[5] (36,23) -> (36,23)
Info: Sink u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_5.DI
Info: setup 0.00 13.33 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q_5.DI
Info: 6.67 ns logic, 6.66 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source rst$tr_io.O
Info: routing 3.60 3.60 Net rst$TRELLIS_IO_IN (0,23) -> (63,24)
Info: Sink start_LUT4_B_2.C
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:9.11-9.14
Info: logic 0.18 3.78 Source start_LUT4_B_2.F
Info: routing 1.31 5.09 Net start_LUT4_B_2_Z (63,24) -> (67,27)
Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_31.LSR
Info: setup 0.29 5.38 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_31.LSR
Info: 0.47 ns logic, 4.91 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_layer.GEN_NEURON[2].u_neuron.y_TRELLIS_FF_Q_4.Q
Info: routing 4.40 4.79 Net y_bus[20]$TRELLIS_IO_OUT (64,25) -> (18,71)
Info: Sink y_bus[20]$tr_io.I
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.v:6.26-6.31
Info: 0.40 ns logic, 4.40 ns routing
ERROR: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 75.01 MHz (FAIL at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.38 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.79 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ -831, -207) |*******+
Info: [ -207, 417) |
Info: [ 417, 1041) |
Info: [ 1041, 1665) |
Info: [ 1665, 2289) |*+
Info: [ 2289, 2913) |*********************+
Info: [ 2913, 3537) |*******+
Info: [ 3537, 4161) |***+
Info: [ 4161, 4785) |**+
Info: [ 4785, 5409) |
Info: [ 5409, 6033) |***+
Info: [ 6033, 6657) |**********+
Info: [ 6657, 7281) |****+
Info: [ 7281, 7905) |*+
Info: [ 7905, 8529) |*+
Info: [ 8529, 9153) |********************+
Info: [ 9153, 9777) |************************+
Info: [ 9777, 10401) |************************************************************
Info: [ 10401, 11025) |*******************************************************+
Info: [ 11025, 11649) |**********************************************+
37 warnings, 1 error
Info: Program finished normally.
synth/ecp5/p4/synth.ys
-8
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@@ -1,8 +0,0 @@
read_verilog -sv /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.v
hierarchy -top top
synth_ecp5 -top top
write_json /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p4/top.json
synth/ecp5/p4/top.config
-15757
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File diff suppressed because it is too large Load Diff
synth/ecp5/p4/top.json
-57007
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File diff suppressed because one or more lines are too long
synth/ecp5/p4/top.lpf
View File
synth/ecp5/p4/top.v
-78
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@@ -1,78 +0,0 @@
module top (
input clk,
input rst,
input start,
output signed [31:0] y_bus,
output busy,
output done
);
localparam DATA_WIDTH = 8;
localparam N_INPUTS = 256;
localparam N_NEURONS = 4;
localparam PARALLEL = 4;
localparam ACC_WIDTH = 32;
reg signed [DATA_WIDTH*N_INPUTS-1:0] x_bus;
reg signed [DATA_WIDTH*N_INPUTS*N_NEURONS-1:0] weights_bus;
reg signed [DATA_WIDTH*N_NEURONS-1:0] bias_bus;
integer i;
initial begin
x_bus = 0;
weights_bus = 0;
bias_bus = 0;
// X = 1
for (i = 0; i < N_INPUTS; i = i + 1)
x_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd1;
// Neuron 0: first 32 weights = +1
for (i = 0; i < 32; i = i + 1)
weights_bus[
0*N_INPUTS*DATA_WIDTH +
i*DATA_WIDTH +:
DATA_WIDTH
] = 8'sd1;
// Neuron 1: all zero, bias = 10
bias_bus[1*DATA_WIDTH +: DATA_WIDTH] = 8'sd10;
// Neuron 2: all weights = -1
for (i = 0; i < N_INPUTS; i = i + 1)
weights_bus[
2*N_INPUTS*DATA_WIDTH +
i*DATA_WIDTH +:
DATA_WIDTH
] = -8'sd1;
// Neuron 3: first 32 weights = +4
for (i = 0; i < 32; i = i + 1)
weights_bus[
3*N_INPUTS*DATA_WIDTH +
i*DATA_WIDTH +:
DATA_WIDTH
] = 8'sd4;
end
layer #(
.DATA_WIDTH(DATA_WIDTH),
.N_INPUTS(N_INPUTS),
.N_NEURONS(N_NEURONS),
.PARALLEL(PARALLEL),
.ACC_WIDTH(ACC_WIDTH)
) u_layer (
.clk(clk),
.rst(rst),
.start(start),
.x_bus(x_bus),
.weights_bus(weights_bus),
.bias_bus(bias_bus),
.y_bus(y_bus),
.busy(busy),
.done(done)
);
endmodule
synth/ecp5/p4/yosys.log
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synth/ecp5/p8/nextpnr.log
-10364
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File diff suppressed because it is too large Load Diff
synth/ecp5/p8/report.txt
-275
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@@ -1,275 +0,0 @@
Warning: IO 'y_bus[31]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[30]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[29]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[28]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[27]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[26]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[25]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[24]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[23]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[22]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[21]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[20]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[19]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[18]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[17]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[16]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[15]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[14]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[13]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[12]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[11]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[10]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[9]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[8]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[7]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[6]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[5]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[4]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[3]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[2]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[1]' is unconstrained in LPF and will be automatically placed
Warning: IO 'y_bus[0]' is unconstrained in LPF and will be automatically placed
Warning: IO 'start' is unconstrained in LPF and will be automatically placed
Warning: IO 'rst' is unconstrained in LPF and will be automatically placed
Warning: IO 'done' is unconstrained in LPF and will be automatically placed
Warning: IO 'clk' is unconstrained in LPF and will be automatically placed
Warning: IO 'busy' is unconstrained in LPF and will be automatically placed
Info: Logic utilisation before packing:
Info: Total LUT4s: 737/43848 1%
Info: logic LUTs: 737/43848 1%
Info: carry LUTs: 0/43848 0%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 164/43848 0%
Info: Packing IOs..
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 143 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0xba108497
Info: Device utilisation:
Info: TRELLIS_IO: 37/ 245 15%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 0/ 108 0%
Info: MULT18X18D: 0/ 72 0%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 164/ 43848 0%
Info: TRELLIS_COMB: 738/ 43848 1%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 0 cells based on constraints.
Info: Creating initial analytic placement for 316 cells, random placement wirelen = 29789.
Info: at initial placer iter 0, wirelen = 1963
Info: at initial placer iter 1, wirelen = 1613
Info: at initial placer iter 2, wirelen = 1586
Info: at initial placer iter 3, wirelen = 1563
Info: Running main analytical placer, max placement attempts per cell = 110450.
Info: at iteration #1, type ALL: wirelen solved = 1570, spread = 2941, legal = 3088; time = 0.01s
Info: at iteration #2, type ALL: wirelen solved = 1684, spread = 2706, legal = 2843; time = 0.01s
Info: at iteration #3, type ALL: wirelen solved = 1708, spread = 2620, legal = 2790; time = 0.01s
Info: at iteration #4, type ALL: wirelen solved = 1737, spread = 2552, legal = 2659; time = 0.01s
Info: at iteration #5, type ALL: wirelen solved = 1777, spread = 2535, legal = 2630; time = 0.01s
Info: at iteration #6, type ALL: wirelen solved = 1824, spread = 2651, legal = 2719; time = 0.01s
Info: at iteration #7, type ALL: wirelen solved = 1832, spread = 2550, legal = 2667; time = 0.01s
Info: at iteration #8, type ALL: wirelen solved = 1864, spread = 2610, legal = 2719; time = 0.01s
Info: at iteration #9, type ALL: wirelen solved = 1928, spread = 2544, legal = 2641; time = 0.01s
Info: at iteration #10, type ALL: wirelen solved = 1940, spread = 2863, legal = 2901; time = 0.01s
Info: HeAP Placer Time: 0.10s
Info: of which solving equations: 0.07s
Info: of which spreading cells: 0.01s
Info: of which strict legalisation: 0.00s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 96, wirelen = 2630
Info: at iteration #5: temp = 0.000000, timing cost = 138, wirelen = 2016
Info: at iteration #10: temp = 0.000000, timing cost = 108, wirelen = 1947
Info: at iteration #15: temp = 0.000000, timing cost = 100, wirelen = 1917
Info: at iteration #17: temp = 0.000000, timing cost = 118, wirelen = 1911
Info: SA placement time 0.21s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 132.89 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.99 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.41 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 4975, 5323) |*****+
Info: [ 5323, 5671) |
Info: [ 5671, 6019) |****+
Info: [ 6019, 6367) |*********+
Info: [ 6367, 6715) |*******+
Info: [ 6715, 7063) |*******+
Info: [ 7063, 7411) |******+
Info: [ 7411, 7759) |*****+
Info: [ 7759, 8107) |*******************+
Info: [ 8107, 8455) |*****************+
Info: [ 8455, 8803) |***************************+
Info: [ 8803, 9151) |************+
Info: [ 9151, 9499) |***********+
Info: [ 9499, 9847) |**************************+
Info: [ 9847, 10195) |****************************************************+
Info: [ 10195, 10543) |************************************************************
Info: [ 10543, 10891) |***********************+
Info: [ 10891, 11239) |**************************************+
Info: [ 11239, 11587) |************************************+
Info: [ 11587, 11935) |*****+
Info: Checksum: 0xf1666ddb
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 2723 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 341 658 | 341 658 | 2076| 0.08 0.08|
Info: 2000 | 540 1426 | 199 768 | 1288| 0.04 0.12|
Info: 3000 | 602 2280 | 62 854 | 350| 0.03 0.15|
Info: 3372 | 625 2485 | 23 205 | 0| 0.07 0.22|
Info: Routing complete.
Info: Router1 time 0.22s
Info: Checksum: 0x3dbc8311
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q.Q
Info: routing 0.84 1.24 Net u_layer.GEN_NEURON[1].u_neuron.acc[2] (21,30) -> (20,30)
Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_ALUT_LUT4_Z.D
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v:9.35-9.42
Info: logic 0.18 1.42 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_ALUT_LUT4_Z.F
Info: routing 0.00 1.42 Net u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_ALUT (20,30) -> (20,30)
Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_BLUT_LUT4_Z.F1
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:133.22-133.24
Info: logic 0.13 1.54 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.78 2.33 Net u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D[6] (20,30) -> (22,27)
Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 2.52 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.58 3.10 Net u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_1_DI_LUT4_Z_C_LUT4_Z_D_PFUMX_C0_Z_LUT4_Z_D_L6MUX21_SD_Z[6] (22,27) -> (21,26)
Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 3.29 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.00 3.29 Net u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1 (21,26) -> (21,26)
Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72
Info: logic 0.18 3.47 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.53 4.00 Net u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z[6] (21,26) -> (20,27)
Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 4.20 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.53 4.73 Net u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_5_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_SD_Z[6] (20,27) -> (18,27)
Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 4.92 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.68 5.60 Net u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_16_DI_LUT4_Z_C_L6MUX21_SD_Z_L6MUX21_SD_Z[3] (18,27) -> (18,28)
Info: Sink u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.31 5.91 Source u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.OFX
Info: routing 0.00 5.91 Net u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D0 (18,28) -> (18,28)
Info: Sink u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXA
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52
Info: logic 0.18 6.09 Source u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.00 6.09 Net u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D0 (18,28) -> (18,28)
Info: Sink u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXA
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68
Info: logic 0.18 6.27 Source u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info: routing 0.51 6.77 Net u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3_DI (18,28) -> (18,27)
Info: Sink u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3.M
Info: setup 0.00 6.77 Source u_layer.GEN_NEURON[1].u_neuron.y_TRELLIS_FF_Q_3.M
Info: 2.32 ns logic, 4.46 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source rst$tr_io.O
Info: routing 2.64 2.64 Net rst$TRELLIS_IO_IN (44,0) -> (20,21)
Info: Sink u_layer.GEN_NEURON[1].u_neuron.busy_LUT4_D.C
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v:9.11-9.14
Info: logic 0.18 2.82 Source u_layer.GEN_NEURON[1].u_neuron.busy_LUT4_D.F
Info: routing 1.19 4.01 Net u_layer.GEN_NEURON[1].u_neuron.busy_LUT4_D_Z (20,21) -> (16,30)
Info: Sink u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_29.LSR
Info: setup 0.29 4.29 Source u_layer.GEN_NEURON[1].u_neuron.acc_TRELLIS_FF_Q_29.LSR
Info: 0.47 ns logic, 3.83 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_layer.GEN_NEURON[0].u_neuron.y_TRELLIS_FF_Q.Q
Info: routing 3.92 4.31 Net y_bus[0]$TRELLIS_IO_OUT (31,7) -> (90,29)
Info: Sink y_bus[2]$tr_io.I
Info: Defined in:
Info: /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v:6.26-6.31
Info: 0.40 ns logic, 3.92 ns routing
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 147.62 MHz (PASS at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.29 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.31 ns
Info: Slack histogram:
Info: legend: * represents 1 endpoint(s)
Info: + represents [1,1) endpoint(s)
Info: [ 5726, 6025) |**+
Info: [ 6025, 6324) |******+
Info: [ 6324, 6623) |*********+
Info: [ 6623, 6922) |****+
Info: [ 6922, 7221) |**********+
Info: [ 7221, 7520) |********+
Info: [ 7520, 7819) |***********+
Info: [ 7819, 8118) |***+
Info: [ 8118, 8417) |*******+
Info: [ 8417, 8716) |***********************+
Info: [ 8716, 9015) |****************************+
Info: [ 9015, 9314) |****************+
Info: [ 9314, 9613) |******************+
Info: [ 9613, 9912) |**************+
Info: [ 9912, 10211) |********+
Info: [ 10211, 10510) |******************************************************+
Info: [ 10510, 10809) |***************************************************+
Info: [ 10809, 11108) |*********************************+
Info: [ 11108, 11407) |************************************************************
Info: [ 11407, 11706) |**************+
37 warnings, 0 errors
Info: Program finished normally.
synth/ecp5/p8/synth.log
-1
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@@ -1 +0,0 @@
ERROR: Module `top' not found!
synth/ecp5/p8/synth.ys
-20
View File
@@ -1,20 +0,0 @@
read_verilog -sv \
/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac_unit.v \
/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/mac8.v \
/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/neuron_parallel.v \
/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/rtl/layer.v \
/Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.v
hierarchy -top top
proc
flatten
opt
memory
opt
techmap
opt
abc -g simple
clean
synth_ecp5 -top top -json /Users/michelebigi/Development/FPGA-Neural/FPGA-Neural/synth/ecp5/p8/top.json
synth/ecp5/p8/top.config
-11777
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File diff suppressed because it is too large Load Diff
synth/ecp5/p8/top.json
-66138
View File
File diff suppressed because one or more lines are too long
synth/ecp5/p8/top.lpf
View File
synth/ecp5/p8/top.v
-125
View File
@@ -1,125 +0,0 @@
module top #(
parameter DATA_WIDTH = 8,
parameter N_INPUTS = 256,
parameter N_NEURONS = 4,
parameter PARALLEL = 8,
parameter ACC_WIDTH = 32
)(
input wire clk,
input wire rst,
input wire start,
output wire signed [31:0] y_bus,
output wire busy,
output wire done
);
localparam X_BITS = DATA_WIDTH * N_INPUTS;
localparam W_BITS = DATA_WIDTH * N_INPUTS * N_NEURONS;
localparam B_BITS = DATA_WIDTH * N_NEURONS;
/*
* Internal neural-network data.
*
* These are deliberately registers, not parameters/constants.
* This prevents the complete datapath from disappearing during
* synthesis.
*/
reg signed [X_BITS-1:0] x_bus;
reg signed [W_BITS-1:0] weights_bus;
reg signed [B_BITS-1:0] bias_bus;
integer i;
integer n;
/*
* Deterministic initialization.
*
* The actual datapath remains present because the vectors are
* stored in registers and loaded through the clocked process.
*/
always @(posedge clk) begin
if (rst) begin
x_bus <= '0;
weights_bus <= '0;
bias_bus <= '0;
end
else if (start) begin
/*
* INT8 input vector.
*
* Pattern:
* -16 ... +15
*/
for (i = 0; i < N_INPUTS; i = i + 1) begin
x_bus[i*DATA_WIDTH +: DATA_WIDTH]
<= ((i * 17 + 3) % 31) - 15;
end
/*
* INT8 weights.
*/
for (n = 0; n < N_NEURONS; n = n + 1) begin
for (i = 0; i < N_INPUTS; i = i + 1) begin
weights_bus[
(n*N_INPUTS+i)*DATA_WIDTH
+: DATA_WIDTH
]
<= ((n * 29 + i * 13 + 5) % 31) - 15;
end
end
/*
* INT8 biases.
*/
for (n = 0; n < N_NEURONS; n = n + 1) begin
bias_bus[
n*DATA_WIDTH
+: DATA_WIDTH
]
<= ((n * 7 + 1) % 9) - 4;
end
end
end
/*
* Real neural-network layer.
*/
layer #(
.DATA_WIDTH(DATA_WIDTH),
.N_INPUTS(N_INPUTS),
.N_NEURONS(N_NEURONS),
.PARALLEL(PARALLEL),
.ACC_WIDTH(ACC_WIDTH)
) dut (
.clk(clk),
.rst(rst),
.start(start),
.x_bus(x_bus),
.weights_bus(weights_bus),
.bias_bus(bias_bus),
.y_bus(y_bus),
.busy(busy),
.done(done)
);
endmodule
synth/ecp5/p8/yosys.log
-11080
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File diff suppressed because it is too large Load Diff
synth/ecp5/post_fix_verify/nextpnr.log
-550
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@@ -1,550 +0,0 @@
Info: Logic utilisation before packing:
Info: Total LUT4s: 8907/43848 20%
Info: logic LUTs: 7795/43848 17%
Info: carry LUTs: 1112/43848 2%
Info: RAM LUTs: 0/ 5481 0%
Info: RAMW LUTs: 0/10962 0%
Info: Total DFFs: 4900/43848 11%
Info: Packing IOs..
Info: $psram_dq[15]$iobuf_i: psram_dq_$_TBUF__Y.Y
Info: pin 'psram_dq[15]$tr_io' constrained to Bel 'X90/Y41/PIOD'.
Info: $psram_dq[14]$iobuf_i: psram_dq_$_TBUF__Y_10.Y
Info: pin 'psram_dq[14]$tr_io' constrained to Bel 'X90/Y41/PIOC'.
Info: $psram_dq[13]$iobuf_i: psram_dq_$_TBUF__Y_9.Y
Info: pin 'psram_dq[13]$tr_io' constrained to Bel 'X90/Y41/PIOA'.
Info: $psram_dq[12]$iobuf_i: psram_dq_$_TBUF__Y_8.Y
Info: pin 'psram_dq[12]$tr_io' constrained to Bel 'X90/Y41/PIOB'.
Info: $psram_dq[11]$iobuf_i: psram_dq_$_TBUF__Y_7.Y
Info: pin 'psram_dq[11]$tr_io' constrained to Bel 'X90/Y38/PIOD'.
Info: $psram_dq[10]$iobuf_i: psram_dq_$_TBUF__Y_6.Y
Info: pin 'psram_dq[10]$tr_io' constrained to Bel 'X90/Y38/PIOB'.
Info: $psram_dq[9]$iobuf_i: psram_dq_$_TBUF__Y_4.Y
Info: pin 'psram_dq[9]$tr_io' constrained to Bel 'X90/Y32/PIOD'.
Info: $psram_dq[8]$iobuf_i: psram_dq_$_TBUF__Y_3.Y
Info: pin 'psram_dq[8]$tr_io' constrained to Bel 'X90/Y32/PIOB'.
Info: $psram_dq[7]$iobuf_i: psram_dq_$_TBUF__Y_1.Y
Info: pin 'psram_dq[7]$tr_io' constrained to Bel 'X90/Y32/PIOC'.
Info: $psram_dq[6]$iobuf_i: psram_dq_$_TBUF__Y_15.Y
Info: pin 'psram_dq[6]$tr_io' constrained to Bel 'X90/Y32/PIOA'.
Info: $psram_dq[5]$iobuf_i: psram_dq_$_TBUF__Y_14.Y
Info: pin 'psram_dq[5]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
Info: $psram_dq[4]$iobuf_i: psram_dq_$_TBUF__Y_13.Y
Info: pin 'psram_dq[4]$tr_io' constrained to Bel 'X90/Y29/PIOA'.
Info: $psram_dq[3]$iobuf_i: psram_dq_$_TBUF__Y_12.Y
Info: pin 'psram_dq[3]$tr_io' constrained to Bel 'X90/Y23/PIOC'.
Info: $psram_dq[2]$iobuf_i: psram_dq_$_TBUF__Y_11.Y
Info: pin 'psram_dq[2]$tr_io' constrained to Bel 'X90/Y11/PIOB'.
Info: $psram_dq[1]$iobuf_i: psram_dq_$_TBUF__Y_5.Y
Info: pin 'psram_dq[1]$tr_io' constrained to Bel 'X90/Y11/PIOA'.
Info: $psram_dq[0]$iobuf_i: psram_dq_$_TBUF__Y_2.Y
Info: pin 'psram_dq[0]$tr_io' constrained to Bel 'X90/Y29/PIOD'.
Info: pin 'sclk$tr_io' constrained to Bel 'X0/Y11/PIOC'.
Info: pin 'rst$tr_io' constrained to Bel 'X0/Y14/PIOB'.
Info: pin 'psram_zz_n$tr_io' constrained to Bel 'X90/Y59/PIOB'.
Info: pin 'psram_we_n$tr_io' constrained to Bel 'X90/Y44/PIOD'.
Info: pin 'psram_ub_n$tr_io' constrained to Bel 'X90/Y59/PIOA'.
Info: pin 'psram_oe_n$tr_io' constrained to Bel 'X90/Y44/PIOC'.
Info: pin 'psram_lb_n$tr_io' constrained to Bel 'X90/Y53/PIOA'.
Info: pin 'psram_ce_n$tr_io' constrained to Bel 'X90/Y44/PIOA'.
Info: pin 'psram_a[22]$tr_io' constrained to Bel 'X90/Y59/PIOD'.
Info: pin 'psram_a[21]$tr_io' constrained to Bel 'X90/Y29/PIOB'.
Info: pin 'psram_a[20]$tr_io' constrained to Bel 'X90/Y26/PIOD'.
Info: pin 'psram_a[19]$tr_io' constrained to Bel 'X90/Y26/PIOC'.
Info: pin 'psram_a[18]$tr_io' constrained to Bel 'X90/Y26/PIOB'.
Info: pin 'psram_a[17]$tr_io' constrained to Bel 'X90/Y26/PIOA'.
Info: pin 'psram_a[16]$tr_io' constrained to Bel 'X90/Y23/PIOD'.
Info: pin 'psram_a[15]$tr_io' constrained to Bel 'X90/Y23/PIOB'.
Info: pin 'psram_a[14]$tr_io' constrained to Bel 'X90/Y23/PIOA'.
Info: pin 'psram_a[13]$tr_io' constrained to Bel 'X90/Y20/PIOC'.
Info: pin 'psram_a[12]$tr_io' constrained to Bel 'X90/Y20/PIOD'.
Info: pin 'psram_a[11]$tr_io' constrained to Bel 'X90/Y20/PIOA'.
Info: pin 'psram_a[10]$tr_io' constrained to Bel 'X90/Y20/PIOB'.
Info: pin 'psram_a[9]$tr_io' constrained to Bel 'X90/Y17/PIOD'.
Info: pin 'psram_a[8]$tr_io' constrained to Bel 'X90/Y17/PIOB'.
Info: pin 'psram_a[7]$tr_io' constrained to Bel 'X90/Y17/PIOC'.
Info: pin 'psram_a[6]$tr_io' constrained to Bel 'X90/Y17/PIOA'.
Info: pin 'psram_a[5]$tr_io' constrained to Bel 'X90/Y14/PIOD'.
Info: pin 'psram_a[4]$tr_io' constrained to Bel 'X90/Y14/PIOC'.
Info: pin 'psram_a[3]$tr_io' constrained to Bel 'X90/Y14/PIOB'.
Info: pin 'psram_a[2]$tr_io' constrained to Bel 'X90/Y14/PIOA'.
Info: pin 'psram_a[1]$tr_io' constrained to Bel 'X90/Y11/PIOD'.
Info: pin 'psram_a[0]$tr_io' constrained to Bel 'X90/Y11/PIOC'.
Info: pin 'mosi$tr_io' constrained to Bel 'X0/Y11/PIOD'.
Info: pin 'miso$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: pin 'irq_n$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'flash_sclk$tr_io' constrained to Bel 'X0/Y20/PIOB'.
Info: pin 'flash_mosi$tr_io' constrained to Bel 'X0/Y17/PIOD'.
Info: pin 'flash_miso$tr_io' constrained to Bel 'X0/Y17/PIOB'.
Info: pin 'flash_cs_n$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: pin 'data_ready_n$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'cs_n$tr_io' constrained to Bel 'X0/Y14/PIOD'.
Info: pin 'clk$tr_io' constrained to Bel 'X0/Y29/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info: 1080 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info: promoting clock net clk$TRELLIS_IO_IN to global network
Info: Checksum: 0x08746c0c
Info: Device utilisation:
Info: TRELLIS_IO: 57/ 245 23%
Info: DCCA: 1/ 56 1%
Info: DP16KD: 2/ 108 1%
Info: MULT18X18D: 16/ 72 22%
Info: ALU54B: 0/ 36 0%
Info: EHXPLLL: 0/ 4 0%
Info: EXTREFB: 0/ 2 0%
Info: DCUA: 0/ 2 0%
Info: PCSCLKDIV: 0/ 2 0%
Info: IOLOGIC: 0/ 160 0%
Info: SIOLOGIC: 0/ 85 0%
Info: GSR: 0/ 1 0%
Info: JTAGG: 0/ 1 0%
Info: OSCG: 0/ 1 0%
Info: SEDGA: 0/ 1 0%
Info: DTR: 0/ 1 0%
Info: USRMCLK: 0/ 1 0%
Info: CLKDIVF: 0/ 4 0%
Info: ECLKSYNCB: 0/ 10 0%
Info: DLLDELD: 0/ 8 0%
Info: DDRDLL: 0/ 4 0%
Info: DQSBUFM: 0/ 10 0%
Info: TRELLIS_ECLKBUF: 0/ 8 0%
Info: ECLKBRIDGECS: 0/ 2 0%
Info: DCSC: 0/ 2 0%
Info: TRELLIS_FF: 4900/ 43848 11%
Info: TRELLIS_COMB: 9165/ 43848 20%
Info: TRELLIS_RAMW: 0/ 5481 0%
Info: Placed 57 cells based on constraints.
Info: Creating initial analytic placement for 10492 cells, random placement wirelen = 797330.
Info: at initial placer iter 0, wirelen = 5197
Info: at initial placer iter 1, wirelen = 4389
Info: at initial placer iter 2, wirelen = 3693
Info: at initial placer iter 3, wirelen = 3760
Info: Running main analytical placer, max placement attempts per cell = 24995985.
Info: at iteration #1, type ALL: wirelen solved = 3883, spread = 120927, legal = 125831; time = 0.18s
Info: at iteration #2, type ALL: wirelen solved = 14310, spread = 76912, legal = 79644; time = 0.16s
Info: at iteration #3, type ALL: wirelen solved = 22217, spread = 61928, legal = 65679; time = 0.15s
Info: at iteration #4, type ALL: wirelen solved = 25026, spread = 56917, legal = 60005; time = 0.14s
Info: at iteration #5, type ALL: wirelen solved = 27121, spread = 52557, legal = 56138; time = 0.14s
Info: at iteration #6, type ALL: wirelen solved = 28450, spread = 51631, legal = 55626; time = 0.13s
Info: at iteration #7, type ALL: wirelen solved = 30390, spread = 48094, legal = 51822; time = 0.13s
Info: at iteration #8, type ALL: wirelen solved = 29967, spread = 48054, legal = 53555; time = 0.13s
Info: at iteration #9, type ALL: wirelen solved = 31078, spread = 47661, legal = 52458; time = 0.14s
Info: at iteration #10, type ALL: wirelen solved = 31564, spread = 47468, legal = 51996; time = 0.14s
Info: at iteration #11, type ALL: wirelen solved = 31872, spread = 46038, legal = 51814; time = 0.14s
Info: at iteration #12, type ALL: wirelen solved = 32380, spread = 45796, legal = 50432; time = 0.16s
Info: at iteration #13, type ALL: wirelen solved = 32602, spread = 43880, legal = 50578; time = 0.14s
Info: at iteration #14, type ALL: wirelen solved = 32739, spread = 42924, legal = 49487; time = 0.13s
Info: at iteration #15, type ALL: wirelen solved = 32708, spread = 42518, legal = 49797; time = 0.13s
Info: at iteration #16, type ALL: wirelen solved = 32550, spread = 42599, legal = 48936; time = 0.13s
Info: at iteration #17, type ALL: wirelen solved = 32792, spread = 43189, legal = 48933; time = 0.13s
Info: at iteration #18, type ALL: wirelen solved = 33591, spread = 44028, legal = 49702; time = 0.13s
Info: at iteration #19, type ALL: wirelen solved = 33859, spread = 44016, legal = 50416; time = 0.13s
Info: at iteration #20, type ALL: wirelen solved = 33997, spread = 43827, legal = 49049; time = 0.13s
Info: at iteration #21, type ALL: wirelen solved = 34355, spread = 43271, legal = 48495; time = 0.13s
Info: at iteration #22, type ALL: wirelen solved = 34654, spread = 42843, legal = 48497; time = 0.13s
Info: at iteration #23, type ALL: wirelen solved = 34737, spread = 43802, legal = 48650; time = 0.13s
Info: at iteration #24, type ALL: wirelen solved = 35197, spread = 43297, legal = 47914; time = 0.13s
Info: at iteration #25, type ALL: wirelen solved = 35104, spread = 44266, legal = 48721; time = 0.12s
Info: at iteration #26, type ALL: wirelen solved = 35633, spread = 43981, legal = 48519; time = 0.12s
Info: at iteration #27, type ALL: wirelen solved = 35804, spread = 44946, legal = 49959; time = 0.13s
Info: at iteration #28, type ALL: wirelen solved = 36354, spread = 44422, legal = 48670; time = 0.12s
Info: at iteration #29, type ALL: wirelen solved = 36374, spread = 44811, legal = 48646; time = 0.13s
Info: HeAP Placer Time: 5.27s
Info: of which solving equations: 3.55s
Info: of which spreading cells: 0.61s
Info: of which strict legalisation: 0.24s
Info: Running simulated annealing placer for refinement.
Info: at iteration #1: temp = 0.000000, timing cost = 2010, wirelen = 47914
Info: at iteration #5: temp = 0.000000, timing cost = 2003, wirelen = 42879
Info: at iteration #10: temp = 0.000000, timing cost = 2287, wirelen = 41464
Info: at iteration #15: temp = 0.000000, timing cost = 2292, wirelen = 40670
Info: at iteration #20: temp = 0.000000, timing cost = 2268, wirelen = 40347
Info: at iteration #25: temp = 0.000000, timing cost = 2277, wirelen = 40217
Info: at iteration #30: temp = 0.000000, timing cost = 2281, wirelen = 40188
Info: at iteration #31: temp = 0.000000, timing cost = 2277, wirelen = 40190
Info: SA placement time 8.83s
Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 69.13 MHz (FAIL at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 12.18 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 6.53 ns
Info: Slack histogram:
Info: legend: * represents 22 endpoint(s)
Info: + represents [1,22) endpoint(s)
Info: [ -1966, -1271) |**+
Info: [ -1271, -576) |+
Info: [ -576, 119) |+
Info: [ 119, 814) |+
Info: [ 814, 1509) |*+
Info: [ 1509, 2204) |*+
Info: [ 2204, 2899) |**+
Info: [ 2899, 3594) |************************
Info: [ 3594, 4289) |*****************************+
Info: [ 4289, 4984) |***********************************+
Info: [ 4984, 5679) |**************************************+
Info: [ 5679, 6374) |************************************************************
Info: [ 6374, 7069) |*********************************************************+
Info: [ 7069, 7764) |********************************************+
Info: [ 7764, 8459) |******************************+
Info: [ 8459, 9154) |*************************+
Info: [ 9154, 9849) |************************+
Info: [ 9849, 10544) |*******************************+
Info: [ 10544, 11239) |***************************************+
Info: [ 11239, 11934) |***************************+
Info: Checksum: 0xbb72b7df
Info: Routing globals...
Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
Info: Routing..
Info: Setting up routing queue.
Info: Routing 45569 arcs.
Info: | (re-)routed arcs | delta | remaining| time spent |
Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
Info: 1000 | 108 891 | 108 891 | 44727| 0.29 0.29|
Info: 2000 | 261 1738 | 153 847 | 43940| 0.10 0.38|
Info: 3000 | 393 2606 | 132 868 | 43201| 0.10 0.49|
Info: 4000 | 699 3300 | 306 694 | 42567| 0.12 0.60|
Info: 5000 | 1027 3972 | 328 672 | 41986| 0.12 0.73|
Info: 6000 | 1404 4595 | 377 623 | 41468| 0.13 0.86|
Info: 7000 | 1739 5260 | 335 665 | 40967| 0.12 0.98|
Info: 8000 | 1994 6005 | 255 745 | 40346| 0.10 1.08|
Info: 9000 | 2361 6638 | 367 633 | 39780| 0.11 1.19|
Info: 10000 | 2629 7370 | 268 732 | 39171| 0.15 1.35|
Info: 11000 | 2891 8108 | 262 738 | 38517| 0.13 1.47|
Info: 12000 | 3156 8843 | 265 735 | 37919| 0.12 1.60|
Info: 13000 | 3388 9611 | 232 768 | 37254| 0.12 1.72|
Info: 14000 | 3708 10291 | 320 680 | 36797| 0.13 1.85|
Info: 15000 | 4071 10928 | 363 637 | 36279| 0.14 1.99|
Info: 16000 | 4336 11663 | 265 735 | 35600| 0.13 2.12|
Info: 17000 | 4647 12352 | 311 689 | 35107| 0.12 2.24|
Info: 18000 | 5057 12942 | 410 590 | 34691| 0.16 2.40|
Info: 19000 | 5293 13706 | 236 764 | 34340| 0.12 2.52|
Info: 20000 | 5531 14468 | 238 762 | 33627| 0.11 2.63|
Info: 21000 | 5888 15111 | 357 643 | 33118| 0.16 2.79|
Info: 22000 | 6318 15681 | 430 570 | 32746| 0.14 2.94|
Info: 23000 | 6662 16337 | 344 656 | 32235| 0.15 3.08|
Info: 24000 | 6891 17108 | 229 771 | 31540| 0.11 3.20|
Info: 25000 | 7231 17768 | 340 660 | 31021| 0.21 3.41|
Info: 26000 | 7629 18370 | 398 602 | 30541| 0.18 3.59|
Info: 27000 | 8033 18966 | 404 596 | 30019| 0.17 3.76|
Info: 28000 | 8388 19611 | 355 645 | 29544| 0.12 3.88|
Info: 29000 | 8626 20373 | 238 762 | 28953| 0.13 4.01|
Info: 30000 | 8801 21130 | 175 757 | 28198| 0.10 4.11|
Info: 31000 | 9127 21687 | 326 557 | 27607| 0.14 4.24|
Info: 32000 | 9443 22269 | 316 582 | 27001| 0.13 4.38|
Info: 33000 | 9894 22771 | 451 502 | 26633| 0.13 4.51|
Info: 34000 | 10416 23210 | 522 439 | 26252| 0.14 4.65|
Info: 35000 | 10946 23659 | 530 449 | 25858| 0.11 4.76|
Info: 36000 | 11524 24067 | 578 408 | 25537| 0.13 4.90|
Info: 37000 | 12055 24535 | 531 468 | 25134| 0.13 5.03|
Info: 38000 | 12567 25022 | 512 487 | 24708| 0.16 5.19|
Info: 39000 | 13083 25502 | 516 480 | 24297| 0.15 5.34|
Info: 40000 | 13538 26036 | 455 534 | 23774| 0.12 5.46|
Info: 41000 | 13874 26696 | 336 660 | 23176| 0.14 5.60|
Info: 42000 | 14128 27421 | 254 725 | 22519| 0.15 5.76|
Info: 43000 | 14309 28210 | 181 789 | 21742| 0.13 5.88|
Info: 44000 | 14566 28906 | 257 696 | 21054| 0.13 6.01|
Info: 45000 | 14804 29637 | 238 731 | 20349| 0.13 6.14|
Info: 46000 | 15035 30347 | 231 710 | 19675| 0.14 6.28|
Info: 47000 | 15313 31029 | 278 682 | 19042| 0.13 6.40|
Info: 48000 | 15586 31729 | 273 700 | 18397| 0.12 6.53|
Info: 49000 | 15873 32414 | 287 685 | 18003| 0.14 6.67|
Info: 50000 | 16178 33075 | 305 661 | 17410| 0.14 6.81|
Info: 51000 | 16462 33760 | 284 685 | 16870| 0.18 6.99|
Info: 52000 | 16771 34412 | 309 652 | 16335| 0.15 7.13|
Info: 53000 | 17077 35059 | 306 647 | 15703| 0.19 7.33|
Info: 54000 | 17360 35747 | 283 688 | 15451| 0.14 7.46|
Info: 55000 | 17619 36460 | 259 713 | 14931| 0.12 7.58|
Info: 56000 | 17955 37085 | 336 625 | 14434| 0.21 7.80|
Info: 57000 | 18276 37748 | 321 663 | 13820| 0.14 7.93|
Info: 58000 | 18559 38414 | 283 666 | 13170| 0.13 8.06|
Info: 59000 | 18870 39084 | 311 670 | 12555| 0.18 8.25|
Info: 60000 | 19171 39757 | 301 673 | 11979| 0.15 8.40|
Info: 61000 | 19468 40427 | 297 670 | 11397| 0.17 8.57|
Info: 62000 | 19800 41041 | 332 614 | 10787| 0.20 8.77|
Info: 63000 | 20083 41724 | 283 683 | 10276| 0.17 8.94|
Info: 64000 | 20371 42401 | 288 677 | 9716| 0.22 9.15|
Info: 65000 | 20597 43113 | 226 712 | 9038| 0.14 9.29|
Info: 66000 | 20823 43869 | 226 756 | 8337| 0.13 9.43|
Info: 67000 | 21071 44604 | 248 735 | 7888| 0.21 9.63|
Info: 68000 | 21287 45342 | 216 738 | 7176| 0.14 9.77|
Info: 69000 | 21518 46007 | 231 665 | 6497| 0.15 9.92|
Info: 70000 | 21681 46782 | 163 775 | 5677| 0.13 10.06|
Info: 71000 | 21955 47470 | 274 688 | 5083| 0.20 10.26|
Info: 72000 | 22208 48217 | 253 747 | 4602| 0.16 10.42|
Info: 73000 | 22520 48905 | 312 688 | 4221| 0.20 10.61|
Info: 74000 | 22834 49566 | 314 661 | 3633| 0.24 10.86|
Info: 75000 | 23168 50211 | 334 645 | 3379| 0.25 11.11|
Info: 76000 | 23381 50951 | 213 740 | 2781| 0.29 11.40|
Info: 77000 | 23627 51671 | 246 720 | 2222| 0.30 11.70|
Info: 78000 | 23907 52384 | 280 713 | 2220| 0.51 12.21|
Info: 79000 | 24128 53135 | 221 751 | 1810| 0.48 12.69|
Info: 80000 | 24416 53816 | 288 681 | 1228| 0.64 13.34|
Info: 81000 | 24735 54479 | 319 663 | 888| 0.86 14.19|
Info: 82000 | 25041 55147 | 306 668 | 392| 1.46 15.65|
Info: 83000 | 25389 55773 | 348 626 | 30| 1.86 17.50|
Info: 83072 | 25416 55819 | 27 46 | 0| 0.16 17.66|
Info: Routing complete.
Info: Router1 time 17.66s
Info: Checksum: 0x08684ecd
Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_neuron_memory.u_neuron.group_index_TRELLIS_FF_Q_1.Q
Info: routing 1.22 1.62 Net u_neuron_memory.neuron_start_LUT4_C_Z_LUT4_Z_D[1] (68,21) -> (61,25)
Info: Sink u_neuron_memory.u_neuron.u_mac8.x_bus_PFUMX_Z_52_C0_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 1.80 Source u_neuron_memory.u_neuron.u_mac8.x_bus_PFUMX_Z_52_C0_LUT4_Z.F
Info: routing 1.18 2.97 Net u_neuron_memory.u_neuron.u_mac8.x_bus_PFUMX_Z_52_C0[4] (61,25) -> (56,21)
Info: Sink u_neuron_memory.u_neuron.u_mac8.x_bus_PFUMX_Z_52_BLUT_LUT4_Z.M
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.19 3.17 Source u_neuron_memory.u_neuron.u_mac8.x_bus_PFUMX_Z_52_BLUT_LUT4_Z.OFX
Info: routing 0.99 4.16 Net u_neuron_memory.u_neuron.x_group[55] (56,21) -> (56,22)
Info: Sink u_neuron_memory.u_neuron.u_mac8.GEN_MAC[6].u_mac.product_MULT18X18D_P9.A15
Info: Defined in:
Info: rtl/neuron_parallel.v:103.43-103.50
Info: logic 3.07 7.22 Source u_neuron_memory.u_neuron.u_mac8.GEN_MAC[6].u_mac.product_MULT18X18D_P9.P3
Info: routing 1.58 8.80 Net u_neuron_memory.u_neuron.u_mac8.products[6][3] (56,22) -> (62,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_1$CCU2_COMB1.B
Info: Defined in:
Info: rtl/mac8.v:73.9-73.13
Info: logic 0.35 9.16 Source u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_1$CCU2_COMB1.FCO
Info: routing 0.00 9.16 Net u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_S1_CCU2C_S1_1_COUT (62,23) -> (62,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_1$CCU2_COMB0.FCI
Info: Defined in:
Info: rtl/mac8.v:101.21-102.44
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 9.21 Source u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_1$CCU2_COMB0.FCO
Info: routing 0.00 9.21 Net u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_1$CCU2_FCI_INT (62,23) -> (62,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_1$CCU2_COMB1.FCI
Info: logic 0.29 9.51 Source u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1_CCU2C_S1_1$CCU2_COMB1.F
Info: routing 0.69 10.19 Net u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S1[1] (62,23) -> (63,25)
Info: Sink u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_Z.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 10.37 Source u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_Z.F
Info: routing 0.84 11.21 Net u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0[4] (63,25) -> (65,26)
Info: Sink u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 11.39 Source u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0_LUT4_Z.F
Info: routing 0.48 11.87 Net u_neuron_memory.u_neuron.acc_next_LUT4_Z_D_CCU2C_S0_COUT_CCU2C_CIN_COUT_CCU2C_CIN_COUT_CCU2C_CIN_S0[3] (65,26) -> (65,26)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_5_A0_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 12.05 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_5_A0_LUT4_Z.F
Info: routing 1.08 13.13 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_5_A0 (65,26) -> (67,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_5$CCU2_COMB0.A
Info: logic 0.35 13.48 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_5$CCU2_COMB0.FCO
Info: routing 0.00 13.48 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_5$CCU2_FCI_INT (67,23) -> (67,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_5$CCU2_COMB1.FCI
Info: logic 0.00 13.48 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_5$CCU2_COMB1.FCO
Info: routing 0.00 13.48 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_5_COUT (67,23) -> (67,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_6$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 13.54 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_6$CCU2_COMB0.FCO
Info: routing 0.00 13.54 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_6$CCU2_FCI_INT (67,23) -> (67,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_6$CCU2_COMB1.FCI
Info: logic 0.00 13.54 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_6$CCU2_COMB1.FCO
Info: routing 0.00 13.54 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_6_COUT (67,23) -> (67,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 13.60 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB0.FCO
Info: routing 0.00 13.60 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_1$CCU2_FCI_INT (67,23) -> (67,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB1.FCI
Info: logic 0.00 13.60 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_1$CCU2_COMB1.FCO
Info: routing 0.00 13.60 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_1_COUT (67,23) -> (67,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 13.65 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB0.FCO
Info: routing 0.00 13.65 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_10$CCU2_FCI_INT (67,23) -> (67,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB1.FCI
Info: logic 0.00 13.65 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_10$CCU2_COMB1.FCO
Info: routing 0.00 13.65 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_10_COUT (67,23) -> (68,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_15$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 13.71 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_15$CCU2_COMB0.FCO
Info: routing 0.00 13.71 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_15$CCU2_FCI_INT (68,23) -> (68,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_15$CCU2_COMB1.FCI
Info: logic 0.00 13.71 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_15$CCU2_COMB1.FCO
Info: routing 0.00 13.71 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_15_COUT (68,23) -> (68,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_9$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 13.76 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_9$CCU2_COMB0.FCO
Info: routing 0.00 13.76 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_9$CCU2_FCI_INT (68,23) -> (68,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_9$CCU2_COMB1.FCI
Info: logic 0.00 13.76 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_9$CCU2_COMB1.FCO
Info: routing 0.00 13.76 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_9_COUT (68,23) -> (68,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_7$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 13.82 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_7$CCU2_COMB0.FCO
Info: routing 0.00 13.82 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_7$CCU2_FCI_INT (68,23) -> (68,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_7$CCU2_COMB1.FCI
Info: logic 0.00 13.82 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_7$CCU2_COMB1.FCO
Info: routing 0.00 13.82 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_7_COUT (68,23) -> (68,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 13.88 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB0.FCO
Info: routing 0.00 13.88 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_12$CCU2_FCI_INT (68,23) -> (68,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB1.FCI
Info: logic 0.00 13.88 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_12$CCU2_COMB1.FCO
Info: routing 0.00 13.88 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_12_COUT (68,23) -> (69,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 13.93 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB0.FCO
Info: routing 0.00 13.93 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_13$CCU2_FCI_INT (69,23) -> (69,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB1.FCI
Info: logic 0.00 13.93 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_13$CCU2_COMB1.FCO
Info: routing 0.00 13.93 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_13_COUT (69,23) -> (69,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_8$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 13.99 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_8$CCU2_COMB0.FCO
Info: routing 0.00 13.99 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_8$CCU2_FCI_INT (69,23) -> (69,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_8$CCU2_COMB1.FCI
Info: logic 0.00 13.99 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_8$CCU2_COMB1.FCO
Info: routing 0.00 13.99 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_8_COUT (69,23) -> (69,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_11$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 14.04 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_11$CCU2_COMB0.FCO
Info: routing 0.00 14.04 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_11$CCU2_FCI_INT (69,23) -> (69,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_11$CCU2_COMB1.FCI
Info: logic 0.00 14.04 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_11$CCU2_COMB1.FCO
Info: routing 0.00 14.04 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_11_COUT (69,23) -> (69,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 14.10 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB0.FCO
Info: routing 0.00 14.10 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_14$CCU2_FCI_INT (69,23) -> (69,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB1.FCI
Info: logic 0.00 14.10 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1_14$CCU2_COMB1.FCO
Info: routing 0.00 14.10 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1_14_COUT (69,23) -> (70,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1$CCU2_COMB0.FCI
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4
Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13
Info: logic 0.06 14.16 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1$CCU2_COMB0.FCO
Info: routing 0.00 14.16 Net u_neuron_memory.u_neuron.acc_next_CCU2C_S1$CCU2_FCI_INT (70,23) -> (70,23)
Info: Sink u_neuron_memory.u_neuron.acc_next_CCU2C_S1$CCU2_COMB1.FCI
Info: logic 0.29 14.45 Source u_neuron_memory.u_neuron.acc_next_CCU2C_S1$CCU2_COMB1.F
Info: routing 0.12 14.57 Net u_neuron_memory.u_neuron.acc_next[31] (70,23) -> (70,23)
Info: Sink u_neuron_memory.u_neuron.acc_TRELLIS_FF_Q_30.DI
Info: Defined in:
Info: rtl/mac8.v:9.35-9.42
Info: setup 0.00 14.57 Source u_neuron_memory.u_neuron.acc_TRELLIS_FF_Q_30.DI
Info: 6.40 ns logic, 8.17 ns routing
Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
Info: type curr total name
Info: source 0.00 0.00 Source rst$tr_io.O
Info: routing 4.46 4.46 Net rst$TRELLIS_IO_IN (0,14) -> (63,9)
Info: Sink u_flash_slot_manager.crc_active_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_D_C_LUT4_D_Z_LUT4_Z.B
Info: Defined in:
Info: rtl/spi_slave.v:23.16-23.19
Info: logic 0.18 4.64 Source u_flash_slot_manager.crc_active_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_D_C_LUT4_D_Z_LUT4_Z.F
Info: routing 0.78 5.42 Net u_flash_slot_manager.cat_valid[9]_TRELLIS_FF_Q_DI_LUT4_Z_B[2] (63,9) -> (56,8)
Info: Sink u_spi_engine.flash_op_start_LUT4_B_1_Z_LUT4_B_1_C_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 5.60 Source u_spi_engine.flash_op_start_LUT4_B_1_Z_LUT4_B_1_C_LUT4_Z.F
Info: routing 0.47 6.07 Net u_spi_engine.flash_op_start_LUT4_B_1_Z_LUT4_B_1_C[2] (56,8) -> (55,8)
Info: Sink u_spi_engine.flash_op_start_LUT4_B_1_Z_LUT4_B_1_D_LUT4_D_Z_LUT4_Z.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.25 Source u_spi_engine.flash_op_start_LUT4_B_1_Z_LUT4_B_1_D_LUT4_D_Z_LUT4_Z.F
Info: routing 0.49 6.74 Net u_flash_slot_manager.active_slot_LUT4_B_1_Z_LUT4_D_Z_LUT4_D_C_LUT4_C_1_D[1] (55,8) -> (55,8)
Info: Sink u_flash_slot_manager.active_slot_LUT4_B_1_Z_LUT4_D_Z_LUT4_C_2_D_LUT4_Z.C
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 6.92 Source u_flash_slot_manager.active_slot_LUT4_B_1_Z_LUT4_D_Z_LUT4_C_2_D_LUT4_Z.F
Info: routing 0.88 7.80 Net u_flash_slot_manager.active_slot_LUT4_B_1_Z_LUT4_D_Z_LUT4_C_2_D[2] (55,8) -> (54,9)
Info: Sink u_flash_slot_manager.active_slot_LUT4_B_1_Z_LUT4_D_Z_LUT4_C_2_D_LUT4_D_1.D
Info: Defined in:
Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
Info: logic 0.18 7.97 Source u_flash_slot_manager.active_slot_LUT4_B_1_Z_LUT4_D_Z_LUT4_C_2_D_LUT4_D_1.F
Info: routing 2.19 10.16 Net u_flash_slot_manager.active_slot_LUT4_B_1_Z_LUT4_D_Z_LUT4_C_2_D_LUT4_D_1_Z (54,9) -> (44,25)
Info: Sink u_flash_slot_manager.cat_crc[11]_TRELLIS_FF_Q_30.CE
Info: setup 0.00 10.16 Source u_flash_slot_manager.cat_crc[11]_TRELLIS_FF_Q_30.CE
Info: 0.90 ns logic, 9.26 ns routing
Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
Info: type curr total name
Info: clk-to-q 0.40 0.40 Source u_spi_engine.status_done_sticky_TRELLIS_FF_Q.Q
Info: routing 2.18 2.58 Net data_ready (64,13) -> (25,17)
Info: Sink data_ready_n_LUT4_Z.D
Info: Defined in:
Info: rtl/spi_engine.v:321.9-321.27
Info: logic 0.18 2.76 Source data_ready_n_LUT4_Z.F
Info: routing 1.44 4.19 Net data_ready_n$TRELLIS_IO_OUT (25,17) -> (0,17)
Info: Sink data_ready_n$tr_io.I
Info: Defined in:
Info: rtl/spi_neuron_top.v:68.17-68.29
Info: 0.57 ns logic, 3.62 ns routing
ERROR: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 68.65 MHz (FAIL at 80.00 MHz)
Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 10.16 ns
Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.19 ns
Info: Slack histogram:
Info: legend: * represents 22 endpoint(s)
Info: + represents [1,22) endpoint(s)
Info: [ -2067, -1373) |*+
Info: [ -1373, -679) |+
Info: [ -679, 15) |+
Info: [ 15, 709) |+
Info: [ 709, 1403) |+
Info: [ 1403, 2097) |+
Info: [ 2097, 2791) |+
Info: [ 2791, 3485) |*+
Info: [ 3485, 4179) |**+
Info: [ 4179, 4873) |*******************************+
Info: [ 4873, 5567) |****************************+
Info: [ 5567, 6261) |*****************************************+
Info: [ 6261, 6955) |************************************************************
Info: [ 6955, 7649) |******************************************************+
Info: [ 7649, 8343) |*****************************************************+
Info: [ 8343, 9037) |******************************************+
Info: [ 9037, 9731) |**********************************+
Info: [ 9731, 10425) |****************************+
Info: [ 10425, 11119) |*********************************************+
Info: [ 11119, 11813) |**************************************+
0 warnings, 1 error
Info: Program finished normally.
synth/ecp5/post_fix_verify/top.config
-203698
View File
File diff suppressed because it is too large Load Diff
synth/ecp5/post_fix_verify/top.json
-473515
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File diff suppressed because it is too large Load Diff
synth/ecp5/post_fix_verify/yosys.log
-11392
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File diff suppressed because it is too large Load Diff