michele
cfd5e98a0e
tools/fpga_benchmark.py: parametric Yosys + nextpnr-ecp5 benchmark harness for the LFE5U-45F-8BG381 (speed grade -8, 80 MHz target), sweeping PARALLEL over the neuron layer and parsing Fmax/LUT4/DFF/DSP utilization out of the nextpnr report into JSON/CSV. synth/ecp5/p2, p4, p8: real synthesis+PnR results backing the same-price-tier FPGA comparison (P2: 87.88 MHz PASS, P4: 75.01 MHz FAIL, P8: 147.62 MHz PASS -- non-monotonic, dominated by placement noise since the whole design uses <2% of the device's LUT4 fabric at every setting, and P8 notably maps to 0 DSP blocks vs 8/16 for P2/P4). synth/ecp5/top.v: benchmark harness top-level, reworked to generate deterministic non-constant X/weights/bias via `keep`-attributed generate blocks so Yosys can't constant-fold the datapath away. Also adds .gitignore for Python's __pycache__/*.pyc.
79 lines
1.8 KiB
Verilog
79 lines
1.8 KiB
Verilog
module top (
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input clk,
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input rst,
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input start,
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output signed [31:0] y_bus,
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output busy,
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output done
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);
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localparam DATA_WIDTH = 8;
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localparam N_INPUTS = 256;
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localparam N_NEURONS = 4;
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localparam PARALLEL = 4;
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localparam ACC_WIDTH = 32;
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reg signed [DATA_WIDTH*N_INPUTS-1:0] x_bus;
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reg signed [DATA_WIDTH*N_INPUTS*N_NEURONS-1:0] weights_bus;
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reg signed [DATA_WIDTH*N_NEURONS-1:0] bias_bus;
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integer i;
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initial begin
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x_bus = 0;
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weights_bus = 0;
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bias_bus = 0;
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// X = 1
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for (i = 0; i < N_INPUTS; i = i + 1)
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x_bus[i*DATA_WIDTH +: DATA_WIDTH] = 8'sd1;
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// Neuron 0: first 32 weights = +1
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for (i = 0; i < 32; i = i + 1)
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weights_bus[
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0*N_INPUTS*DATA_WIDTH +
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i*DATA_WIDTH +:
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DATA_WIDTH
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] = 8'sd1;
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// Neuron 1: all zero, bias = 10
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bias_bus[1*DATA_WIDTH +: DATA_WIDTH] = 8'sd10;
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// Neuron 2: all weights = -1
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for (i = 0; i < N_INPUTS; i = i + 1)
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weights_bus[
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2*N_INPUTS*DATA_WIDTH +
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i*DATA_WIDTH +:
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DATA_WIDTH
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] = -8'sd1;
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// Neuron 3: first 32 weights = +4
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for (i = 0; i < 32; i = i + 1)
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weights_bus[
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3*N_INPUTS*DATA_WIDTH +
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i*DATA_WIDTH +:
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DATA_WIDTH
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] = 8'sd4;
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end
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layer #(
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.DATA_WIDTH(DATA_WIDTH),
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.N_INPUTS(N_INPUTS),
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.N_NEURONS(N_NEURONS),
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.PARALLEL(PARALLEL),
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.ACC_WIDTH(ACC_WIDTH)
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) u_layer (
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.clk(clk),
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.rst(rst),
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.start(start),
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.x_bus(x_bus),
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.weights_bus(weights_bus),
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.bias_bus(bias_bus),
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.y_bus(y_bus),
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.busy(busy),
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.done(done)
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);
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endmodule
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