feat(v2): M7 Dataflow Core - full M1-M6 integration, wake-up loop closed end-to-end
dataflow_core.v integrates dependency_manager (M6) -> neural_director (M5) -> N_SLOTS x (memory_manager (M4) + neural_processor (M1)) for the first time. A slot's completion (via neural_director's new slot_node_id tracking, an additive port) feeds back as a producer_done event to dependency_manager, waking up any node that depended on it - closing the dataflow loop without external glue. Verified end-to-end (Verilator) on a 3-node DAG: two independent nodes plus a third depending on both, confirmed to dispatch only after both genuinely complete via real neural_processor computation. 4/4 PASS. Real synthesis + nextpnr-ecp5 P&R via a synthesis-only timing harness (bare per-slot backend ports exceed the LFE5U-45F's TRELLIS_IO budget, same pattern as ERR-0005): N_SLOTS=2 -> 165.15 MHz, N_SLOTS=4 -> 133.19 MHz, both PASS at 80MHz, 0 synthesis problems. Scope explicitly deferred to M8 (DEC-0009): M3's BRAM buffers not wired in yet, per-slot Memory Backend Interface ports not arbitrated to one shared PSRAM master yet - both need real measured data before committing to a design, not guessed at here. Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0009)/ experiments (EXP-0008)/errors (ERR-0007, a Yosys chparam-ordering build quirk, not an RTL bug)/development.log, ROADMAP.md updated. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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Claude Sonnet 5
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// ================================================================
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// SYNTHESIS-ONLY TIMING HARNESS -- NOT a functional deliverable.
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// Same rationale/pattern as harness_neural_processor_array.v and
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// harness_memory_manager.v (see their headers, and
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// hardware/v2/logs/errors.log ERR-0005): dataflow_core's own ports
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// (per-slot mem_addr/wdata/rdata buses, node registration fields)
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// exceed the LFE5U-45F's ~245 TRELLIS_IO budget as a bare top-level
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// module well before N_SLOTS=2 (measured: N_SLOTS=4 alone needs 280
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// bits just for the per-slot Memory Backend Interface arrays).
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//
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// dataflow_core.v additionally instantiates N_SLOTS REAL copies of
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// (memory_manager + neural_processor) via `generate` -- exactly the
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// same CSE risk already hit and fixed once in
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// harness_neural_processor_array.v (giving every instance IDENTICAL
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// LFSR data lets Yosys collapse all N_SLOTS copies down to 1). This
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// harness reuses that fix: each slot's mem_rdata/mem_ready input gets
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// its own distinct bit-rotated LFSR slice, and the checksum folds in
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// a real bit from EVERY slot's own outputs, not just slot 0's.
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//
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// Only clk/rst/seed/checksum are exposed as real top-level pins.
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// ================================================================
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module harness_dataflow_core #(
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parameter DATA_WIDTH = 8,
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parameter P_IN = 8,
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parameter ACC_WIDTH = 32,
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parameter ADDR_WIDTH = 23,
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parameter N_SLOTS = 4,
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parameter N_NODES = 16,
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parameter MAX_DEPS = 4,
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parameter QUEUE_DEPTH = 8
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)(
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input wire clk,
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input wire rst,
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input wire [7:0] seed,
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output wire [7:0] checksum
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);
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localparam NODE_IDW = $clog2(N_NODES);
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reg [31:0] lfsr;
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always @(posedge clk) begin
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if (rst) lfsr <= {24'h0, seed} | 32'h1;
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else lfsr <= {lfsr[30:0], lfsr[31] ^ lfsr[21] ^ lfsr[1] ^ lfsr[0]};
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end
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// ---- node-registration side: a single port, no per-instance
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// CSE risk -- plain LFSR slices are enough. ----
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wire reg_valid = lfsr[0];
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wire [NODE_IDW-1:0] reg_node_id = lfsr[NODE_IDW-1:0];
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wire [$clog2(MAX_DEPS+1)-1:0] reg_required = lfsr[$clog2(MAX_DEPS+1)-1:0];
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wire [MAX_DEPS*NODE_IDW-1:0] reg_producer_ids;
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wire [ADDR_WIDTH-1:0] reg_x_base = lfsr[ADDR_WIDTH-1:0];
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wire [ADDR_WIDTH-1:0] reg_w_base = {lfsr[3:0], lfsr[ADDR_WIDTH-5:0]};
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wire [15:0] reg_n_tiles = lfsr[15:0];
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wire [ADDR_WIDTH-1:0] reg_result_addr = {lfsr[6:0], lfsr[ADDR_WIDTH-8:0]};
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genvar pgi;
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generate
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for (pgi = 0; pgi < MAX_DEPS; pgi = pgi + 1) begin : GEN_PID
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wire [31:0] prot = {lfsr[pgi:0], lfsr[31:pgi+1]};
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assign reg_producer_ids[pgi*NODE_IDW +: NODE_IDW] = prot[NODE_IDW-1:0];
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end
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endgenerate
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// ---- per-slot Memory Backend Interface inputs: EACH slot needs
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// a DISTINCT rotated slice (see file header) so the N_SLOTS
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// memory_manager+neural_processor pairs stay N_SLOTS real,
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// distinguishable instances instead of collapsing to 1. ----
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wire signed [8*N_SLOTS-1:0] slot_mem_rdata;
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wire [N_SLOTS-1:0] slot_mem_ready;
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genvar sgi;
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generate
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for (sgi = 0; sgi < N_SLOTS; sgi = sgi + 1) begin : GEN_SLOT_DRIVE
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wire [31:0] srot = {lfsr[sgi:0], lfsr[31:sgi+1]};
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assign slot_mem_rdata[sgi*8 +: 8] = srot[7:0];
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assign slot_mem_ready[sgi] = srot[8];
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end
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endgenerate
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wire reg_ready;
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wire [N_SLOTS-1:0] slot_mem_req, slot_mem_wr;
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wire [ADDR_WIDTH*N_SLOTS-1:0] slot_mem_addr;
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wire signed [8*N_SLOTS-1:0] slot_mem_wdata;
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dataflow_core #(
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.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH), .ADDR_WIDTH(ADDR_WIDTH),
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.N_SLOTS(N_SLOTS), .N_NODES(N_NODES), .MAX_DEPS(MAX_DEPS), .QUEUE_DEPTH(QUEUE_DEPTH)
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) dut (
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.clk(clk), .rst(rst),
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.reg_valid(reg_valid), .reg_ready(reg_ready), .reg_node_id(reg_node_id),
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.reg_required(reg_required), .reg_producer_ids(reg_producer_ids),
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.reg_x_base(reg_x_base), .reg_w_base(reg_w_base), .reg_n_tiles(reg_n_tiles),
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.reg_result_addr(reg_result_addr),
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.slot_mem_req(slot_mem_req), .slot_mem_wr(slot_mem_wr), .slot_mem_addr(slot_mem_addr),
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.slot_mem_wdata(slot_mem_wdata), .slot_mem_rdata(slot_mem_rdata), .slot_mem_ready(slot_mem_ready)
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);
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// Fold in a real bit from EVERY slot's own outputs (not just slot
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// 0's) -- otherwise all slots but one have no observable output
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// path and Yosys correctly strips them as dead logic.
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wire [N_SLOTS-1:0] addr_lsb, wdata_lsb;
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generate
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for (sgi = 0; sgi < N_SLOTS; sgi = sgi + 1) begin : GEN_CHK_LANE
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assign addr_lsb[sgi] = slot_mem_addr[sgi*ADDR_WIDTH];
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assign wdata_lsb[sgi] = slot_mem_wdata[sgi*8];
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end
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endgenerate
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reg [7:0] chk;
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always @(posedge clk) begin
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if (rst) chk <= 8'h0;
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else chk <= chk ^ {7'h0, reg_ready} ^ slot_mem_req ^ slot_mem_wr
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^ addr_lsb ^ wdata_lsb;
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end
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assign checksum = chk;
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endmodule
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