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feat(v2): M7 Dataflow Core - full M1-M6 integration, wake-up loop closed end-to-end

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dataflow_core.v integrates dependency_manager (M6) -> neural_director
(M5) -> N_SLOTS x (memory_manager (M4) + neural_processor (M1)) for
the first time. A slot's completion (via neural_director's new
slot_node_id tracking, an additive port) feeds back as a
producer_done event to dependency_manager, waking up any node that
depended on it - closing the dataflow loop without external glue.

Verified end-to-end (Verilator) on a 3-node DAG: two independent
nodes plus a third depending on both, confirmed to dispatch only
after both genuinely complete via real neural_processor computation.
4/4 PASS.

Real synthesis + nextpnr-ecp5 P&R via a synthesis-only timing harness
(bare per-slot backend ports exceed the LFE5U-45F's TRELLIS_IO
budget, same pattern as ERR-0005): N_SLOTS=2 -> 165.15 MHz,
N_SLOTS=4 -> 133.19 MHz, both PASS at 80MHz, 0 synthesis problems.

Scope explicitly deferred to M8 (DEC-0009): M3's BRAM buffers not
wired in yet, per-slot Memory Backend Interface ports not arbitrated
to one shared PSRAM master yet - both need real measured data before
committing to a design, not guessed at here.

Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0009)/
experiments (EXP-0008)/errors (ERR-0007, a Yosys chparam-ordering
build quirk, not an RTL bug)/development.log, ROADMAP.md updated.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 15:05:28 +02:00
co-authored by Claude Sonnet 5
parent 8af16d3a12
commit 77baa8fc16
13 changed files with 798 additions and 1 deletions
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hardware/v2/logs/simulation.log
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@@ -60,3 +60,18 @@ test: 4 cases on a 4-node DAG (2 independent + 1 dual-dependency +
1 single-dependency-shared-producer)
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: 4/4 PASS
[2026-09-05] EXP-0008 -- hardware/v2/sim/tb_dataflow_core.v
test: full end-to-end M1-M6 integration through dataflow_core.v (M7),
a 3-node DAG (node0/node1 independent, node2 depends on BOTH) run
through the REAL dependency_manager -> neural_director -> N_SLOTS x
(memory_manager + neural_processor) chain for the first time, each
slot backed by its own independent behavioral byte memory
simulator: Verilator 5.050 (--binary --timing)
PASS/FAIL: 4/4 PASS -- node0=48, node1=8 (both real neural_processor
computations via the full stack), node2=40 dispatched only after
BOTH node0 and node1 genuinely completed (continuously polled every
cycle up to completion, not just checked at the end) -- the
dependency-manager-to-director wake-up loop closes correctly
end-to-end with real hardware in between, not just in isolation
(M6's own testbench already proved the wake-up logic alone)