feat(v2): M7 Dataflow Core - full M1-M6 integration, wake-up loop closed end-to-end

dataflow_core.v integrates dependency_manager (M6) -> neural_director
(M5) -> N_SLOTS x (memory_manager (M4) + neural_processor (M1)) for
the first time. A slot's completion (via neural_director's new
slot_node_id tracking, an additive port) feeds back as a
producer_done event to dependency_manager, waking up any node that
depended on it - closing the dataflow loop without external glue.

Verified end-to-end (Verilator) on a 3-node DAG: two independent
nodes plus a third depending on both, confirmed to dispatch only
after both genuinely complete via real neural_processor computation.
4/4 PASS.

Real synthesis + nextpnr-ecp5 P&R via a synthesis-only timing harness
(bare per-slot backend ports exceed the LFE5U-45F's TRELLIS_IO
budget, same pattern as ERR-0005): N_SLOTS=2 -> 165.15 MHz,
N_SLOTS=4 -> 133.19 MHz, both PASS at 80MHz, 0 synthesis problems.

Scope explicitly deferred to M8 (DEC-0009): M3's BRAM buffers not
wired in yet, per-slot Memory Backend Interface ports not arbitrated
to one shared PSRAM master yet - both need real measured data before
committing to a design, not guessed at here.

Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0009)/
experiments (EXP-0008)/errors (ERR-0007, a Yosys chparam-ordering
build quirk, not an RTL bug)/development.log, ROADMAP.md updated.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/logs/experiments.log

@@ -365,3 +365,39 @@ decision: see decisions.log DEC-0008 (no value forwarding yet, no
 next_action: M7 -- dataflow_core.v, integrating Director + Dependency
   Manager + Memory Manager + Processor Array + Buffers into one top-
   level module for the first time.
+
+[2026-09-05] EXP-0008 -- hardware/v2/rtl/dataflow_core.v (M7, full
+M1-M6 integration)
+test: hardware/v2/sim/tb_dataflow_core.v -- a 3-node DAG (node0/node1
+  independent, node2 depends on BOTH) run through the REAL
+  dependency_manager -> neural_director -> N_SLOTS x (memory_manager +
+  neural_processor) chain end-to-end for the first time, each slot
+  backed by its own independent behavioral byte memory (shared real
+  PSRAM arbitration explicitly deferred to M8, decisions.log DEC-0009)
+simulator: Verilator 5.050 (--binary --timing)
+PASS/FAIL:
+  SIMULATED: 4/4 PASS -- node0=48, node1=8 (correct real
+    neural_processor computations via the full stack), node2=40
+    dispatched only after BOTH node0 and node1 genuinely completed
+    (continuously polled every cycle, not just checked at the end).
+  SYNTHESIZED (via harness_dataflow_core.v -- see errors.log ERR-0005):
+    N_SLOTS=2: 0 CHECK problems, LUT4=2127, CCU2C=248, TRELLIS_FF=2505,
+      MULT18X18D=16, DP16KD=0.
+    N_SLOTS=4: 0 CHECK problems, LUT4=3953, CCU2C=500, TRELLIS_FF=4688,
+      MULT18X18D=32, DP16KD=0.
+  POST-P&R (real, harness-based): N_SLOTS=2 Fmax=165.15 MHz,
+    N_SLOTS=4 Fmax=133.19 MHz -- both PASS at 80MHz.
+errors: one Yosys build-script usage quirk (chparam ordering against
+  a non-top module vs synth_ecp5's own internal re-hierarchy pass) --
+  see errors.log ERR-0007. Not an RTL bug; no dataflow_core.v or
+  harness_dataflow_core.v source change needed, only the build command
+  itself.
+decision: see decisions.log DEC-0009 (no M3 buffers wired in yet, no
+  shared-PSRAM arbitration across slots yet -- both explicitly
+  deferred to M8/a future measurement-driven decision, not missing by
+  oversight).
+next_action: M8 -- PSRAM integration. Wire the real (unmodified) V1
+  PSRAM backend chain (int8_memory_access -> memory_interface ->
+  psram_controller) end-to-end through dataflow_core, and design/
+  measure whatever N_SLOTS>1 arbitration across ONE physical PSRAM
+  port actually requires.