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feat(v2): M7 Dataflow Core - full M1-M6 integration, wake-up loop closed end-to-end

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dataflow_core.v integrates dependency_manager (M6) -> neural_director
(M5) -> N_SLOTS x (memory_manager (M4) + neural_processor (M1)) for
the first time. A slot's completion (via neural_director's new
slot_node_id tracking, an additive port) feeds back as a
producer_done event to dependency_manager, waking up any node that
depended on it - closing the dataflow loop without external glue.

Verified end-to-end (Verilator) on a 3-node DAG: two independent
nodes plus a third depending on both, confirmed to dispatch only
after both genuinely complete via real neural_processor computation.
4/4 PASS.

Real synthesis + nextpnr-ecp5 P&R via a synthesis-only timing harness
(bare per-slot backend ports exceed the LFE5U-45F's TRELLIS_IO
budget, same pattern as ERR-0005): N_SLOTS=2 -> 165.15 MHz,
N_SLOTS=4 -> 133.19 MHz, both PASS at 80MHz, 0 synthesis problems.

Scope explicitly deferred to M8 (DEC-0009): M3's BRAM buffers not
wired in yet, per-slot Memory Backend Interface ports not arbitrated
to one shared PSRAM master yet - both need real measured data before
committing to a design, not guessed at here.

Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0009)/
experiments (EXP-0008)/errors (ERR-0007, a Yosys chparam-ordering
build quirk, not an RTL bug)/development.log, ROADMAP.md updated.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 15:05:28 +02:00
co-authored by Claude Sonnet 5
parent 8af16d3a12
commit 77baa8fc16
13 changed files with 798 additions and 1 deletions
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@@ -36,7 +36,16 @@ reali, non solo scritto).
PASS (dipendenze multiple + produttore condiviso/piu' consumer).
Fmax 155.30 MHz. Forwarding di valori e riuso slot rimandati
(`logs/decisions.log` DEC-0008).
- [ ] **M7 — Dataflow Core** (`dataflow_core.v`), integrazione completa.
- [x] **M7 — Dataflow Core** (`dataflow_core.v`), prima integrazione
completa: Dependency Manager (M6) -> Neural Director (M5) ->
N_SLOTS x (Memory Manager (M4) + Neural Processor (M1)), loop di
wake-up chiuso end-to-end. 4/4 test PASS su un DAG a 3 nodi (node2
dipende da entrambi node0+node1, dispatch confermato solo dopo che
ENTRAMBI completano davvero). Sintesi reale 0 problemi a
N_SLOTS=2 e N_SLOTS=4. Fmax reale (harness): 165.15 MHz
(N_SLOTS=2), 133.19 MHz (N_SLOTS=4). Buffer M3 e arbitraggio PSRAM
condiviso rimandati esplicitamente a M8 (`logs/decisions.log`
DEC-0009).
- [ ] **M8 — PSRAM integration**, controller V1 non modificato, misura reale.
- [ ] **M9 — Full benchmark**, tabella V1 vs V2 (§32 del mandato).
- [ ] **M10 — Optimization**, solo sulla base dei dati raccolti in M1-M9.