feat(v2): M8 PSRAM integration - real V1 backend shared across concurrent slots

neural_multiprocessor.v wraps dataflow_core.v (M7, unmodified) around
the real, unmodified V1 PSRAM backend chain (int8_memory_access ->
memory_interface -> psram_controller), funneling N_SLOTS independent
Memory Backend Interface ports through a new generic N-port arbiter
(slot_mem_arbiter.v) inspired by (not copied from) V1's own
mem_arbiter.v.

Real concurrent-slot simulation immediately surfaced a genuine bug
(ERR-0008): memory_manager/prefetch_engine's byte-level backend
protocol is fire-and-forget (a single-cycle mem_req pulse with no
accept handshake) - correct for M4's direct 1:1 connection, but a
naive arbiter silently drops a pulse arriving while the shared bus is
owned by another slot, hanging that slot forever. Fixed with a
per-port pending-request latch, the same "queue, don't drop" idiom
already used by memory_manager's own pf_pending register (ERR-0006).

Verified (Verilator): 4/4 PASS with 2 slots genuinely contending for
one real PSRAM port (444 cycles). No regression on M4's own
testbench. Real synthesis + nextpnr-ecp5 P&R (no harness needed - real
PSRAM pins keep the top-level at 157 pins): 0 problems, Fmax 142.45
MHz, PASS at 80MHz.

Arbitration policy is fixed lowest-index priority, not fairness-
balanced (DEC-0010) - consistent with every other "simplest correct
policy first" scheduling choice in this roadmap, revisited only if
M9's real measurement shows starvation matters.

Logged: simulation/synthesis/timing/benchmark/decisions (DEC-0010)/
experiments (EXP-0009)/errors (ERR-0008)/development.log, ROADMAP.md
updated.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/docs/ROADMAP.md

@@ -46,7 +46,18 @@ reali, non solo scritto).
       (N_SLOTS=2), 133.19 MHz (N_SLOTS=4). Buffer M3 e arbitraggio PSRAM
       condiviso rimandati esplicitamente a M8 (`logs/decisions.log`
       DEC-0009).
-- [ ] **M8 — PSRAM integration**, controller V1 non modificato, misura reale.
+- [x] **M8 — PSRAM integration** (`neural_multiprocessor.v`,
+      `slot_mem_arbiter.v`), controller V1 riusato SENZA MODIFICHE,
+      condiviso tra N_SLOTS memory_manager concorrenti reali. Trovato e
+      risolto un bug RTL reale: il primo arbitro perdeva silenziosamente
+      una richiesta arrivata durante la contesa (protocollo byte-level
+      "fire-and-forget", mai esposto da M4 che collega un solo master
+      direttamente) — vedi `logs/errors.log` ERR-0008. Dopo il fix: 4/4
+      test PASS (2 slot in vera contesa concorrente sulla stessa PSRAM
+      reale). Sintesi reale 0 problemi (nessun harness necessario — pin
+      reali PSRAM tengono il top-level a 157 pin). Fmax reale 142.45
+      MHz. Politica di arbitraggio a priorità fissa, non ancora fair
+      (`logs/decisions.log` DEC-0010).
 - [ ] **M9 — Full benchmark**, tabella V1 vs V2 (§32 del mandato).
 - [ ] **M10 — Optimization**, solo sulla base dei dati raccolti in M1-M9.