fix: neural_director_packed.v SV literal for synth; exonerate it from a testbench race (EXP-0073)

Replaced three uses of the SystemVerilog '0 self-sizing literal with
explicit-width zero-fill so the file synthesizes under Vivado's
synth_design (which has no -sv equivalent in this flow), needed while
adding this module to the real in-context P&R project.

Re-running its isolated regression after that edit surfaced 3/8
failures. Root-caused via git stash (reproduces on the untouched
committed file, not caused by this edit) and a DUT-internal $display:
tb_neural_director_packed.v's own submit_job task drove DUT inputs
with blocking assignment across two separate @(posedge clk) waits,
racing the DUT's own always block under Icarus and causing a spurious
duplicate enqueue. Fixed by switching to nonblocking assignment
(race-free by construction). neural_director_packed.v itself was
correct all along - 8/8 tests pass after the testbench fix.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

hardware/v3/rtl/neural_director_packed.v

@@ -115,7 +115,7 @@ module neural_director_packed #(
     reg [$clog2(N_SLOTS)-1:0] free_slot_idx;
     integer fi;
     always @(*) begin
-        free_slot_idx = '0;
+        free_slot_idx = {$clog2(N_SLOTS){1'b0}};
         for (fi = N_SLOTS-1; fi >= 0; fi = fi - 1) begin
             if (slot_free[fi]) free_slot_idx = fi[$clog2(N_SLOTS)-1:0];
         end
@@ -152,7 +152,7 @@ module neural_director_packed #(
     reg [$clog2(N_SLOTS)-1:0] done_slot_idx;
     integer di;
     always @(*) begin
-        done_slot_idx = '0;
+        done_slot_idx = {$clog2(N_SLOTS){1'b0}};
         for (di = N_SLOTS-1; di >= 0; di = di - 1) begin
             if (slot_job_done[di]) done_slot_idx = di[$clog2(N_SLOTS)-1:0];
         end
@@ -178,7 +178,7 @@ module neural_director_packed #(
                 slot_node_id_b_r[fi]     <= 16'b0;
             end
             job_out_done <= 1'b0;
-            job_out_slot <= '0;
+            job_out_slot <= {$clog2(N_SLOTS){1'b0}};
         end else begin
             for (fi = 0; fi < N_SLOTS; fi = fi + 1) slot_job_start_r[fi] <= 1'b0;
             job_out_done <= 1'b0;