micheleandClaude Sonnet 5
6caea54b8e
Replaced three uses of the SystemVerilog '0 self-sizing literal with explicit-width zero-fill so the file synthesizes under Vivado's synth_design (which has no -sv equivalent in this flow), needed while adding this module to the real in-context P&R project. Re-running its isolated regression after that edit surfaced 3/8 failures. Root-caused via git stash (reproduces on the untouched committed file, not caused by this edit) and a DUT-internal $display: tb_neural_director_packed.v's own submit_job task drove DUT inputs with blocking assignment across two separate @(posedge clk) waits, racing the DUT's own always block under Icarus and causing a spurious duplicate enqueue. Fixed by switching to nonblocking assignment (race-free by construction). neural_director_packed.v itself was correct all along - 8/8 tests pass after the testbench fix. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
254 lines
11 KiB
Verilog
254 lines
11 KiB
Verilog
`timescale 1ns/1ps
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// ================================================================
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// V3 -- Neural Director, forked from hardware/v2/rtl/neural_director.v
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// (M5) for the DSP48-packed, weight-reuse compute core
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// (neural_processor_packed.v, EXP-0059/0062).
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//
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// KEY DIFFERENCE FROM V2: each "slot" here is one packed core, which
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// processes TWO jobs (A, B) per dispatch, SHARING one weight stream
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// (one w_base/n_tiles). This module therefore dispatches PAIRS of
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// queued job descriptors, not single jobs.
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//
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// PAIRING RULE (real, disclosed scope limitation, not hidden): the
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// two oldest entries in the queue (q_head, q_head+1) are dispatched
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// together ONLY if they share the SAME w_base and n_tiles -- i.e.
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// the job submitter is REQUIRED to enqueue reuse-position jobs for
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// the same resident weight consecutively, in pairs (exactly the
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// pattern this project's own EXP-0057/0058/0062 testbenches already
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// use: M reuse positions per layer, submitted in order). If the two
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// oldest entries do NOT share w_base/n_tiles, this Director does NOT
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// dispatch (stalls, does not error, does not silently mis-pair) --
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// matches this project's own "an error must not block the rest of
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// the system, but a wrong dispatch must never happen" standard
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// (§34). A submitter that violates the pairing assumption will see
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// the queue simply stop draining, a visible, diagnosable symptom,
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// not silent data corruption. Odd-length reuse-position batches (M
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// odd) are therefore also not supported by this Director alone --
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// the submitter must pad to an even count or handle the last single
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// position through a different path (out of scope here).
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//
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// job_x_base becomes job_x_base_a/job_x_base_b (each position's own
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// activation base); w_base/n_tiles/result region addressing convention
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// stays per-job (job_result_addr_a/b) since each position still
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// writes its own independent result.
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// ================================================================
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module neural_director_packed #(
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parameter ADDR_WIDTH = 26,
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parameter N_SLOTS = 4,
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parameter QUEUE_DEPTH = 8
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)(
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input wire clk,
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input wire rst,
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// ---- job submission: unchanged single-job-descriptor producer
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// interface (pairing happens internally, on dequeue) ----
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input wire job_in_valid,
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output wire job_in_ready,
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input wire [ADDR_WIDTH-1:0] job_in_x_base,
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input wire [ADDR_WIDTH-1:0] job_in_w_base,
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input wire [15:0] job_in_n_tiles,
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input wire [ADDR_WIDTH-1:0] job_in_result_addr,
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input wire [15:0] job_in_node_id,
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// ---- per-slot packed-core job control (arrayed) ----
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output wire [N_SLOTS-1:0] slot_job_start,
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output wire [ADDR_WIDTH*N_SLOTS-1:0] slot_x_base_a,
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output wire [ADDR_WIDTH*N_SLOTS-1:0] slot_x_base_b,
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output wire [ADDR_WIDTH*N_SLOTS-1:0] slot_w_base, // shared A/B
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output wire [16*N_SLOTS-1:0] slot_n_tiles, // shared A/B
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output wire [ADDR_WIDTH*N_SLOTS-1:0] slot_result_addr_a,
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output wire [ADDR_WIDTH*N_SLOTS-1:0] slot_result_addr_b,
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output wire [16*N_SLOTS-1:0] slot_node_id_a,
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output wire [16*N_SLOTS-1:0] slot_node_id_b,
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input wire [N_SLOTS-1:0] slot_job_done, // both A+B done together
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output reg job_out_done, // one-cycle pulse
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output reg [$clog2(N_SLOTS)-1:0] job_out_slot,
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output reg [3:0] dir_state,
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output reg dir_error,
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output wire queue_empty
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);
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localparam DIR_IDLE = 4'd0;
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localparam DIR_SCAN_READY = 4'd1;
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localparam DIR_ALLOCATE = 4'd2;
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localparam DIR_ERROR = 4'd3;
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localparam Q_ADDR_WIDTH = $clog2(QUEUE_DEPTH);
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reg [ADDR_WIDTH-1:0] q_x_base [0:QUEUE_DEPTH-1];
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reg [ADDR_WIDTH-1:0] q_w_base [0:QUEUE_DEPTH-1];
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reg [15:0] q_n_tiles [0:QUEUE_DEPTH-1];
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reg [ADDR_WIDTH-1:0] q_result_addr [0:QUEUE_DEPTH-1];
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reg [15:0] q_node_id [0:QUEUE_DEPTH-1];
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reg [Q_ADDR_WIDTH-1:0] q_head, q_tail;
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reg [Q_ADDR_WIDTH:0] q_count;
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wire q_empty = (q_count == 0);
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assign queue_empty = q_empty;
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wire q_full = (q_count == QUEUE_DEPTH[Q_ADDR_WIDTH:0]);
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wire q_has_pair = (q_count >= 2);
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assign job_in_ready = !q_full;
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// second-oldest entry's index (q_head+1, wrapping)
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wire [Q_ADDR_WIDTH-1:0] q_head_plus1 =
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(q_head == QUEUE_DEPTH[Q_ADDR_WIDTH-1:0]-1'b1) ? {Q_ADDR_WIDTH{1'b0}} : q_head + 1'b1;
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// the two oldest entries share a resident weight iff w_base AND
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// n_tiles both match -- both are checked (not just w_base) since a
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// real mismatched n_tiles with a coincidentally-equal w_base would
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// otherwise still be wrongly accepted as a pair.
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wire pair_ready = q_has_pair &&
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(q_w_base[q_head] == q_w_base[q_head_plus1]) &&
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(q_n_tiles[q_head] == q_n_tiles[q_head_plus1]);
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reg [N_SLOTS-1:0] slot_busy;
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wire [N_SLOTS-1:0] slot_free = ~slot_busy;
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wire any_slot_free = |slot_free;
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reg [$clog2(N_SLOTS)-1:0] free_slot_idx;
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integer fi;
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always @(*) begin
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free_slot_idx = {$clog2(N_SLOTS){1'b0}};
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for (fi = N_SLOTS-1; fi >= 0; fi = fi - 1) begin
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if (slot_free[fi]) free_slot_idx = fi[$clog2(N_SLOTS)-1:0];
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end
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end
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// per-slot output storage -- N_SLOTS parallel constant-indexed
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// writes, same anti-pattern-avoidance as V2's own neural_director.v
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// (see that file's own slot_x_base_r comment, ERR-0027).
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reg slot_job_start_r [0:N_SLOTS-1];
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reg [ADDR_WIDTH-1:0] slot_x_base_a_r [0:N_SLOTS-1];
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reg [ADDR_WIDTH-1:0] slot_x_base_b_r [0:N_SLOTS-1];
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reg [ADDR_WIDTH-1:0] slot_w_base_r [0:N_SLOTS-1];
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reg [15:0] slot_n_tiles_r [0:N_SLOTS-1];
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reg [ADDR_WIDTH-1:0] slot_result_addr_a_r [0:N_SLOTS-1];
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reg [ADDR_WIDTH-1:0] slot_result_addr_b_r [0:N_SLOTS-1];
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reg [15:0] slot_node_id_a_r [0:N_SLOTS-1];
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reg [15:0] slot_node_id_b_r [0:N_SLOTS-1];
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genvar gs;
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generate
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for (gs = 0; gs < N_SLOTS; gs = gs + 1) begin : GEN_SLOT_OUT
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assign slot_job_start[gs] = slot_job_start_r[gs];
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assign slot_x_base_a[gs*ADDR_WIDTH +: ADDR_WIDTH] = slot_x_base_a_r[gs];
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assign slot_x_base_b[gs*ADDR_WIDTH +: ADDR_WIDTH] = slot_x_base_b_r[gs];
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assign slot_w_base[gs*ADDR_WIDTH +: ADDR_WIDTH] = slot_w_base_r[gs];
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assign slot_n_tiles[gs*16 +: 16] = slot_n_tiles_r[gs];
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assign slot_result_addr_a[gs*ADDR_WIDTH +: ADDR_WIDTH] = slot_result_addr_a_r[gs];
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assign slot_result_addr_b[gs*ADDR_WIDTH +: ADDR_WIDTH] = slot_result_addr_b_r[gs];
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assign slot_node_id_a[gs*16 +: 16] = slot_node_id_a_r[gs];
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assign slot_node_id_b[gs*16 +: 16] = slot_node_id_b_r[gs];
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end
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endgenerate
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reg [$clog2(N_SLOTS)-1:0] done_slot_idx;
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integer di;
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always @(*) begin
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done_slot_idx = {$clog2(N_SLOTS){1'b0}};
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for (di = N_SLOTS-1; di >= 0; di = di - 1) begin
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if (slot_job_done[di]) done_slot_idx = di[$clog2(N_SLOTS)-1:0];
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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dir_state <= DIR_IDLE;
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dir_error <= 1'b0;
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q_head <= {Q_ADDR_WIDTH{1'b0}};
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q_tail <= {Q_ADDR_WIDTH{1'b0}};
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q_count <= {(Q_ADDR_WIDTH+1){1'b0}};
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slot_busy <= {N_SLOTS{1'b0}};
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for (fi = 0; fi < N_SLOTS; fi = fi + 1) begin
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slot_job_start_r[fi] <= 1'b0;
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slot_x_base_a_r[fi] <= {ADDR_WIDTH{1'b0}};
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slot_x_base_b_r[fi] <= {ADDR_WIDTH{1'b0}};
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slot_w_base_r[fi] <= {ADDR_WIDTH{1'b0}};
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slot_n_tiles_r[fi] <= 16'b0;
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slot_result_addr_a_r[fi] <= {ADDR_WIDTH{1'b0}};
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slot_result_addr_b_r[fi] <= {ADDR_WIDTH{1'b0}};
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slot_node_id_a_r[fi] <= 16'b0;
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slot_node_id_b_r[fi] <= 16'b0;
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end
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job_out_done <= 1'b0;
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job_out_slot <= {$clog2(N_SLOTS){1'b0}};
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end else begin
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for (fi = 0; fi < N_SLOTS; fi = fi + 1) slot_job_start_r[fi] <= 1'b0;
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job_out_done <= 1'b0;
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if (job_in_valid && job_in_ready) begin
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q_x_base[q_tail] <= job_in_x_base;
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q_w_base[q_tail] <= job_in_w_base;
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q_n_tiles[q_tail] <= job_in_n_tiles;
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q_result_addr[q_tail] <= job_in_result_addr;
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q_node_id[q_tail] <= job_in_node_id;
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q_tail <= (q_tail == QUEUE_DEPTH[Q_ADDR_WIDTH-1:0]-1'b1) ? {Q_ADDR_WIDTH{1'b0}} : q_tail + 1'b1;
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end
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slot_busy <= slot_busy & ~slot_job_done;
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if (|slot_job_done) begin
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job_out_done <= 1'b1;
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job_out_slot <= done_slot_idx;
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end
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case (dir_state)
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DIR_IDLE: begin
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dir_state <= DIR_SCAN_READY;
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end
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DIR_SCAN_READY: begin
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if (pair_ready && any_slot_free) begin
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dir_state <= DIR_ALLOCATE;
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end
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end
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DIR_ALLOCATE: begin
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for (fi = 0; fi < N_SLOTS; fi = fi + 1) begin
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if (fi[$clog2(N_SLOTS)-1:0] == free_slot_idx) begin
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slot_job_start_r[fi] <= 1'b1;
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slot_x_base_a_r[fi] <= q_x_base[q_head];
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slot_x_base_b_r[fi] <= q_x_base[q_head_plus1];
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slot_w_base_r[fi] <= q_w_base[q_head]; // == q_w_base[q_head_plus1], checked by pair_ready
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slot_n_tiles_r[fi] <= q_n_tiles[q_head];
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slot_result_addr_a_r[fi] <= q_result_addr[q_head];
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slot_result_addr_b_r[fi] <= q_result_addr[q_head_plus1];
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slot_node_id_a_r[fi] <= q_node_id[q_head];
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slot_node_id_b_r[fi] <= q_node_id[q_head_plus1];
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end
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end
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slot_busy[free_slot_idx] <= 1'b1;
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q_head <= (q_head_plus1 == QUEUE_DEPTH[Q_ADDR_WIDTH-1:0]-1'b1)
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? {Q_ADDR_WIDTH{1'b0}} : q_head_plus1 + 1'b1;
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dir_state <= DIR_SCAN_READY;
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end
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DIR_ERROR: begin
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end
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default: dir_state <= DIR_ERROR;
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endcase
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// q_count: +1 per accepted push, -2 per dispatched PAIR
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// (not -1, unlike V2 -- each DIR_ALLOCATE cycle here
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// consumes TWO queue entries, not one)
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case ({job_in_valid && job_in_ready,
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(dir_state == DIR_SCAN_READY) && pair_ready && any_slot_free})
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2'b10: q_count <= q_count + 1'b1;
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2'b01: q_count <= q_count - 2'b10;
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2'b11: q_count <= q_count - 2'b10 + 1'b1;
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2'b00: q_count <= q_count;
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endcase
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end
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end
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endmodule
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