docs: real timing closure for 32-bit DDR3 channel (EXP-0086)
Reverting Clock Period to 3225ps (keeping Data Width=32) closes real timing: WNS=+0.095707ns, WHS=+0.036275ns, 0 failing endpoints, all user-specified constraints met. This is the real final signoff for the 32-bit DDR3 channel widening effort (EXP-0083 through EXP-0086), replacing EXP-0083's 16-bit-era baseline as the project's current trustworthy number. Confirms the EXP-0084 root-cause analysis: the earlier -0.618ns failure was caused by a separate, stacked clock speedup, not the width change itself. Also found and fixed a second, wholesale real occurrence of the stale-import bug: the MIG wizard regeneration needed to revert Clock Period silently re-imported the entire v3 RTL tree (9 files) plus the top XDC back to pre-EXP-0084 stale copies, not just the file(s) the regeneration touched. CLAUDE.md's lesson extended accordingly.
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@@ -5617,3 +5617,93 @@ the tight I/O/VCCO budget further. Document the real ESP32-side
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GPIO/interrupt wiring implication once the board's own reset-circuit
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pin planning (S7, still open) is decided, since data_ready_n and
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sys_rst now share bank 15's own real, tentative pin choices.
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EXP-0086 -- real timing closure for the 32-bit DDR3 channel (clock
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period revert), plus a real recurrence of the stale-import bug
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(2026-09-20, continuation: user reverted Clock Period 2900->3225ps via
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a second real MIG wizard session, keeping Data Width=32, per this
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session's own EXP-0084 root-cause recommendation: "torna esattamente
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nelle condizioni gia' testate")
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CONTEXT: EXP-0084 left the 32-bit DDR3 channel functionally complete
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but with real timing FAILING (WNS=-0.618ns) at the paired 2900ps/
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172.414MHz ui_clk speedup. Root cause (EXP-0084) was decoupled from the
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width change itself: the failing path was neural_processor_packed.v's
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own packed-MAC accumulation tree, unchanged since EXP-0059, which had
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real margin at the OLD 155.039MHz clock but not the new, faster one.
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Recommendation given to the user: revert ONLY Clock Period back to the
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already-proven-safe 3225ps, keep Data Width=32 (the width alone already
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delivers the full 2x bandwidth target, independent of clock speed).
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REAL BUG FOUND BEFORE THE REAL FIX COULD EVEN BE MEASURED: the first
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re-run of the final P&R (Clock Period=3225ps, Data Width=32, all
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EXP-0084 RTL/XDC fixes already committed) failed immediately with
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"ERROR: [Place 30-58] IO placement is infeasible. Number of unplaced IO
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Ports (41) is greater than number of available pins (10)" plus a
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CRITICAL WARNING that PROHIBIT was again an invalid property. Both were
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supposedly-already-fixed EXP-0084 bugs. Root-caused (not guessed) by
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checking which XDC file Vivado actually parsed in the log
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(".../constrs_1/imports/constraints/n2_system_ddr3_top.xdc" -- the
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STALE IMPORTED COPY, not the live hardware/v3/ source) and then
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querying the project's sources_1 fileset directly: the user's own
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second real MIG wizard regeneration (the one that produced the
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3225ps/DataWidth=32 mig_a.prj) had triggered Vivado to rescan and
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RE-IMPORT THE ENTIRE v3 RTL SOURCE TREE, not just the XDC -- 9 RTL
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files (host_mem_bridge.v, layer_prefetch_ctrl.v, layer_weight_buffer.v,
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mig_native_adapter.v, neural_director_packed.v, neural_processor_
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packed.v, sdram_arbiter_n.v, weight_tile_gather.v, mac2_dsp_packed.v)
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plus n2_system_ddr3_top.xdc were all silently reset to stale copies
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predating EXP-0084's fixes. This is the SAME class of bug CLAUDE.md
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already documented for EXP-0078 (RTL) and EXP-0084 (XDC, single file)
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-- but this is the first real confirmation that it can recur on ANY
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MIG IP regeneration, wholesale, across the entire project, not just
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once per file. Fixed via the same technique as before: remove_files +
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add_files -norecurse to make each one a direct reference again
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(/tmp/fix_all_stale_srcs.tcl for the 9 RTL files, /tmp/fix_stale_xdc2.tcl
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for the XDC), verified via a real TCL query that zero non-IP-owned
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*/imports/* paths remained in either fileset before re-running.
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REAL RESULT (after the stale-source fix, real synth_design + opt_design
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+ place_design + route_design, xc7a100tcsg324-2, in-context on
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n2_system_ddr3_top): **WNS = +0.095707 ns, WHS = +0.036275 ns**, 0
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failing endpoints out of 25172 (setup) / 25169 (hold) / 9505 (pulse
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width). "All user specified timing constraints are met." The
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clk_pll_i domain (155.039 MHz, 6.45ns period -- the exact domain that
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failed at -0.618ns in EXP-0084's 2900ps attempt) closes at WNS=+0.096ns
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across 24522 endpoints, confirming the EXP-0084 root-cause analysis:
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the width change was never the problem, and reverting only the clock
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period restores real margin on neural_processor_packed.v's own MAC
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tree, matching EXP-0083's real 16-bit-era WNS (+0.073ns) closely (small
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+0.023ns difference is normal P&R placement-seed variance, not a real
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regression or improvement tied to the width change).
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Real utilization (routed): 6382 LUTs (vs EXP-0083's 5644 -- +738,
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+13%, expected: doubled DQ/DM/mask handling, 4-way tile-offset muxes in
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act_tile_fetch.v, wider ctrl bus through ddr_prefetch_mgr.v), 7769
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registers, 16 DSP48E1 (unchanged -- same core count), 119 Bonded IOB
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used of 207 available (57.49%, real headroom remains). data_ready_n
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(EXP-0085) confirmed placed at D14/LVCMOS33, sys_clk_p/n at N5/P5/
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DIFF_SSTL15, clk_ref_p/n at T14/T15/LVDS_25 -- all real, routed,
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verified via a direct open_checkpoint query on n2_system_ddr3_top_
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routed.dcp, not assumed from the XDC alone.
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DECISION: real, final signoff for the 32-bit DDR3 channel widening
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(EXP-0083 DDRManager phase 1 through EXP-0086 this entry). This
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REPLACES EXP-0083's 16-bit-era number as the project's current
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trustworthy real P&R baseline. Bandwidth ceiling: real 32-bit width x
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real closed 155.039MHz clk_pll_i domain = the full originally-targeted
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~2.48GB/s (2x EXP-0083's 16-bit ~1.24GB/s), with real, closed timing,
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not a projection.
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next_action: (1) CLAUDE.md's stale-import lesson updated to note MIG
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IP regeneration can re-trigger a wholesale project source rescan, not
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just a single-file staleness risk -- check ALL filesets after ANY IP
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regeneration, not just the files touched by that regeneration. (2)
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Re-measure EXP-0083's DDRManager (ddr_prefetch_mgr.v) real benefit
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against this now-closed wider channel, per the project's own established
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sequencing ("re-measure once the wider channel's timing actually
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closes"). (3) Build the result-writeback engine (ARCHITECTURE_ANALYSIS
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§5.3, long-disclosed blocker for N>2 core scaling). (4) Real N=2/4/8/16
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core-count scaling tests, each with its own real P&R signoff, per the
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user's own standing directive ("senza illusioni ma analizzando la
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situazione piu' performante").
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