feat(v2): M3 activation/weight/result buffers, real BRAM mapping
Implements M3: three parametric dual-port buffers for the §12 data-plane (Input/Weight/Result), reusing the proven BRAM-inference idiom from the frozen hardware/v1/rtl/act_buffer.v (synchronous write, synchronous REGISTERED read, no reset on the read register -- keeps Yosys off the LUT-RAM path). Verified with Verilator: 10/10 tests pass (write-then-read correctness, extreme INT8 round-tripping, weight_buffer's full 64-bit tile width round-tripping, undisturbed re-reads). Real synthesis at two depths per module (6 configs total): 0 CHECK problems, every configuration correctly infers DP16KD (never LUT-RAM). Non-obvious real finding: weight_buffer's BRAM cost is driven by its P_IN*DATA_WIDTH tile width, not its DEPTH -- an 8x depth reduction (512->64) left DP16KD usage unchanged at 2, while activation_buffer/result_buffer (byte-wide) scale as naively expected (2->1). All default-depth configs PASS at 80MHz with large margin (287-367 MHz) via real nextpnr-ecp5 place&route. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
Claude Sonnet 5
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 88/43848 0%
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Info: logic LUTs: 88/43848 0%
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Info: carry LUTs: 0/43848 0%
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Info: RAM LUTs: 0/ 5481 0%
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Info: RAMW LUTs: 0/10962 0%
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Info: Total DFFs: 139/43848 0%
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Info: Packing IOs..
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 1 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0x8d179719
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Info: Device utilisation:
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Info: TRELLIS_IO: 148/ 245 60%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 2/ 108 1%
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Info: MULT18X18D: 0/ 72 0%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 139/ 43848 0%
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Info: TRELLIS_COMB: 90/ 43848 0%
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Info: TRELLIS_RAMW: 0/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 214 cells, random placement wirelen = 21853.
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Info: at initial placer iter 0, wirelen = 8761
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Info: at initial placer iter 1, wirelen = 8682
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Info: at initial placer iter 2, wirelen = 8664
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Info: at initial placer iter 3, wirelen = 8654
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Info: Running main analytical placer, max placement attempts per cell = 18050.
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Info: at iteration #1, type ALL: wirelen solved = 8649, spread = 9182, legal = 10156; time = 0.00s
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Info: HeAP Placer Time: 0.02s
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Info: of which solving equations: 0.00s
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Info: of which spreading cells: 0.00s
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Info: of which strict legalisation: 0.00s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 85, wirelen = 10156
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Info: at iteration #5: temp = 0.000000, timing cost = 31, wirelen = 8157
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Info: at iteration #10: temp = 0.000000, timing cost = 12, wirelen = 8054
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Info: at iteration #13: temp = 0.000000, timing cost = 10, wirelen = 7961
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Info: SA placement time 0.03s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 366.57 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 7.42 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 10.27 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 9772, 9871) |*
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Info: [ 9871, 9970) |
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Info: [ 9970, 10069) |*
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Info: [ 10069, 10168) |
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Info: [ 10168, 10267) |***
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Info: [ 10267, 10366) |**
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Info: [ 10366, 10465) |**
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Info: [ 10465, 10564) |*******
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Info: [ 10564, 10663) |****
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Info: [ 10663, 10762) |*************
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Info: [ 10762, 10861) |*****
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Info: [ 10861, 10960) |******
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Info: [ 10960, 11059) |**********
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Info: [ 11059, 11158) |*******
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Info: [ 11158, 11257) |***************
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Info: [ 11257, 11356) |******
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Info: [ 11356, 11455) |*************************
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Info: [ 11455, 11554) |**********
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Info: [ 11554, 11653) |*************
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Info: [ 11653, 11752) |*************************
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Info: Checksum: 0x6f062bf9
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 568 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 586 | 18 560 | 18 560 | 0| 0.09 0.09|
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Info: Routing complete.
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Info: Router1 time 0.09s
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Info: Checksum: 0x1cfed5f0
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source mem.0.0_ADA8_TRELLIS_FF_Q.Q
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Info: routing 0.67 1.06 Net mem.0.0_ADA8[1] (41,26) -> (41,27)
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Info: Sink wr_en_TRELLIS_FF_DI_Q_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 1.24 Source wr_en_TRELLIS_FF_DI_Q_LUT4_Z.F
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Info: routing 0.56 1.80 Net wr_en_TRELLIS_FF_DI_Q[6] (41,27) -> (40,28)
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Info: Sink mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.19 2.00 Source mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
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Info: routing 0.65 2.65 Net mem.0.0_ADA5_LUT4_D_Z[2] (40,28) -> (40,26)
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Info: Sink mem.0.0_DOA0_TRELLIS_FF_Q_1_DI_LUT4_Z.C
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 2.83 Source mem.0.0_DOA0_TRELLIS_FF_Q_1_DI_LUT4_Z.F
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Info: routing 0.12 2.94 Net mem.0.0_DOA0_TRELLIS_FF_Q_1_DI (40,26) -> (40,26)
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Info: Sink mem.0.0_DOA0_TRELLIS_FF_Q_1.DI
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Info: setup 0.00 2.94 Source mem.0.0_DOA0_TRELLIS_FF_Q_1.DI
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Info: 0.95 ns logic, 2.00 ns routing
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Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
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Info: type curr total name
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Info: source 0.00 0.00 Source rd_addr[6]$tr_io.O
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Info: routing 4.15 4.15 Net rd_addr[6]$TRELLIS_IO_IN (13,71) -> (41,25)
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Info: Sink mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.A
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Info: Defined in:
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Info: hardware/v2/rtl/weight_buffer.v:33.48-33.55
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Info: logic 0.18 4.33 Source mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.F
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Info: routing 0.00 4.33 Net mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_ALUT (41,25) -> (41,25)
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Info: Sink mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.F1
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.22-157.24
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Info: logic 0.13 4.45 Source mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.OFX
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Info: routing 0.00 4.45 Net mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D0 (41,25) -> (41,25)
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Info: Sink mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXA
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.50-157.52
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Info: logic 0.18 4.63 Source mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
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Info: routing 0.00 4.63 Net mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D0 (41,25) -> (41,25)
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Info: Sink mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXA
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68
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Info: logic 0.18 4.81 Source mem.0.0_ADA5_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
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Info: routing 0.52 5.34 Net mem.0.0_ADA5_LUT4_D_Z[3] (41,25) -> (40,26)
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Info: Sink mem.0.0_DOA0_TRELLIS_FF_Q_1_DI_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 5.52 Source mem.0.0_DOA0_TRELLIS_FF_Q_1_DI_LUT4_Z.F
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Info: routing 0.12 5.63 Net mem.0.0_DOA0_TRELLIS_FF_Q_1_DI (40,26) -> (40,26)
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Info: Sink mem.0.0_DOA0_TRELLIS_FF_Q_1.DI
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Info: setup 0.00 5.63 Source mem.0.0_DOA0_TRELLIS_FF_Q_1.DI
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Info: 0.84 ns logic, 4.79 ns routing
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Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
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Info: type curr total name
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Info: clk-to-q 4.26 4.26 Source mem.0.0.DOB10
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Info: routing 1.07 5.33 Net mem.0.0_DOB10[0] (37,34) -> (37,35)
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Info: Sink rd_data_LUT4_Z_30.B
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 5.51 Source rd_data_LUT4_Z_30.F
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Info: routing 3.27 8.78 Net rd_data[28]$TRELLIS_IO_OUT (37,35) -> (67,0)
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Info: Sink rd_data[28]$tr_io.I
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Info: Defined in:
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Info: hardware/v2/rtl/weight_buffer.v:34.48-34.55
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Info: 4.44 ns logic, 4.33 ns routing
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 339.67 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 5.63 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 8.78 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 9556, 9668) |*
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Info: [ 9668, 9780) |
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Info: [ 9780, 9892) |
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Info: [ 9892, 10004) |
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Info: [ 10004, 10116) |
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Info: [ 10116, 10228) |
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Info: [ 10228, 10340) |
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Info: [ 10340, 10452) |
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Info: [ 10452, 10564) |
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Info: [ 10564, 10676) |****
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Info: [ 10676, 10788) |*****
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Info: [ 10788, 10900) |*****
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Info: [ 10900, 11012) |************************
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Info: [ 11012, 11124) |********************
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Info: [ 11124, 11236) |***************
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Info: [ 11236, 11348) |*****************
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Info: [ 11348, 11460) |***********
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Info: [ 11460, 11572) |*************
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Info: [ 11572, 11684) |***********
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Info: [ 11684, 11796) |*****************************
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Info: Program finished normally.
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