feat(v2): M3 activation/weight/result buffers, real BRAM mapping
Implements M3: three parametric dual-port buffers for the §12 data-plane (Input/Weight/Result), reusing the proven BRAM-inference idiom from the frozen hardware/v1/rtl/act_buffer.v (synchronous write, synchronous REGISTERED read, no reset on the read register -- keeps Yosys off the LUT-RAM path). Verified with Verilator: 10/10 tests pass (write-then-read correctness, extreme INT8 round-tripping, weight_buffer's full 64-bit tile width round-tripping, undisturbed re-reads). Real synthesis at two depths per module (6 configs total): 0 CHECK problems, every configuration correctly infers DP16KD (never LUT-RAM). Non-obvious real finding: weight_buffer's BRAM cost is driven by its P_IN*DATA_WIDTH tile width, not its DEPTH -- an 8x depth reduction (512->64) left DP16KD usage unchanged at 2, while activation_buffer/result_buffer (byte-wide) scale as naively expected (2->1). All default-depth configs PASS at 80MHz with large margin (287-367 MHz) via real nextpnr-ecp5 place&route. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
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Claude Sonnet 5
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`timescale 1ns/1ps
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// ============================================================
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// M3 testbench (docs/v2-description.md §14/§20): activation_buffer.v,
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// weight_buffer.v, result_buffer.v. Verified with Verilator (see
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// hardware/v2/logs/decisions.log DEC-0004).
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//
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// Coverage: write-then-read correctness (incl. the 1-cycle registered
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// read latency all three share with hardware/v1/rtl/act_buffer.v),
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// back-to-back writes to different addresses without corrupting
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// earlier entries, and extreme INT8 values (-128, 127) round-tripping
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// exactly.
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// ============================================================
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module tb;
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localparam DATA_WIDTH = 8;
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localparam P_IN = 8;
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localparam AB_DEPTH = 64;
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localparam WB_DEPTH = 16;
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localparam RB_DEPTH = 64;
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reg clk;
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initial begin clk = 0; forever #5 clk = ~clk; end
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integer errors, tests;
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// ---- activation_buffer ----
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reg ab_wr_en;
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reg [$clog2(AB_DEPTH)-1:0] ab_wr_addr, ab_rd_addr;
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reg signed [DATA_WIDTH-1:0] ab_wr_data;
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wire signed [DATA_WIDTH-1:0] ab_rd_data;
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activation_buffer #(.DEPTH(AB_DEPTH), .DATA_WIDTH(DATA_WIDTH)) u_ab (
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.clk(clk), .wr_en(ab_wr_en), .wr_addr(ab_wr_addr), .wr_data(ab_wr_data),
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.rd_addr(ab_rd_addr), .rd_data(ab_rd_data)
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);
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// ---- weight_buffer ----
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reg wb_wr_en;
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reg [$clog2(WB_DEPTH)-1:0] wb_wr_addr, wb_rd_addr;
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reg signed [DATA_WIDTH*P_IN-1:0] wb_wr_data;
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wire signed [DATA_WIDTH*P_IN-1:0] wb_rd_data;
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weight_buffer #(.DEPTH(WB_DEPTH), .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN)) u_wb (
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.clk(clk), .wr_en(wb_wr_en), .wr_addr(wb_wr_addr), .wr_data(wb_wr_data),
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.rd_addr(wb_rd_addr), .rd_data(wb_rd_data)
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);
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// ---- result_buffer ----
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reg rb_wr_en;
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reg [$clog2(RB_DEPTH)-1:0] rb_wr_addr, rb_rd_addr;
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reg signed [DATA_WIDTH-1:0] rb_wr_data;
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wire signed [DATA_WIDTH-1:0] rb_rd_data;
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result_buffer #(.DEPTH(RB_DEPTH), .DATA_WIDTH(DATA_WIDTH)) u_rb (
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.clk(clk), .wr_en(rb_wr_en), .wr_addr(rb_wr_addr), .wr_data(rb_wr_data),
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.rd_addr(rb_rd_addr), .rd_data(rb_rd_data)
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);
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task automatic check_ab(input [$clog2(AB_DEPTH)-1:0] addr, input signed [DATA_WIDTH-1:0] exp_val);
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begin
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tests = tests + 1;
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ab_rd_addr = addr;
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@(posedge clk);
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@(posedge clk); // registered read: value settles one cycle after rd_addr
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if (ab_rd_data !== exp_val) begin
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$display("FAIL activation_buffer[%0d]: got %0d expected %0d", addr, ab_rd_data, exp_val);
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errors = errors + 1;
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end else
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$display("PASS activation_buffer[%0d] = %0d", addr, ab_rd_data);
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end
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endtask
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task automatic check_wb(input [$clog2(WB_DEPTH)-1:0] addr, input signed [DATA_WIDTH*P_IN-1:0] exp_val);
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begin
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tests = tests + 1;
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wb_rd_addr = addr;
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@(posedge clk);
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@(posedge clk);
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if (wb_rd_data !== exp_val) begin
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$display("FAIL weight_buffer[%0d]: got %h expected %h", addr, wb_rd_data, exp_val);
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errors = errors + 1;
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end else
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$display("PASS weight_buffer[%0d] = %h", addr, wb_rd_data);
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end
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endtask
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task automatic check_rb(input [$clog2(RB_DEPTH)-1:0] addr, input signed [DATA_WIDTH-1:0] exp_val);
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begin
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tests = tests + 1;
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rb_rd_addr = addr;
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@(posedge clk);
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@(posedge clk);
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if (rb_rd_data !== exp_val) begin
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$display("FAIL result_buffer[%0d]: got %0d expected %0d", addr, rb_rd_data, exp_val);
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errors = errors + 1;
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end else
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$display("PASS result_buffer[%0d] = %0d", addr, rb_rd_data);
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end
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endtask
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integer i;
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initial begin
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errors = 0; tests = 0;
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ab_wr_en = 0; ab_wr_addr = 0; ab_wr_data = 0; ab_rd_addr = 0;
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wb_wr_en = 0; wb_wr_addr = 0; wb_wr_data = 0; wb_rd_addr = 0;
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rb_wr_en = 0; rb_wr_addr = 0; rb_wr_data = 0; rb_rd_addr = 0;
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@(posedge clk);
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// ---- activation_buffer: write extreme + regular values at
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// several addresses, confirm each reads back correctly and
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// earlier writes are not disturbed by later ones. ----
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@(posedge clk);
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ab_wr_en = 1; ab_wr_addr = 0; ab_wr_data = -8'sd128; @(posedge clk);
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ab_wr_addr = 1; ab_wr_data = 8'sd127; @(posedge clk);
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ab_wr_addr = 5; ab_wr_data = 8'sd42; @(posedge clk);
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ab_wr_addr = 63; ab_wr_data = -8'sd1; @(posedge clk);
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ab_wr_en = 0;
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check_ab(0, -8'sd128);
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check_ab(1, 8'sd127);
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check_ab(5, 8'sd42);
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check_ab(63, -8'sd1);
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check_ab(1, 8'sd127); // re-read: confirm earlier writes undisturbed
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// ---- weight_buffer: write two whole tiles, confirm full
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// TILE_WIDTH round-trips exactly (not just one lane). ----
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@(posedge clk);
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wb_wr_en = 1; wb_wr_addr = 0;
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wb_wr_data = 0;
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for (i = 0; i < P_IN; i = i + 1)
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wb_wr_data[i*DATA_WIDTH +: DATA_WIDTH] = i[DATA_WIDTH-1:0]; // 0,1,2,...,7
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@(posedge clk);
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wb_wr_addr = 3;
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wb_wr_data = 0;
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for (i = 0; i < P_IN; i = i + 1)
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wb_wr_data[i*DATA_WIDTH +: DATA_WIDTH] = -8'sd1; // all-lanes -1
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@(posedge clk);
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wb_wr_en = 0;
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begin
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reg signed [DATA_WIDTH*P_IN-1:0] expect0, expect3;
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expect0 = 0;
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for (i = 0; i < P_IN; i = i + 1) expect0[i*DATA_WIDTH +: DATA_WIDTH] = i[DATA_WIDTH-1:0];
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expect3 = {P_IN{8'hFF}};
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check_wb(0, expect0);
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check_wb(3, expect3);
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check_wb(0, expect0); // re-read: confirm undisturbed
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end
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// ---- result_buffer: same pattern as activation_buffer ----
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@(posedge clk);
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rb_wr_en = 1; rb_wr_addr = 7; rb_wr_data = 8'sd100; @(posedge clk);
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rb_wr_addr = 8; rb_wr_data = -8'sd100; @(posedge clk);
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rb_wr_en = 0;
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check_rb(7, 8'sd100);
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check_rb(8, -8'sd100);
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$display("========================================");
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if (errors == 0)
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$display("ALL %0d TESTS PASSED (activation/weight/result buffers)", tests);
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else
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$display("FAILED: %0d/%0d test(s) had errors -- see messages above", errors, tests);
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$display("========================================");
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$finish;
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end
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endmodule
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