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feat(v2): M3 activation/weight/result buffers, real BRAM mapping

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Implements M3: three parametric dual-port buffers for the §12
data-plane (Input/Weight/Result), reusing the proven BRAM-inference
idiom from the frozen hardware/v1/rtl/act_buffer.v (synchronous write,
synchronous REGISTERED read, no reset on the read register -- keeps
Yosys off the LUT-RAM path).

Verified with Verilator: 10/10 tests pass (write-then-read
correctness, extreme INT8 round-tripping, weight_buffer's full 64-bit
tile width round-tripping, undisturbed re-reads).

Real synthesis at two depths per module (6 configs total): 0 CHECK
problems, every configuration correctly infers DP16KD (never
LUT-RAM). Non-obvious real finding: weight_buffer's BRAM cost is
driven by its P_IN*DATA_WIDTH tile width, not its DEPTH -- an 8x depth
reduction (512->64) left DP16KD usage unchanged at 2, while
activation_buffer/result_buffer (byte-wide) scale as naively expected
(2->1). All default-depth configs PASS at 80MHz with large margin
(287-367 MHz) via real nextpnr-ecp5 place&route.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
michele
2026-09-05 14:19:11 +02:00
co-authored by Claude Sonnet 5
parent 3026dcd997
commit 5f0d7f101c
29 changed files with 178330 additions and 2 deletions
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hardware/v2/logs/synthesis.log
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@@ -27,3 +27,12 @@ CHECK: 0 problems in all 4 configurations. Perfectly linear scaling in
flawed harness attempt fed identical data to every processor/lane
and Yosys silently deduplicated down to 1x regardless of N -- caught
by checking for exactly this linearity before trusting the numbers).
[2026-09-05] EXP-0004 -- activation_buffer/weight_buffer/result_buffer,
2 depths each
activation_buffer D=4096: LUT=37 FF=30 DP16KD=2 (D=256: LUT=21 FF=26 DP16KD=1)
weight_buffer D=512: LUT=88 FF=139 DP16KD=2 (D=64: LUT=73 FF=136 DP16KD=2)
result_buffer D=4096: LUT=37 FF=30 DP16KD=2 (D=256: LUT=21 FF=26 DP16KD=1)
CHECK: 0 problems, all 6 configs correctly infer DP16KD (no LUT-RAM
fallback). weight_buffer's DP16KD count does NOT drop with depth
(width-bound, not depth-bound -- see decisions.log / benchmark.log).