feat(v2): M3 activation/weight/result buffers, real BRAM mapping

Implements M3: three parametric dual-port buffers for the §12
data-plane (Input/Weight/Result), reusing the proven BRAM-inference
idiom from the frozen hardware/v1/rtl/act_buffer.v (synchronous write,
synchronous REGISTERED read, no reset on the read register -- keeps
Yosys off the LUT-RAM path).

Verified with Verilator: 10/10 tests pass (write-then-read
correctness, extreme INT8 round-tripping, weight_buffer's full 64-bit
tile width round-tripping, undisturbed re-reads).

Real synthesis at two depths per module (6 configs total): 0 CHECK
problems, every configuration correctly infers DP16KD (never
LUT-RAM). Non-obvious real finding: weight_buffer's BRAM cost is
driven by its P_IN*DATA_WIDTH tile width, not its DEPTH -- an 8x depth
reduction (512->64) left DP16KD usage unchanged at 2, while
activation_buffer/result_buffer (byte-wide) scale as naively expected
(2->1). All default-depth configs PASS at 80MHz with large margin
(287-367 MHz) via real nextpnr-ecp5 place&route.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/logs/simulation.log

@@ -28,3 +28,11 @@ concurrency: confirmed genuine -- in the staggered test, the
   later-launched, shorter job (processor 1) completes BEFORE the
   earlier-launched, longer job (processor 0), proving independent
   progress rather than serialization.
+
+[2026-09-05] EXP-0004 -- hardware/v2/sim/tb_buffers.v
+test: 10 cases across activation_buffer/weight_buffer/result_buffer
+vectors: extreme INT8 (-128, 127, -100, 100), regular values, full
+  64-bit tile round-trip (weight_buffer), re-reads confirming earlier
+  writes undisturbed
+simulator: Verilator 5.050 (--binary --timing)
+PASS/FAIL: 10/10 PASS