docs: real, full P&R for N=16 hybrid systolic system -- timing NOT met (EXP-0093)

Real place_design/route_design against XC7A100T-CSG324-2: post-route
utilization holds (128 DSP48E1/53.33%, matching EXP-0091's projection),
but real timing fails on clk_pll_i (155.039MHz): WNS=-0.913ns,
WHS=+0.029ns, 3021 failing setup endpoints. Root-caused to
sdram_arbiter_n.v's req_wdata mux, now a real 20/21-way select (up
from 3-way at N=2) feeding mig_native_adapter.v's wdata_lat_reg.

N=16 is functionally correct (EXP-0092) but not yet timing-closed --
honestly not ready for real hardware at the target clock. N=2
(EXP-0088) remains the trustworthy, deployable signoff. Real options
for closing timing documented as next_action, not yet attempted.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

docs/ARCHITECTURE_ANALYSIS.md

@@ -659,7 +659,7 @@ specifically to document where/how it breaks rather than to succeed):
 
 ---
 
-### 5.6 [Steps 1–4 DONE, EXP-0089/0090/0091/0092] Hybrid systolic scaling: 4 groups × 4-PE weight-stationary chains
+### 5.6 [Functionally DONE, TIMING NOT YET CLOSED — EXP-0089/0090/0091/0092/0093] Hybrid systolic scaling: 4 groups × 4-PE weight-stationary chains
 
 Captured from a 2026-09-20 brainstorming session as a purely exploratory
 idea; the same day, per the user's own explicit reprioritization, the real
@@ -706,12 +706,43 @@ systolic shift register) was resolved with the user directly (not guessed).
   broadcast barrier all really work wired together at full N=16 scale,
   not just in isolated unit tests.
 
-**Not yet done, real and disclosed**: **real timing** — no
-place_design/route_design run yet against the real XC7A100T-CSG324-2
-part. EXP-0091's own 128 DSP48E1/240 (53.33%) is a real synthesis-only
-utilization number, not yet post-route-confirmed, and WNS/WHS have not
-been measured at all for this larger top-level — see EXP-0092's own
-`next_action`.
+- **Real, full P&R (EXP-0093)**: real `place_design`/`route_design`
+  against the real XC7A100T-CSG324-2 part, same real Vivado project
+  EXP-0086/0088's own N=2 signoffs used. Real post-route utilization
+  confirmed: 19751 LUTs (31.15%), 34877 registers (27.51%), **128
+  DSP48E1/240 (53.33%)** — holds through real place+route, not just
+  synthesis. **Real timing result: WNS=−0.913ns, WHS=+0.029ns,
+  TNS=−690.085ns, 3021 failing setup endpoints — TIMING CONSTRAINTS
+  ARE NOT MET** on the real `clk_pll_i` (155.039MHz) domain, the same
+  clock N=2's own real EXP-0088 signoff closed at +0.099962ns.
+
+**Real, honest root cause (traced via the actual worst violated path,
+not guessed)**: the critical path runs from one of the 16 real per-PE
+`act_tile_fetch.v` FSM state registers, through 11 real logic levels, into
+`mig_native_adapter.v`'s own `wdata_lat_reg`. That register is fed by
+`sdram_arbiter_n.v`'s own `req_wdata` select mux, which grew from a
+3-way select at N=2 to a real **20/21-way** select at N=16 over the
+same 256-bit-wide bus — a real, substantial combinational fan-in
+increase on the one shared resource every PE's DDR3 write must pass
+through.
+
+**Current real status**: N=16 is **functionally correct (EXP-0092)
+but NOT YET timing-closed (EXP-0093)** — honestly not ready for real
+hardware at the target clock. This does not invalidate the functional/
+connectivity results; timing closure is a genuinely separate gate. N=2
+(EXP-0088) remains the real, trustworthy, deployable signoff.
+
+**Not yet done, real and disclosed, real options for closing timing**
+(need a real decision on direction before committing more RTL effort):
+(1) pipeline `sdram_arbiter_n.v`'s own req_wdata/req_addr mux by one
+real cycle — adds one cycle of real arbitration latency per request,
+likely acceptable given DDR3's own already-dominant real latency
+(EXP-0087); probably the most direct fix, targets the exact real
+critical path found above. (2) a real, hierarchical 2-level arbiter
+(e.g. 4 groups' own 5-way sub-arbiters feeding one real 4-way top
+arbiter) instead of one flat 20/21-way mux. (3) lower the real target
+clock for the N=16 variant specifically (a real, unquantified
+throughput tradeoff against N=2). See EXP-0093's own `next_action`.
 
 **The problem it targets**: plain N=16 independent cores (§5.5's own
 "documentary, expected to break" framing) means 16 independent DDR3