diff --git a/docs/ARCHITECTURE_ANALYSIS.md b/docs/ARCHITECTURE_ANALYSIS.md index a33fb0b..508d48f 100644 --- a/docs/ARCHITECTURE_ANALYSIS.md +++ b/docs/ARCHITECTURE_ANALYSIS.md @@ -659,7 +659,7 @@ specifically to document where/how it breaks rather than to succeed): --- -### 5.6 [Steps 1–4 DONE, EXP-0089/0090/0091/0092] Hybrid systolic scaling: 4 groups × 4-PE weight-stationary chains +### 5.6 [Functionally DONE, TIMING NOT YET CLOSED — EXP-0089/0090/0091/0092/0093] Hybrid systolic scaling: 4 groups × 4-PE weight-stationary chains Captured from a 2026-09-20 brainstorming session as a purely exploratory idea; the same day, per the user's own explicit reprioritization, the real @@ -706,12 +706,43 @@ systolic shift register) was resolved with the user directly (not guessed). broadcast barrier all really work wired together at full N=16 scale, not just in isolated unit tests. -**Not yet done, real and disclosed**: **real timing** — no -place_design/route_design run yet against the real XC7A100T-CSG324-2 -part. EXP-0091's own 128 DSP48E1/240 (53.33%) is a real synthesis-only -utilization number, not yet post-route-confirmed, and WNS/WHS have not -been measured at all for this larger top-level — see EXP-0092's own -`next_action`. +- **Real, full P&R (EXP-0093)**: real `place_design`/`route_design` + against the real XC7A100T-CSG324-2 part, same real Vivado project + EXP-0086/0088's own N=2 signoffs used. Real post-route utilization + confirmed: 19751 LUTs (31.15%), 34877 registers (27.51%), **128 + DSP48E1/240 (53.33%)** — holds through real place+route, not just + synthesis. **Real timing result: WNS=−0.913ns, WHS=+0.029ns, + TNS=−690.085ns, 3021 failing setup endpoints — TIMING CONSTRAINTS + ARE NOT MET** on the real `clk_pll_i` (155.039MHz) domain, the same + clock N=2's own real EXP-0088 signoff closed at +0.099962ns. + +**Real, honest root cause (traced via the actual worst violated path, +not guessed)**: the critical path runs from one of the 16 real per-PE +`act_tile_fetch.v` FSM state registers, through 11 real logic levels, into +`mig_native_adapter.v`'s own `wdata_lat_reg`. That register is fed by +`sdram_arbiter_n.v`'s own `req_wdata` select mux, which grew from a +3-way select at N=2 to a real **20/21-way** select at N=16 over the +same 256-bit-wide bus — a real, substantial combinational fan-in +increase on the one shared resource every PE's DDR3 write must pass +through. + +**Current real status**: N=16 is **functionally correct (EXP-0092) +but NOT YET timing-closed (EXP-0093)** — honestly not ready for real +hardware at the target clock. This does not invalidate the functional/ +connectivity results; timing closure is a genuinely separate gate. N=2 +(EXP-0088) remains the real, trustworthy, deployable signoff. + +**Not yet done, real and disclosed, real options for closing timing** +(need a real decision on direction before committing more RTL effort): +(1) pipeline `sdram_arbiter_n.v`'s own req_wdata/req_addr mux by one +real cycle — adds one cycle of real arbitration latency per request, +likely acceptable given DDR3's own already-dominant real latency +(EXP-0087); probably the most direct fix, targets the exact real +critical path found above. (2) a real, hierarchical 2-level arbiter +(e.g. 4 groups' own 5-way sub-arbiters feeding one real 4-way top +arbiter) instead of one flat 20/21-way mux. (3) lower the real target +clock for the N=16 variant specifically (a real, unquantified +throughput tradeoff against N=2). See EXP-0093's own `next_action`. **The problem it targets**: plain N=16 independent cores (§5.5's own "documentary, expected to break" framing) means 16 independent DDR3 diff --git a/hardware/v2/logs/experiments.log b/hardware/v2/logs/experiments.log index 3dcd958..c09ae9d 100644 --- a/hardware/v2/logs/experiments.log +++ b/hardware/v2/logs/experiments.log @@ -6311,3 +6311,89 @@ real timing signoff (WNS/WHS), per this project's own standing "real, measured numbers only" discipline -- EXP-0091's own 128 DSP48E1/53.33% utilization projection still needs a real post-route confirmation, and timing has not been checked at all yet for this larger top-level. + +EXP-0093 -- real, full P&R for the N=16 hybrid systolic system: TIMING +FAILS on first attempt (2026-09-21, EXP-0092's own next_action, +continuing the user's "Ok procedi ad implementare quel che manca") + +CONTEXT: EXP-0092 proved the N=16 system functionally correct against +real DDR3 (32/32 PASS); EXP-0091 proved it synthesis-clean with the +projected DSP budget. Neither checked real, in-context, post-route +timing at all. This experiment runs the real, full flow (synth_design ++ opt_design + place_design + route_design) against the real +XC7A100T-CSG324-2 part, in the real Vivado project (same one EXP-0086/ +0088's own real N=2 signoffs used), to find out honestly whether it +closes. + +REAL SETUP FIX FOUND BEFORE TRUSTING THE RUN (per CLAUDE.md's own +stale-import lesson): `NeuralProcessor.srcs/constrs_1/imports/ +constraints/n2_system_ddr3_top.xdc` -- the ONE real constraint file in +the project's `constrs_1` fileset -- was STALE, predating EXP-0084's +real flash-bus bank-16 move and EXP-0088's own result_writeback.v pin +removal (confirmed via a real diff against the live `hardware/v3/ +constraints/n2_system_ddr3_top.xdc`, not assumed). Fixed by overwriting +the imported copy with the live one before running P&R (same real fix +EXP-0084/0086 already established for this exact class of staleness). +Also verified, via a real Vivado fileset query (`get_files -of_objects +[get_filesets sources_1]` + `IS_ENABLED`/`USED_IN`), that every real RTL +dependency of `n16_system_ddr3_top.v` (host_mem_bridge.v, mig_native_ +adapter.v, sdram_arbiter_n.v, spi_host_bridge_v3.v, packed_slot.v, +layer_prefetch_ctrl.v, etc.) resolves to its LIVE `hardware/v3/`/ +`hardware/v2/` path in the active fileset, NOT the several stale +`*/imports/*` copies also found sitting on disk (orphaned leftovers, +never actually `IS_ENABLED` in the current fileset) -- so EXP-0091's +own synthesis-only result was already built on correct RTL; only the +XDC needed fixing before this run. + +REAL RESULT: synth_design/opt_design/place_design/route_design all +completed without error (11 Infos, 1 Warning, 0 Critical Warnings, 0 +Errors from route_design itself). Real post-route utilization: 19751 +LUTs (31.15%), 34877 registers (27.51%), **128 DSP48E1/240 (53.33%)** -- +confirms EXP-0091's projection held through real place+route, not just +synthesis. **Real post-route `report_timing_summary` on the real +`clk_pll_i` domain (the same real 155.039MHz internal system clock +EXP-0086/0088's own N=2 signoff was measured on): WNS=-0.913ns, +WHS=+0.029ns, TNS=-690.085ns, 3021 failing setup endpoints (out of +104247 total on this clock) -- TIMING CONSTRAINTS ARE NOT MET.** This +is a real, measured FAILURE, not a projection -- N=2's own real EXP- +0088 signoff closed at +0.099962ns on the same clock; N=16 does not +close on this first real attempt. + +REAL ROOT CAUSE (traced via the actual worst violated path, not +guessed): the critical path runs from `packed_pe.v`'s own `act_tile_ +fetch.v` FSM state register (one of 16 real per-PE instances, this +occurrence in group 3 / PE 3) through 11 real logic levels (LUT3/ +LUT4x3/LUT6x5/MUXF7/MUXF8 -- a wide mux tree) into `mig_native_ +adapter.v`'s own `wdata_lat_reg[96]`. That destination register is fed +by `sdram_arbiter_n.v`'s own real `req_wdata` selection mux, which grew +from a 3-way select at N=2 (`NUM_REQ=3`) to a real **20-way** select at +N=16 (`NUM_REQ=20` in this test's own scope; 21 in the real top with +host_mem_bridge.v) over the SAME 256-bit-wide (`32*BURST_LEN`) bus -- +a real, substantial combinational fan-in growth on exactly the shared +resource every one of the 16 PEs' own real DDR3 writes must pass +through, not a coincidental or unrelated critical path. + +DECISION: N=16's real RTL is functionally correct (EXP-0092) but NOT +YET timing-closed at the real target clock -- honestly NOT ready for +real hardware at this clock. This is a real, disclosed, not-yet-solved +problem, not a project blocker in itself (N=2 remains the real, +trustworthy, deployable signoff, EXP-0088). Does not invalidate +EXP-0091/0092's own real findings (synthesis-clean, functionally +correct) -- timing closure is a genuinely separate, additional gate, +exactly as CLAUDE.md's own "real numbers only" discipline anticipates +("out-of-context synthesis is not a real signoff"). + +next_action: real options to close timing, not yet attempted (need a +real decision on direction, likely worth discussing before committing +RTL effort): (1) pipeline `sdram_arbiter_n.v`'s own req_wdata/req_addr +mux by one real cycle (adds one cycle of real arbitration latency per +request, likely acceptable given DDR3's own already-dominant real +latency, EXP-0087) -- probably the most direct real fix, targets the +exact real critical path found above. (2) a real, hierarchical 2-level +arbiter (e.g. 4 groups' own 5-way sub-arbiters feeding one real 4-way +top arbiter) instead of one flat 20/21-way mux, reducing the real +fan-in at the final stage. (3) lower the real target clock for the +N=16 variant specifically (a real, measured tradeoff against N=2's own +real throughput, not yet quantified). Real signal-tracing already done +above narrows the fix to the arbiter's own write-data mux specifically +-- future work should start there, not guess elsewhere in the design.