exp: layer_prefetch_ctrl.v, real synthesizable RTL for layer-weight-reuse prefetch, fixes a real address-truncation bug (EXP-0057b)
Built the real FSM version of EXP-0057's own task-based prefetch pattern (bulk-sequential layer fetch via sdram_controller_openrow.v into layer_weight_buffer.v), so it's an actual instantiable module, not just a simulation convenience. Found and fixed a real bug in the process: cur_fill_addr's own address arithmetic bit-sliced BYTES_PER_BURST down to too few bits (BYTES_PER_BURST[BIDXW-1:0]), silently truncating 16 to 0 -- every burst's bytes landed at fill offset 0-15 instead of their real position, overwriting each other (only each layer's last burst survived). Root cause: misapplied a widening idiom used safely elsewhere in this codebase to a case where the target width was actually too small. Found via a standalone control-flow debug test first, then tracing data once control-flow was cleared. Verified: 8192/8192 bit-exact, 0 errors (was 512/8192 before the fix) through the real controller + SDRAM model, 16 layers. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
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Claude Sonnet 5
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`timescale 1ns/1ps
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// ============================================================
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// EXP-0057 -- layer prefetch controller: bulk-sequential fetch of one
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// layer's weights from the real SDRAM controller (sdram_controller_
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// openrow.v's own req/wr/addr/wdata/wmask -> rdata/ready/busy
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// contract, BURST_LEN words per transaction) into a layer_weight_
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// buffer.v's inactive side. Real RTL version of the exact access
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// pattern tb_layer_reuse_vs_zero_reuse.v's own prefetch_layer task
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// already measured (7.16x real memory-side speedup vs zero-reuse,
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// same hardware, see that testbench's own header).
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//
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// One layer = LAYER_BYTES bytes, fetched as LAYER_BYTES/(2*BURST_LEN)
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// back-to-back BURST_LEN-word transactions starting at layer_base
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// (word address). Sequential -> lands in the SAME open row for any
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// layer that fits within one row (1024 columns = 256 tile-blocks at
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// BURST_LEN=8 -- true for any real layer size this project's own
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// target models use), so this composes directly with EXP-0054's
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// open-row policy without needing anything special here.
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//
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// Each captured burst (ctrl_rdata, 16*BURST_LEN bits) is LATCHED
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// locally before draining -- does not assume the controller holds
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// rdata stable beyond the cycle `ready` pulses (its own documented
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// contract is "valid the same cycle ready pulses", nothing more).
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// Drained one byte/cycle via a flat byte-index counter (drain_cnt)
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// indexing directly into the latched burst -- no separate word/byte
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// sub-counters to keep in sync, deliberately simpler than a first
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// draft of this module that tracked them separately and was harder to
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// convince correct by inspection.
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// ============================================================
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module layer_prefetch_ctrl #(
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parameter DATA_WIDTH = 8,
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parameter LAYER_BYTES = 128,
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parameter BURST_LEN = 8,
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parameter ADDR_WIDTH = 25, // matches sdram_controller_openrow.v's own word-address convention
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parameter BUFADDRW = (LAYER_BYTES <= 1) ? 1 : $clog2(LAYER_BYTES)
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)(
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input wire clk,
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input wire rst,
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// ---- job control ----
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input wire start, // pulse: begin fetching `layer_base` into the inactive buffer
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input wire [ADDR_WIDTH-1:0] layer_base, // word address of this layer's weights in SDRAM
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output reg busy,
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output reg done, // pulse: matches layer_weight_buffer.v's own fill_done
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// ---- layer_weight_buffer.v fill side ----
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output reg fill_we,
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output reg [BUFADDRW-1:0] fill_addr,
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output reg [DATA_WIDTH-1:0] fill_data,
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// ---- sdram_controller_openrow.v (or plain sdram_controller.v --
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// identical port contract) ----
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output reg ctrl_req,
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output wire ctrl_wr, // always 0: read-only
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output reg [ADDR_WIDTH-1:0] ctrl_addr,
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output wire [16*BURST_LEN-1:0] ctrl_wdata, // unused (read-only), tied off
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output wire [2*BURST_LEN-1:0] ctrl_wmask, // unused (read-only), tied off
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input wire [16*BURST_LEN-1:0] ctrl_rdata,
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input wire ctrl_ready,
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input wire ctrl_busy
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);
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localparam BYTES_PER_BURST = 2*BURST_LEN;
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localparam BURSTS_PER_LAYER = LAYER_BYTES/BYTES_PER_BURST;
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localparam BIDXW = (BURSTS_PER_LAYER <= 1) ? 1 : $clog2(BURSTS_PER_LAYER);
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localparam DIDXW = $clog2(BYTES_PER_BURST);
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assign ctrl_wr = 1'b0;
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assign ctrl_wdata = {(16*BURST_LEN){1'b0}};
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assign ctrl_wmask = {(2*BURST_LEN){1'b0}};
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localparam S_IDLE = 3'd0,
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S_WAIT = 3'd1,
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S_DRAIN = 3'd2,
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S_TAIL = 3'd3;
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reg [2:0] state;
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reg [BIDXW-1:0] burst_idx;
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reg [DIDXW-1:0] drain_cnt;
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reg [ADDR_WIDTH-1:0] base_lat;
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reg [16*BURST_LEN-1:0] burst_lat;
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// combinational: which byte of the layer is currently being drained
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wire [BUFADDRW-1:0] cur_fill_addr = burst_idx * BYTES_PER_BURST + drain_cnt;
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always @(posedge clk) begin
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if (rst) begin
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state <= S_IDLE;
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busy <= 1'b0;
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done <= 1'b0;
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fill_we <= 1'b0;
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fill_addr <= {BUFADDRW{1'b0}};
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fill_data <= {DATA_WIDTH{1'b0}};
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ctrl_req <= 1'b0;
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ctrl_addr <= {ADDR_WIDTH{1'b0}};
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burst_idx <= {BIDXW{1'b0}};
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drain_cnt <= {DIDXW{1'b0}};
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base_lat <= {ADDR_WIDTH{1'b0}};
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burst_lat <= {(16*BURST_LEN){1'b0}};
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end else begin
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ctrl_req <= 1'b0;
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fill_we <= 1'b0;
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done <= 1'b0;
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case (state)
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S_IDLE: begin
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busy <= 1'b0;
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if (start) begin
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busy <= 1'b1;
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base_lat <= layer_base;
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burst_idx <= {BIDXW{1'b0}};
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ctrl_req <= 1'b1;
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ctrl_addr <= layer_base;
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state <= S_WAIT;
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end
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end
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S_WAIT: begin
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if (ctrl_ready) begin
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burst_lat <= ctrl_rdata;
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drain_cnt <= {DIDXW{1'b0}};
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state <= S_DRAIN;
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end
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end
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S_DRAIN: begin
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fill_we <= 1'b1;
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fill_addr <= cur_fill_addr;
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fill_data <= burst_lat[drain_cnt*8 +: 8];
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if (drain_cnt == BYTES_PER_BURST - 1) begin
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// this cycle drains the LAST byte of this burst
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if (burst_idx == BURSTS_PER_LAYER - 1) begin
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// last burst of the layer too -- one more
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// cycle for this final fill_we to land, then done
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state <= S_IDLE; // will be overridden below to a tail state
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end else begin
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burst_idx <= burst_idx + 1'b1;
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ctrl_req <= 1'b1;
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ctrl_addr <= base_lat + ((burst_idx + 1'b1) * BURST_LEN[ADDR_WIDTH-1:0]);
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state <= S_WAIT;
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end
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end else begin
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drain_cnt <= drain_cnt + 1'b1;
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end
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if (drain_cnt == BYTES_PER_BURST - 1 &&
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burst_idx == BURSTS_PER_LAYER - 1) begin
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state <= S_TAIL;
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end
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end
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S_TAIL: begin
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// the last fill_we (asserted combinationally in the
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// S_DRAIN cycle above) is landing on THIS clock edge's
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// rising edge as far as layer_weight_buffer.v is
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// concerned (fill_we/_addr/_data were registered
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// outputs of the previous cycle) -- signal done now.
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busy <= 1'b0;
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done <= 1'b1;
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state <= S_IDLE;
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end
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default: state <= S_IDLE;
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endcase
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end
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end
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endmodule
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