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feat: MILESTONE - real activation-fetch engine, full N=2 system verified on real DDR3 (EXP-0079)

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Closes the last major disclosed functional gap: packed_slot.v's
activation data was read through a combinational stand-in since
EXP-0062. New act_tile_fetch.v reads activation tiles directly from
DDR3 (no on-chip buffering needed, unlike weights -- activation data
has no reuse), sharing each slot's existing ctrl port with its own
weight-prefetch engine. Real memory layout: one full BURST_LEN=8-word
burst per tile, deliberately avoiding any runtime-indexed part-select
given this project's thin P&R timing margin (EXP-0078).

Verified at three levels: act_tile_fetch.v alone (6/6), packed_slot.v
with real preloaded activation data (9/9), and the full N=2 system
against real DDR3 via xsim (8/8, 0 errors) -- the first time this
project's compute path has been verified end-to-end with real DDR3
for both weights and activations.

Retired hardware/v3/rtl/n2_system_top.v and its testbench (pre-DDR3
SDR-placeholder era, fully superseded by n2_system_ddr3_top.v).

Also: docs/PHYSICAL_REALIZATION.md (real pinout/parts/timing/protocol
reference for the physical board) and CLAUDE.md (persistent project
instructions for future Claude Code sessions).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
michele
2026-09-20 08:13:15 +02:00
co-authored by Claude Sonnet 5
parent 78577dde59
commit 43a12379a5
11 changed files with 946 additions and 682 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hardware/v3/rtl/packed_slot.v
+97 -32
View File
@@ -14,17 +14,30 @@
// packed.v already expects (job_start/x_base_a/b/w_base/n_tiles/
// node_id_a/b -> job_done/result_data_a/b/result_node_id_a/b).
//
// SCOPE LIMITATION (disclosed, matches this project's own established
// precedent -- EXP-0058/0062's own header comments: "activation data
// ... representing the activation/sliding-window path, which is a
// separate, already-existing memory path not the subject of this
// test"): activations are read through a WIDE, per-tile, combinational
// stand-in port (act_tile_addr_a/b -> act_tile_data_a/b), mirroring
// this project's own earlier ideal_memory_model.v-style staging
// (establish the architectural contract before committing to a
// specific real fetch engine). A real activation fetch engine
// (analogous to weight_tile_gather.v, but for the sliding-window/
// activation path) is a separate, later deliverable, NOT built here.
// ACTIVATION FETCH (EXP-0079, real, closes the gap this header used to
// disclose as deferred): act_tile_fetch.v reads each tile's activation
// data DIRECTLY from the shared DDR3 bus, one tile at a time -- no
// on-chip buffering/prefetch (unlike weights, activation data is read
// exactly once per job, so buffering it would add complexity for zero
// reuse benefit). It shares THIS slot's own single ctrl_req/addr/etc
// port with layer_prefetch_ctrl.v (u_pf): the two are mutually
// exclusive in time by FSM construction (weight prefetch always fully
// completes, including its own consume_done, before the tile loop
// that needs activation data ever starts), muxed below on act_mem_
// active. The outer arbiter's grant (mem_active/mem_grant, this
// module's own top-level ports) is now also needed during activation
// fetch, not just weight prefetch -- held PER TILE (one 2-burst fetch,
// lane A then lane B), released between tiles, matching this
// project's own established "lock the grant for one whole logical
// fetch, not longer" discipline (avoids starving the other slot for
// the whole tile loop's duration).
//
// MEMORY LAYOUT this requires of activation data in DDR3: each tile
// occupies its own full BURST_LEN=8-word burst slot (see act_tile_
// fetch.v's own header for why -- avoiding a runtime-indexed part-
// select, a known Fmax risk this project's already-thin P&R margin,
// EXP-0078, can't afford right now). Documented for whoever prepares
// host-side data layout in the physical realization doc.
//
// Also disclosed: no result-writeback engine exists yet either --
// result_addr_a/b are passed through unused, for a future writeback
@@ -72,18 +85,11 @@ module packed_slot #(
output reg [ADDR_WIDTH-1:0] result_addr_b_out,
// high exactly while this slot needs exclusive access to the
// shared SDRAM controller (its own weight-fetch phase) -- a
// shared-controller arbiter uses this to lock a grant for the
// whole multi-burst fetch, not just one transaction.
// shared SDRAM controller (its own weight-fetch OR activation-
// fetch phase) -- a shared-controller arbiter uses this to lock a
// grant for the whole multi-burst fetch, not just one transaction.
output wire mem_active,
// ---- activation stand-in port (see header -- real fetch engine
// deferred) ----
output reg [ADDR_WIDTH-1:0] act_tile_addr_a,
output reg [ADDR_WIDTH-1:0] act_tile_addr_b,
input wire signed [DATA_WIDTH*P_IN-1:0] act_tile_data_a,
input wire signed [DATA_WIDTH*P_IN-1:0] act_tile_data_b,
// grant from a shared-controller arbiter (see mem_active's own
// comment): must be asserted before this slot may pulse its own
// layer_prefetch_ctrl.v start, since that module's ctrl_req is a
@@ -118,7 +124,6 @@ module packed_slot #(
S_DONE = 4'd9;
reg [3:0] state;
assign mem_active = (state == S_MEMWAIT) || (state == S_PREFETCH);
reg [ADDR_WIDTH-1:0] w_base_lat, x_base_a_lat, x_base_b_lat;
reg [15:0] n_tiles_lat;
reg [ADDR_WIDTH-1:0] result_addr_a_lat, result_addr_b_lat;
@@ -132,17 +137,58 @@ module packed_slot #(
wire [BUFADDRW-1:0] pf_fill_addr;
wire [DATA_WIDTH-1:0] pf_fill_data;
wire pf_ctrl_req, pf_ctrl_wr;
wire [ADDR_WIDTH-2:0] pf_ctrl_addr;
wire [16*BURST_LEN-1:0] pf_ctrl_wdata;
wire [2*BURST_LEN-1:0] pf_ctrl_wmask;
layer_prefetch_ctrl #(
.DATA_WIDTH(DATA_WIDTH), .LAYER_BYTES(LAYER_BYTES), .BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH-1)
) u_pf (
.clk(clk), .rst(rst),
.start(pf_start), .layer_base(w_base_lat[ADDR_WIDTH-2:0]), .busy(pf_busy), .done(pf_done),
.fill_we(pf_fill_we), .fill_addr(pf_fill_addr), .fill_data(pf_fill_data),
.ctrl_req(ctrl_req), .ctrl_wr(ctrl_wr), .ctrl_addr(ctrl_addr),
.ctrl_wdata(ctrl_wdata), .ctrl_wmask(ctrl_wmask),
.ctrl_req(pf_ctrl_req), .ctrl_wr(pf_ctrl_wr), .ctrl_addr(pf_ctrl_addr),
.ctrl_wdata(pf_ctrl_wdata), .ctrl_wmask(pf_ctrl_wmask),
.ctrl_rdata(ctrl_rdata), .ctrl_ready(ctrl_ready), .ctrl_busy(ctrl_busy)
);
// ---- act_tile_fetch.v (EXP-0079): real activation fetch, shares
// this slot's own ctrl port with u_pf above (mutually exclusive in
// time -- see header) ----
reg act_req;
wire act_valid;
wire signed [DATA_WIDTH*P_IN-1:0] act_data_a_w, act_data_b_w;
wire act_mem_active;
wire act_ctrl_req, act_ctrl_wr;
wire [ADDR_WIDTH-2:0] act_ctrl_addr;
wire [16*BURST_LEN-1:0] act_ctrl_wdata;
wire [2*BURST_LEN-1:0] act_ctrl_wmask;
act_tile_fetch #(
.DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .BURST_LEN(BURST_LEN), .ADDR_WIDTH(ADDR_WIDTH-1)
) u_act (
.clk(clk), .rst(rst),
.req(act_req), .base_a(x_base_a_lat[ADDR_WIDTH-2:0]), .base_b(x_base_b_lat[ADDR_WIDTH-2:0]),
.tcnt(tcnt), .valid(act_valid), .data_a(act_data_a_w), .data_b(act_data_b_w),
.mem_active(act_mem_active), .mem_grant(mem_grant),
.ctrl_req(act_ctrl_req), .ctrl_wr(act_ctrl_wr), .ctrl_addr(act_ctrl_addr),
.ctrl_wdata(act_ctrl_wdata), .ctrl_wmask(act_ctrl_wmask),
.ctrl_rdata(ctrl_rdata), .ctrl_ready(ctrl_ready), .ctrl_busy(ctrl_busy)
);
// mutually exclusive by FSM construction (weight prefetch always
// fully completes, incl. consume_done, before the tile loop that
// triggers act_req ever starts) -- safe to select on act_mem_active alone.
assign ctrl_req = act_mem_active ? act_ctrl_req : pf_ctrl_req;
assign ctrl_wr = act_mem_active ? act_ctrl_wr : pf_ctrl_wr;
assign ctrl_addr = act_mem_active ? act_ctrl_addr : pf_ctrl_addr;
assign ctrl_wdata = act_mem_active ? act_ctrl_wdata : pf_ctrl_wdata;
assign ctrl_wmask = act_mem_active ? act_ctrl_wmask : pf_ctrl_wmask;
assign mem_active = (state == S_MEMWAIT) || (state == S_PREFETCH) || act_mem_active;
// ---- layer_weight_buffer.v ----
wire [BUFADDRW-1:0] lwb_rd_addr;
wire [DATA_WIDTH-1:0] lwb_rd_data;
@@ -158,6 +204,7 @@ module packed_slot #(
// ---- weight_tile_gather.v ----
reg tile_req;
reg [BUFADDRW-1:0] tile_base;
reg tile_seen, act_seen; // S_TILEWAIT join latches (weight vs activation, see header)
wire tile_valid;
wire [DATA_WIDTH*P_IN-1:0] tile_data;
@@ -214,6 +261,9 @@ module packed_slot #(
pf_start <= 1'b0;
consume_done <= 1'b0;
tile_req <= 1'b0;
act_req <= 1'b0;
tile_seen <= 1'b0;
act_seen <= 1'b0;
job_valid_np <= 1'b0;
operand_valid<= 1'b0;
tile_last <= 1'b0;
@@ -226,6 +276,7 @@ module packed_slot #(
pf_start <= 1'b0;
consume_done <= 1'b0;
tile_req <= 1'b0;
act_req <= 1'b0;
case (state)
S_IDLE: begin
@@ -278,19 +329,33 @@ module packed_slot #(
S_TILEREQ: begin
tile_req <= 1'b1;
tile_base <= tcnt[BUFADDRW-1:0]*P_IN[BUFADDRW-1:0];
act_tile_addr_a <= x_base_a_lat + {{(ADDR_WIDTH-16){1'b0}}, tcnt};
act_tile_addr_b <= x_base_b_lat + {{(ADDR_WIDTH-16){1'b0}}, tcnt};
act_req <= 1'b1;
tile_seen <= 1'b0;
act_seen <= 1'b0;
state <= S_TILEWAIT;
end
// Real join: weight_tile_gather.v's tile_valid (fast,
// on-chip) and act_tile_fetch.v's act_valid (real
// DDR3 latency, 2 bursts) do NOT arrive on the same
// cycle in general -- latch whichever comes first,
// proceed only once BOTH have been seen. Handles
// either arrival order correctly, not just the
// expected-common one (weight first).
S_TILEWAIT: begin
if (tile_valid) begin
weight_data_r <= tile_data;
input_data_a_r <= act_tile_data_a;
input_data_b_r <= act_tile_data_b;
tile_last <= (tcnt == n_tiles_lat - 16'd1);
operand_valid <= 1'b1;
state <= S_OPERAND;
weight_data_r <= tile_data;
tile_seen <= 1'b1;
end
if (act_valid) begin
input_data_a_r <= act_data_a_w;
input_data_b_r <= act_data_b_w;
act_seen <= 1'b1;
end
if ((tile_valid || tile_seen) && (act_valid || act_seen)) begin
tile_last <= (tcnt == n_tiles_lat - 16'd1);
operand_valid <= 1'b1;
state <= S_OPERAND;
end
end