feat(v2): M5 Neural Director, first-free job scheduling
Implements M5: neural_director.v dispatches job descriptors to whichever of N_SLOTS (memory_manager, neural_processor) pairs is currently free (first-free scheduling per §9's initial policy), with a parametric-depth ready-queue FIFO for jobs arriving faster than slots can absorb them. Scope for this milestone (see decisions.log DEC-0007): a reduced 4-state FSM (DIR_IDLE/SCAN_READY/ALLOCATE/ERROR) rather than §9's full 8-state baseline -- dependency tracking, the waiting queue, and wake-up are §10's explicit responsibility (Dependency Manager, M6, not yet built), and slot-completion detection runs as an always-active per-slot tracker rather than a dedicated FSM state, for the same reason DEC-0002 already gave for the Neural Processor's own FSM (gating concurrent per-unit progress behind one shared state kills throughput). Verified with Verilator (N_SLOTS=2, each slot backed by its own independent behavioral memory rather than sharing V1's real PSRAM -- M4 already proved that path for one slot; this milestone's own concern is scheduling across multiple slots): 4/4 tests pass -- 3 jobs submitted to 2 slots (first two dispatch immediately, third correctly queues until a slot frees), and a deliberate burst that forces the ready queue to genuinely fill and recover. Real synthesis: 0 CHECK problems, 382 LUT4/366 FF/4 CCU2C/0 DSP. Real place&route (via a synthesis-only timing harness, same TRELLIS_IO pin-budget reason as M2/M4): Fmax 250.50 MHz, PASS at 80MHz. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
Claude Sonnet 5
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Info: Logic utilisation before packing:
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Info: Total LUT4s: 163/43848 0%
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Info: logic LUTs: 107/43848 0%
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Info: carry LUTs: 8/43848 0%
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Info: RAM LUTs: 32/ 5481 0%
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Info: RAMW LUTs: 16/10962 0%
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Info: Total DFFs: 98/43848 0%
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Info: Packing IOs..
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Info: Packing constants..
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Info: Packing carries...
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Info: Packing LUTs...
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Info: Packing LUT5-7s...
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Info: Packing FFs...
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Info: 66 FFs paired with LUTs.
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Info: Generating derived timing constraints...
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Info: Promoting globals...
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Info: promoting clock net clk$TRELLIS_IO_IN to global network
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Info: Checksum: 0x77eb46c4
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Info: Device utilisation:
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Info: TRELLIS_IO: 18/ 245 7%
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Info: DCCA: 1/ 56 1%
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Info: DP16KD: 0/ 108 0%
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Info: MULT18X18D: 0/ 72 0%
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Info: ALU54B: 0/ 36 0%
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Info: EHXPLLL: 0/ 4 0%
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Info: EXTREFB: 0/ 2 0%
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Info: DCUA: 0/ 2 0%
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Info: PCSCLKDIV: 0/ 2 0%
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Info: IOLOGIC: 0/ 160 0%
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Info: SIOLOGIC: 0/ 85 0%
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Info: GSR: 0/ 1 0%
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Info: JTAGG: 0/ 1 0%
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Info: OSCG: 0/ 1 0%
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Info: SEDGA: 0/ 1 0%
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Info: DTR: 0/ 1 0%
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Info: USRMCLK: 0/ 1 0%
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Info: CLKDIVF: 0/ 4 0%
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Info: ECLKSYNCB: 0/ 10 0%
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Info: DLLDELD: 0/ 8 0%
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Info: DDRDLL: 0/ 4 0%
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Info: DQSBUFM: 0/ 10 0%
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Info: TRELLIS_ECLKBUF: 0/ 8 0%
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Info: ECLKBRIDGECS: 0/ 2 0%
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Info: DCSC: 0/ 2 0%
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Info: TRELLIS_FF: 98/ 43848 0%
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Info: TRELLIS_COMB: 169/ 43848 0%
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Info: TRELLIS_RAMW: 8/ 5481 0%
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Info: Placed 0 cells based on constraints.
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Info: Creating initial analytic placement for 134 cells, random placement wirelen = 12480.
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Info: at initial placer iter 0, wirelen = 1480
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Info: at initial placer iter 1, wirelen = 1128
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Info: at initial placer iter 2, wirelen = 1103
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Info: at initial placer iter 3, wirelen = 1100
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Info: Running main analytical placer, max placement attempts per cell = 10804.
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Info: at iteration #1, type ALL: wirelen solved = 1119, spread = 1315, legal = 1359; time = 0.00s
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Info: HeAP Placer Time: 0.02s
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Info: of which solving equations: 0.01s
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Info: of which spreading cells: 0.00s
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Info: of which strict legalisation: 0.00s
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Info: Running simulated annealing placer for refinement.
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Info: at iteration #1: temp = 0.000000, timing cost = 12, wirelen = 1359
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Info: at iteration #5: temp = 0.000000, timing cost = 33, wirelen = 1072
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Info: at iteration #10: temp = 0.000000, timing cost = 31, wirelen = 1074
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Info: at iteration #12: temp = 0.000000, timing cost = 23, wirelen = 1051
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Info: SA placement time 0.05s
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 275.10 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.52 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 4.86 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 8865, 9019) |*********************
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Info: [ 9019, 9173) |*******************
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Info: [ 9173, 9327) |*****************
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Info: [ 9327, 9481) |**************
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Info: [ 9481, 9635) |***
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Info: [ 9635, 9789) |***
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Info: [ 9789, 9943) |**
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Info: [ 9943, 10097) |****
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Info: [ 10097, 10251) |*****
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Info: [ 10251, 10405) |*****
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Info: [ 10405, 10559) |**************
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Info: [ 10559, 10713) |********************************
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Info: [ 10713, 10867) |*****************************************
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Info: [ 10867, 11021) |************************************
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Info: [ 11021, 11175) |****************************
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Info: [ 11175, 11329) |******************************
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Info: [ 11329, 11483) |****
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Info: [ 11483, 11637) |************
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Info: [ 11637, 11791) |***************
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Info: [ 11791, 11945) |***
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Info: Checksum: 0x23c4f63e
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Info: Routing globals...
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Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0
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Info: Routing..
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Info: Setting up routing queue.
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Info: Routing 887 arcs.
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Info: | (re-)routed arcs | delta | remaining| time spent |
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Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)|
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Info: 1000 | 154 829 | 154 829 | 48| 0.08 0.08|
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Info: 1047 | 154 875 | 0 46 | 0| 0.04 0.11|
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Info: Routing complete.
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Info: Router1 time 0.11s
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Info: Checksum: 0x86bbec10
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Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge):
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source dut.slot_busy_TRELLIS_FF_Q_2.Q
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Info: routing 0.68 1.07 Net dut.dir_state_LUT4_D_Z[1] (27,37) -> (28,37)
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Info: Sink dut.slot_busy_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C_D_CCU2C_S0_B0_LUT4_Z.D
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Info: Defined in:
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Info: hardware/v2/rtl/neural_director.v:93.23-93.32
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Info: logic 0.18 1.25 Source dut.slot_busy_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C_D_CCU2C_S0_B0_LUT4_Z.F
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Info: routing 0.85 2.10 Net dut.slot_busy_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C_D_CCU2C_S0_B0 (28,37) -> (30,38)
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Info: Sink dut.slot_busy_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C_D_CCU2C_S0$CCU2_COMB0.B
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Info: logic 0.35 2.46 Source dut.slot_busy_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C_D_CCU2C_S0$CCU2_COMB0.FCO
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Info: routing 0.00 2.46 Net dut.slot_busy_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C_D_CCU2C_S0$CCU2_FCI_INT (30,38) -> (30,38)
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Info: Sink dut.slot_busy_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C_D_CCU2C_S0$CCU2_COMB1.FCI
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Info: logic 0.29 2.75 Source dut.slot_busy_TRELLIS_FF_Q_DI_LUT4_Z_D_LUT4_C_D_CCU2C_S0$CCU2_COMB1.F
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Info: routing 0.94 3.69 Net dut.dir_state_LUT4_D_Z[3] (30,38) -> (28,35)
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Info: Sink dut.q_w_base.0.1_DO_LUT4_B_Z_LUT4_Z.D
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Info: Defined in:
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Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24
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Info: logic 0.18 3.87 Source dut.q_w_base.0.1_DO_LUT4_B_Z_LUT4_Z.F
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Info: routing 0.12 3.99 Net dut.q_w_base.0.1_DO_LUT4_B_Z[2] (28,35) -> (28,35)
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Info: Sink dut.slot_w_base_TRELLIS_FF_Q_2.DI
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Info: setup 0.00 3.99 Source dut.slot_w_base_TRELLIS_FF_Q_2.DI
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Info: 1.40 ns logic, 2.59 ns routing
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Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk$TRELLIS_IO_IN':
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Info: type curr total name
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Info: source 0.00 0.00 Source rst$tr_io.O
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Info: routing 2.75 2.75 Net rst$TRELLIS_IO_IN (29,0) -> (29,37)
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Info: Sink dut.slot_job_start_TRELLIS_FF_Q_LSR_LUT4_Z.C
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Info: Defined in:
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Info: hardware/v2/synthesis/harness_neural_director.v:15.17-15.20
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Info: logic 0.18 2.93 Source dut.slot_job_start_TRELLIS_FF_Q_LSR_LUT4_Z.F
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Info: routing 0.47 3.40 Net dut.slot_job_start_TRELLIS_FF_Q_LSR (29,37) -> (28,36)
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Info: Sink dut.slot_job_start_TRELLIS_FF_Q_3.LSR
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Info: setup 0.29 3.68 Source dut.slot_job_start_TRELLIS_FF_Q_3.LSR
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Info: 0.47 ns logic, 3.22 ns routing
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Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '<async>':
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Info: type curr total name
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Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_5.Q
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Info: routing 2.94 3.34 Net checksum[6]$TRELLIS_IO_OUT (32,39) -> (90,38)
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Info: Sink checksum[6]$tr_io.I
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Info: Defined in:
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Info: hardware/v2/synthesis/harness_neural_director.v:57.15-57.18
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Info: 0.40 ns logic, 2.94 ns routing
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Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 250.50 MHz (PASS at 80.00 MHz)
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Info: Max delay <async> -> posedge $glbnet$clk$TRELLIS_IO_IN: 3.68 ns
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Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> <async> : 3.34 ns
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Info: Slack histogram:
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Info: legend: * represents 1 endpoint(s)
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Info: + represents [1,1) endpoint(s)
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Info: [ 8508, 8673) |**
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Info: [ 8673, 8838) |********
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Info: [ 8838, 9003) |***********************
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Info: [ 9003, 9168) |******
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Info: [ 9168, 9333) |***********************
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Info: [ 9333, 9498) |****************
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Info: [ 9498, 9663) |*
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Info: [ 9663, 9828) |
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Info: [ 9828, 9993) |***
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Info: [ 9993, 10158) |*
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Info: [ 10158, 10323) |*******
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Info: [ 10323, 10488) |****
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Info: [ 10488, 10653) |*********
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Info: [ 10653, 10818) |*****************************
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Info: [ 10818, 10983) |***************************
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Info: [ 10983, 11148) |******************************************
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Info: [ 11148, 11313) |***************************************
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Info: [ 11313, 11478) |***********************************
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Info: [ 11478, 11643) |********************
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Info: [ 11643, 11808) |*************
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Info: Program finished normally.
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