feat(v2): M5 Neural Director, first-free job scheduling

Implements M5: neural_director.v dispatches job descriptors to
whichever of N_SLOTS (memory_manager, neural_processor) pairs is
currently free (first-free scheduling per §9's initial policy), with
a parametric-depth ready-queue FIFO for jobs arriving faster than
slots can absorb them.

Scope for this milestone (see decisions.log DEC-0007): a reduced
4-state FSM (DIR_IDLE/SCAN_READY/ALLOCATE/ERROR) rather than §9's full
8-state baseline -- dependency tracking, the waiting queue, and
wake-up are §10's explicit responsibility (Dependency Manager, M6, not
yet built), and slot-completion detection runs as an always-active
per-slot tracker rather than a dedicated FSM state, for the same
reason DEC-0002 already gave for the Neural Processor's own FSM
(gating concurrent per-unit progress behind one shared state kills
throughput).

Verified with Verilator (N_SLOTS=2, each slot backed by its own
independent behavioral memory rather than sharing V1's real PSRAM --
M4 already proved that path for one slot; this milestone's own concern
is scheduling across multiple slots): 4/4 tests pass -- 3 jobs
submitted to 2 slots (first two dispatch immediately, third correctly
queues until a slot frees), and a deliberate burst that forces the
ready queue to genuinely fill and recover.

Real synthesis: 0 CHECK problems, 382 LUT4/366 FF/4 CCU2C/0 DSP. Real
place&route (via a synthesis-only timing harness, same TRELLIS_IO
pin-budget reason as M2/M4): Fmax 250.50 MHz, PASS at 80MHz.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

This commit is contained in:

michele

2026-09-05 14:46:32 +02:00

co-authored by

Claude Sonnet 5

parent 175f697ae1

commit 2e4cedc761

18 changed files with 82810 additions and 1 deletions

hardware/v2/logs/simulation.log

View File

@@ -48,3 +48,9 @@ bit-exact result: PSRAM-read-back result byte matches hand-computed
   RTL under test)
 cycles: 446 (3 tiles), 166 (1 tile), 728 (5 tiles) -- real PSRAM
   latency dominates, not memory_manager's own control overhead
 [2026-09-05] EXP-0006 -- hardware/v2/sim/tb_neural_director.v
 test: 4 cases (3-jobs-2-slots first-free dispatch + queueing,
   backpressure fill/recover)
 simulator: Verilator 5.050 (--binary --timing)
 PASS/FAIL: 4/4 PASS