feat: N=8 hybrid systolic promoted to the real, definitive deployment target (EXP-0096)

New n8_system_ddr3_top.v: a real, permanent, named top-level (not a
build-time -generic override), byte-for-byte the same RTL as
n16_system_ddr3_top.v with N_GROUPS defaulting to 2. Real, full P&R
under this file's own name reproduces EXP-0095's own generic-override
result exactly: WNS=0.000ns, WHS=+0.017ns, 0 failing setup endpoints,
64 DSP48E1/26.7%, 12535 LUTs/19.77%.

New tb_n8_system_ddr3.v (real DDR3-model methodology, adapted from
tb_n16_system_ddr3.v, M=16 positions covering every one of the 2
groups x 4 PEs x 2 lanes exactly once): real functional xsim, 16/16
PASS, 0 errors -- closes the real functional-verification gap this
specific N previously had.

N=8 is now BOTH functionally verified AND timing-closed under its own
permanent name -- the real, definitive deployment target. N=2 kept as
a documented, valid fallback; N=16 kept as documented, functionally-
verified-but-not-timing-closed future work, not abandoned.

docs/PHYSICAL_REALIZATION.md, docs/ARCHITECTURE_ANALYSIS.md,
docs/PINOUT.md updated to reflect N=8 as the current real signoff.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

hardware/v2/logs/experiments.log

@@ -6720,3 +6720,67 @@ DIRECTLY measured at N=16 so far). (2) optionally, real P&R at N=12
 (N_GROUPS=3) to pin down the exact real N where the WNS trend crosses
 zero. (3) optionally, a real re-attempt at N=4 (likely closes on retry,
 given how close -0.005ns already is).
+
+EXP-0096 -- N=8 promoted to the real, definitive deployment target:
+dedicated top-level, real P&R re-confirmed under its own name, real
+functional xsim 16/16 PASS (2026-09-21, user's own explicit direction:
+"si creaiamo una versione funzionante completamente per n=8 la
+pushiamo come versione definitiva")
+
+CONTEXT: EXP-0095's own real N=8 closure (WNS=0.000ns) was measured via
+a build-time `synth_design -generic N_GROUPS=2` override against
+n16_system_ddr3_top.v -- real and trustworthy, but not yet a real,
+permanent, named top-level file (this project's own established
+convention: one real file per real deployment configuration, e.g.
+n2_system_ddr3_top.v), and not yet functionally verified at this
+specific N (only N=16's full-scale RTL had a dedicated functional
+xsim, EXP-0092/0094).
+
+METHOD: (1) new `hardware/v3/rtl/n8_system_ddr3_top.v` -- byte-for-byte
+the same real RTL structure as n16_system_ddr3_top.v, N_GROUPS
+defaulting to 2 instead of 4 (still a real, visible parameter, not
+hardcoded away), real header documenting this as the definitive
+2026-09-21 target. (2) new `hardware/v3/sim/tb_n8_system_ddr3.v`,
+directly adapted from tb_n16_system_ddr3.v's own real DDR3-model
+methodology (same real 2-chip 32-bit DDR3 model, same real
+mig_7series_0_mig, real Vivado xsim), scaled to N_GROUPS=2/M=16
+positions (exercises every one of the 2 groups x 4 PEs x 2 lanes
+exactly once). (3) real, full P&R re-run under n8_system_ddr3_top.v's
+own real name (added to the real Vivado project's sources_1 fileset as
+a direct reference, real stale-import check confirmed empty before
+trusting the result) with the same real directive stack that closed
+N=8 the first time (EXP-0094/0095: Explore/ExtraNetDelay_high/
+AggressiveExplore).
+
+REAL RESULT: P&R under the real n8_system_ddr3_top.v name gives the
+EXACT SAME real numbers as EXP-0095's own generic-override result --
+**WNS=0.000ns, TNS=0.000ns, 0 failing setup endpoints, WHS=+0.017ns**,
+12535 LUTs (19.77%), 19902 registers (15.70%), 64 DSP48E1/240 (26.7%)
+-- confirms the real file split was done correctly, byte-for-byte
+equivalent RTL. Real functional xsim (`tb_n8_system_ddr3.v`, real DDR3
+model, real Vivado xsim): **16/16 PASS, 0 errors**, `$finish` at
+131145.8335ns -- closes the real, disclosed functional-verification
+gap for this specific N.
+
+DECISION: N=8 (`n8_system_ddr3_top.v`) is now the real, definitive
+deployment target -- BOTH functionally verified AND timing-closed
+under its own permanent real name, not a build-time override. Real,
+disclosed caveat carried forward: WNS=0.000ns is an exact-zero real
+margin, not a comfortable one -- any future RTL change to this top-
+level or its dependents needs a fresh real P&R (same directive stack)
+before trusting timing again, per this project's own "re-verify after
+any further logic addition" discipline.
+
+`docs/PHYSICAL_REALIZATION.md` §3 and §7, and
+`docs/ARCHITECTURE_ANALYSIS.md`'s own top-of-document pointer, updated
+to promote this as the current real signoff (replacing the EXP-0088
+N=2 pointer) -- N=2 (`n2_system_ddr3_top.v`) kept documented as a real,
+valid, simpler fallback; N=16 (`n16_system_ddr3_top.v`) kept documented
+as real, functionally-verified-but-not-timing-closed future work, not
+abandoned.
+
+next_action: real board bring-up planning (schematic capture from
+docs/PINOUT.md, BOM confirmation from docs/BOM.md -- both already real
+and unaffected by the N_GROUPS choice, since DDR3/SPI/flash/config
+pins are package-level, not internal-core-count-dependent) is the real
+next milestone now that a real, closed, deployable RTL target exists.