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feat: N=8 hybrid systolic promoted to the real, definitive deployment target (EXP-0096)

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New n8_system_ddr3_top.v: a real, permanent, named top-level (not a
build-time -generic override), byte-for-byte the same RTL as
n16_system_ddr3_top.v with N_GROUPS defaulting to 2. Real, full P&R
under this file's own name reproduces EXP-0095's own generic-override
result exactly: WNS=0.000ns, WHS=+0.017ns, 0 failing setup endpoints,
64 DSP48E1/26.7%, 12535 LUTs/19.77%.

New tb_n8_system_ddr3.v (real DDR3-model methodology, adapted from
tb_n16_system_ddr3.v, M=16 positions covering every one of the 2
groups x 4 PEs x 2 lanes exactly once): real functional xsim, 16/16
PASS, 0 errors -- closes the real functional-verification gap this
specific N previously had.

N=8 is now BOTH functionally verified AND timing-closed under its own
permanent name -- the real, definitive deployment target. N=2 kept as
a documented, valid fallback; N=16 kept as documented, functionally-
verified-but-not-timing-closed future work, not abandoned.

docs/PHYSICAL_REALIZATION.md, docs/ARCHITECTURE_ANALYSIS.md,
docs/PINOUT.md updated to reflect N=8 as the current real signoff.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
michele
2026-09-21 08:29:04 +02:00
co-authored by Claude Sonnet 5
parent 6d06404428
commit 264950923b
6 changed files with 1006 additions and 51 deletions
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docs/PINOUT.md
+7 -3
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@@ -6,9 +6,13 @@ board). This is a flattened, board-layout-ready extract of
narrated source (it explains *why* each pin was chosen and every real
conflict/fix found along the way); this file is the quick reference for
schematic capture. Every pin below comes from a real routed design
(`n2_system_ddr3_top_routed.dcp`, EXP-0086 signoff) or the MIG-generated
`mig_7series_0.xdc` — none of it is guessed. Re-generate this file if
`docs/PHYSICAL_REALIZATION.md` §2 ever changes.
(originally `n2_system_ddr3_top_routed.dcp`, EXP-0086; the same real pin
set — DDR3/SPI/flash/config are all package-level, unaffected by internal
core count — was re-confirmed real and unchanged in `n8_system_ddr3_top.v`'s
own real routed signoff, EXP-0095/0096, now the current definitive
deployment target, see `docs/PHYSICAL_REALIZATION.md` §3) or the
MIG-generated `mig_7series_0.xdc` — none of it is guessed. Re-generate
this file if `docs/PHYSICAL_REALIZATION.md` §2 ever changes.
## Bank summary