feat: N=8 hybrid systolic promoted to the real, definitive deployment target (EXP-0096)

New n8_system_ddr3_top.v: a real, permanent, named top-level (not a
build-time -generic override), byte-for-byte the same RTL as
n16_system_ddr3_top.v with N_GROUPS defaulting to 2. Real, full P&R
under this file's own name reproduces EXP-0095's own generic-override
result exactly: WNS=0.000ns, WHS=+0.017ns, 0 failing setup endpoints,
64 DSP48E1/26.7%, 12535 LUTs/19.77%.

New tb_n8_system_ddr3.v (real DDR3-model methodology, adapted from
tb_n16_system_ddr3.v, M=16 positions covering every one of the 2
groups x 4 PEs x 2 lanes exactly once): real functional xsim, 16/16
PASS, 0 errors -- closes the real functional-verification gap this
specific N previously had.

N=8 is now BOTH functionally verified AND timing-closed under its own
permanent name -- the real, definitive deployment target. N=2 kept as
a documented, valid fallback; N=16 kept as documented, functionally-
verified-but-not-timing-closed future work, not abandoned.

docs/PHYSICAL_REALIZATION.md, docs/ARCHITECTURE_ANALYSIS.md,
docs/PINOUT.md updated to reflect N=8 as the current real signoff.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

docs/ARCHITECTURE_ANALYSIS.md

@@ -1,11 +1,16 @@
 # FPGA-Neural V3 — Architecture Analysis: Timing, Bottlenecks, and Recommended Interventions
 
 Scope: the current, real, P&R-verified V3 design (`hardware/v3/`, branch
-`v3-artix7`), updated through EXP-0088 (result-writeback engine, real,
-closed timing). The current real, trustworthy *timing* signoff is now
-EXP-0088 (32-bit, 155.039MHz, WNS +0.100ns), replacing EXP-0086's own
-pointer (which itself replaced EXP-0083's 16-bit-era one). Every number
-in this document is either
+`v3-artix7`), updated through EXP-0095/0096 (N=8 hybrid systolic, real,
+closed timing — the current, definitive real deployment target, chosen
+by the user after a real, measured N=4/8/16 timing curve). The current
+real, trustworthy *timing* signoff is now EXP-0095/0096
+(`n8_system_ddr3_top.v`, 32-bit DDR3, 155.039MHz, WNS 0.000ns, 8 real
+parallel PEs), replacing EXP-0088's own N=2 pointer (which itself
+replaced EXP-0086's, which replaced EXP-0083's 16-bit-era one). See §5.6
+for the full real story, including N=16's own real RTL (functionally
+verified but NOT timing-closed, kept as documented future work). Every
+number in this document is either
 directly measured (real simulation trace, real P&R report) or a calculation
 built from directly-measured building blocks — the two are labeled
 explicitly throughout. Nothing here is guessed.
@@ -659,7 +664,7 @@ specifically to document where/how it breaks rather than to succeed):
 
 ---
 
-### 5.6 [N=8 REALLY CLOSES timing (0 failing endpoints); N=16 still -0.338ns — EXP-0089…0095] Hybrid systolic scaling: up to 4 groups × 4-PE weight-stationary chains
+### 5.6 [N=8 IS THE REAL, DEFINITIVE DEPLOYMENT TARGET — `n8_system_ddr3_top.v`, EXP-0089…0096] Hybrid systolic scaling: up to 4 groups × 4-PE weight-stationary chains
 
 Captured from a 2026-09-20 brainstorming session as a purely exploratory
 idea; the same day, per the user's own explicit reprioritization, the real
@@ -832,16 +837,36 @@ and clock domain, not a projection. N=4 is a hair's breadth away
 placer/router variance, not a contradiction). **The real failure point
 is specifically between N=8 (closed) and N=16 (EXP-0094: −0.338ns)** —
 N=12 (N_GROUPS=3) has not yet been measured and would narrow this
-further. Real, disclosed caveat: N=4/N=8 have not yet had their own
-dedicated functional xsim (only N=16's full-scale RTL is functionally
-verified, EXP-0092/0094) — the correctness argument for N=4/N=8 rests
-on the architecture's own embarrassingly-parallel-across-groups design,
-not yet a directly measured result at those specific N. Real bug found
-and fixed first: `neural_director_grouped.v`'s own bare
-`$clog2(N_GROUPS)` was invalid (`[-1:0]`) for the never-before-tested
-N_GROUPS=1 case — fixed with the same real `SELW`-style guard pattern
-`sdram_arbiter_n.v` already established. See EXP-0095's own
-`next_action`.
+further. Real bug found and fixed first: `neural_director_grouped.v`'s
+own bare `$clog2(N_GROUPS)` was invalid (`[-1:0]`) for the
+never-before-tested N_GROUPS=1 case — fixed with the same real
+`SELW`-style guard pattern `sdram_arbiter_n.v` already established.
+
+**N=8 promoted to the real, definitive deployment target (EXP-0096)**
+— the user's own explicit decision ("creiamo una versione funzionante
+completamente per N=8, la pushiamo come versione definitiva"). New
+`hardware/v3/rtl/n8_system_ddr3_top.v` — a real, permanent, named
+top-level (not a build-time override), byte-for-byte the same RTL as
+`n16_system_ddr3_top.v` with `N_GROUPS` defaulting to 2. Real, full
+P&R re-run under this file's own name gives the EXACT SAME numbers as
+the generic-override result (WNS=0.000ns, WHS=+0.017ns, 0 failing
+endpoints, 64 DSP48E1/26.7%, 12535 LUTs/19.77%) — confirms the file
+split is correct. New `tb_n8_system_ddr3.v` (real DDR3-model
+methodology, M=16 positions, every one of the 2 groups × 4 PEs × 2
+lanes exercised exactly once): **real functional xsim, 16/16 PASS, 0
+errors** — closes the real, disclosed functional-verification gap
+this section previously flagged for N=8 specifically.
+
+**Current real status: N=8 (`n8_system_ddr3_top.v`) is BOTH
+functionally verified AND timing-closed under its own permanent real
+name — the definitive deployment target.** N=2 (`n2_system_ddr3_top.v`,
+EXP-0088) remains documented as a real, valid, simpler fallback. N=16
+(`n16_system_ddr3_top.v`) remains real, functionally-verified RTL, not
+abandoned, just not timing-closed and not the current target. Real,
+disclosed caveat carried forward: N=8's WNS=0.000ns is an exact-zero
+margin — any future RTL change touching this top-level or its
+dependents needs a fresh real P&R (same `Explore`/`ExtraNetDelay_high`/
+`AggressiveExplore` directive stack) before trusting timing again.
 
 **The problem it targets**: plain N=16 independent cores (§5.5's own
 "documentary, expected to break" framing) means 16 independent DDR3