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feat: N=8 hybrid systolic promoted to the real, definitive deployment target (EXP-0096)

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New n8_system_ddr3_top.v: a real, permanent, named top-level (not a
build-time -generic override), byte-for-byte the same RTL as
n16_system_ddr3_top.v with N_GROUPS defaulting to 2. Real, full P&R
under this file's own name reproduces EXP-0095's own generic-override
result exactly: WNS=0.000ns, WHS=+0.017ns, 0 failing setup endpoints,
64 DSP48E1/26.7%, 12535 LUTs/19.77%.

New tb_n8_system_ddr3.v (real DDR3-model methodology, adapted from
tb_n16_system_ddr3.v, M=16 positions covering every one of the 2
groups x 4 PEs x 2 lanes exactly once): real functional xsim, 16/16
PASS, 0 errors -- closes the real functional-verification gap this
specific N previously had.

N=8 is now BOTH functionally verified AND timing-closed under its own
permanent name -- the real, definitive deployment target. N=2 kept as
a documented, valid fallback; N=16 kept as documented, functionally-
verified-but-not-timing-closed future work, not abandoned.

docs/PHYSICAL_REALIZATION.md, docs/ARCHITECTURE_ANALYSIS.md,
docs/PINOUT.md updated to reflect N=8 as the current real signoff.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC
This commit is contained in:
michele
2026-09-21 08:29:04 +02:00
co-authored by Claude Sonnet 5
parent 6d06404428
commit 264950923b
6 changed files with 1006 additions and 51 deletions
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docs/ARCHITECTURE_ANALYSIS.md
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@@ -1,11 +1,16 @@
# FPGA-Neural V3 — Architecture Analysis: Timing, Bottlenecks, and Recommended Interventions
Scope: the current, real, P&R-verified V3 design (`hardware/v3/`, branch
`v3-artix7`), updated through EXP-0088 (result-writeback engine, real,
closed timing). The current real, trustworthy *timing* signoff is now
EXP-0088 (32-bit, 155.039MHz, WNS +0.100ns), replacing EXP-0086's own
pointer (which itself replaced EXP-0083's 16-bit-era one). Every number
in this document is either
`v3-artix7`), updated through EXP-0095/0096 (N=8 hybrid systolic, real,
closed timing — the current, definitive real deployment target, chosen
by the user after a real, measured N=4/8/16 timing curve). The current
real, trustworthy *timing* signoff is now EXP-0095/0096
(`n8_system_ddr3_top.v`, 32-bit DDR3, 155.039MHz, WNS 0.000ns, 8 real
parallel PEs), replacing EXP-0088's own N=2 pointer (which itself
replaced EXP-0086's, which replaced EXP-0083's 16-bit-era one). See §5.6
for the full real story, including N=16's own real RTL (functionally
verified but NOT timing-closed, kept as documented future work). Every
number in this document is either
directly measured (real simulation trace, real P&R report) or a calculation
built from directly-measured building blocks — the two are labeled
explicitly throughout. Nothing here is guessed.
@@ -659,7 +664,7 @@ specifically to document where/how it breaks rather than to succeed):
---
### 5.6 [N=8 REALLY CLOSES timing (0 failing endpoints); N=16 still -0.338ns — EXP-0089…0095] Hybrid systolic scaling: up to 4 groups × 4-PE weight-stationary chains
### 5.6 [N=8 IS THE REAL, DEFINITIVE DEPLOYMENT TARGET — `n8_system_ddr3_top.v`, EXP-0089…0096] Hybrid systolic scaling: up to 4 groups × 4-PE weight-stationary chains
Captured from a 2026-09-20 brainstorming session as a purely exploratory
idea; the same day, per the user's own explicit reprioritization, the real
@@ -832,16 +837,36 @@ and clock domain, not a projection. N=4 is a hair's breadth away
placer/router variance, not a contradiction). **The real failure point
is specifically between N=8 (closed) and N=16 (EXP-0094: −0.338ns)** —
N=12 (N_GROUPS=3) has not yet been measured and would narrow this
further. Real, disclosed caveat: N=4/N=8 have not yet had their own
dedicated functional xsim (only N=16's full-scale RTL is functionally
verified, EXP-0092/0094) — the correctness argument for N=4/N=8 rests
on the architecture's own embarrassingly-parallel-across-groups design,
not yet a directly measured result at those specific N. Real bug found
and fixed first: `neural_director_grouped.v`'s own bare
`$clog2(N_GROUPS)` was invalid (`[-1:0]`) for the never-before-tested
N_GROUPS=1 case — fixed with the same real `SELW`-style guard pattern
`sdram_arbiter_n.v` already established. See EXP-0095's own
`next_action`.
further. Real bug found and fixed first: `neural_director_grouped.v`'s
own bare `$clog2(N_GROUPS)` was invalid (`[-1:0]`) for the
never-before-tested N_GROUPS=1 case — fixed with the same real
`SELW`-style guard pattern `sdram_arbiter_n.v` already established.
**N=8 promoted to the real, definitive deployment target (EXP-0096)**
— the user's own explicit decision ("creiamo una versione funzionante
completamente per N=8, la pushiamo come versione definitiva"). New
`hardware/v3/rtl/n8_system_ddr3_top.v` — a real, permanent, named
top-level (not a build-time override), byte-for-byte the same RTL as
`n16_system_ddr3_top.v` with `N_GROUPS` defaulting to 2. Real, full
P&R re-run under this file's own name gives the EXACT SAME numbers as
the generic-override result (WNS=0.000ns, WHS=+0.017ns, 0 failing
endpoints, 64 DSP48E1/26.7%, 12535 LUTs/19.77%) — confirms the file
split is correct. New `tb_n8_system_ddr3.v` (real DDR3-model
methodology, M=16 positions, every one of the 2 groups × 4 PEs × 2
lanes exercised exactly once): **real functional xsim, 16/16 PASS, 0
errors** — closes the real, disclosed functional-verification gap
this section previously flagged for N=8 specifically.
**Current real status: N=8 (`n8_system_ddr3_top.v`) is BOTH
functionally verified AND timing-closed under its own permanent real
name — the definitive deployment target.** N=2 (`n2_system_ddr3_top.v`,
EXP-0088) remains documented as a real, valid, simpler fallback. N=16
(`n16_system_ddr3_top.v`) remains real, functionally-verified RTL, not
abandoned, just not timing-closed and not the current target. Real,
disclosed caveat carried forward: N=8's WNS=0.000ns is an exact-zero
margin — any future RTL change touching this top-level or its
dependents needs a fresh real P&R (same `Explore`/`ExtraNetDelay_high`/
`AggressiveExplore` directive stack) before trusting timing again.
**The problem it targets**: plain N=16 independent cores (§5.5's own
"documentary, expected to break" framing) means 16 independent DDR3
docs/PHYSICAL_REALIZATION.md
+71 -32
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@@ -165,38 +165,72 @@ these from an ESP32 doing real JTAG bit-banging (TAP state machine, IR/DR
shifting) rather than a bench programmer — that firmware is separate,
software-side work, not covered here.
## 3. Real timing signoff (EXP-0088, the current, trustworthy number — real 32-bit DDR3 channel + result-writeback engine, CLOSED)
## 3. Real timing signoff (EXP-0095/0096, the current, definitive target — N=8 hybrid systolic, `n8_system_ddr3_top.v`, CLOSED)
Real in-context Vivado place-and-route (not out-of-context, not estimated):
**This is the real, definitive deployment target as of 2026-09-21**
(the user's own explicit decision, after a real, measured N=4/8/16
timing curve found N=8 to be the largest real configuration that
closes timing cleanly — see `docs/ARCHITECTURE_ANALYSIS.md` §5.6 for
the full real story). Top-level RTL: `hardware/v3/rtl/
n8_system_ddr3_top.v` — 2 groups × 4 PEs, shared-weight-broadcast
systolic architecture (`systolic_group.v`/`packed_pe.v`,
`neural_director_grouped.v`, `sdram_arbiter_hier.v`'s own real
hierarchical 2-level arbiter), same real DDR3/SPI/flash bridge as
every other real V3 top-level. Real in-context Vivado place-and-route
(not out-of-context, not estimated):
| Metric | Value |
|---|---|
| DDR3 PHY clock (sys_clk_p/n) | **310.078 MHz** (3.225ns period) |
| Compute domain clock (ui_clk/clk_pll_i, PLL-derived 2:1 from sys_clk) | **155.039 MHz** |
| WNS (setup slack) | **+0.099962 ns** — real, closed. Re-verify with a fresh P&R after ANY further logic addition. |
| WHS (hold slack) | +0.036275 ns |
| Failing endpoints | 0 of 27868 (setup), 0 of 27865 (hold), 0 of 10529 (pulse width) |
| LUTs used | 6642 / 63400 (10.48%) |
| DSP48E1 used | 16 / 240 (6.67%) — 8 per compute core × 2 cores, unchanged since EXP-0059 |
| Block RAM used | 0 |
| STARTUPE2 used | 1 / 1 (100%) — the config-flash bridge |
| WNS (setup slack) | **0.000 ns** — real, closed, 0 failing setup endpoints (EXP-0095/0096). Re-verify with a fresh P&R after ANY further logic addition — this margin is exactly zero, no slack to spare. |
| WHS (hold slack) | +0.017 ns |
| Failing endpoints | 0 of 63212 (setup), 0 of 63209 (hold) |
| LUTs used | 12535 / 63400 (19.77%) |
| Registers used | 19902 / 126800 (15.70%) |
| DSP48E1 used | 64 / 240 (26.7%) — 8 per PE × 8 real parallel PEs |
| DDR3 channel width | **32-bit real physical channel** (two MT41J128M16JT-125:K chips) — see §3.1 |
| Real physical bandwidth ceiling | **~2.48 GB/s** (2× EXP-0083's 16-bit ~1.24 GB/s, real, closed timing — not a projection) |
| Result writeback | **real, into DDR3** (EXP-0088, `result_writeback.v`) — no longer literal top-level pins, see §4.6/§5.3 of `docs/ARCHITECTURE_ANALYSIS.md` |
| Real physical bandwidth ceiling | **~2.48 GB/s** (unchanged from the N=2 baseline — same DDR3 channel, shared across 8 real parallel PEs instead of 2) |
| Real parallelism | **8 real parallel processing elements** (4× the original N=2 design) |
| Result writeback | **real, into DDR3** (`result_writeback.v`), see §4.6/§5.3 of `docs/ARCHITECTURE_ANALYSIS.md` |
Signoff history (every real change, same target, in-context P&R):
**Real, disclosed caveat**: this WNS=0.000ns margin is exactly zero —
real, closed, but with zero slack. Re-run a real P&R (same
`opt_design -directive Explore` / `place_design -directive
ExtraNetDelay_high` / `phys_opt_design -directive AggressiveExplore` /
`route_design -directive AggressiveExplore` directive stack used to
reach this result, EXP-0094/0095) after ANY further RTL change before
trusting timing again — do not assume it still holds.
| EXP | WNS (ns) | LUTs | DSP48E1 |
|---|---|---|---|
| 0074 (first real DDR3 + pins) | +0.040 | 5140 | 16 |
| 0076 (+regfile, +pins, +SPI fix) | +0.056 | 5173 | 16 |
| 0078 (+flash bridge, STARTUPE2) | +0.013 | 5213 | 16 |
| 0079 (+real activation engine) | +0.030 | 5379 | 16 |
| 0082 (+denser activation packing) | +0.068 | 5437 | 16 |
| 0083 (+DDRManager phase 1, `ddr_prefetch_mgr.v`, 16-bit) | +0.073 | 5644 | 16 |
| 0084 (32-bit DDR3 widening, 2900ps/172.414MHz) | -0.618 (FAILED) | 6418 | 16 |
| 0086 (32-bit DDR3 widening, clock reverted to 3225ps/155.039MHz) | +0.096 (CLOSED) | 6382 | 16 |
| 0088 (+result-writeback engine, `result_writeback.v`) | **+0.100 (CLOSED)** | 6642 | 16 |
**Superseded, real predecessor signoff (N=2, flat architecture,
`n2_system_ddr3_top.v`, EXP-0088)** — kept below for reference; still
a real, valid, simpler fallback target if N=8's zero-margin closure
ever proves too fragile in practice:
| Metric | Value |
|---|---|
| WNS (setup slack) | +0.099962 ns |
| WHS (hold slack) | +0.036275 ns |
| LUTs used | 6642 / 63400 (10.48%) |
| DSP48E1 used | 16 / 240 (6.67%) — 8 per compute core × 2 cores |
| Real parallelism | 2 real parallel processing elements |
Signoff history (every real change, in-context P&R):
| EXP | Target | WNS (ns) | LUTs | DSP48E1 |
|---|---|---|---|---|
| 0074 (first real DDR3 + pins) | N=2 | +0.040 | 5140 | 16 |
| 0076 (+regfile, +pins, +SPI fix) | N=2 | +0.056 | 5173 | 16 |
| 0078 (+flash bridge, STARTUPE2) | N=2 | +0.013 | 5213 | 16 |
| 0079 (+real activation engine) | N=2 | +0.030 | 5379 | 16 |
| 0082 (+denser activation packing) | N=2 | +0.068 | 5437 | 16 |
| 0083 (+DDRManager phase 1, `ddr_prefetch_mgr.v`, 16-bit) | N=2 | +0.073 | 5644 | 16 |
| 0084 (32-bit DDR3 widening, 2900ps/172.414MHz) | N=2 | -0.618 (FAILED) | 6418 | 16 |
| 0086 (32-bit DDR3 widening, clock reverted to 3225ps/155.039MHz) | N=2 | +0.096 (CLOSED) | 6382 | 16 |
| 0088 (+result-writeback engine, `result_writeback.v`) | N=2 | +0.100 (CLOSED) | 6642 | 16 |
| 0093 (hybrid systolic, flat 21-way arbiter) | N=16 | -0.913 (FAILED) | 19751 | 128 |
| 0094 (+hierarchical 2-level arbiter, +P&R directive tuning) | N=16 | -0.338 (still FAILED) | 19936 | 128 |
| 0095/0096 (`n8_system_ddr3_top.v`, hybrid systolic) | **N=8** | **0.000 (CLOSED)** | 12535 | 64 |
### 3.1 Real 32-bit DDR3 widening — functionally verified AND timing CLOSED (EXP-0084 → EXP-0086)
@@ -363,12 +397,17 @@ when it actually fires, instead of polling every loop iteration.
## 7. Known-open items (honestly disclosed, not hidden)
- Scaling past N=2 compute cores (silicon budget allows up to ~30 per the
DSP48E1 count) is not yet built or timing-verified. The real pin-budget
blocker that used to require this (`result_data_a/b` as literal
top-level pins) is now REMOVED (EXP-0088, `result_writeback.v` — see
`docs/ARCHITECTURE_ANALYSIS.md` §4.6/§5.3) — real N=2/4/8/16 P&R
scaling tests are the next real milestone, no longer blocked.
- Scaling past N=2 compute cores: **RESOLVED, real N=8 is now the
definitive deployment target** (§3, EXP-0095/0096, `n8_system_ddr3_
top.v`, a real hybrid systolic shared-weight-broadcast architecture,
2 groups × 4 PEs, WNS=0.000ns CLOSED). Real N=4/8/16 P&R curve
measured: N=4 −0.005ns (2 failing endpoints, essentially at the
edge), N=8 **0.000ns (CLOSED)**, N=16 −0.338ns (still failing even
after a real hierarchical-arbiter fix + P&R directive tuning, EXP-
0093/0094) — see `docs/ARCHITECTURE_ANALYSIS.md` §5.6 for the full
real story. N=16 remains real, functionally verified RTL
(`n16_system_ddr3_top.v`), just not yet timing-closed; not the
current real deployment target.
- `sys_rst` has only a *tentative* real pin (G13, bank 15, EXP-0084 —
chosen just to unblock real P&R, not a final board decision) — assign
its real, permanent location once the rest of the board layout (reset
@@ -392,6 +431,6 @@ when it actually fires, instead of polling every loop iteration.
checkpoint) — see §6.
- `result_writeback.v` (EXP-0088) is real, built, and verified (9/9 PASS
including a new real DDR3 read-after-write check, `tb_packed_slot.v`).
Real P&R re-verification for this specific addition is the next real
step, together with the N=2/4/8/16 core-count scaling tests it
unblocks — see `docs/ARCHITECTURE_ANALYSIS.md` §5.3/§5.5.
P&R re-verified with the result-writeback addition (EXP-0088) and,
since then, real N=4/8/16 scaling has been built and P&R-tested — see
§3 above and `docs/ARCHITECTURE_ANALYSIS.md` §5.3/§5.6.
docs/PINOUT.md
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@@ -6,9 +6,13 @@ board). This is a flattened, board-layout-ready extract of
narrated source (it explains *why* each pin was chosen and every real
conflict/fix found along the way); this file is the quick reference for
schematic capture. Every pin below comes from a real routed design
(`n2_system_ddr3_top_routed.dcp`, EXP-0086 signoff) or the MIG-generated
`mig_7series_0.xdc` — none of it is guessed. Re-generate this file if
`docs/PHYSICAL_REALIZATION.md` §2 ever changes.
(originally `n2_system_ddr3_top_routed.dcp`, EXP-0086; the same real pin
set — DDR3/SPI/flash/config are all package-level, unaffected by internal
core count — was re-confirmed real and unchanged in `n8_system_ddr3_top.v`'s
own real routed signoff, EXP-0095/0096, now the current definitive
deployment target, see `docs/PHYSICAL_REALIZATION.md` §3) or the
MIG-generated `mig_7series_0.xdc` — none of it is guessed. Re-generate
this file if `docs/PHYSICAL_REALIZATION.md` §2 ever changes.
## Bank summary