test: certify mac_unit/mac8 datapath (C.1), confirm real N_INPUTS=0 guard gap
mac_unit.v: exhaustive unit test (all 65536 (x,w) combinations at DATA_WIDTH=8, plus 486 boundary acc_in vectors) against an independent Python oracle (tools/validation/mac_oracle.py). 66022/66022 match, 0 reserves. mac8.v: first-ever dedicated unit test (previously only indirect coverage at whatever single PARALLEL neuron_parallel_tb.v happens to use). Verified at PARALLEL=2/8/32 with structural adversarial vectors (catches swapped/duplicated tree wiring), 300 random INT8 pairs per PARALLEL with realistic accumulating acc_in, and worst-case magnitude adversarial vectors. 939/939 match. Confirms BUG-002 (N_INPUTS=0 bypasses the N_INPUTS%PARALLEL elaboration guard) is real, on both simulation and real Yosys synthesis -- root cause: [DATA_WIDTH*N_INPUTS-1:0] becomes [-1:0] for N_INPUTS=0, which both tools treat as a genuine 2-bit undriven vector rather than collapsing to zero width. Includes a documented self-correction: the first verification attempt produced a false "hang" using an invalid one-shot late check of a single-cycle done pulse -- caught by reproducing the same false result on a known-good sanity config before trusting it. Full regression re-run clean after adding 3 new testbenches: 36/36 real tests pass. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
This commit is contained in:
Claude Sonnet 5
+42
@@ -1194,3 +1194,45 @@ integrazione nel top level (F5), verifica consolidata e misure reali (F6).
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modulo→testbench, discrepanze doc↔codice), `docs/validation/bugs.md` (registro aperto).
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- **Prossimo passo**: aspetti C.1–C.14 uno alla volta, ciascuno con test avversari e oracolo
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Python indipendente, verdetto tracciato in un capitolo dedicato.
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## Campagna di ri-certificazione — C.1: Datapath aritmetico (2026-09-04)
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- **`tools/validation/mac_oracle.py`**: oracolo Python indipendente per `mac_unit.v`/
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`mac8.v` (complemento a due da zero, non trascritto dall'RTL), auto-verificato contro 6
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casi derivati a mano prima dell'uso.
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- **`mac_unit.v` certificato ESAUSTIVAMENTE**: `sim/mac_unit_tb.v`, tutte le 65536
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combinazioni possibili di `(x,w)` a DATA_WIDTH=8 (non un campione) + 486 vettori a
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`acc_in` di bordo per il contratto di porta completo. **66022/66022 PASS, 0 mismatch.**
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- **`mac8.v` certificato** (mai testato isolatamente prima, Fase 0 §0.4): `sim/mac8_tree_tb.v`
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a PARALLEL=2/8/32, 939 vettori — pattern strutturale avversariale (somma nota
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`PARALLEL×(PARALLEL+1)/2`, cattura cablaggi scambiati), 300 coppie INT8 casuali/PARALLEL
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con `acc_in` realistico (accumulatore multi-gruppo, non 0 come si potrebbe assumere), e
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casi avversariali di grandezza massima del prodotto. **939/939 PASS, 0 mismatch.**
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- **BUG-002 (guard `N_INPUTS%PARALLEL` non copre `N_INPUTS=0`) confermato reale**, con una
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narrativa di autocorrezione degna di nota: il primo tentativo di verifica ha riportato
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"hang" con un metodo di test **invalido** (controllo tardivo e singolo di `done`, che è un
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impulso di un solo ciclo — lo stesso falso "hang" si riproduceva anche su una config
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nota-buona, N_INPUTS=2/PARALLEL=2, il che ha smascherato il problema). Corretto il metodo
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(osservare `done` ogni ciclo), riverificata la config nota-buona (ora PASS
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correttamente), e **confermato** il sintomo reale per N_INPUTS=0: `start` viene accettato
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ma `busy` non si alza mai, `done` non pulsa mai in 200 cicli — un sintomo diverso da
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quello descritto nel commento originale del guard ("busy alto per sempre"). **Causa
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radice trovata**: `x_bus`/`w_bus` dichiarati `[-1:0]` per N_INPUTS=0 non collassano a
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larghezza zero — sia Icarus sia Yosys li trattano come vettori reali a 2 bit non
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pilotati (confermato dai warning di Yosys stesso). **Confermato su ENTRAMBI i piani di
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verifica** (§A.4): sintesi reale Yosys elabora la config con 0 problemi CHECK, stesso
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silenzio del simulatore. Creato test di regressione permanente
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(`sim/neuron_parallel_bug002_n_inputs_zero_tb.v`) che documenta il sintomo attuale come
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APERTO, non come comportamento accettabile. Impatto pratico basso (N_INPUTS è fissato in
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sintesi, non raggiungibile via SPI a runtime) ma il buco nella protezione è reale, non
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teorico.
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- **Regressione completa ri-eseguita** con `tools/run_regression.py` dopo l'aggiunta dei 3
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nuovi testbench: **36/36 test reali PASS**, 0 regressioni, 1 benchmark invariato.
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- **Deliverable**: `docs/validation/01-datapath.md` (verdetto per sotto-aspetto: mac_unit
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CERTIFICATO, mac8 CERTIFICATO, saturazione CERTIFICATO CON RISERVA — test pre-esistente
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riverificato, guard NON CERTIFICATO per N_INPUTS=0), `docs/validation/bugs.md` aggiornato
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con evidenza completa per BUG-002.
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- **Prossimo passo**: C.2 (larghezza runtime `n_inputs_real`/`n_neurons_real`) — nota:
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l'header di `neuron_parallel.v` dichiara esplicitamente che `n_inputs_real=0` riproduce lo
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stesso rischio di BUG-002 "per responsabilità del chiamante" — da verificare se questo
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claim tiene, con lo stesso rigore.
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@@ -0,0 +1,162 @@
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# C.1 — Datapath aritmetico (`mac_unit`, `mac8`, `neuron_parallel`)
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Data: 2026-09-04. Chiude i due punti aperti in Fase 0 (§0.4 copertura `mac_unit`/`mac8`,
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§0.6 gap del guard `N_INPUTS=0`).
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---
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## 1.1 `mac_unit.v` — CERTIFICATO
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**Metodo**: test esaustivo, non a campione. `mac_unit` è puramente combinazionale
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(`x`, `w`, `acc_in` → `acc_out = acc_in + sign_extend(x*w)`), a `DATA_WIDTH=8` esistono
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esattamente 256×256=65536 combinazioni possibili di `(x,w)` — tutte esercitate, non un
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sottoinsieme casuale.
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**Oracolo**: `tools/validation/mac_oracle.py`, reimplementazione Python indipendente
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dell'aritmetica complemento-a-due da zero (non trascritta dall'RTL) — auto-verificata contro
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6 casi derivati a mano prima di essere usata come oracolo per chiunque altro
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(`python3 tools/validation/mac_oracle.py` → `ALL SELF-CHECKS PASSED`).
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**Test**: `sim/mac_unit_tb.v`, due batterie:
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1. Le 65536 combinazioni esaustive di `(x,w)`, `acc_in=0` (l'uso reale in `mac8.v`, dove
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`acc_in` è cablato a 0 per ogni istanza `mac_unit`).
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2. 486 vettori a `acc_in` diverso da zero — inclusi i 4 valori limite (`0`, `±2³¹`, `±2³⁰`) e
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i 4 angoli di grandezza massima del prodotto (`±128×±128`, `±128×∓127`) — a copertura del
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**contratto di porta completo** del modulo, non solo di come viene usato oggi.
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```
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$ iverilog -g2012 -o /tmp/mac_unit_tb.out rtl/mac_unit.v sim/mac_unit_tb.v && vvp /tmp/mac_unit_tb.out
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ALL TESTS PASSED (66022 vectors, 0 mismatches against independent Python oracle)
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```
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**Verdetto: CERTIFICATO.** 66022/66022 vettori, 0 mismatch, copertura esaustiva sullo
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spazio degli input a INT8. Nessuna riserva.
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---
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## 1.2 `mac8.v` — adder tree bilanciato — CERTIFICATO
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**Metodo**: `mac8.v` non aveva alcun test unitario dedicato (Fase 0, §0.4) — solo copertura
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indiretta a un singolo `PARALLEL` tramite `neuron_parallel_tb.v`. Un bug di cablaggio
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dell'albero (linea scambiata/duplicata/persa) a un `PARALLEL` diverso da quello usato dai
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test esistenti sarebbe passato inosservato.
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**Test**: `sim/mac8_tree_tb.v`, verificato a **PARALLEL=2, 8 (il default/omonimo del modulo)
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e 32** — gli estremi realmente usati nei benchmark del progetto
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(`docs/FPGA-Neural-Datapatch-Benchmark.md`), non un solo valore a piacere. Tre famiglie per
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ciascun `PARALLEL` (939 vettori totali):
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1. **Strutturale/avversariale**: `x=[1..PARALLEL]`, `w=1`, ordine sia ascendente che
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invertito. La somma attesa (`PARALLEL×(PARALLEL+1)/2`) torna corretta **solo se ogni
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linea è sommata esattamente una volta** — un modo efficace di scoprire un cablaggio
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scambiato che un test casuale potrebbe non notare (uno scambio+una linea persa possono
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annullarsi per caso su input casuali, mai su questo pattern esatto).
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2. **300 coppie INT8 casuali per `PARALLEL`**, `acc_in` variato su un range realistico —
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riproduce il collegamento reale (`neuron_parallel.v`: `mac8.acc_in = acc`, l'accumulatore
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che cresce gruppo dopo gruppo, **non** cablato a 0 come si potrebbe erroneamente
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assumere).
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3. **Avversariale**: tutte le linee al prodotto di grandezza massima (`±16384`/`∓16256`)
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simultaneamente, con `acc_in` ai bordi di `ACC_WIDTH=32` — conferma che l'eventuale
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wraparound complemento-a-due dell'albero è ben definito (non X/indefinito), pur essendo
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una magnitudine ben oltre quanto un layer reale (`N_INPUTS≤256`) accumulerebbe mai
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(dichiarato, non presentato come condizione operativa reale).
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```
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$ iverilog -g2012 -o /tmp/mac8_tb.out rtl/mac_unit.v rtl/mac8.v sim/mac8_tree_tb.v && vvp /tmp/mac8_tb.out
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ALL TESTS PASSED (939 vectors across PARALLEL=2/8/32, 0 mismatches against independent Python oracle)
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```
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**Verdetto: CERTIFICATO** a PARALLEL=2/8/32. **Riserva dichiarata**: non verificato ad ogni
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altro `PARALLEL` usato nel progetto (es. 4, 16) — il rischio residuo è basso (la costruzione
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dell'albero è generica via `$clog2(PARALLEL)`, identica per ogni potenza di due, e 3 valori
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distinti già la esercitano a profondità diverse: 1, 3, 5 livelli), ma non è "esaustivo su
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tutti i PARALLEL" nello stesso senso in cui §1.1 lo è su `(x,w)`.
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---
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## 1.3 Saturazione INT8 / attivazione — CERTIFICATO CON RISERVA (test pre-esistente, riverificato)
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`sim/neuron_parallel_saturation_bounds_tb.v` (già presente prima di questa campagna) copre
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gli 8 valori di bordo dichiarati nel task di timing-closure (126, 127, 128, 129, -128, -129,
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-1, 0) per `ACT_NONE` e `ACT_RELU`, con oracolo **calcolato a mano** (non derivato dal
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codice) — verificato bit-esatto per confermare che la riscrittura a bit-test delle
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comparazioni di saturazione (da confronti aritmetici `>127`/`<-128` a riduzioni AND/OR)
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durante la timing closure non ha alterato il comportamento.
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Ri-eseguito da zero in questa campagna (non solo citato dal WORKLOG): **PASS**, invariato.
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**Riserva**: il test usa `N_INPUTS=PARALLEL=1` (una sola corsia MAC), per raggiungere ogni
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valore di bordo esattamente con una singola tripla `(x,w,bias)` scelta a mano. Non esercita
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l'interazione tra l'albero a più corsie (§1.2, ora certificato separatamente) e la
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saturazione finale nello stesso run — cioè non c'è un test che porti un accumulo
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multi-gruppo/multi-corsia esattamente a uno di questi bordi. Rischio basso (la saturazione
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opera sul valore finale di `acc+bias`, indipendentemente da come quel valore è stato
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costruito), ma non è stato verificato esplicitamente in questa campagna.
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---
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## 1.4 Guard `N_INPUTS % PARALLEL != 0` — CERTIFICATO CON RISERVA GRAVE (BUG-002 confermato)
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### Cosa funziona (già coperto, riverificato)
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`sim/neuron_parallel_guard_negative_{nonmultiple,degenerate}_tb.v`: due test negativi che
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provano che il guard blocca l'elaborazione per `N_INPUTS % PARALLEL != 0` (incl. il caso
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degenere "PARALLEL > N_INPUTS" per N_INPUTS≥1, dove il resto della divisione coincide con
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N_INPUTS stesso, quindi è comunque non-zero). Rieseguiti da zero: **entrambi falliscono a
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compilare come previsto** — è il PASS.
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### BUG-002 — confermato reale, su ENTRAMBI i piani di verifica (non solo ipotizzato)
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**Il finding aperto in Fase 0 §0.6 era corretto nell'ipotesi ma la mia prima verifica
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empirica era sbagliata per un bug nella MIA testbench** — narrativa completa perché è
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rilevante per la fiducia nel resto della campagna:
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1. Primo tentativo: un test con `repeat(50) @(posedge clk); if (done) ... else "HANG"` ha
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riportato "hang" per `N_INPUTS=0`. **Metodologicamente invalido**: `done` è un impulso di
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**un solo ciclo** (`rtl/neuron_parallel.v:207/227`, `done <= 0` incondizionato subito dopo
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averlo asserito), quindi un controllo tardivo e singolo di `done` mostra sempre 0 **anche
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quando tutto funziona correttamente** — confermato riproducendo lo stesso falso "HANG" su
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una config nota-buona (`N_INPUTS=2, PARALLEL=2`, valida, mai dovrebbe fallire).
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2. Corretto il metodo: osservare `done` **ogni ciclo** (non un controllo singolo tardivo).
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Sulla config nota-buona, ora **PASS correttamente** (`done` pulsa al ciclo giusto, `y=5`
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coerente col calcolo a mano). Sul caso `N_INPUTS=0`: **confermato, `busy` non si alza mai
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e `done` non pulsa mai in 200 cicli** — non è più un'ipotesi, è un fatto osservato con un
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metodo verificato corretto prima su un caso di controllo.
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3. **Causa architetturale trovata** (non solo il sintomo): `x_bus`/`w_bus` sono dichiarati
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`[DATA_WIDTH*N_INPUTS-1:0]` — per `N_INPUTS=0` questo è `[-1:0]`, che **non collassa a
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larghezza zero**: sia Icarus che Yosys lo trattano come un vettore a **2 bit** reali
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(larghezza = |MSB-LSB|+1 = |-1-0|+1 = 2), lasciato **non pilotato**. Confermato dai
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warning di Yosys stesso: `Wire ...x_bus[1] is used but has no driver` (×2 per x_bus/w_bus).
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4. **Confermato anche in sintesi reale**, non solo in simulazione (§A.4): `yosys synth_ecp5`
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elabora `neuron_parallel #(.N_INPUTS(0), .PARALLEL(2))` con **0 problemi segnalati** dal
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CHECK pass — lo stesso silenzio che permette al guard di non scattare in simulazione si
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ripete identico sul secondo piano di verifica indipendente.
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**Test di regressione permanente**: `sim/neuron_parallel_bug002_n_inputs_zero_tb.v` —
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riproduce il sintomo esatto in modo deterministico, PASSA oggi confermando che il bug è
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ancora presente (non è un'asserzione che questo comportamento sia desiderabile — il file
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stesso lo dichiara esplicitamente in testa, con l'istruzione di riscriverlo, non
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allentarlo, quando il bug verrà corretto).
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**Verdetto: NON CERTIFICATO per `N_INPUTS=0`.** Il guard copre correttamente ogni
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combinazione `N_INPUTS≥1` non multipla di `PARALLEL` (incl. il caso degenere
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`PARALLEL>N_INPUTS≥1`), ma **non copre `N_INPUTS=0`**, che produce un `start` silenziosamente
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inefficace (non l'hang "busy alto per sempre" descritto nel commento originale del guard —
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un sintomo diverso, osservato per la prima volta in questa campagna) su entrambi i piani di
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verifica. Vedi `docs/validation/bugs.md` BUG-002 per severità e fix proposto.
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---
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## 1.5 Verdetto complessivo C.1
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| Sotto-aspetto | Verdetto |
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|---|---|
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| `mac_unit.v` | **CERTIFICATO** (esaustivo, 66022 vettori, 0 riserve) |
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| `mac8.v` (adder tree) | **CERTIFICATO** (939 vettori, PARALLEL=2/8/32; riserva: non esaustivo su ogni PARALLEL) |
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| Saturazione/attivazione | **CERTIFICATO CON RISERVA** (test pre-esistente valido; riserva: non testato in combinazione con l'albero multi-corsia) |
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| Guard `N_INPUTS%PARALLEL` | **NON CERTIFICATO per N_INPUTS=0** — BUG-002 confermato su sim + sintesi reale |
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**Il datapath aritmetico di base (moltiplicazione, estensione di segno, albero di somma) è
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solido** — certificato esaustivamente dove possibile. **Il guard di protezione attorno ad
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esso ha un buco reale e confermato**, non un rischio teorico: `N_INPUTS=0` produce hardware
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sintetizzabile (0 errori Yosys) che silenziosamente non fa nulla quando l'host tenta di
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avviarlo.
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+28
-15
@@ -24,22 +24,35 @@ funzionale pratico), **INFO** (non un bug: gap di copertura, ambiguità document
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- **Stato**: aperto, non corretto per policy §E (analisi separata dalla correzione). Azione
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proposta: rimuovere il file o aggiornarlo, decisione da confermare con l'utente.
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### BUG-002 (da classificare, indagine formale in C.1) — guard `N_INPUTS % PARALLEL` non copre `N_INPUTS=0`
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### BUG-002 (MEDIA, CONFERMATO su sim + sintesi reale) — `N_INPUTS=0` bypassa il guard, `start` viene silenziosamente ignorato
|
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|
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- **Sintomo potenziale**: se `N_INPUTS=0`, il guard elaboration-time in
|
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`rtl/neuron_parallel.v:71` (`if (N_INPUTS % PARALLEL != 0)`) non scatta (`0 % PARALLEL ==
|
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0` per ogni `PARALLEL`), ma `GROUPS = N_INPUTS / PARALLEL = 0` — la stessa condizione di
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hang (`group_index == GROUPS-1` mai soddisfatta) che il guard dichiara di prevenire nel
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proprio commento (righe 55-58).
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- **Causa radice (ipotesi, non ancora confermata su hardware simulato)**: il guard controlla
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solo la divisibilità, non `N_INPUTS > 0` esplicitamente.
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- **Evidenza**: lettura diretta di `rtl/neuron_parallel.v:55-73` — vedi
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`docs/validation/00-inventario.md` §0.6 per il testo esatto.
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- **Stato**: **APERTO, non ancora verificato con un test reale**. Non è ancora chiaro se
|
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`N_INPUTS=0` sia una configurazione raggiungibile nella pratica (nessun layer con zero
|
||||
ingressi ha senso a livello di sistema) — da chiudere in C.1 con un test avversariale
|
||||
dedicato e un oracolo indipendente, prima di classificarlo come bug vero o come rischio
|
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teorico non rilevante.
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- **Sintomo confermato** (non più un'ipotesi — vedi `docs/validation/01-datapath.md` §1.4 per
|
||||
la narrativa completa, incl. un falso positivo iniziale nella mia stessa metodologia di
|
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test, corretto e ridocumentato per trasparenza): con
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||||
`neuron_parallel #(.N_INPUTS(0), .PARALLEL(P))`, il guard elaboration-time
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(`rtl/neuron_parallel.v:71`, `if (N_INPUTS % PARALLEL != 0)`) **non scatta** (`0 % P == 0`
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per ogni `P`), il modulo **elabora con successo** (sia in simulazione Icarus sia in sintesi
|
||||
reale Yosys, 0 problemi CHECK). A runtime: `start` viene accettato ma **`busy` non si alza
|
||||
mai e `done` non pulsa mai** — non l'hang "busy resta alto per sempre" descritto nel
|
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commento originale del guard (righe 55-58), un sintomo diverso, osservato per la prima
|
||||
volta in questa campagna.
|
||||
- **Causa radice, confermata (non più ipotesi)**: `x_bus`/`w_bus` sono dichiarati
|
||||
`[DATA_WIDTH*N_INPUTS-1:0]`, che per `N_INPUTS=0` diventa `[-1:0]` — un range che **non
|
||||
collassa a larghezza zero**: sia Icarus sia Yosys lo trattano come un vettore reale a
|
||||
**2 bit** (larghezza = |MSB-LSB|+1 = 2), lasciato non pilotato. Confermato dai warning di
|
||||
Yosys: `Wire ...x_bus[1] is used but has no driver` (×2, per x_bus e w_bus).
|
||||
- **Evidenza**:
|
||||
- `iverilog -g2012 -o /tmp/n0proper.out rtl/neuron_parallel.v rtl/mac8.v rtl/mac_unit.v sim/neuron_parallel_bug002_n_inputs_zero_tb.v && vvp /tmp/n0proper.out` → conferma il sintomo, ogni volta.
|
||||
- `yosys -p "synth_ecp5 -json /tmp/n0.json -top n0_synth_wrap" rtl/neuron_parallel.v rtl/mac8.v rtl/mac_unit.v <wrapper>` → **0 problemi CHECK**, 4 warning "no driver" su x_bus/w_bus[1:0].
|
||||
- Test di regressione permanente: `sim/neuron_parallel_bug002_n_inputs_zero_tb.v`.
|
||||
- **Impatto pratico**: `N_INPUTS` è un parametro Verilog fissato in fase di sintesi (non un
|
||||
registro configurabile via SPI a runtime) — per essere raggiunto, qualcuno deve
|
||||
deliberatamente istanziare il modulo con `N_INPUTS=0`, cosa che non ha senso semantico per
|
||||
un layer reale. Rischio quindi basso in pratica (nessun percorso runtime/host-controllato
|
||||
può innescarlo), ma è un buco reale e confermato nella protezione, non solo teorico.
|
||||
- **Fix proposto** (non applicato — analisi separata dalla correzione, §E del prompt di
|
||||
certificazione): estendere il guard a `if (N_INPUTS == 0 || N_INPUTS % PARALLEL != 0)`.
|
||||
- **Stato**: **APERTO, confermato, non corretto.**
|
||||
|
||||
---
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
$date
|
||||
Fri Sep 4 13:22:49 2026
|
||||
Fri Sep 4 13:40:12 2026
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
$date
|
||||
Fri Sep 4 13:22:53 2026
|
||||
Fri Sep 4 13:40:16 2026
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
$date
|
||||
Fri Sep 4 13:22:54 2026
|
||||
Fri Sep 4 13:40:17 2026
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
$date
|
||||
Fri Sep 4 13:22:54 2026
|
||||
Fri Sep 4 13:40:17 2026
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
|
||||
@@ -0,0 +1,165 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
// ================================================================
|
||||
// MAC8 TESTBENCH -- balanced binary adder tree (certification
|
||||
// campaign, aspect C.1)
|
||||
//
|
||||
// rtl/mac8.v had NO dedicated unit-level testbench before this
|
||||
// (docs/validation/00-inventario.md §0.4/§0.5): only indirect coverage
|
||||
// through neuron_parallel_tb.v, always at whatever single PARALLEL that
|
||||
// testbench happens to use. A tree-wiring bug (swapped/duplicated/
|
||||
// dropped lane) at a DIFFERENT PARALLEL than what neuron_parallel_tb.v
|
||||
// exercises would go completely undetected.
|
||||
//
|
||||
// Checked at PARALLEL=2, 8 (the module's own default/namesake), and 32
|
||||
// -- the extremes actually used across this project's own benchmarks
|
||||
// (docs/FPGA-Neural-Datapatch-Benchmark.md), not just the one value a
|
||||
// single higher-level test happens to pick.
|
||||
//
|
||||
// Oracle: tools/validation/mac_oracle.py's mac8_full() -- an
|
||||
// independent Python model (two's complement tree-sum from first
|
||||
// principles). Vectors pre-generated per PARALLEL
|
||||
// (tools/validation/mac8_tree_p{2,8,32}.hex), three families each:
|
||||
// 1. Structural (x=[1..PARALLEL], w=1, ascending AND reversed lane
|
||||
// order): the expected sum PARALLEL*(PARALLEL+1)/2 only comes out
|
||||
// right if every lane is summed EXACTLY once -- catches a
|
||||
// swapped/duplicated/dropped tree input that random testing could
|
||||
// miss by chance (a duplicate+drop pair can cancel out on some
|
||||
// random inputs but never on this exact structural pattern).
|
||||
// 2. 300 realistic random INT8 (x,w) pairs per PARALLEL with a
|
||||
// boundary-swept acc_in -- matches the REAL wiring in
|
||||
// neuron_parallel.v (acc_in = running accumulator across
|
||||
// previous MAC groups, NOT hardwired to 0).
|
||||
// 3. Adversarial worst-case product magnitude
|
||||
// (x=w=-128 -> +16384/lane, or x=-128,w=127 -> -16256/lane) at
|
||||
// every lane simultaneously, with boundary acc_in near the
|
||||
// ACC_WIDTH=32 edge -- confirms the tree's wraparound behavior is
|
||||
// well-defined two's complement, not X/undefined, even though
|
||||
// this magnitude is far beyond what any realistic N_INPUTS<=256
|
||||
// layer would ever accumulate to (documented, not asserted as a
|
||||
// real operating condition).
|
||||
// ================================================================
|
||||
|
||||
module tb;
|
||||
|
||||
localparam DATA_WIDTH = 8;
|
||||
localparam ACC_WIDTH = 32;
|
||||
|
||||
integer total_errors;
|
||||
integer total_checked;
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// PARALLEL = 2
|
||||
// ------------------------------------------------------------
|
||||
localparam P2 = 2;
|
||||
localparam W2 = 16*P2 + 64;
|
||||
reg [W2-1:0] vec2 [0:312];
|
||||
reg signed [DATA_WIDTH*P2-1:0] x_bus2, w_bus2;
|
||||
reg signed [ACC_WIDTH-1:0] acc_in2;
|
||||
wire signed [ACC_WIDTH-1:0] acc_out2;
|
||||
reg signed [ACC_WIDTH-1:0] expected2;
|
||||
integer li2;
|
||||
|
||||
mac8 #(.DATA_WIDTH(DATA_WIDTH), .ACC_WIDTH(ACC_WIDTH), .PARALLEL(P2)) dut2 (
|
||||
.x_bus(x_bus2), .w_bus(w_bus2), .acc_in(acc_in2), .acc_out(acc_out2)
|
||||
);
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// PARALLEL = 8 (mac8's own namesake default)
|
||||
// ------------------------------------------------------------
|
||||
localparam P8 = 8;
|
||||
localparam W8 = 16*P8 + 64;
|
||||
reg [W8-1:0] vec8 [0:312];
|
||||
reg signed [DATA_WIDTH*P8-1:0] x_bus8, w_bus8;
|
||||
reg signed [ACC_WIDTH-1:0] acc_in8;
|
||||
wire signed [ACC_WIDTH-1:0] acc_out8;
|
||||
reg signed [ACC_WIDTH-1:0] expected8;
|
||||
integer li8;
|
||||
|
||||
mac8 #(.DATA_WIDTH(DATA_WIDTH), .ACC_WIDTH(ACC_WIDTH), .PARALLEL(P8)) dut8 (
|
||||
.x_bus(x_bus8), .w_bus(w_bus8), .acc_in(acc_in8), .acc_out(acc_out8)
|
||||
);
|
||||
|
||||
// ------------------------------------------------------------
|
||||
// PARALLEL = 32
|
||||
// ------------------------------------------------------------
|
||||
localparam P32 = 32;
|
||||
localparam W32 = 16*P32 + 64;
|
||||
reg [W32-1:0] vec32 [0:312];
|
||||
reg signed [DATA_WIDTH*P32-1:0] x_bus32, w_bus32;
|
||||
reg signed [ACC_WIDTH-1:0] acc_in32;
|
||||
wire signed [ACC_WIDTH-1:0] acc_out32;
|
||||
reg signed [ACC_WIDTH-1:0] expected32;
|
||||
integer li32;
|
||||
|
||||
mac8 #(.DATA_WIDTH(DATA_WIDTH), .ACC_WIDTH(ACC_WIDTH), .PARALLEL(P32)) dut32 (
|
||||
.x_bus(x_bus32), .w_bus(w_bus32), .acc_in(acc_in32), .acc_out(acc_out32)
|
||||
);
|
||||
|
||||
initial begin
|
||||
total_errors = 0;
|
||||
total_checked = 0;
|
||||
|
||||
// ---- PARALLEL = 2 ----
|
||||
$readmemh("tools/validation/mac8_tree_p2.hex", vec2);
|
||||
$display("--- PARALLEL=2: 313 vectors ---");
|
||||
for (li2 = 0; li2 < 313; li2 = li2 + 1) begin
|
||||
for (integer lane = 0; lane < P2; lane = lane + 1) begin
|
||||
x_bus2[lane*8 +: 8] = vec2[li2][W2-1-16*lane -: 8];
|
||||
w_bus2[lane*8 +: 8] = vec2[li2][W2-1-16*lane-8 -: 8];
|
||||
end
|
||||
acc_in2 = vec2[li2][63:32];
|
||||
expected2 = vec2[li2][31:0];
|
||||
#1;
|
||||
total_checked = total_checked + 1;
|
||||
if (acc_out2 !== expected2) begin
|
||||
total_errors = total_errors + 1;
|
||||
$display("MISMATCH P2 idx=%0d: got=%0d expected=%0d", li2, acc_out2, expected2);
|
||||
end
|
||||
end
|
||||
|
||||
// ---- PARALLEL = 8 ----
|
||||
$readmemh("tools/validation/mac8_tree_p8.hex", vec8);
|
||||
$display("--- PARALLEL=8: 313 vectors ---");
|
||||
for (li8 = 0; li8 < 313; li8 = li8 + 1) begin
|
||||
for (integer lane = 0; lane < P8; lane = lane + 1) begin
|
||||
x_bus8[lane*8 +: 8] = vec8[li8][W8-1-16*lane -: 8];
|
||||
w_bus8[lane*8 +: 8] = vec8[li8][W8-1-16*lane-8 -: 8];
|
||||
end
|
||||
acc_in8 = vec8[li8][63:32];
|
||||
expected8 = vec8[li8][31:0];
|
||||
#1;
|
||||
total_checked = total_checked + 1;
|
||||
if (acc_out8 !== expected8) begin
|
||||
total_errors = total_errors + 1;
|
||||
$display("MISMATCH P8 idx=%0d: got=%0d expected=%0d", li8, acc_out8, expected8);
|
||||
end
|
||||
end
|
||||
|
||||
// ---- PARALLEL = 32 ----
|
||||
$readmemh("tools/validation/mac8_tree_p32.hex", vec32);
|
||||
$display("--- PARALLEL=32: 313 vectors ---");
|
||||
for (li32 = 0; li32 < 313; li32 = li32 + 1) begin
|
||||
for (integer lane = 0; lane < P32; lane = lane + 1) begin
|
||||
x_bus32[lane*8 +: 8] = vec32[li32][W32-1-16*lane -: 8];
|
||||
w_bus32[lane*8 +: 8] = vec32[li32][W32-1-16*lane-8 -: 8];
|
||||
end
|
||||
acc_in32 = vec32[li32][63:32];
|
||||
expected32 = vec32[li32][31:0];
|
||||
#1;
|
||||
total_checked = total_checked + 1;
|
||||
if (acc_out32 !== expected32) begin
|
||||
total_errors = total_errors + 1;
|
||||
$display("MISMATCH P32 idx=%0d: got=%0d expected=%0d", li32, acc_out32, expected32);
|
||||
end
|
||||
end
|
||||
|
||||
$display("--- TOTAL: checked=%0d errors=%0d ---", total_checked, total_errors);
|
||||
if (total_errors == 0)
|
||||
$display("ALL TESTS PASSED (%0d vectors across PARALLEL=2/8/32, 0 mismatches against independent Python oracle)", total_checked);
|
||||
else
|
||||
$display("FAILED: %0d/%0d vectors mismatched", total_errors, total_checked);
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,104 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
// ================================================================
|
||||
// MAC_UNIT TESTBENCH (certification campaign, aspect C.1)
|
||||
//
|
||||
// rtl/mac_unit.v had NO dedicated unit-level testbench before this
|
||||
// (docs/validation/00-inventario.md §0.4/§0.5): only indirect coverage
|
||||
// through neuron_parallel_tb.v and friends, where acc_in is always
|
||||
// hardwired to 0 by mac8.v and a bug isolated to this module would only
|
||||
// surface if it happened to propagate visibly through the full layer.
|
||||
//
|
||||
// Oracle: tools/validation/mac_oracle.py, an independent Python
|
||||
// reimplementation (two's complement from first principles, not a
|
||||
// transcription of this RTL) -- see that file's own header. Vectors are
|
||||
// pre-generated (tools/validation/mac_unit_vectors_*.hex) rather than
|
||||
// computed at Verilog runtime, so the comparison at each step is purely
|
||||
// mechanical (no chance of Verilog-side arithmetic accidentally
|
||||
// re-deriving the same bug the oracle exists to catch).
|
||||
//
|
||||
// Coverage: EXHAUSTIVE on (x,w) at DATA_WIDTH=8 -- all 256*256=65536
|
||||
// combinations, acc_in=0 (matches mac8.v's real usage). Plus a second,
|
||||
// separate file exercising the module's own full port contract
|
||||
// (acc_out = acc_in + product for ANY acc_in, not just the acc_in=0 case
|
||||
// this design happens to use today) across boundary/random acc_in values
|
||||
// including the four true product-magnitude corners
|
||||
// (-128*-128, 127*127, -128*127, 127*-128).
|
||||
// ================================================================
|
||||
|
||||
module tb;
|
||||
|
||||
localparam DATA_WIDTH = 8;
|
||||
localparam ACC_WIDTH = 32;
|
||||
|
||||
reg signed [DATA_WIDTH-1:0] x;
|
||||
reg signed [DATA_WIDTH-1:0] w;
|
||||
reg signed [ACC_WIDTH-1:0] acc_in;
|
||||
wire signed [ACC_WIDTH-1:0] acc_out;
|
||||
|
||||
mac_unit #(.DATA_WIDTH(DATA_WIDTH), .ACC_WIDTH(ACC_WIDTH)) dut (
|
||||
.x(x), .w(w), .acc_in(acc_in), .acc_out(acc_out)
|
||||
);
|
||||
|
||||
// 80-bit packed vector: x[79:72] w[71:64] acc_in[63:32] expected[31:0]
|
||||
reg [79:0] exhaustive_vec [0:65535];
|
||||
reg [79:0] boundary_vec [0:485];
|
||||
|
||||
integer i;
|
||||
integer errors;
|
||||
integer checked;
|
||||
|
||||
reg [7:0] vx;
|
||||
reg [7:0] vw;
|
||||
reg [31:0] vacc_in;
|
||||
reg [31:0] vexpected;
|
||||
|
||||
task automatic check_one(input [79:0] packed_vec);
|
||||
begin
|
||||
vx = packed_vec[79:72];
|
||||
vw = packed_vec[71:64];
|
||||
vacc_in = packed_vec[63:32];
|
||||
vexpected = packed_vec[31:0];
|
||||
x = vx;
|
||||
w = vw;
|
||||
acc_in = vacc_in;
|
||||
#1;
|
||||
checked = checked + 1;
|
||||
if (acc_out !== $signed(vexpected)) begin
|
||||
errors = errors + 1;
|
||||
if (errors <= 20) begin
|
||||
$display("MISMATCH: x=%0d w=%0d acc_in=%0d -> got=%0d expected=%0d",
|
||||
$signed(vx), $signed(vw), $signed(vacc_in), acc_out, $signed(vexpected));
|
||||
end
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
initial begin
|
||||
errors = 0;
|
||||
checked = 0;
|
||||
|
||||
$readmemh("tools/validation/mac_unit_vectors_exhaustive.hex", exhaustive_vec);
|
||||
$readmemh("tools/validation/mac_unit_vectors_boundary_accin.hex", boundary_vec);
|
||||
|
||||
$display("--- TEST 1: exhaustive (x,w), acc_in=0 -- 65536 combinations ---");
|
||||
for (i = 0; i < 65536; i = i + 1) begin
|
||||
check_one(exhaustive_vec[i]);
|
||||
end
|
||||
$display(" checked %0d, errors so far %0d", checked, errors);
|
||||
|
||||
$display("--- TEST 2: full port contract, boundary/random acc_in -- 486 vectors ---");
|
||||
for (i = 0; i < 486; i = i + 1) begin
|
||||
check_one(boundary_vec[i]);
|
||||
end
|
||||
$display(" checked %0d total, errors %0d", checked, errors);
|
||||
|
||||
if (errors == 0) begin
|
||||
$display("ALL TESTS PASSED (%0d vectors, 0 mismatches against independent Python oracle)", checked);
|
||||
end else begin
|
||||
$display("FAILED: %0d/%0d vectors mismatched", errors, checked);
|
||||
end
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,5 +1,5 @@
|
||||
$date
|
||||
Fri Sep 4 13:22:54 2026
|
||||
Fri Sep 4 13:40:17 2026
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
$date
|
||||
Fri Sep 4 13:23:02 2026
|
||||
Fri Sep 4 13:40:25 2026
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
$date
|
||||
Fri Sep 4 13:22:58 2026
|
||||
Fri Sep 4 13:40:21 2026
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
$date
|
||||
Fri Sep 4 13:23:02 2026
|
||||
Fri Sep 4 13:40:25 2026
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
|
||||
@@ -0,0 +1,115 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
// ================================================================
|
||||
// BUG-002 REGRESSION TRAP (certification campaign, aspect C.1,
|
||||
// docs/validation/bugs.md) -- N_INPUTS=0 bypasses the elaboration-
|
||||
// time guard and produces a confirmed, real hang.
|
||||
//
|
||||
// rtl/neuron_parallel.v:71's guard is a single condition:
|
||||
// if (N_INPUTS % PARALLEL != 0) ... force elaboration failure
|
||||
// For N_INPUTS=0, `0 % PARALLEL == 0` for any PARALLEL != 0 -- the
|
||||
// guard does NOT fire, yet GROUPS = N_INPUTS/PARALLEL = 0, the exact
|
||||
// condition the guard's own header comment (lines 55-58) says causes
|
||||
// a hang. This module DOES compile/elaborate (unlike the two
|
||||
// deliberate negative tests, neuron_parallel_guard_negative_*_tb.v)
|
||||
// -- that is itself part of the bug: no elaboration-time protection
|
||||
// exists for this specific boundary value.
|
||||
//
|
||||
// CONFIRMED on BOTH verification planes (§A.4):
|
||||
// - Simulation (this file): `start` never causes `busy` to assert;
|
||||
// `done` never pulses. Checked cycle-by-cycle for 200 cycles, not
|
||||
// a one-shot late check (an early investigation attempt used a
|
||||
// one-shot check-at-the-end and produced a methodologically
|
||||
// invalid "hang" verdict even for a KNOWN-GOOD N_INPUTS=2 sanity
|
||||
// config, because `done` is a documented single-cycle pulse,
|
||||
// rtl/neuron_parallel.v:207/227 -- see docs/validation/01-datapath.md
|
||||
// for the full self-correction narrative).
|
||||
// - Real synthesis: `yosys synth_ecp5` elaborates this exact
|
||||
// configuration with 0 reported problems. Root cause visible in
|
||||
// Yosys's own warnings: `x_bus`/`w_bus`, declared
|
||||
// `[DATA_WIDTH*N_INPUTS-1:0]` = `[-1:0]` for N_INPUTS=0, do NOT
|
||||
// collapse to a true zero-width bus -- Yosys (and, per this
|
||||
// simulation, Icarus) interpret a `[-1:0]` range as a genuine
|
||||
// 2-bit vector (width = |MSB-LSB|+1 = |-1-0|+1 = 2), left
|
||||
// completely undriven ("Wire ... is used but has no driver").
|
||||
//
|
||||
// This test currently PASSES by confirming the bug's exact symptom is
|
||||
// still present and unchanged -- it is a regression trap for the
|
||||
// CURRENT, documented-as-open, unfixed behavior (docs/validation/
|
||||
// bugs.md BUG-002), not a correctness assertion that this behavior is
|
||||
// desirable. If/when BUG-002 is fixed (e.g. an explicit `N_INPUTS==0`
|
||||
// elaboration guard is added), THIS test must be rewritten to expect
|
||||
// the new, fixed behavior instead -- do not "fix" it by loosening the
|
||||
// check.
|
||||
// ================================================================
|
||||
|
||||
module tb;
|
||||
|
||||
localparam DATA_WIDTH = 8;
|
||||
localparam PARALLEL = 2;
|
||||
localparam ACC_WIDTH = 32;
|
||||
|
||||
reg clk;
|
||||
initial begin
|
||||
clk = 1'b0;
|
||||
forever #5 clk = ~clk;
|
||||
end
|
||||
|
||||
reg rst, start;
|
||||
wire busy, done;
|
||||
wire signed [DATA_WIDTH-1:0] y;
|
||||
|
||||
integer cyc;
|
||||
integer errors;
|
||||
|
||||
neuron_parallel #(
|
||||
.DATA_WIDTH(DATA_WIDTH), .N_INPUTS(0), .PARALLEL(PARALLEL), .ACC_WIDTH(ACC_WIDTH)
|
||||
) dut (
|
||||
.clk(clk), .rst(rst), .start(start),
|
||||
.x_bus(), .w_bus(), .bias(8'sd0),
|
||||
.y(y), .busy(busy), .done(done)
|
||||
);
|
||||
|
||||
initial begin
|
||||
errors = 0;
|
||||
|
||||
$display("--- TEST 1: N_INPUTS=0 elaborates without error (confirms guard gap) ---");
|
||||
// If this file failed to compile/elaborate, the guard would
|
||||
// have started covering N_INPUTS=0 too -- that would be a fix
|
||||
// landing, not a regression. This $display only runs if
|
||||
// elaboration succeeded, which it must, for the test below to
|
||||
// even execute.
|
||||
$display(" elaborated successfully -- guard did NOT fire for N_INPUTS=0 (as of this writing)");
|
||||
|
||||
$display("--- TEST 2: start is accepted (busy asserts) within 200 cycles? ---");
|
||||
rst = 1; start = 0;
|
||||
repeat(3) @(posedge clk);
|
||||
rst = 0;
|
||||
@(posedge clk);
|
||||
start = 1;
|
||||
@(posedge clk);
|
||||
start = 0;
|
||||
|
||||
cyc = 0;
|
||||
while (!done && !busy && cyc < 200) begin
|
||||
@(posedge clk);
|
||||
cyc = cyc + 1;
|
||||
end
|
||||
|
||||
if (busy || done) begin
|
||||
// Behavior CHANGED from the confirmed-broken state -- this
|
||||
// is the "fix landed" case, not expected today.
|
||||
$display(" UNEXPECTED (relative to BUG-002 as currently documented): busy=%b done=%b at cycle %0d -- if this is a deliberate fix, update this test's expectations, don't just delete the check.", busy, done, cyc);
|
||||
errors = errors + 1;
|
||||
end else begin
|
||||
$display(" CONFIRMED (matches BUG-002, docs/validation/bugs.md): busy never asserted, done never pulsed in 200 cycles -- start was silently ineffective.");
|
||||
end
|
||||
|
||||
if (errors == 0)
|
||||
$display("ALL TESTS PASSED (BUG-002 symptom reproduced exactly as documented -- this is a KNOWN, OPEN bug, not a clean bill of health for N_INPUTS=0)");
|
||||
else
|
||||
$display("FAILED: %0d unexpected result(s) -- see messages above", errors);
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,5 +1,5 @@
|
||||
$date
|
||||
Fri Sep 4 13:23:02 2026
|
||||
Fri Sep 4 13:40:25 2026
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
$date
|
||||
Fri Sep 4 13:23:02 2026
|
||||
Fri Sep 4 13:40:25 2026
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
$date
|
||||
Fri Sep 4 13:23:07 2026
|
||||
Fri Sep 4 13:40:30 2026
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
$date
|
||||
Fri Sep 4 13:23:07 2026
|
||||
Fri Sep 4 13:40:30 2026
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
$date
|
||||
Fri Sep 4 13:23:07 2026
|
||||
Fri Sep 4 13:40:30 2026
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
$date
|
||||
Fri Sep 4 13:23:33 2026
|
||||
Fri Sep 4 13:40:57 2026
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
$date
|
||||
Fri Sep 4 13:23:17 2026
|
||||
Fri Sep 4 13:40:41 2026
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
$date
|
||||
Fri Sep 4 13:23:28 2026
|
||||
Fri Sep 4 13:40:52 2026
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
$date
|
||||
Fri Sep 4 13:23:35 2026
|
||||
Fri Sep 4 13:40:58 2026
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
|
||||
@@ -0,0 +1,313 @@
|
||||
010102010000000000000003
|
||||
01010201000003e8000003eb
|
||||
02010101000003e8000003eb
|
||||
bd4be50f0018cd950018b85f
|
||||
ff7afec3ffe201f6ffe201f6
|
||||
0a733a08ffefd14affefd798
|
||||
0cc49dadfff87fccfff89d15
|
||||
1d9b7be4000dc1da000da8f5
|
||||
518e08db0006102e0005eaf4
|
||||
020873adffe94b82ffe92649
|
||||
4586613effe49f1fffe495bb
|
||||
5dc3db5efffb7993fffb55d4
|
||||
000d8ec2ffe7b08bffe7cc27
|
||||
6a2d0d24ffff2aeeffff3f64
|
||||
9fdb2eeefffd2e32fffd38fb
|
||||
60e536130005083e00050220
|
||||
fcbe4fa5ffe9f34dffe9d840
|
||||
1468468effeefd23ffeee617
|
||||
c6d8c7c40015fa85001610f1
|
||||
729062190001366100010e13
|
||||
3625df60ffe6d55effe6d0cc
|
||||
6ca9d49afffc4da4fffc3a78
|
||||
dff589f8ffe8da9affe8dfbd
|
||||
4a8439c1fff44c47fff41a68
|
||||
f838cdd7ffe95c12ffe9627d
|
||||
7c11807d0019ab16001974d2
|
||||
ec3d9232001e5c0d001e41cd
|
||||
e796233d000236be0002496f
|
||||
75d886370005ed470005c0c9
|
||||
4b542a430019d8150019fbaf
|
||||
c6ff8ebc0018ab880018ca0a
|
||||
0191475a001b17e7001b306e
|
||||
89a8be3200066e1600068a1a
|
||||
c4b7555f0000e3a80001144f
|
||||
d076684effed2df2ffed3782
|
||||
5640429ffffb8ddafffb8a58
|
||||
4117ca88ffeaab8effeacab5
|
||||
a8c8576ffff92268fff95b61
|
||||
3699aae0fffcb954fffcae5a
|
||||
22a650990009702e0009440a
|
||||
01aed7a8fffa3798fffa455e
|
||||
8f85a70afff59ed4fff5d1a5
|
||||
75b451bdfff480bbfff448cc
|
||||
e807fc26000e4f58000e4e18
|
||||
8dce0e6f001c8f7c001cac04
|
||||
f212f33cfff61190fff60d88
|
||||
47e8493efff4c5d7fff4d0dd
|
||||
90a6ba8e00065c850006a311
|
||||
06467307ffeb5f30ffeb63f9
|
||||
df01ea67fffd474cfffd3e51
|
||||
57dbef48fffb3582fffb2427
|
||||
d0e0a190000786790007b609
|
||||
18bf4e1a00000bed00000dc1
|
||||
4d0c90c5fff9f65ffffa13cb
|
||||
bd5ac4faffe1c904ffe1b2de
|
||||
d351238a0005b7e500059986
|
||||
cca902e5ffe4fea9ffe5101f
|
||||
2aee00f9ffefcb56ffefc862
|
||||
262d65e2001610e600160bbe
|
||||
e83c7786ffe45874ffe41a1e
|
||||
c0d3b71afff8091afff80cf0
|
||||
158651e4001a1dfb001a0b1d
|
||||
2528ed6d000f9846000f95f7
|
||||
818d72c300040eda00042cbd
|
||||
569a14c1ffe35fdeffe338ae
|
||||
c65666fdffec908bffec7bdd
|
||||
8b2b8c8900056c0000058e45
|
||||
da075361ffe91ba1ffe93a0a
|
||||
d1b323befff280c4fff285e1
|
||||
22a36a4efff4570cfff46afe
|
||||
a2e5e8a5000a98d5000aab47
|
||||
1806ddb6000ebe28000ec8d6
|
||||
cc0f01f0ffeccfa4ffeccc88
|
||||
e1f88b06000aaeec000aad26
|
||||
f9a0742cffeba0b8ffebb748
|
||||
dd701d67ffee5b3bffee5796
|
||||
6ee89cbefff5ced2fff5de4a
|
||||
f764246d00000bbe0000178e
|
||||
d9e7ec75ffe6106bffe60b16
|
||||
1087d468000a1aea000a017a
|
||||
fb4c4542000408cf0004191d
|
||||
ad8513ddffebfdf4ffec233c
|
||||
c857dd2cffedff1fffede613
|
||||
f58610e00000ea550000ed93
|
||||
e08d873e000a2688000a179a
|
||||
5a5805befff4fa3cfff517e2
|
||||
28be8b00001cbe7c001cb42c
|
||||
c6b09528fff33d6afff33ed2
|
||||
5104857c00026c25000231d5
|
||||
0dcf3a68ffe54401ffe55914
|
||||
005098cd000fe29c000ff754
|
||||
0fe227a5ffedd757ffedc7b8
|
||||
02242eb20012993900128b7d
|
||||
1c0fdccc001a4bf8001a54ec
|
||||
fbad7b4d00175e8e0017852c
|
||||
edf7978b0008510f000881b7
|
||||
be1290d900075546000761b2
|
||||
5f82de74000c0f56000bd12c
|
||||
3fd736d4fff5aa50fff596f1
|
||||
158cb806ffeadfcfffead49b
|
||||
f9109392fff281cafff2b030
|
||||
24d9bcdefff14a52fff14dde
|
||||
ce987afeffee4aa2ffee5dfe
|
||||
5bd538e8001d54e6001d405d
|
||||
e295dbab0011dd3b0011f60e
|
||||
98d4b1300000c8ee0000cbfe
|
||||
d20d3e3cfff46124fff46d56
|
||||
bbb98c4800025276000244f9
|
||||
6d7d0d280010e58000111cc1
|
||||
e46e3766ffe429d7ffe433b9
|
||||
16e45fd0000814130007ffdb
|
||||
e9c9ca810017828e0017a249
|
||||
acfb04c9ffefbf47ffefc00f
|
||||
6214fc7bffea734fffea790b
|
||||
723a814b0011787a00116d19
|
||||
931e969a0013e2b70014002d
|
||||
8070984ffff40561fff3ad49
|
||||
667a3b760000eb8f0001375d
|
||||
f5826451fff6d249fff6f757
|
||||
60be22ba0005dc600005ba54
|
||||
e7e33a56001b4244001b5895
|
||||
2e56624300007ae20000a3fc
|
||||
7e8c3039000919e10008eb79
|
||||
7ae441adfffbd2ebfffbb080
|
||||
858bed6700019f650001cff7
|
||||
a8e6ebadfff8c48ffff8d44e
|
||||
5fa08676fffc382cfffbdc50
|
||||
53e41748000a084b000a05af
|
||||
95cbb6ac001b7bd3001baa42
|
||||
71eb5c63001072fa00108d49
|
||||
6fabe1a0ffea6066ffea472b
|
||||
a71a8387000f27ef000f59fa
|
||||
4e1173f2001a5d5f001a5c43
|
||||
29b8b1470004b00300048e92
|
||||
db1cd7e5fff815c8fff8160f
|
||||
3b77d220fffbe3dbfffbf988
|
||||
ff2b8ae7ffe853d2ffe85f2d
|
||||
141cadb8ffeaefacffeb0934
|
||||
c1f8e920fffd7840fffd7758
|
||||
770eca72000f8fbc000f7e32
|
||||
912cf5eafff65ffbfff64dd9
|
||||
ec6bc941fff1f3d1fff1dd7e
|
||||
7279f2e600177a630017b1b1
|
||||
8fb5eb02000a150b000a35fc
|
||||
d061af25000046a2000028bd
|
||||
e018796700012509000152b8
|
||||
cf68ffb8ffe96fccffe95c2c
|
||||
da396a58ffefb77affefd374
|
||||
d1c5447dffe4cff6ffe4fbff
|
||||
5aa1bcef0016b20400169522
|
||||
5385e2c1fff43347fff412c8
|
||||
a470fb25ffe95c3dffe93344
|
||||
7ac9d65e0008739a000849f8
|
||||
3e9b54bb000e8812000e58f8
|
||||
53ad5aedffe91c99ffe8fb02
|
||||
53718c9d00072b4f00077cce
|
||||
5aa84e25000a86f0000a7346
|
||||
8a6f14d30019a19800196aea
|
||||
a30ce8ee000c3c3b000c398f
|
||||
541bdc500014c30a0014c0a6
|
||||
dd7e2e2f001df291001de9c9
|
||||
7f70d3bb000c6d70000cb121
|
||||
d8a0830ffff605ebfff60d98
|
||||
e8f75f56ffeb152affeb35ec
|
||||
b2116cd8ffe82a97ffe81489
|
||||
e8c8f3f400195f5900196535
|
||||
c9ddc1cc00156fe100158432
|
||||
05eefe06fffd2a9efffd2a38
|
||||
c702f4dd0018d2140018d346
|
||||
fe905fe5ffe6ecc7ffe6e3a2
|
||||
c839475afffaeea7fffafb25
|
||||
1eb92900ffebe60cffebddba
|
||||
3387b1eaffffbcbeffffab6d
|
||||
375319a6fff841a5fff84ab0
|
||||
37c0abaefff16e10fff17b8a
|
||||
58e15d9dffe93e90ffe90ff1
|
||||
0608f0a9001aa3bc001aa95c
|
||||
57387ae8fff4dd48fff4e4e0
|
||||
d50c7bf0fffcf9eafffcf036
|
||||
765f6f0affea3899ffea68b9
|
||||
779ca35afff142b5fff0f387
|
||||
e52db31f0002538300024571
|
||||
79b4bb9dffeaafdcffeaa69f
|
||||
4df6a2270011b9e20011a88e
|
||||
83fb97c70003759f00038f71
|
||||
c5e953a5fffb076dfffaef39
|
||||
e36e3631001a7e88001a7c68
|
||||
c60d67affff807a9fff7e420
|
||||
87cdee52fff7c6f1fff7d948
|
||||
4007693f0000b1550000ccec
|
||||
cb59e67c0010e45f0010c55a
|
||||
ab126a5c0002c8890002e8a7
|
||||
ad0ecf19ffeefeafffeef55c
|
||||
1594631f0003f3ec0003f70d
|
||||
10bf6e4cffeffeacfff01b44
|
||||
f6bce59b0005f4f500060244
|
||||
dfb3f459001191ca0011978b
|
||||
6aac6ba2ffe8eb95ffe8a183
|
||||
469a77b800132ee60012f18a
|
||||
5f4c0e11ffe80987ffe826a9
|
||||
ed07ed3bfff57238fff56d52
|
||||
4524a14d00092d6300091a84
|
||||
6da73ea700016bce0001305b
|
||||
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|
||||
4b1b177bffe95188ffe9647e
|
||||
516bee000010b65d0010d838
|
||||
2c2e483bfff90577fff91df7
|
||||
52c79733ffffd4f0ffffadc3
|
||||
9a8876bb001cb489001cc48b
|
||||
d017936dfff7513ffff71e86
|
||||
fe406099fffbb688fffb8f68
|
||||
4d41a9fa0000bc040000d19b
|
||||
2be3b042000217d70001fe58
|
||||
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|
||||
15543321fff9c073fff9cdea
|
||||
00b0456a001e3125001e4db7
|
||||
a9c24f5ffffe9ae0fffecd43
|
||||
e4b540580010ed9500110bc9
|
||||
9914566dffe30f0cffe32b9e
|
||||
934b5c8d000f5e20000f14dd
|
||||
01e8e447fffcc85afffcc07e
|
||||
b186310dffff9006ffffb829
|
||||
9531b440000b8d06000b658b
|
||||
5e91ac9bfff8b9e8fff8b24a
|
||||
e2cf86cbffe290d2ffe2afd2
|
||||
352a774affec354cffec6064
|
||||
1b28625c0011bcd20011e442
|
||||
ebb924d2fffd973cfffd9697
|
||||
f628063200112e2300112dbf
|
||||
f0ebd212001ddcc0001ddad4
|
||||
9809356bffed82d6ffed9555
|
||||
87760c65ffe82b7effe7f874
|
||||
7cf12f75000e27a1000e35d8
|
||||
7818690b000afc7a000b0c3d
|
||||
cd8003b3fffaadc2fffac65b
|
||||
5cf076df0006a1de00068ce8
|
||||
87bc0071ffed22caffed42ee
|
||||
1d5aef1cffeb76daffeb7f30
|
||||
9405e60000096b2d00096911
|
||||
cd803798000d550c000d5834
|
||||
78ae10bcfffe5296fffe27e6
|
||||
6fe3d11600035f2e00034e91
|
||||
00da01e7fff76c6dfff76c54
|
||||
7425d4d200066b9d00068449
|
||||
fc98810e0004c82a0004c2d8
|
||||
43470923ffe6f196ffe70566
|
||||
e2dd1fcdfffd17bffffd15ac
|
||||
dc6c6a5effe7135affe72b16
|
||||
c9bafe95fff5f191fff60171
|
||||
77db3bd00011a4f0001188ad
|
||||
c247cd16ffea3ce7ffea2753
|
||||
3bb375b7001b8a72001b5756
|
||||
c7e3b109001cb08a001cb438
|
||||
ae22add9000c1902000c1ac3
|
||||
7add47470008b1aa0008b4ad
|
||||
0c1c78f10014e7ff0014e247
|
||||
5f0af63e0001410f00014259
|
||||
b95a6ed3fffbd619fffba9cd
|
||||
7e0dd8e9ffe38120ffe38b1e
|
||||
8d444401000dd383000db53b
|
||||
da03c35f001a5a49001a4334
|
||||
0d57fd99001cff2a001d04ca
|
||||
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93249eb07fb94c7ca1719d502bdf347c0017c83e0017a3e7
|
||||
bf89e99ee41a5289900b72af1b35f6f1ffed859cffed60f6
|
||||
4610fecf337e89567b1f1e182801c33b00099b35000994e5
|
||||
808080808080808080808080808080800000000000020000
|
||||
807f807f807f807f807f807f807f807f00000000fffe0400
|
||||
808080808080808080808080808080807fffffff8001ffff
|
||||
807f807f807f807f807f807f807f807f7fffffff7ffe03ff
|
||||
808080808080808080808080808080808000000080020000
|
||||
807f807f807f807f807f807f807f807f800000007ffe0400
|
||||
808080808080808080808080808080804000000040020000
|
||||
807f807f807f807f807f807f807f807f400000003ffe0400
|
||||
80808080808080808080808080808080c0000000c0020000
|
||||
807f807f807f807f807f807f807f807fc0000000bffe0400
|
||||
@@ -0,0 +1,81 @@
|
||||
#!/usr/bin/env python3
|
||||
"""
|
||||
Independent Python oracle for rtl/mac_unit.v and rtl/mac8.v (aspect C.1 of
|
||||
the re-certification campaign, docs/validation/01-datapath.md).
|
||||
|
||||
Deliberately reimplements the arithmetic from first principles (two's
|
||||
complement wraparound, sign extension) -- NOT by reading the Verilog and
|
||||
transcribing it. Every function below is checked against Python's own
|
||||
built-in arbitrary-precision integers, which have no width and cannot
|
||||
share a truncation/sign-extension bug with the RTL.
|
||||
|
||||
Run standalone to regenerate the golden vectors used by
|
||||
sim/mac_unit_tb.v / sim/mac8_tree_tb.v:
|
||||
python3 tools/validation/mac_oracle.py
|
||||
"""
|
||||
|
||||
def to_signed(val: int, width: int) -> int:
|
||||
"""Interpret the low `width` bits of `val` as two's complement."""
|
||||
val &= (1 << width) - 1
|
||||
if val >= (1 << (width - 1)):
|
||||
val -= (1 << width)
|
||||
return val
|
||||
|
||||
def to_unsigned(val: int, width: int) -> int:
|
||||
return val & ((1 << width) - 1)
|
||||
|
||||
def mac_unit(x: int, w: int, acc_in: int, data_width: int = 8, acc_width: int = 32) -> int:
|
||||
"""Bit-exact model of rtl/mac_unit.v: acc_out = acc_in + sign_extend(x*w)."""
|
||||
assert -(1 << (data_width - 1)) <= x < (1 << (data_width - 1))
|
||||
assert -(1 << (data_width - 1)) <= w < (1 << (data_width - 1))
|
||||
product = x * w # Python int, exact, no width -- the whole point of an independent oracle
|
||||
prod_width = 2 * data_width
|
||||
assert -(1 << (prod_width - 1)) <= product < (1 << (prod_width - 1)), \
|
||||
"product overflowed PROD_WIDTH -- data_width assumption violated"
|
||||
raw = to_unsigned(acc_in, acc_width) + to_unsigned(product, prod_width if product >= 0 else prod_width)
|
||||
# acc_in + sign_extend(product) computed directly in signed arithmetic,
|
||||
# then wrapped to acc_width bits (matches Verilog's silent wraparound
|
||||
# on a fixed-width signed reg/wire -- confirmed intentional, not a
|
||||
# bug, because callers rely on it: see docs/validation/01-datapath.md).
|
||||
return to_signed(acc_in + product, acc_width)
|
||||
|
||||
def mac8_tree(products: list[int], acc_in: int, acc_width: int = 32) -> int:
|
||||
"""
|
||||
Bit-exact model of rtl/mac8.v's balanced binary adder tree +
|
||||
final accumulator add. `products` must have length PARALLEL (a power
|
||||
of two, matching the RTL's $clog2-based tree construction).
|
||||
"""
|
||||
n = len(products)
|
||||
assert n > 0 and (n & (n - 1)) == 0, "PARALLEL must be a power of two"
|
||||
level = list(products)
|
||||
while len(level) > 1:
|
||||
level = [to_signed(level[i] + level[i + 1], acc_width) for i in range(0, len(level), 2)]
|
||||
return to_signed(acc_in + level[0], acc_width)
|
||||
|
||||
def mac8_full(x_vals: list[int], w_vals: list[int], acc_in: int,
|
||||
data_width: int = 8, acc_width: int = 32) -> int:
|
||||
"""End-to-end oracle: PARALLEL independent products -> balanced tree -> + acc_in."""
|
||||
assert len(x_vals) == len(w_vals)
|
||||
products = [mac_unit(x, w, 0, data_width, acc_width) for x, w in zip(x_vals, w_vals)]
|
||||
return mac8_tree(products, acc_in, acc_width)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
# Self-check: a handful of hand-verifiable cases, printed for a human
|
||||
# to eyeball before trusting this file as an oracle for anything else.
|
||||
cases = [
|
||||
(5, 7, 0, 35),
|
||||
(-128, -128, 0, 16384), # the one INT8 x INT8 case that does NOT fit in INT16 magnitude terms symmetrically
|
||||
(127, 127, 0, 16129),
|
||||
(-128, 127, 0, -16256),
|
||||
(0, 0, 0, 0),
|
||||
(-1, -1, 0, 1),
|
||||
]
|
||||
ok = True
|
||||
for x, w, acc_in, expected in cases:
|
||||
got = mac_unit(x, w, acc_in)
|
||||
status = "OK" if got == expected else "MISMATCH"
|
||||
if got != expected:
|
||||
ok = False
|
||||
print(f"mac_unit(x={x}, w={w}, acc_in={acc_in}) = {got} (expected {expected}) {status}")
|
||||
print("ALL SELF-CHECKS PASSED" if ok else "SELF-CHECK FAILURE -- oracle itself is wrong, fix before using it")
|
||||
@@ -0,0 +1,486 @@
|
||||
bde50000000000000711
|
||||
4b0f0000000000000465
|
||||
fffe0000000000000002
|
||||
7ac300000000ffffe2ee
|
||||
840a00000000fffffb28
|
||||
3a730000000000001a0e
|
||||
08f200000000ffffff90
|
||||
0c9d00000000fffffb5c
|
||||
c4ad0000000000001374
|
||||
381d0000000000000658
|
||||
7b9b00000000ffffcf79
|
||||
e45100000000fffff724
|
||||
088e00000000fffffc70
|
||||
db0200000000ffffffb6
|
||||
73080000000000000398
|
||||
adbe0000000000001566
|
||||
45610000000000001a25
|
||||
863e00000000ffffe274
|
||||
995d00000000ffffda95
|
||||
dbc300000000000008d1
|
||||
5e4f0000000000001d02
|
||||
008e0000000000000000
|
||||
0dc200000000fffffcda
|
||||
b16a00000000ffffdf4a
|
||||
0d2d0000000000000249
|
||||
246d0000000000000f54
|
||||
9f2e00000000ffffee92
|
||||
dbee000000000000029a
|
||||
5d6000000000000022e0
|
||||
36e500000000fffffa4e
|
||||
13fc00000000ffffffb4
|
||||
4fbe00000000ffffeba2
|
||||
a5c300000000000015af
|
||||
14460000000000000578
|
||||
688e00000000ffffd1b0
|
||||
ecc60000000000000488
|
||||
c7d800000000000008e8
|
||||
c47200000000ffffe548
|
||||
629000000000ffffd520
|
||||
197d0000000000000c35
|
||||
36df00000000fffff90a
|
||||
25600000000000000de0
|
||||
aa6c00000000ffffdbb8
|
||||
d4a90000000000000ef4
|
||||
9a5600000000ffffddbc
|
||||
df890000000000000f57
|
||||
f5f80000000000000058
|
||||
ba4a00000000ffffebc4
|
||||
398400000000ffffe464
|
||||
c11600000000fffffa96
|
||||
f8cd0000000100000199
|
||||
38d700000001fffff709
|
||||
bf7c00000001ffffe085
|
||||
801100000001fffff781
|
||||
7dec00000001fffff63d
|
||||
923d00000001ffffe5cb
|
||||
32e700000001fffffb1f
|
||||
239600000001fffff183
|
||||
3d750000000100001be2
|
||||
86d80000000100001311
|
||||
374b000000010000101e
|
||||
2a540000000100000dc9
|
||||
43c600000001fffff0d3
|
||||
8eff0000000100000073
|
||||
bc0100000001ffffffbd
|
||||
479100000001ffffe138
|
||||
5a8900000001ffffd62b
|
||||
bea800000001000016b1
|
||||
32c400000001fffff449
|
||||
55b700000001ffffe7c4
|
||||
5f7b0000000100002da6
|
||||
d06800000001ffffec81
|
||||
764e00000001000023f5
|
||||
dd5600000001fffff43f
|
||||
42400000000100001081
|
||||
9f5000000001ffffe1b1
|
||||
41ca00000001fffff24b
|
||||
178800000001fffff539
|
||||
c9a800000001000012e9
|
||||
57c800000001ffffecf9
|
||||
6f3d0000000100001a74
|
||||
36aa00000001ffffeddd
|
||||
99e00000000100000ce1
|
||||
59220000000100000bd3
|
||||
50a600000001ffffe3e1
|
||||
990100000001ffffff9a
|
||||
d7ae0000000100000d23
|
||||
a84500000001ffffe849
|
||||
8fa7000000010000274a
|
||||
850a00000001fffffb33
|
||||
21750000000100000f16
|
||||
51b400000001ffffe7f5
|
||||
bd1800000001fffff9b9
|
||||
e8fc0000000100000061
|
||||
0726000000010000010b
|
||||
8d0e00000001fffff9b7
|
||||
ce6f00000001ffffea53
|
||||
f2f300000001000000b7
|
||||
123c0000000100000439
|
||||
244700000001000009fd
|
||||
49e8fffffffffffff927
|
||||
3e1affffffff0000064b
|
||||
90baffffffff00001e9f
|
||||
a68effffffff00002813
|
||||
0673ffffffff000002b1
|
||||
4607ffffffff000001e9
|
||||
cfdfffffffff00000650
|
||||
ea01ffffffffffffffe9
|
||||
675effffffff000025d1
|
||||
57effffffffffffffa38
|
||||
db48fffffffffffff597
|
||||
4dd0fffffffffffff18f
|
||||
a1e0ffffffff00000bdf
|
||||
9018fffffffffffff57f
|
||||
4ebfffffffffffffec31
|
||||
1a74ffffffff00000bc7
|
||||
4d90ffffffffffffde4f
|
||||
0cc5fffffffffffffd3b
|
||||
43bdffffffffffffee76
|
||||
c45affffffffffffeae7
|
||||
fa82ffffffff000002f3
|
||||
d323fffffffffffff9d8
|
||||
518affffffffffffdaa9
|
||||
cc02ffffffffffffff97
|
||||
a9e5ffffffff0000092c
|
||||
9c2affffffffffffef97
|
||||
00eeffffffffffffffff
|
||||
f9f2ffffffff00000061
|
||||
2665ffffffff00000efd
|
||||
2de2fffffffffffffab9
|
||||
e877fffffffffffff4d7
|
||||
3c86ffffffffffffe367
|
||||
96c0ffffffff00001a7f
|
||||
b7d3ffffffff00000cd4
|
||||
1a34ffffffff00000547
|
||||
1551ffffffff000006a4
|
||||
86e4ffffffff00000d57
|
||||
25edfffffffffffffd40
|
||||
286dffffffff00001107
|
||||
8172ffffffffffffc771
|
||||
8dc3ffffffff00001b66
|
||||
5614ffffffff000006b7
|
||||
9ac1ffffffff00001919
|
||||
8fc6ffffffff00001999
|
||||
6656ffffffff00002243
|
||||
fdd8ffffffff00000077
|
||||
8b8cffffffff00003503
|
||||
2b89ffffffffffffec02
|
||||
da53fffffffffffff3ad
|
||||
0761ffffffff000002a6
|
||||
bdd17fffffff80000c4c
|
||||
23b37fffffff7ffff578
|
||||
be087fffffff7ffffdef
|
||||
226a7fffffff80000e13
|
||||
a34e7fffffff7fffe3a9
|
||||
16a27fffffff7ffff7eb
|
||||
e8e57fffffff80000287
|
||||
a5187fffffff7ffff777
|
||||
dd067fffffff7fffff2d
|
||||
b6cc7fffffff80000f07
|
||||
010f7fffffff8000000e
|
||||
f0da7fffffff8000025f
|
||||
e18b7fffffff80000e2a
|
||||
f8067fffffff7fffffcf
|
||||
f9747fffffff7ffffcd3
|
||||
a02c7fffffff7fffef7f
|
||||
d1dd7fffffff8000066c
|
||||
1d707fffffff80000caf
|
||||
67e67fffffff7ffff589
|
||||
6e9c7fffffff7fffd507
|
||||
e8be7fffffff8000062f
|
||||
22f77fffffff7ffffecd
|
||||
24647fffffff80000e0f
|
||||
6d747fffffff80003163
|
||||
d9ec7fffffff8000030b
|
||||
e7757fffffff7ffff492
|
||||
a4107fffffff7ffffa3f
|
||||
d4877fffffff800014cb
|
||||
68fb7fffffff7ffffdf7
|
||||
454c7fffffff8000147b
|
||||
42ad7fffffff7fffea99
|
||||
13857fffffff7ffff6de
|
||||
ddd47fffffff80000603
|
||||
c8dd7fffffff800007a7
|
||||
572c7fffffff80000ef3
|
||||
e4f57fffffff80000133
|
||||
10867fffffff7ffff85f
|
||||
e07b7fffffff7ffff09f
|
||||
e0877fffffff80000f1f
|
||||
8d3e7fffffff7fffe425
|
||||
5a057fffffff800001c1
|
||||
58be7fffffff7fffe94f
|
||||
1b287fffffff80000437
|
||||
8bbe7fffffff80001e29
|
||||
00c67fffffff7fffffff
|
||||
95b07fffffff8000216f
|
||||
280e7fffffff8000022f
|
||||
51857fffffff7fffd914
|
||||
047c7fffffff800001ef
|
||||
0d3a7fffffff800002f1
|
||||
cf68800000007fffec18
|
||||
9e008000000080000000
|
||||
9850800000007fffdf80
|
||||
cd0f800000007ffffd03
|
||||
27e2800000007ffffb6e
|
||||
a5e28000000080000aaa
|
||||
022e800000008000005c
|
||||
24b2800000007ffff508
|
||||
1cdc800000007ffffc10
|
||||
0fcc800000007ffffcf4
|
||||
fb7b800000007ffffd99
|
||||
ad4d800000007fffe709
|
||||
ed9780000000800007cb
|
||||
f78b800000008000041d
|
||||
be908000000080001ce0
|
||||
12d9800000007ffffd42
|
||||
5fde800000007ffff362
|
||||
8274800000007fffc6e8
|
||||
3f368000000080000d4a
|
||||
d7d4800000008000070c
|
||||
211580000000800002b5
|
||||
b88c80000000800020a0
|
||||
06cb800000007ffffec2
|
||||
f99380000000800002fb
|
||||
1092800000007ffff920
|
||||
08248000000080000120
|
||||
bcd98000000080000a5c
|
||||
defe8000000080000044
|
||||
ce7a800000007fffe82c
|
||||
98fe80000000800000d0
|
||||
e65b800000007ffff6c2
|
||||
38d5800000007ffff698
|
||||
e8e280000000800002d0
|
||||
db958000000080000f77
|
||||
ab988000000080002288
|
||||
b1d48000000080000d94
|
||||
307a80000000800016e0
|
||||
d23e800000007ffff4dc
|
||||
0d3c800000008000030c
|
||||
17bb800000007ffff9cd
|
||||
8cb9800000008000202c
|
||||
486d8000000080001ea8
|
||||
0d7d8000000080000659
|
||||
28e4800000007ffffba0
|
||||
376e80000000800017a2
|
||||
6695800000007fffd55e
|
||||
165f800000008000082a
|
||||
e4d08000000080000540
|
||||
e9ca80000000800004da
|
||||
c9818000000080001b49
|
||||
ac04400000003ffffeb0
|
||||
fbc94000000040000113
|
||||
f262400000003ffffaa4
|
||||
fc14400000003fffffb0
|
||||
7bc7400000003fffe49d
|
||||
7281400000003fffc772
|
||||
3a4b40000000400010fe
|
||||
93964000000040002d22
|
||||
1e9a400000003ffff40c
|
||||
80984000000040003400
|
||||
704f4000000040002290
|
||||
146640000000400007f8
|
||||
3b7a4000000040001c1e
|
||||
767b40000000400038b2
|
||||
f564400000003ffffbb4
|
||||
8251400000003fffd822
|
||||
2a604000000040000fc0
|
||||
22be400000003ffff73c
|
||||
bae740000000400006d6
|
||||
3ae3400000003ffff96e
|
||||
562e4000000040000f74
|
||||
625640000000400020ec
|
||||
43774000000040001f25
|
||||
7e3040000000400017a0
|
||||
8c39400000003fffe62c
|
||||
7a414000000040001efa
|
||||
e4ad4000000040000914
|
||||
5285400000003fffd89a
|
||||
ed8b40000000400008af
|
||||
67a8400000003fffdc98
|
||||
ebe64000000040000222
|
||||
ad3a400000003fffed32
|
||||
5f86400000003fffd2ba
|
||||
a076400000003fffd3c0
|
||||
55534000000040001b8f
|
||||
17e4400000003ffffd7c
|
||||
4895400000003fffe1e8
|
||||
b6cb4000000040000f52
|
||||
ac71400000003fffdaec
|
||||
5ceb400000003ffff874
|
||||
636f4000000040002aed
|
||||
e1ab4000000040000a4b
|
||||
a0c74000000040001560
|
||||
a7834000000040002b75
|
||||
1a87400000003ffff3b6
|
||||
4e73400000004000230a
|
||||
11f2400000003fffff12
|
||||
29b1400000003ffff359
|
||||
b847400000003fffec08
|
||||
dbd740000000400005ed
|
||||
1ce5c0000000bffffd0c
|
||||
343bc0000000c0000bfc
|
||||
d277c0000000bfffea9e
|
||||
2053c0000000c0000a60
|
||||
ff8ac0000000c0000076
|
||||
2be7c0000000bffffbcd
|
||||
b614c0000000bffffa38
|
||||
ad1cc0000000bffff6ec
|
||||
b8cbc0000000c0000ee8
|
||||
c1e9c0000000c00005a9
|
||||
f820c0000000bfffff00
|
||||
5f77c0000000c0002c29
|
||||
ca0ec0000000bffffd0c
|
||||
7291c0000000bfffce92
|
||||
f52cc0000000bffffe1c
|
||||
ea27c0000000bffffca6
|
||||
ecc9c0000000c000044c
|
||||
6b41c0000000c0001b2b
|
||||
0372c0000000c0000156
|
||||
f279c0000000bffff962
|
||||
e68fc0000000c0000b7a
|
||||
ebb5c0000000c0000627
|
||||
02d0c0000000bfffffa0
|
||||
af61c0000000bfffe14f
|
||||
2576c0000000c000110e
|
||||
e079c0000000bffff0e0
|
||||
1867c0000000c00009a8
|
||||
7dcfc0000000bfffe813
|
||||
ff68c0000000bfffff98
|
||||
b8bfc0000000c0001248
|
||||
da6ac0000000bffff044
|
||||
3958c0000000c0001398
|
||||
f1d1c0000000c00002c1
|
||||
44c5c0000000bffff054
|
||||
7d9ac0000000bfffce32
|
||||
5abcc0000000bfffe818
|
||||
a1efc0000000c000064f
|
||||
53e2c0000000bffff646
|
||||
85c1c0000000c0001e45
|
||||
15a4c0000000bffff874
|
||||
fb70c0000000bffffdd0
|
||||
25bfc0000000bffff69b
|
||||
7ad6c0000000bfffebfc
|
||||
c95ec0000000bfffebce
|
||||
3e54c0000000c0001458
|
||||
9bbbc0000000c0001b39
|
||||
535ac0000000c0001d2e
|
||||
adedc0000000c0000629
|
||||
bd53c0000000bfffea47
|
||||
8c71c0000000bfffcccc
|
||||
9d5a00bc614e00bc3e80
|
||||
4ea800bc614e00bc467e
|
||||
258a00bc614e00bc5040
|
||||
146f00bc614e00bc69fa
|
||||
d3a300bc614e00bc71a7
|
||||
e80c00bc614e00bc602e
|
||||
ee5400bc614e00bc5b66
|
||||
dc1b00bc614e00bc5d82
|
||||
50dd00bc614e00bc565e
|
||||
2e7e00bc614e00bc77f2
|
||||
2f7f00bc614e00bc789f
|
||||
d37000bc614e00bc4d9e
|
||||
bbd800bc614e00bc6c16
|
||||
83a000bc614e00bc902e
|
||||
0f2400bc614e00bc636a
|
||||
e85f00bc614e00bc5866
|
||||
f75600bc614e00bc5e48
|
||||
ccb200bc614e00bc7126
|
||||
6c1100bc614e00bc687a
|
||||
d8b500bc614e00bc6d06
|
||||
e8f300bc614e00bc6286
|
||||
c8f400bc614e00bc63ee
|
||||
c9c100bc614e00bc6ed7
|
||||
ddcc00bc614e00bc686a
|
||||
05fe00bc614e00bc6144
|
||||
ee0600bc614e00bc60e2
|
||||
5dc700bc614e00bc4c99
|
||||
f40200bc614e00bc6136
|
||||
ddfe00bc614e00bc6194
|
||||
5f9000bc614e00bc37be
|
||||
e5ab00bc614e00bc6a45
|
||||
c84700bc614e00bc51c6
|
||||
395a00bc614e00bc7558
|
||||
4b1e00bc614e00bc6a18
|
||||
29b900bc614e00bc55ef
|
||||
00d300bc614e00bc614e
|
||||
33b100bc614e00bc5191
|
||||
87ea00bc614e00bc6bb4
|
||||
723700bc614e00bc79cc
|
||||
195300bc614e00bc6969
|
||||
a63600bc614e00bc4e52
|
||||
37ab00bc614e00bc4f0b
|
||||
c0ae00bc614e00bc75ce
|
||||
ff5800bc614e00bc60f6
|
||||
5de100bc614e00bc560b
|
||||
9dbe00bc614e00bc7ad4
|
||||
06f000bc614e00bc60ee
|
||||
08a900bc614e00bc5e96
|
||||
577a00bc614e00bc8ac4
|
||||
38e800bc614e00bc5c0e
|
||||
1bd5ff439eb2ff439a29
|
||||
7b0cff439eb2ff43a476
|
||||
f05bff439eb2ff439902
|
||||
766fff439eb2ff43d1dc
|
||||
5f0aff439eb2ff43a268
|
||||
c577ff439eb2ff438345
|
||||
a39cff439eb2ff43c306
|
||||
5afeff439eb2ff439dfe
|
||||
e5b3ff439eb2ff43a6d1
|
||||
2d1fff439eb2ff43a425
|
||||
79bbff439eb2ff437e15
|
||||
b49dff439eb2ff43bc16
|
||||
c94dff439eb2ff438e27
|
||||
a2f6ff439eb2ff43a25e
|
||||
2783ff439eb2ff438ba7
|
||||
97fbff439eb2ff43a0bf
|
||||
c7c5ff439eb2ff43abd5
|
||||
53e9ff439eb2ff43973d
|
||||
a54cff439eb2ff4383ae
|
||||
e336ff439eb2ff439894
|
||||
6e31ff439eb2ff43b3c0
|
||||
c667ff439eb2ff43875c
|
||||
0dafff439eb2ff439a95
|
||||
3487ff439eb2ff43861e
|
||||
eecdff439eb2ff43a248
|
||||
5232ff439eb2ff43aeb6
|
||||
4069ff439eb2ff43b8f2
|
||||
073fff439eb2ff43a06b
|
||||
79cbff439eb2ff4385a5
|
||||
e659ff439eb2ff4395a8
|
||||
7cabff439eb2ff437586
|
||||
6a12ff439eb2ff43a626
|
||||
5cadff439eb2ff4380de
|
||||
cf0eff439eb2ff439c04
|
||||
19ecff439eb2ff439cbe
|
||||
1563ff439eb2ff43a6d1
|
||||
941fff439eb2ff43919e
|
||||
106eff439eb2ff43a592
|
||||
bf4cff439eb2ff438b66
|
||||
f4f6ff439eb2ff439f2a
|
||||
e5bcff439eb2ff43a5de
|
||||
9bdfff439eb2ff43abb7
|
||||
f4b3ff439eb2ff43a24e
|
||||
596aff439eb2ff43c38c
|
||||
6bacff439eb2ff437b96
|
||||
a2bbff439eb2ff43b808
|
||||
4677ff439eb2ff43bf3c
|
||||
9ab8ff439eb2ff43bb62
|
||||
5f0eff439eb2ff43a3e4
|
||||
4c11ff439eb2ff43a3be
|
||||
80800000000000004000
|
||||
80800000000100004001
|
||||
8080ffffffff00003fff
|
||||
80807fffffff80003fff
|
||||
80808000000080004000
|
||||
80804000000040004000
|
||||
8080c0000000c0004000
|
||||
808000bc614e00bca14e
|
||||
8080ff439eb2ff43deb2
|
||||
7f7f0000000000003f01
|
||||
7f7f0000000100003f02
|
||||
7f7fffffffff00003f00
|
||||
7f7f7fffffff80003f00
|
||||
7f7f8000000080003f01
|
||||
7f7f4000000040003f01
|
||||
7f7fc0000000c0003f01
|
||||
7f7f00bc614e00bca04f
|
||||
7f7fff439eb2ff43ddb3
|
||||
807f00000000ffffc080
|
||||
807f00000001ffffc081
|
||||
807fffffffffffffc07f
|
||||
807f7fffffff7fffc07f
|
||||
807f800000007fffc080
|
||||
807f400000003fffc080
|
||||
807fc0000000bfffc080
|
||||
807f00bc614e00bc21ce
|
||||
807fff439eb2ff435f32
|
||||
7f8000000000ffffc080
|
||||
7f8000000001ffffc081
|
||||
7f80ffffffffffffc07f
|
||||
7f807fffffff7fffc07f
|
||||
7f80800000007fffc080
|
||||
7f80400000003fffc080
|
||||
7f80c0000000bfffc080
|
||||
7f8000bc614e00bc21ce
|
||||
7f80ff439eb2ff435f32
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user