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20b0b1f4c0de7b84c0b73b1c5369045a19c0ccc3
FPGA-Neural/sim/parameter_sweep.vcd
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micheleandClaude Sonnet 5 20b0b1f4c0 test: certify mac_unit/mac8 datapath (C.1), confirm real N_INPUTS=0 guard gap 
mac_unit.v: exhaustive unit test (all 65536 (x,w) combinations at
DATA_WIDTH=8, plus 486 boundary acc_in vectors) against an independent
Python oracle (tools/validation/mac_oracle.py). 66022/66022 match, 0
reserves.

mac8.v: first-ever dedicated unit test (previously only indirect
coverage at whatever single PARALLEL neuron_parallel_tb.v happens to
use). Verified at PARALLEL=2/8/32 with structural adversarial vectors
(catches swapped/duplicated tree wiring), 300 random INT8 pairs per
PARALLEL with realistic accumulating acc_in, and worst-case magnitude
adversarial vectors. 939/939 match.

Confirms BUG-002 (N_INPUTS=0 bypasses the N_INPUTS%PARALLEL elaboration
guard) is real, on both simulation and real Yosys synthesis -- root
cause: [DATA_WIDTH*N_INPUTS-1:0] becomes [-1:0] for N_INPUTS=0, which
both tools treat as a genuine 2-bit undriven vector rather than
collapsing to zero width. Includes a documented self-correction: the
first verification attempt produced a false "hang" using an invalid
one-shot late check of a single-cycle done pulse -- caught by
reproducing the same false result on a known-good sanity config before
trusting it.

Full regression re-run clean after adding 3 new testbenches: 36/36 real
tests pass.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v
2026-09-04 13:42:57 +02:00

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$date
Fri Sep 4 13:40:25 2026
$end
$version
Icarus Verilog
$end
$timescale
1ps
$end
$scope module tb $end
$var wire 8 ! y_g [7:0] $end
$var wire 8 " y_f [7:0] $end
$var wire 8 # y_d [7:0] $end
$var wire 8 $ y_a [7:0] $end
$var wire 1 % done_g $end
$var wire 1 & done_f $end
$var wire 1 ' done_d $end
$var wire 1 ( done_a $end
$var wire 1 ) busy_g $end
$var wire 1 * busy_f $end
$var wire 1 + busy_d $end
$var wire 1 , busy_a $end
$var parameter 32 - A_ACC_WIDTH $end
$var parameter 32 . A_DATA_WIDTH $end
$var parameter 32 / A_N_INPUTS $end
$var parameter 32 0 A_PARALLEL $end
$var parameter 32 1 D_ACC_WIDTH $end
$var parameter 32 2 D_DATA_WIDTH $end
$var parameter 32 3 D_N_INPUTS $end
$var parameter 32 4 D_PARALLEL $end
$var parameter 32 5 F_ACC_WIDTH $end
$var parameter 32 6 F_DATA_WIDTH $end
$var parameter 32 7 F_N_INPUTS $end
$var parameter 32 8 F_PARALLEL $end
$var parameter 32 9 G_ACC_WIDTH $end
$var parameter 32 : G_DATA_WIDTH $end
$var parameter 32 ; G_N_INPUTS $end
$var parameter 32 < G_PARALLEL $end
$var reg 8 = bias_a [7:0] $end
$var reg 8 > bias_d [7:0] $end
$var reg 8 ? bias_f [7:0] $end
$var reg 8 @ bias_g [7:0] $end
$var reg 1 A clk $end
$var reg 1 B rst $end
$var reg 1 C start_a $end
$var reg 1 D start_d $end
$var reg 1 E start_f $end
$var reg 1 F start_g $end
$var reg 256 G w_bus_a [255:0] $end
$var reg 512 H w_bus_d [511:0] $end
$var reg 256 I w_bus_f [255:0] $end
$var reg 256 J w_bus_g [255:0] $end
$var reg 256 K x_bus_a [255:0] $end
$var reg 512 L x_bus_d [511:0] $end
$var reg 256 M x_bus_f [255:0] $end
$var reg 256 N x_bus_g [255:0] $end
$var integer 32 O count [31:0] $end
$var integer 32 P errors [31:0] $end
$scope module u_a $end
$var wire 2 Q activation [1:0] $end
$var wire 8 R bias [7:0] $end
$var wire 1 A clk $end
$var wire 1 S final_acc_in_range $end
$var wire 1 T final_acc_le_zero $end
$var wire 1 U final_acc_upper_all0 $end
$var wire 16 V n_inputs_real [15:0] $end
$var wire 1 B rst $end
$var wire 1 C start $end
$var wire 256 W w_bus [255:0] $end
$var wire 256 X x_bus [255:0] $end
$var wire 8 Y y_relu [7:0] $end
$var wire 8 Z y_none [7:0] $end
$var wire 64 [ x_group [63:0] $end
$var wire 64 \ w_group [63:0] $end
$var wire 16 ] groups_real [15:0] $end
$var wire 1 ^ final_acc_upper_all1 $end
$var wire 1 _ final_acc_sign $end
$var wire 32 ` final_acc [31:0] $end
$var wire 32 a bias_ext [31:0] $end
$var wire 32 b acc_next [31:0] $end
$var parameter 32 c ACC_WIDTH $end
$var parameter 2 d ACT_NONE $end
$var parameter 2 e ACT_RELU $end
$var parameter 32 f DATA_WIDTH $end
$var parameter 32 g GROUPS $end
$var parameter 32 h GROUP_INDEX_WIDTH $end
$var parameter 32 i N_INPUTS $end
$var parameter 32 j PARALLEL $end
$var reg 32 k acc [31:0] $end
$var reg 1 , busy $end
$var reg 1 ( done $end
$var reg 1 l finishing $end
$var reg 2 m group_index [1:0] $end
$var reg 8 n y [7:0] $end
$scope module u_mac8 $end
$var wire 32 o acc_in [31:0] $end
$var wire 64 p w_bus [63:0] $end
$var wire 64 q x_bus [63:0] $end
$var wire 32 r acc_out [31:0] $end
$var parameter 32 s ACC_WIDTH $end
$var parameter 32 t DATA_WIDTH $end
$var parameter 32 u PARALLEL $end
$var parameter 32 v TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 w i $end
$scope module u_mac $end
$var wire 32 x acc_in [31:0] $end
$var wire 8 y w [7:0] $end
$var wire 8 z x [7:0] $end
$var wire 32 { product_ext [31:0] $end
$var wire 16 | product [15:0] $end
$var wire 32 } acc_out [31:0] $end
$var parameter 32 ~ ACC_WIDTH $end
$var parameter 32 !" DATA_WIDTH $end
$var parameter 64 "" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 #" i $end
$scope module u_mac $end
$var wire 32 $" acc_in [31:0] $end
$var wire 8 %" w [7:0] $end
$var wire 8 &" x [7:0] $end
$var wire 32 '" product_ext [31:0] $end
$var wire 16 (" product [15:0] $end
$var wire 32 )" acc_out [31:0] $end
$var parameter 32 *" ACC_WIDTH $end
$var parameter 32 +" DATA_WIDTH $end
$var parameter 64 ," PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 -" i $end
$scope module u_mac $end
$var wire 32 ." acc_in [31:0] $end
$var wire 8 /" w [7:0] $end
$var wire 8 0" x [7:0] $end
$var wire 32 1" product_ext [31:0] $end
$var wire 16 2" product [15:0] $end
$var wire 32 3" acc_out [31:0] $end
$var parameter 32 4" ACC_WIDTH $end
$var parameter 32 5" DATA_WIDTH $end
$var parameter 64 6" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 7" i $end
$scope module u_mac $end
$var wire 32 8" acc_in [31:0] $end
$var wire 8 9" w [7:0] $end
$var wire 8 :" x [7:0] $end
$var wire 32 ;" product_ext [31:0] $end
$var wire 16 <" product [15:0] $end
$var wire 32 =" acc_out [31:0] $end
$var parameter 32 >" ACC_WIDTH $end
$var parameter 32 ?" DATA_WIDTH $end
$var parameter 64 @" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 A" i $end
$scope module u_mac $end
$var wire 32 B" acc_in [31:0] $end
$var wire 8 C" w [7:0] $end
$var wire 8 D" x [7:0] $end
$var wire 32 E" product_ext [31:0] $end
$var wire 16 F" product [15:0] $end
$var wire 32 G" acc_out [31:0] $end
$var parameter 32 H" ACC_WIDTH $end
$var parameter 32 I" DATA_WIDTH $end
$var parameter 64 J" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 K" i $end
$scope module u_mac $end
$var wire 32 L" acc_in [31:0] $end
$var wire 8 M" w [7:0] $end
$var wire 8 N" x [7:0] $end
$var wire 32 O" product_ext [31:0] $end
$var wire 16 P" product [15:0] $end
$var wire 32 Q" acc_out [31:0] $end
$var parameter 32 R" ACC_WIDTH $end
$var parameter 32 S" DATA_WIDTH $end
$var parameter 64 T" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 U" i $end
$scope module u_mac $end
$var wire 32 V" acc_in [31:0] $end
$var wire 8 W" w [7:0] $end
$var wire 8 X" x [7:0] $end
$var wire 32 Y" product_ext [31:0] $end
$var wire 16 Z" product [15:0] $end
$var wire 32 [" acc_out [31:0] $end
$var parameter 32 \" ACC_WIDTH $end
$var parameter 32 ]" DATA_WIDTH $end
$var parameter 64 ^" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 _" i $end
$scope module u_mac $end
$var wire 32 `" acc_in [31:0] $end
$var wire 8 a" w [7:0] $end
$var wire 8 b" x [7:0] $end
$var wire 32 c" product_ext [31:0] $end
$var wire 16 d" product [15:0] $end
$var wire 32 e" acc_out [31:0] $end
$var parameter 32 f" ACC_WIDTH $end
$var parameter 32 g" DATA_WIDTH $end
$var parameter 64 h" PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 i" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 j" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 k" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 l" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 m" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 n" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 o" i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 p" i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 q" level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 r" node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 s" node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 t" node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 u" node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 v" level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 w" node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 x" node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 y" level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 z" node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module u_d $end
$var wire 2 {" activation [1:0] $end
$var wire 8 |" bias [7:0] $end
$var wire 1 A clk $end
$var wire 1 }" final_acc_in_range $end
$var wire 1 ~" final_acc_le_zero $end
$var wire 1 !# final_acc_upper_all0 $end
$var wire 16 "# n_inputs_real [15:0] $end
$var wire 1 B rst $end
$var wire 1 D start $end
$var wire 512 ## w_bus [511:0] $end
$var wire 512 $# x_bus [511:0] $end
$var wire 8 %# y_relu [7:0] $end
$var wire 8 &# y_none [7:0] $end
$var wire 256 '# x_group [255:0] $end
$var wire 256 (# w_group [255:0] $end
$var wire 16 )# groups_real [15:0] $end
$var wire 1 *# final_acc_upper_all1 $end
$var wire 1 +# final_acc_sign $end
$var wire 32 ,# final_acc [31:0] $end
$var wire 32 -# bias_ext [31:0] $end
$var wire 32 .# acc_next [31:0] $end
$var parameter 32 /# ACC_WIDTH $end
$var parameter 2 0# ACT_NONE $end
$var parameter 2 1# ACT_RELU $end
$var parameter 32 2# DATA_WIDTH $end
$var parameter 32 3# GROUPS $end
$var parameter 32 4# GROUP_INDEX_WIDTH $end
$var parameter 32 5# N_INPUTS $end
$var parameter 32 6# PARALLEL $end
$var reg 32 7# acc [31:0] $end
$var reg 1 + busy $end
$var reg 1 ' done $end
$var reg 1 8# finishing $end
$var reg 1 9# group_index $end
$var reg 8 :# y [7:0] $end
$scope module u_mac8 $end
$var wire 32 ;# acc_in [31:0] $end
$var wire 256 <# w_bus [255:0] $end
$var wire 256 =# x_bus [255:0] $end
$var wire 32 ># acc_out [31:0] $end
$var parameter 32 ?# ACC_WIDTH $end
$var parameter 32 @# DATA_WIDTH $end
$var parameter 32 A# PARALLEL $end
$var parameter 32 B# TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 C# i $end
$scope module u_mac $end
$var wire 32 D# acc_in [31:0] $end
$var wire 8 E# w [7:0] $end
$var wire 8 F# x [7:0] $end
$var wire 32 G# product_ext [31:0] $end
$var wire 16 H# product [15:0] $end
$var wire 32 I# acc_out [31:0] $end
$var parameter 32 J# ACC_WIDTH $end
$var parameter 32 K# DATA_WIDTH $end
$var parameter 64 L# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 M# i $end
$scope module u_mac $end
$var wire 32 N# acc_in [31:0] $end
$var wire 8 O# w [7:0] $end
$var wire 8 P# x [7:0] $end
$var wire 32 Q# product_ext [31:0] $end
$var wire 16 R# product [15:0] $end
$var wire 32 S# acc_out [31:0] $end
$var parameter 32 T# ACC_WIDTH $end
$var parameter 32 U# DATA_WIDTH $end
$var parameter 64 V# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 W# i $end
$scope module u_mac $end
$var wire 32 X# acc_in [31:0] $end
$var wire 8 Y# w [7:0] $end
$var wire 8 Z# x [7:0] $end
$var wire 32 [# product_ext [31:0] $end
$var wire 16 \# product [15:0] $end
$var wire 32 ]# acc_out [31:0] $end
$var parameter 32 ^# ACC_WIDTH $end
$var parameter 32 _# DATA_WIDTH $end
$var parameter 64 `# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 a# i $end
$scope module u_mac $end
$var wire 32 b# acc_in [31:0] $end
$var wire 8 c# w [7:0] $end
$var wire 8 d# x [7:0] $end
$var wire 32 e# product_ext [31:0] $end
$var wire 16 f# product [15:0] $end
$var wire 32 g# acc_out [31:0] $end
$var parameter 32 h# ACC_WIDTH $end
$var parameter 32 i# DATA_WIDTH $end
$var parameter 64 j# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[4] $end
$var parameter 4 k# i $end
$scope module u_mac $end
$var wire 32 l# acc_in [31:0] $end
$var wire 8 m# w [7:0] $end
$var wire 8 n# x [7:0] $end
$var wire 32 o# product_ext [31:0] $end
$var wire 16 p# product [15:0] $end
$var wire 32 q# acc_out [31:0] $end
$var parameter 32 r# ACC_WIDTH $end
$var parameter 32 s# DATA_WIDTH $end
$var parameter 64 t# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[5] $end
$var parameter 4 u# i $end
$scope module u_mac $end
$var wire 32 v# acc_in [31:0] $end
$var wire 8 w# w [7:0] $end
$var wire 8 x# x [7:0] $end
$var wire 32 y# product_ext [31:0] $end
$var wire 16 z# product [15:0] $end
$var wire 32 {# acc_out [31:0] $end
$var parameter 32 |# ACC_WIDTH $end
$var parameter 32 }# DATA_WIDTH $end
$var parameter 64 ~# PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[6] $end
$var parameter 4 !$ i $end
$scope module u_mac $end
$var wire 32 "$ acc_in [31:0] $end
$var wire 8 #$ w [7:0] $end
$var wire 8 $$ x [7:0] $end
$var wire 32 %$ product_ext [31:0] $end
$var wire 16 &$ product [15:0] $end
$var wire 32 '$ acc_out [31:0] $end
$var parameter 32 ($ ACC_WIDTH $end
$var parameter 32 )$ DATA_WIDTH $end
$var parameter 64 *$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[7] $end
$var parameter 4 +$ i $end
$scope module u_mac $end
$var wire 32 ,$ acc_in [31:0] $end
$var wire 8 -$ w [7:0] $end
$var wire 8 .$ x [7:0] $end
$var wire 32 /$ product_ext [31:0] $end
$var wire 16 0$ product [15:0] $end
$var wire 32 1$ acc_out [31:0] $end
$var parameter 32 2$ ACC_WIDTH $end
$var parameter 32 3$ DATA_WIDTH $end
$var parameter 64 4$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[8] $end
$var parameter 5 5$ i $end
$scope module u_mac $end
$var wire 32 6$ acc_in [31:0] $end
$var wire 8 7$ w [7:0] $end
$var wire 8 8$ x [7:0] $end
$var wire 32 9$ product_ext [31:0] $end
$var wire 16 :$ product [15:0] $end
$var wire 32 ;$ acc_out [31:0] $end
$var parameter 32 <$ ACC_WIDTH $end
$var parameter 32 =$ DATA_WIDTH $end
$var parameter 64 >$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[9] $end
$var parameter 5 ?$ i $end
$scope module u_mac $end
$var wire 32 @$ acc_in [31:0] $end
$var wire 8 A$ w [7:0] $end
$var wire 8 B$ x [7:0] $end
$var wire 32 C$ product_ext [31:0] $end
$var wire 16 D$ product [15:0] $end
$var wire 32 E$ acc_out [31:0] $end
$var parameter 32 F$ ACC_WIDTH $end
$var parameter 32 G$ DATA_WIDTH $end
$var parameter 64 H$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[10] $end
$var parameter 5 I$ i $end
$scope module u_mac $end
$var wire 32 J$ acc_in [31:0] $end
$var wire 8 K$ w [7:0] $end
$var wire 8 L$ x [7:0] $end
$var wire 32 M$ product_ext [31:0] $end
$var wire 16 N$ product [15:0] $end
$var wire 32 O$ acc_out [31:0] $end
$var parameter 32 P$ ACC_WIDTH $end
$var parameter 32 Q$ DATA_WIDTH $end
$var parameter 64 R$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[11] $end
$var parameter 5 S$ i $end
$scope module u_mac $end
$var wire 32 T$ acc_in [31:0] $end
$var wire 8 U$ w [7:0] $end
$var wire 8 V$ x [7:0] $end
$var wire 32 W$ product_ext [31:0] $end
$var wire 16 X$ product [15:0] $end
$var wire 32 Y$ acc_out [31:0] $end
$var parameter 32 Z$ ACC_WIDTH $end
$var parameter 32 [$ DATA_WIDTH $end
$var parameter 64 \$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[12] $end
$var parameter 5 ]$ i $end
$scope module u_mac $end
$var wire 32 ^$ acc_in [31:0] $end
$var wire 8 _$ w [7:0] $end
$var wire 8 `$ x [7:0] $end
$var wire 32 a$ product_ext [31:0] $end
$var wire 16 b$ product [15:0] $end
$var wire 32 c$ acc_out [31:0] $end
$var parameter 32 d$ ACC_WIDTH $end
$var parameter 32 e$ DATA_WIDTH $end
$var parameter 64 f$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[13] $end
$var parameter 5 g$ i $end
$scope module u_mac $end
$var wire 32 h$ acc_in [31:0] $end
$var wire 8 i$ w [7:0] $end
$var wire 8 j$ x [7:0] $end
$var wire 32 k$ product_ext [31:0] $end
$var wire 16 l$ product [15:0] $end
$var wire 32 m$ acc_out [31:0] $end
$var parameter 32 n$ ACC_WIDTH $end
$var parameter 32 o$ DATA_WIDTH $end
$var parameter 64 p$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[14] $end
$var parameter 5 q$ i $end
$scope module u_mac $end
$var wire 32 r$ acc_in [31:0] $end
$var wire 8 s$ w [7:0] $end
$var wire 8 t$ x [7:0] $end
$var wire 32 u$ product_ext [31:0] $end
$var wire 16 v$ product [15:0] $end
$var wire 32 w$ acc_out [31:0] $end
$var parameter 32 x$ ACC_WIDTH $end
$var parameter 32 y$ DATA_WIDTH $end
$var parameter 64 z$ PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[15] $end
$var parameter 5 {$ i $end
$scope module u_mac $end
$var wire 32 |$ acc_in [31:0] $end
$var wire 8 }$ w [7:0] $end
$var wire 8 ~$ x [7:0] $end
$var wire 32 !% product_ext [31:0] $end
$var wire 16 "% product [15:0] $end
$var wire 32 #% acc_out [31:0] $end
$var parameter 32 $% ACC_WIDTH $end
$var parameter 32 %% DATA_WIDTH $end
$var parameter 64 &% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[16] $end
$var parameter 6 '% i $end
$scope module u_mac $end
$var wire 32 (% acc_in [31:0] $end
$var wire 8 )% w [7:0] $end
$var wire 8 *% x [7:0] $end
$var wire 32 +% product_ext [31:0] $end
$var wire 16 ,% product [15:0] $end
$var wire 32 -% acc_out [31:0] $end
$var parameter 32 .% ACC_WIDTH $end
$var parameter 32 /% DATA_WIDTH $end
$var parameter 64 0% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[17] $end
$var parameter 6 1% i $end
$scope module u_mac $end
$var wire 32 2% acc_in [31:0] $end
$var wire 8 3% w [7:0] $end
$var wire 8 4% x [7:0] $end
$var wire 32 5% product_ext [31:0] $end
$var wire 16 6% product [15:0] $end
$var wire 32 7% acc_out [31:0] $end
$var parameter 32 8% ACC_WIDTH $end
$var parameter 32 9% DATA_WIDTH $end
$var parameter 64 :% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[18] $end
$var parameter 6 ;% i $end
$scope module u_mac $end
$var wire 32 <% acc_in [31:0] $end
$var wire 8 =% w [7:0] $end
$var wire 8 >% x [7:0] $end
$var wire 32 ?% product_ext [31:0] $end
$var wire 16 @% product [15:0] $end
$var wire 32 A% acc_out [31:0] $end
$var parameter 32 B% ACC_WIDTH $end
$var parameter 32 C% DATA_WIDTH $end
$var parameter 64 D% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[19] $end
$var parameter 6 E% i $end
$scope module u_mac $end
$var wire 32 F% acc_in [31:0] $end
$var wire 8 G% w [7:0] $end
$var wire 8 H% x [7:0] $end
$var wire 32 I% product_ext [31:0] $end
$var wire 16 J% product [15:0] $end
$var wire 32 K% acc_out [31:0] $end
$var parameter 32 L% ACC_WIDTH $end
$var parameter 32 M% DATA_WIDTH $end
$var parameter 64 N% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[20] $end
$var parameter 6 O% i $end
$scope module u_mac $end
$var wire 32 P% acc_in [31:0] $end
$var wire 8 Q% w [7:0] $end
$var wire 8 R% x [7:0] $end
$var wire 32 S% product_ext [31:0] $end
$var wire 16 T% product [15:0] $end
$var wire 32 U% acc_out [31:0] $end
$var parameter 32 V% ACC_WIDTH $end
$var parameter 32 W% DATA_WIDTH $end
$var parameter 64 X% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[21] $end
$var parameter 6 Y% i $end
$scope module u_mac $end
$var wire 32 Z% acc_in [31:0] $end
$var wire 8 [% w [7:0] $end
$var wire 8 \% x [7:0] $end
$var wire 32 ]% product_ext [31:0] $end
$var wire 16 ^% product [15:0] $end
$var wire 32 _% acc_out [31:0] $end
$var parameter 32 `% ACC_WIDTH $end
$var parameter 32 a% DATA_WIDTH $end
$var parameter 64 b% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[22] $end
$var parameter 6 c% i $end
$scope module u_mac $end
$var wire 32 d% acc_in [31:0] $end
$var wire 8 e% w [7:0] $end
$var wire 8 f% x [7:0] $end
$var wire 32 g% product_ext [31:0] $end
$var wire 16 h% product [15:0] $end
$var wire 32 i% acc_out [31:0] $end
$var parameter 32 j% ACC_WIDTH $end
$var parameter 32 k% DATA_WIDTH $end
$var parameter 64 l% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[23] $end
$var parameter 6 m% i $end
$scope module u_mac $end
$var wire 32 n% acc_in [31:0] $end
$var wire 8 o% w [7:0] $end
$var wire 8 p% x [7:0] $end
$var wire 32 q% product_ext [31:0] $end
$var wire 16 r% product [15:0] $end
$var wire 32 s% acc_out [31:0] $end
$var parameter 32 t% ACC_WIDTH $end
$var parameter 32 u% DATA_WIDTH $end
$var parameter 64 v% PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[24] $end
$var parameter 6 w% i $end
$scope module u_mac $end
$var wire 32 x% acc_in [31:0] $end
$var wire 8 y% w [7:0] $end
$var wire 8 z% x [7:0] $end
$var wire 32 {% product_ext [31:0] $end
$var wire 16 |% product [15:0] $end
$var wire 32 }% acc_out [31:0] $end
$var parameter 32 ~% ACC_WIDTH $end
$var parameter 32 !& DATA_WIDTH $end
$var parameter 64 "& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[25] $end
$var parameter 6 #& i $end
$scope module u_mac $end
$var wire 32 $& acc_in [31:0] $end
$var wire 8 %& w [7:0] $end
$var wire 8 && x [7:0] $end
$var wire 32 '& product_ext [31:0] $end
$var wire 16 (& product [15:0] $end
$var wire 32 )& acc_out [31:0] $end
$var parameter 32 *& ACC_WIDTH $end
$var parameter 32 +& DATA_WIDTH $end
$var parameter 64 ,& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[26] $end
$var parameter 6 -& i $end
$scope module u_mac $end
$var wire 32 .& acc_in [31:0] $end
$var wire 8 /& w [7:0] $end
$var wire 8 0& x [7:0] $end
$var wire 32 1& product_ext [31:0] $end
$var wire 16 2& product [15:0] $end
$var wire 32 3& acc_out [31:0] $end
$var parameter 32 4& ACC_WIDTH $end
$var parameter 32 5& DATA_WIDTH $end
$var parameter 64 6& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[27] $end
$var parameter 6 7& i $end
$scope module u_mac $end
$var wire 32 8& acc_in [31:0] $end
$var wire 8 9& w [7:0] $end
$var wire 8 :& x [7:0] $end
$var wire 32 ;& product_ext [31:0] $end
$var wire 16 <& product [15:0] $end
$var wire 32 =& acc_out [31:0] $end
$var parameter 32 >& ACC_WIDTH $end
$var parameter 32 ?& DATA_WIDTH $end
$var parameter 64 @& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[28] $end
$var parameter 6 A& i $end
$scope module u_mac $end
$var wire 32 B& acc_in [31:0] $end
$var wire 8 C& w [7:0] $end
$var wire 8 D& x [7:0] $end
$var wire 32 E& product_ext [31:0] $end
$var wire 16 F& product [15:0] $end
$var wire 32 G& acc_out [31:0] $end
$var parameter 32 H& ACC_WIDTH $end
$var parameter 32 I& DATA_WIDTH $end
$var parameter 64 J& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[29] $end
$var parameter 6 K& i $end
$scope module u_mac $end
$var wire 32 L& acc_in [31:0] $end
$var wire 8 M& w [7:0] $end
$var wire 8 N& x [7:0] $end
$var wire 32 O& product_ext [31:0] $end
$var wire 16 P& product [15:0] $end
$var wire 32 Q& acc_out [31:0] $end
$var parameter 32 R& ACC_WIDTH $end
$var parameter 32 S& DATA_WIDTH $end
$var parameter 64 T& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[30] $end
$var parameter 6 U& i $end
$scope module u_mac $end
$var wire 32 V& acc_in [31:0] $end
$var wire 8 W& w [7:0] $end
$var wire 8 X& x [7:0] $end
$var wire 32 Y& product_ext [31:0] $end
$var wire 16 Z& product [15:0] $end
$var wire 32 [& acc_out [31:0] $end
$var parameter 32 \& ACC_WIDTH $end
$var parameter 32 ]& DATA_WIDTH $end
$var parameter 64 ^& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[31] $end
$var parameter 6 _& i $end
$scope module u_mac $end
$var wire 32 `& acc_in [31:0] $end
$var wire 8 a& w [7:0] $end
$var wire 8 b& x [7:0] $end
$var wire 32 c& product_ext [31:0] $end
$var wire 16 d& product [15:0] $end
$var wire 32 e& acc_out [31:0] $end
$var parameter 32 f& ACC_WIDTH $end
$var parameter 32 g& DATA_WIDTH $end
$var parameter 64 h& PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 i& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 j& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 k& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 l& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[4] $end
$var parameter 4 m& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[5] $end
$var parameter 4 n& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[6] $end
$var parameter 4 o& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[7] $end
$var parameter 4 p& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[8] $end
$var parameter 5 q& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[9] $end
$var parameter 5 r& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[10] $end
$var parameter 5 s& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[11] $end
$var parameter 5 t& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[12] $end
$var parameter 5 u& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[13] $end
$var parameter 5 v& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[14] $end
$var parameter 5 w& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[15] $end
$var parameter 5 x& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[16] $end
$var parameter 6 y& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[17] $end
$var parameter 6 z& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[18] $end
$var parameter 6 {& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[19] $end
$var parameter 6 |& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[20] $end
$var parameter 6 }& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[21] $end
$var parameter 6 ~& i $end
$upscope $end
$scope begin GEN_TREE_INPUT[22] $end
$var parameter 6 !' i $end
$upscope $end
$scope begin GEN_TREE_INPUT[23] $end
$var parameter 6 "' i $end
$upscope $end
$scope begin GEN_TREE_INPUT[24] $end
$var parameter 6 #' i $end
$upscope $end
$scope begin GEN_TREE_INPUT[25] $end
$var parameter 6 $' i $end
$upscope $end
$scope begin GEN_TREE_INPUT[26] $end
$var parameter 6 %' i $end
$upscope $end
$scope begin GEN_TREE_INPUT[27] $end
$var parameter 6 &' i $end
$upscope $end
$scope begin GEN_TREE_INPUT[28] $end
$var parameter 6 '' i $end
$upscope $end
$scope begin GEN_TREE_INPUT[29] $end
$var parameter 6 (' i $end
$upscope $end
$scope begin GEN_TREE_INPUT[30] $end
$var parameter 6 )' i $end
$upscope $end
$scope begin GEN_TREE_INPUT[31] $end
$var parameter 6 *' i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 +' level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 ,' node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 -' node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 .' node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 /' node $end
$upscope $end
$scope begin GEN_TREE_NODE[4] $end
$var parameter 4 0' node $end
$upscope $end
$scope begin GEN_TREE_NODE[5] $end
$var parameter 4 1' node $end
$upscope $end
$scope begin GEN_TREE_NODE[6] $end
$var parameter 4 2' node $end
$upscope $end
$scope begin GEN_TREE_NODE[7] $end
$var parameter 4 3' node $end
$upscope $end
$scope begin GEN_TREE_NODE[8] $end
$var parameter 5 4' node $end
$upscope $end
$scope begin GEN_TREE_NODE[9] $end
$var parameter 5 5' node $end
$upscope $end
$scope begin GEN_TREE_NODE[10] $end
$var parameter 5 6' node $end
$upscope $end
$scope begin GEN_TREE_NODE[11] $end
$var parameter 5 7' node $end
$upscope $end
$scope begin GEN_TREE_NODE[12] $end
$var parameter 5 8' node $end
$upscope $end
$scope begin GEN_TREE_NODE[13] $end
$var parameter 5 9' node $end
$upscope $end
$scope begin GEN_TREE_NODE[14] $end
$var parameter 5 :' node $end
$upscope $end
$scope begin GEN_TREE_NODE[15] $end
$var parameter 5 ;' node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 <' level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 =' node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 >' node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 ?' node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 @' node $end
$upscope $end
$scope begin GEN_TREE_NODE[4] $end
$var parameter 4 A' node $end
$upscope $end
$scope begin GEN_TREE_NODE[5] $end
$var parameter 4 B' node $end
$upscope $end
$scope begin GEN_TREE_NODE[6] $end
$var parameter 4 C' node $end
$upscope $end
$scope begin GEN_TREE_NODE[7] $end
$var parameter 4 D' node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[2] $end
$var parameter 3 E' level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 F' node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 G' node $end
$upscope $end
$scope begin GEN_TREE_NODE[2] $end
$var parameter 3 H' node $end
$upscope $end
$scope begin GEN_TREE_NODE[3] $end
$var parameter 3 I' node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[3] $end
$var parameter 3 J' level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 K' node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 L' node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[4] $end
$var parameter 4 M' level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 N' node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module u_f $end
$var wire 2 O' activation [1:0] $end
$var wire 8 P' bias [7:0] $end
$var wire 1 A clk $end
$var wire 1 Q' final_acc_in_range $end
$var wire 1 R' final_acc_le_zero $end
$var wire 1 S' final_acc_upper_all0 $end
$var wire 16 T' n_inputs_real [15:0] $end
$var wire 1 B rst $end
$var wire 1 E start $end
$var wire 256 U' w_bus [255:0] $end
$var wire 256 V' x_bus [255:0] $end
$var wire 8 W' y_relu [7:0] $end
$var wire 8 X' y_none [7:0] $end
$var wire 16 Y' x_group [15:0] $end
$var wire 16 Z' w_group [15:0] $end
$var wire 16 [' groups_real [15:0] $end
$var wire 1 \' final_acc_upper_all1 $end
$var wire 1 ]' final_acc_sign $end
$var wire 32 ^' final_acc [31:0] $end
$var wire 32 _' bias_ext [31:0] $end
$var wire 32 `' acc_next [31:0] $end
$var parameter 32 a' ACC_WIDTH $end
$var parameter 2 b' ACT_NONE $end
$var parameter 2 c' ACT_RELU $end
$var parameter 32 d' DATA_WIDTH $end
$var parameter 32 e' GROUPS $end
$var parameter 32 f' GROUP_INDEX_WIDTH $end
$var parameter 32 g' N_INPUTS $end
$var parameter 32 h' PARALLEL $end
$var reg 32 i' acc [31:0] $end
$var reg 1 * busy $end
$var reg 1 & done $end
$var reg 1 j' finishing $end
$var reg 4 k' group_index [3:0] $end
$var reg 8 l' y [7:0] $end
$scope module u_mac8 $end
$var wire 32 m' acc_in [31:0] $end
$var wire 16 n' w_bus [15:0] $end
$var wire 16 o' x_bus [15:0] $end
$var wire 32 p' acc_out [31:0] $end
$var parameter 32 q' ACC_WIDTH $end
$var parameter 32 r' DATA_WIDTH $end
$var parameter 32 s' PARALLEL $end
$var parameter 32 t' TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 u' i $end
$scope module u_mac $end
$var wire 32 v' acc_in [31:0] $end
$var wire 8 w' w [7:0] $end
$var wire 8 x' x [7:0] $end
$var wire 32 y' product_ext [31:0] $end
$var wire 16 z' product [15:0] $end
$var wire 32 {' acc_out [31:0] $end
$var parameter 32 |' ACC_WIDTH $end
$var parameter 32 }' DATA_WIDTH $end
$var parameter 64 ~' PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 !( i $end
$scope module u_mac $end
$var wire 32 "( acc_in [31:0] $end
$var wire 8 #( w [7:0] $end
$var wire 8 $( x [7:0] $end
$var wire 32 %( product_ext [31:0] $end
$var wire 16 &( product [15:0] $end
$var wire 32 '( acc_out [31:0] $end
$var parameter 32 (( ACC_WIDTH $end
$var parameter 32 )( DATA_WIDTH $end
$var parameter 64 *( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 +( i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 ,( i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 -( level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 .( node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$scope module u_g $end
$var wire 2 /( activation [1:0] $end
$var wire 8 0( bias [7:0] $end
$var wire 1 A clk $end
$var wire 1 1( final_acc_in_range $end
$var wire 1 2( final_acc_le_zero $end
$var wire 1 3( final_acc_upper_all0 $end
$var wire 16 4( n_inputs_real [15:0] $end
$var wire 1 B rst $end
$var wire 1 F start $end
$var wire 256 5( w_bus [255:0] $end
$var wire 256 6( x_bus [255:0] $end
$var wire 8 7( y_relu [7:0] $end
$var wire 8 8( y_none [7:0] $end
$var wire 32 9( x_group [31:0] $end
$var wire 32 :( w_group [31:0] $end
$var wire 16 ;( groups_real [15:0] $end
$var wire 1 <( final_acc_upper_all1 $end
$var wire 1 =( final_acc_sign $end
$var wire 32 >( final_acc [31:0] $end
$var wire 32 ?( bias_ext [31:0] $end
$var wire 32 @( acc_next [31:0] $end
$var parameter 32 A( ACC_WIDTH $end
$var parameter 2 B( ACT_NONE $end
$var parameter 2 C( ACT_RELU $end
$var parameter 32 D( DATA_WIDTH $end
$var parameter 32 E( GROUPS $end
$var parameter 32 F( GROUP_INDEX_WIDTH $end
$var parameter 32 G( N_INPUTS $end
$var parameter 32 H( PARALLEL $end
$var reg 32 I( acc [31:0] $end
$var reg 1 ) busy $end
$var reg 1 % done $end
$var reg 1 J( finishing $end
$var reg 3 K( group_index [2:0] $end
$var reg 8 L( y [7:0] $end
$scope module u_mac8 $end
$var wire 32 M( acc_in [31:0] $end
$var wire 32 N( w_bus [31:0] $end
$var wire 32 O( x_bus [31:0] $end
$var wire 32 P( acc_out [31:0] $end
$var parameter 32 Q( ACC_WIDTH $end
$var parameter 32 R( DATA_WIDTH $end
$var parameter 32 S( PARALLEL $end
$var parameter 32 T( TREE_LEVELS $end
$scope begin GEN_MAC[0] $end
$var parameter 2 U( i $end
$scope module u_mac $end
$var wire 32 V( acc_in [31:0] $end
$var wire 8 W( w [7:0] $end
$var wire 8 X( x [7:0] $end
$var wire 32 Y( product_ext [31:0] $end
$var wire 16 Z( product [15:0] $end
$var wire 32 [( acc_out [31:0] $end
$var parameter 32 \( ACC_WIDTH $end
$var parameter 32 ]( DATA_WIDTH $end
$var parameter 64 ^( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[1] $end
$var parameter 2 _( i $end
$scope module u_mac $end
$var wire 32 `( acc_in [31:0] $end
$var wire 8 a( w [7:0] $end
$var wire 8 b( x [7:0] $end
$var wire 32 c( product_ext [31:0] $end
$var wire 16 d( product [15:0] $end
$var wire 32 e( acc_out [31:0] $end
$var parameter 32 f( ACC_WIDTH $end
$var parameter 32 g( DATA_WIDTH $end
$var parameter 64 h( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[2] $end
$var parameter 3 i( i $end
$scope module u_mac $end
$var wire 32 j( acc_in [31:0] $end
$var wire 8 k( w [7:0] $end
$var wire 8 l( x [7:0] $end
$var wire 32 m( product_ext [31:0] $end
$var wire 16 n( product [15:0] $end
$var wire 32 o( acc_out [31:0] $end
$var parameter 32 p( ACC_WIDTH $end
$var parameter 32 q( DATA_WIDTH $end
$var parameter 64 r( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_MAC[3] $end
$var parameter 3 s( i $end
$scope module u_mac $end
$var wire 32 t( acc_in [31:0] $end
$var wire 8 u( w [7:0] $end
$var wire 8 v( x [7:0] $end
$var wire 32 w( product_ext [31:0] $end
$var wire 16 x( product [15:0] $end
$var wire 32 y( acc_out [31:0] $end
$var parameter 32 z( ACC_WIDTH $end
$var parameter 32 {( DATA_WIDTH $end
$var parameter 64 |( PROD_WIDTH $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_INPUT[0] $end
$var parameter 2 }( i $end
$upscope $end
$scope begin GEN_TREE_INPUT[1] $end
$var parameter 2 ~( i $end
$upscope $end
$scope begin GEN_TREE_INPUT[2] $end
$var parameter 3 !) i $end
$upscope $end
$scope begin GEN_TREE_INPUT[3] $end
$var parameter 3 ") i $end
$upscope $end
$scope begin GEN_TREE_LEVEL[0] $end
$var parameter 2 #) level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 $) node $end
$upscope $end
$scope begin GEN_TREE_NODE[1] $end
$var parameter 2 %) node $end
$upscope $end
$upscope $end
$scope begin GEN_TREE_LEVEL[1] $end
$var parameter 2 &) level $end
$scope begin GEN_TREE_NODE[0] $end
$var parameter 2 ') node $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b0 ')
b1 &)
b1 %)
b0 $)
b0 #)
b11 ")
b10 !)
b1 ~(
b0 }(
b10000 |(
b1000 {(
b100000 z(
b11 s(
b10000 r(
b1000 q(
b100000 p(
b10 i(
b10000 h(
b1000 g(
b100000 f(
b1 _(
b10000 ^(
b1000 ](
b100000 \(
b0 U(
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$end
#0
$dumpvars
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1A
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b100000001000000010000000100000001000000010000000100000001 \
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b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 (#
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b1000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 H
b1000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 ##
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 '#
b100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 =#
b1000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 L
b1000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 $#
b1000000 O
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