exp: N=16 timing closure fixed (EXP-0056), weight-reuse gives real 7.16x memory speedup without DDR3 (EXP-0057)

EXP-0056: N_SLOTS=16 failed timing on LFE5U-85F (23-24MHz vs 64MHz
target). First hypothesis (dependency_manager.v's serial ready-scan)
was wrong but real -- built and verified priority_encoder_lsb.v (a
generic recursive tree encoder) and dependency_manager_fast.v, bit-
exact equivalent to the original, but integrated it made no real
difference (24.26MHz). The real cause, found from nextpnr's own
critical-path report: nms_activation_fill_ctrl_v3.v's balanced max-
tree was only ever extended to N_SLOTS in {1,2,4,8}, silently falling
back to the original slow scan for 16. Added the missing case
(nms_activation_fill_ctrl_v3_n16.v), verified isolated (10017/10017)
and functionally (D-Stress N=16 still 256/256 bit-exact). Real result:
71.01MHz, PASS at 64MHz (single seed so far).

EXP-0057: built layer_weight_buffer.v, a double-buffered per-layer
weight scratchpad (fill one buffer in the background from SDRAM while
compute reads many times from the other -- weight-stationary reuse,
as opposed to D-Stress's own deliberately zero-reuse pattern). Wired
to the real sdram_controller_openrow.v + sdram_model.v, no new
hardware. For the same 32768 bytes of useful data: zero-reuse costs
27048 real cycles, reuse costs 3777 -- 7.16x real measured speedup on
the SAME SDR SDRAM, no DDR3, no clock change. This is the answer to
whether DDR3 is necessary for a workload class that actually has
reuse (e.g. conv-style face recognition, unlike D-Stress) -- it isn't,
at least not for this reason.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MUG92aM9m68TRc4rG55BcC

hardware/v2/ddr3/litedram_gen/generated_headers/sdram_phy.h

@@ -0,0 +1,115 @@
+#ifndef __GENERATED_SDRAM_PHY_H
+#define __GENERATED_SDRAM_PHY_H
+
+#include <hw/common.h>
+#include <generated/csr.h>
+
+#define DFII_CONTROL_SEL 0x01
+#define DFII_CONTROL_CKE 0x02
+#define DFII_CONTROL_ODT 0x04
+#define DFII_CONTROL_RESET_N 0x08
+
+#define DFII_COMMAND_CS 0x01
+#define DFII_COMMAND_WE 0x02
+#define DFII_COMMAND_CAS 0x04
+#define DFII_COMMAND_RAS 0x08
+#define DFII_COMMAND_WRDATA 0x10
+#define DFII_COMMAND_RDDATA 0x20
+
+#define SDRAM_PHY_ECP5DDRPHY
+#define SDRAM_PHY_XDR 2
+#define SDRAM_PHY_DATABITS 16
+#define SDRAM_PHY_DFI_DATABITS 64
+#define SDRAM_PHY_PHASES 2
+#define SDRAM_PHY_CL 6
+#define SDRAM_PHY_CWL 5
+#define SDRAM_PHY_RDPHASE 0
+#define SDRAM_PHY_WRPHASE 1
+#define SDRAM_PHY_READ_LEVELING_CAPABLE
+#define SDRAM_PHY_DQ_DQS_RATIO 8
+#define SDRAM_PHY_MODULES 2
+#define SDRAM_PHY_DELAYS 8
+#define SDRAM_PHY_BITSLIPS 4
+#define SDRAM_PHY_DDR3
+#define SDRAM_PHY_SUPPORTED_MEMORY 0x0000000020000000ULL
+
+void cdelay(int i);
+
+__attribute__((unused)) static inline void command_p0(int cmd)
+{
+	sdram_dfii_pi0_command_write(cmd);
+	sdram_dfii_pi0_command_issue_write(1);
+}
+__attribute__((unused)) static inline void command_p1(int cmd)
+{
+	sdram_dfii_pi1_command_write(cmd);
+	sdram_dfii_pi1_command_issue_write(1);
+}
+
+#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
+
+static inline unsigned long sdram_dfii_pix_wrdata_addr(int phase)
+{
+	switch (phase) {
+		case 0: return CSR_SDRAM_DFII_PI0_WRDATA_ADDR;
+		case 1: return CSR_SDRAM_DFII_PI1_WRDATA_ADDR;
+		default: return 0;
+	}
+}
+static inline unsigned long sdram_dfii_pix_rddata_addr(int phase)
+{
+	switch (phase) {
+		case 0: return CSR_SDRAM_DFII_PI0_RDDATA_ADDR;
+		case 1: return CSR_SDRAM_DFII_PI1_RDDATA_ADDR;
+		default: return 0;
+	}
+}
+
+#define DDRX_MR_WRLVL_ADDRESS 1
+#define DDRX_MR_WRLVL_RESET 6
+#define DDRX_MR_WRLVL_BIT 7
+
+static inline void init_sequence(void)
+{
+	/* Release reset */
+	sdram_dfii_pi0_address_write(0x0);
+	sdram_dfii_pi0_baddress_write(0);
+	sdram_dfii_control_write(DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
+	cdelay(50000);
+
+	/* Bring CKE high */
+	sdram_dfii_pi0_address_write(0x0);
+	sdram_dfii_pi0_baddress_write(0);
+	sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
+	cdelay(10000);
+
+	/* Load Mode Register 2, CWL=5 */
+	sdram_dfii_pi0_address_write(0x200);
+	sdram_dfii_pi0_baddress_write(2);
+	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
+
+	/* Load Mode Register 3 */
+	sdram_dfii_pi0_address_write(0x0);
+	sdram_dfii_pi0_baddress_write(3);
+	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
+
+	/* Load Mode Register 1 */
+	sdram_dfii_pi0_address_write(0x6);
+	sdram_dfii_pi0_baddress_write(1);
+	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
+
+	/* Load Mode Register 0, CL=6, BL=8 */
+	sdram_dfii_pi0_address_write(0x320);
+	sdram_dfii_pi0_baddress_write(0);
+	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
+	cdelay(200);
+
+	/* ZQ Calibration */
+	sdram_dfii_pi0_address_write(0x400);
+	sdram_dfii_pi0_baddress_write(0);
+	command_p0(DFII_COMMAND_WE|DFII_COMMAND_CS);
+	cdelay(200);
+
+}
+
+#endif /* __GENERATED_SDRAM_PHY_H */