v1 datasheet latex source

2026-09-06 15:02:25 +02:00
parent 43abf28b5b
commit 18bf038ed5
39 changed files with 6644 additions and 0 deletions
@@ -0,0 +1,119 @@
+% ======================================================================
+%  FPGA-Neural -- INT8 Neural Network Engine
+%  Datasheet / Technical reference manual
+%  Repository: github.com/manvalan/FPGA-Neural
+% ======================================================================
+\documentclass[11pt,a4paper,openany]{report}
+
+\newcommand{\datasheetrev}{A1}
+\newcommand{\datasheetdate}{September 2026}
+
+\input{preamble}
+
+\begin{document}
+\sloppy
+
+% ======================================================================
+%  TITLE PAGE
+% ======================================================================
+\begin{titlepage}
+\thispagestyle{empty}
+\begin{tikzpicture}[remember picture,overlay]
+  \fill[fnDark] (current page.north west) rectangle
+       ([yshift=-4.3cm]current page.north east);
+  \fill[fnTeal] ([yshift=-4.3cm]current page.north west) rectangle
+       ([yshift=-4.55cm]current page.north east);
+  \node[anchor=north west,text=white,font=\Huge\bfseries]
+       at ([xshift=2.2cm,yshift=-1.15cm]current page.north west)
+       {FPGA\,--\,Neural};
+  \node[anchor=north west,text=fnLight,font=\large]
+       at ([xshift=2.25cm,yshift=-2.15cm]current page.north west)
+       {INT8 Neural Network Engine for FPGA};
+  \node[anchor=north west,text=fnLight2,font=\normalsize]
+       at ([xshift=2.25cm,yshift=-2.85cm]current page.north west)
+       {Parametric hardware accelerator -- Datasheet and reference manual};
+  \node[anchor=north east,text=white,font=\ttfamily\small]
+       at ([xshift=-2.2cm,yshift=-3.55cm]current page.north east)
+       {Rev.~\datasheetrev~~\textbullet~~\datasheetdate};
+\end{tikzpicture}
+
+\vspace*{5.0cm}
+
+% --- compact block diagram on the title page ---
+\begin{center}
+\begin{tikzpicture}[node distance=7mm and 12mm]
+  \node[fnblockD,minimum width=30mm] (host) {HOST\\{\scriptsize Linux / ESP32 / MCU / PC}};
+  \node[fnblockT,right=18mm of host,minimum width=34mm] (fpga)
+       {FPGA\\{\scriptsize Neural Network Engine}};
+  \node[fnblock,right=18mm of fpga,minimum width=26mm] (ram)
+       {PSRAM\\{\scriptsize 8\,MB dedicated}};
+  \draw[fnbus] (host) -- node[fnlbl,above]{SPI Mode 0} (fpga);
+  \draw[fnbus] (fpga) -- node[fnlbl,above]{async 16-bit} (ram);
+  \node[below=1mm of fpga,font=\scriptsize\itshape,text=fnGrey]
+       {computation entirely on-chip};
+\end{tikzpicture}
+\end{center}
+
+\vfill
+\begin{center}
+\begin{tikzpicture}
+\node[draw=fnRule,rounded corners=3pt,inner sep=10pt,fill=fnLight,text width=15.5cm]{
+\footnotesize
+\textbf{\color{fnDark}Reference target device:} Lattice ECP5 \code{LFE5U-45F-8BG381C}
+(speed grade $-8$, CABGA381, 72$\times$MULT18X18D, $\approx$44k LUT).\\[2pt]
+\textbf{\color{fnDark}Baseline configuration:} INT8/INT32, \code{N\_INPUTS}=256, \code{N\_NEURONS}=4,
+parametric \code{PARALLEL}, PSRAM working memory ISSI \code{IS66WVE4M16EBLL-70BLI}.\\[2pt]
+\textbf{\color{fnDark}Status:} RTL verified in simulation (Icarus) and real synthesis
+(Yosys + nextpnr-ecp5). Document describing the project as of \datasheetdate.
+};
+\end{tikzpicture}
+\end{center}
+\vspace{0.6cm}
+{\footnotesize\color{fnGrey}\raggedright
+Project author: Michele Bigi \textbullet{} MIKILAB / manvalan.\\
+This datasheet documents the RTL code, documentation and benchmarks
+present in the repository \texttt{github.com/manvalan/FPGA-Neural}.\par}
+\end{titlepage}
+
+% ======================================================================
+%  "FEATURES" PAGE (datasheet style)
+% ======================================================================
+\input{chapters/00-features}
+
+% ======================================================================
+%  PINOUT SUMMARY (pages 2-3, pin-by-pin -- not bus ranges)
+% ======================================================================
+\newpage
+\input{chapters/00b-pinout}
+
+% ======================================================================
+%  TABLE OF CONTENTS
+% ======================================================================
+\newpage
+\pagenumbering{roman}
+{\color{fnDark}\tableofcontents}
+\newpage
+\pagenumbering{arabic}
+
+% ======================================================================
+%  CHAPTERS
+% ======================================================================
+\include{chapters/01-overview}
+\include{chapters/02-architettura}
+\include{chapters/03-datapath}
+\include{chapters/04-parametri}
+\include{chapters/05-memoria}
+\include{chapters/06-sequencer}
+\include{chapters/06b-grafo}
+\include{chapters/07-spi}
+\include{chapters/07b-programmazione}
+\include{chapters/08-toplevel}
+\include{chapters/09-implementazione}
+\include{chapters/10-hardware}
+\include{chapters/11-registri}
+\include{chapters/12-roadmap}
+
+\appendix
+\include{chapters/A-moduli}
+
+\end{document}