feat(v2): M4 Memory Manager + Prefetch Engine, real V1 PSRAM backend

Implements M4: memory_manager.v (arbitration/buffering/forwarding/
latency hiding/double buffering, §12) + prefetch_engine.v
(double-buffered tile fetch, §13), sitting on the REAL, UNMODIFIED V1
PSRAM backend chain (int8_memory_access.v -> memory_interface.v ->
psram_controller.v, per §15's explicit mandate not to touch the
controller).

Verified fully end-to-end with Verilator: real neural_processor (M1)
fed entirely by memory_manager, computing against PSRAM-resident X/W
tiles (double-buffered prefetch across up to 5 tiles) and writing its
result back to PSRAM -- checked via an independent PSRAM read-back,
with poison bytes around the operand regions to catch addressing
errors. 3/3 jobs pass (1/3/5-tile configurations).

Three real RTL bugs found and fixed during integration (full
diagnostic trail in errors.log ERR-0006): prefetch_engine had no
single-in-flight-request discipline, letting a queued request corrupt
the bank bookkeeping of a fetch already running; the fix's own
!pf_busy guard had a one-cycle blind spot (pf_busy lags pf_start by a
clock) that needed an explicit !pf_start term; and a state-based mux
for the shared backend port was off by one cycle, silently dropping
the PSRAM result write entirely.

Real synthesis: 0 CHECK problems, 851 LUT4/789 FF/108 CCU2C/0 DSP
(expected, no multiplication in this module). Real place&route (via a
synthesis-only timing harness, needed for the same TRELLIS_IO pin-
budget reason as M2's array): Fmax 165.86 MHz, PASS at 80MHz.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v

hardware/v2/logs/benchmark.log

@@ -59,3 +59,18 @@ wide) scale as expected with depth. Confirms §14's warning literally:
 "non assumere che buffer piu' grandi siano automaticamente migliori"
 -- here, smaller was not cheaper either, because depth was the wrong
 lever for this specific buffer's cost.
+
+[2026-09-05] M4 Memory Manager + Prefetch Engine (standalone resource
+count; Fmax via timing harness -- see errors.log ERR-0005)
+
+| Module                          | Fmax (POST-P&R) | LUT | FF  | DSP | CCU2C |
+|----------------------------------|------------------|-----|-----|-----|-------|
+| memory_manager + prefetch_engine | 165.86 MHz       | 851 | 789 | 0   | 108   |
+
+End-to-end (real PSRAM + real neural_processor, SIMULATED only, no
+system-level P&R yet -- deferred to M7/M9): 3-tile job = 446 cycles,
+1-tile job = 166 cycles, 5-tile job = 728 cycles. ~140-150 cycles/tile,
+dominated by psram_model.v's real ~70ns TAA access latency, not by
+memory_manager's own control overhead (its bank-swap turnaround is
+documented as a fixed +1 cycle/tile in decisions.log DEC-0006, a small
+fraction of the ~140-cycle PSRAM-dominated total).