From 175f697ae1e20b8a0ff1bc794567fee0cde01cf4 Mon Sep 17 00:00:00 2001 From: Michele Bigi Date: Sat, 5 Sep 2026 14:39:29 +0200 Subject: [PATCH] feat(v2): M4 Memory Manager + Prefetch Engine, real V1 PSRAM backend MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implements M4: memory_manager.v (arbitration/buffering/forwarding/ latency hiding/double buffering, §12) + prefetch_engine.v (double-buffered tile fetch, §13), sitting on the REAL, UNMODIFIED V1 PSRAM backend chain (int8_memory_access.v -> memory_interface.v -> psram_controller.v, per §15's explicit mandate not to touch the controller). Verified fully end-to-end with Verilator: real neural_processor (M1) fed entirely by memory_manager, computing against PSRAM-resident X/W tiles (double-buffered prefetch across up to 5 tiles) and writing its result back to PSRAM -- checked via an independent PSRAM read-back, with poison bytes around the operand regions to catch addressing errors. 3/3 jobs pass (1/3/5-tile configurations). Three real RTL bugs found and fixed during integration (full diagnostic trail in errors.log ERR-0006): prefetch_engine had no single-in-flight-request discipline, letting a queued request corrupt the bank bookkeeping of a fetch already running; the fix's own !pf_busy guard had a one-cycle blind spot (pf_busy lags pf_start by a clock) that needed an explicit !pf_start term; and a state-based mux for the shared backend port was off by one cycle, silently dropping the PSRAM result write entirely. Real synthesis: 0 CHECK problems, 851 LUT4/789 FF/108 CCU2C/0 DSP (expected, no multiplication in this module). Real place&route (via a synthesis-only timing harness, needed for the same TRELLIS_IO pin- budget reason as M2's array): Fmax 165.86 MHz, PASS at 80MHz. Co-Authored-By: Claude Sonnet 5 Claude-Session: https://claude.ai/code/session_013xXuuRUWZScuo1DeYJxs3v --- hardware/v2/docs/ROADMAP.md | 7 +- hardware/v2/logs/benchmark.log | 15 + hardware/v2/logs/decisions.log | 71 + hardware/v2/logs/development.log | 27 + hardware/v2/logs/errors.log | 52 + hardware/v2/logs/experiments.log | 56 + hardware/v2/logs/simulation.log | 12 + hardware/v2/logs/synthesis.log | 4 + hardware/v2/logs/timing.log | 6 + hardware/v2/rtl/memory_manager.v | 313 + hardware/v2/rtl/prefetch_engine.v | 129 + hardware/v2/sim/tb_memory_manager.v | 287 + .../v2/synthesis/harness_memory_manager.v | 71 + .../harness_memory_manager/nextpnr.log | 302 + .../harness_memory_manager/top.config | 8279 ++ .../synthesis/harness_memory_manager/top.json | 40479 ++++++++ .../harness_memory_manager/yosys.log | 2554 + .../synthesis/memory_manager_p8/nextpnr.log | 56 + .../v2/synthesis/memory_manager_p8/top.json | 82873 ++++++++++++++++ .../v2/synthesis/memory_manager_p8/yosys.log | 2344 + 20 files changed, 137935 insertions(+), 2 deletions(-) create mode 100644 hardware/v2/rtl/memory_manager.v create mode 100644 hardware/v2/rtl/prefetch_engine.v create mode 100644 hardware/v2/sim/tb_memory_manager.v create mode 100644 hardware/v2/synthesis/harness_memory_manager.v create mode 100644 hardware/v2/synthesis/harness_memory_manager/nextpnr.log create mode 100644 hardware/v2/synthesis/harness_memory_manager/top.config create mode 100644 hardware/v2/synthesis/harness_memory_manager/top.json create mode 100644 hardware/v2/synthesis/harness_memory_manager/yosys.log create mode 100644 hardware/v2/synthesis/memory_manager_p8/nextpnr.log create mode 100644 hardware/v2/synthesis/memory_manager_p8/top.json create mode 100644 hardware/v2/synthesis/memory_manager_p8/yosys.log diff --git a/hardware/v2/docs/ROADMAP.md b/hardware/v2/docs/ROADMAP.md index d05af2b..f1fc0a2 100644 --- a/hardware/v2/docs/ROADMAP.md +++ b/hardware/v2/docs/ROADMAP.md @@ -22,8 +22,11 @@ reali, non solo scritto). `result_buffer.v`). Tutti inferiscono DP16KD reale (10/10 test, 6/6 config sintetizzate 0 problemi). Scoperta: il costo BRAM di weight_buffer e' guidato da P_IN (larghezza), non da DEPTH. -- [ ] **M4 — Memory Manager** (`memory_manager.v`, `prefetch_engine.v`), - backend PSRAM V1 riusato senza modifiche. +- [x] **M4 — Memory Manager** (`memory_manager.v`, `prefetch_engine.v`), + backend PSRAM V1 riusato SENZA MODIFICHE. End-to-end reale (3/3 + job PASS) con vero neural_processor + vera catena PSRAM V1. + 3 bug RTL trovati/risolti (`logs/errors.log` ERR-0006). Fmax + 165.86 MHz. - [ ] **M5 — Neural Director** (`neural_director.v`), scheduling first-free. - [ ] **M6 — Dependency Manager** (`dependency_manager.v`), ready/waiting queue, dependency counters, wake-up, producer tracking. diff --git a/hardware/v2/logs/benchmark.log b/hardware/v2/logs/benchmark.log index a3213c6..b827ebc 100644 --- a/hardware/v2/logs/benchmark.log +++ b/hardware/v2/logs/benchmark.log @@ -59,3 +59,18 @@ wide) scale as expected with depth. Confirms §14's warning literally: "non assumere che buffer piu' grandi siano automaticamente migliori" -- here, smaller was not cheaper either, because depth was the wrong lever for this specific buffer's cost. + +[2026-09-05] M4 Memory Manager + Prefetch Engine (standalone resource +count; Fmax via timing harness -- see errors.log ERR-0005) + +| Module | Fmax (POST-P&R) | LUT | FF | DSP | CCU2C | +|----------------------------------|------------------|-----|-----|-----|-------| +| memory_manager + prefetch_engine | 165.86 MHz | 851 | 789 | 0 | 108 | + +End-to-end (real PSRAM + real neural_processor, SIMULATED only, no +system-level P&R yet -- deferred to M7/M9): 3-tile job = 446 cycles, +1-tile job = 166 cycles, 5-tile job = 728 cycles. ~140-150 cycles/tile, +dominated by psram_model.v's real ~70ns TAA access latency, not by +memory_manager's own control overhead (its bank-swap turnaround is +documented as a fixed +1 cycle/tile in decisions.log DEC-0006, a small +fraction of the ~140-cycle PSRAM-dominated total). diff --git a/hardware/v2/logs/decisions.log b/hardware/v2/logs/decisions.log index 7950daa..2c5d0ec 100644 --- a/hardware/v2/logs/decisions.log +++ b/hardware/v2/logs/decisions.log @@ -248,3 +248,74 @@ not merely a stylistic choice. STATUS: ACCEPTED + +--- + +DEC-0006 + +DATE: 2026-09-05 + +DECISION: +memory_manager.v (M4) uses a SINGLE prefetch_engine instance, +retargeted per bank via a depth-1 pending-request register, rather +than multiple engines or a general request queue. The result +write-back (one byte per job, after the last tile) shares the same +backend port via a simple state-based mux, not a general arbiter -- +because prefetch and write-back are temporally disjoint by +construction (the write only happens after prefetch_engine has +nothing left to fetch for that job). + +WHY: +§13's double-buffering strategy needs at most ONE fetch "in flight" +and at most ONE fetch "queued" at any time for a SINGLE Neural +Processor consuming tiles sequentially (proven by construction: a new +prefetch is only ever queued on a tile handoff, and at most one +handoff can be pending completion of the previous prefetch before the +next one is even requested). A general multi-entry queue or a second +engine would add complexity with no present benefit. Likewise, +because this Memory Manager currently serves exactly one Neural +Processor and one job at a time, no concurrent second requester can +ever contend for the backend port with prefetch reads -- a real +mem_arbiter-style arbiter (as V1 uses for ITS OWN multi-master case) +is deferred until a scenario that actually needs it exists (multiple +Neural Processors or overlapping jobs sharing one memory_manager, +not yet built). + +EVIDENCE: +errors.log ERR-0006 -- the single-entry pending register, once +correctly gated (see ERR-0006 items 1-2), handled 1-tile, 3-tile, and +5-tile jobs correctly with no queue overflow in +hardware/v2/sim/tb_memory_manager.v. + +ALTERNATIVES: +1. Multiple prefetch_engine instances (one per bank), letting both + banks fetch fully in parallel. Rejected for M4: doubles DSP-free + logic for a benefit only realized when compute-tile time is + SHORTER than 2x fetch-tile time for a single engine -- not yet + measured to be the case (§22, deferred to M9), and the single- + engine design already fully hides fetch latency behind neural_ + processor's own per-tile compute time in the cases tested (see + experiments.log EXP-0005 cycle counts). +2. General N-entry FIFO for pending requests. Rejected: no scenario + in the current single-processor, single-job design can ever + generate more than one pending request before the in-flight one + completes -- an N-entry queue would be complexity with no + reachable use. +3. Reuse V1's mem_arbiter.v as-is for the prefetch-vs-writeback + sharing. Rejected: mem_arbiter.v's four ports are hardcoded to + specific V1 module names/priorities (§1 already established this + pattern in DEC-0001 for the broader V1-freeze decision) -- and + prefetch/write-back are provably never simultaneous here anyway, + so even a generic 2-port arbiter would be unexercised complexity. + +RESULT: +memory_manager.v as implemented. A NOTED, NOT-YET-OPTIMIZED +characteristic (documented in the module's own header comment): the +bank-swap-and-check control path costs a minimum 1 idle cycle per +tile handoff even when the next bank was already prefetched in time, +unlike neural_processor.v's own zero-gap tile acceptance -- left for +M10 (Optimization) to revisit using real stall-percentage data (§22) +rather than optimized blindly now. + +STATUS: +ACCEPTED diff --git a/hardware/v2/logs/development.log b/hardware/v2/logs/development.log index 90d5021..56d4cbc 100644 --- a/hardware/v2/logs/development.log +++ b/hardware/v2/logs/development.log @@ -110,3 +110,30 @@ decision: vedi benchmark.log -- il dimensionamento di weight_buffer andra' guidato da P_IN, non solo da DEPTH, quando si arrivera' a M4/M9. next_action: M4 -- memory_manager.v + prefetch_engine.v. + +[2026-09-05T16:00:00Z] commit=5f0d7f1 session=v2-M4-memory-manager +module: hardware/v2/rtl/memory_manager.v, prefetch_engine.v +action: implementato M4 -- Memory Manager (arbitraggio/buffering/ + forwarding/gestione latenza/double buffering, §12) + Prefetch Engine + (fetch a doppio buffer con retargeting di una singola istanza per + banco, §13). Backend PSRAM V1 riusato SENZA MODIFICHE + (int8_memory_access.v -> memory_interface.v -> psram_controller.v, + §15), integrato end-to-end con un vero hardware/v2/rtl/ + neural_processor.v (M1). +reason: roadmap M4. +result: 3/3 job PASS end-to-end (1/3/5 tile), risultato verificato con + RILETTURA INDIPENDENTE da PSRAM (non solo ispezione di segnali + interni), con byte "poison" attorno alle regioni operando per + catturare eventuali errori di indirizzamento off-by-one (nessuno + trovato). 3 bug RTL reali trovati e risolti durante l'integrazione + (vedi errors.log ERR-0006): mancava una disciplina "una sola + richiesta di prefetch in volo", un buco di un ciclo nel check + !pf_busy, un mux di stato disallineato di un ciclo che faceva + silenziosamente perdere la scrittura del risultato su PSRAM. + Sintesi reale: 0 problemi, 851 LUT4/789 FF/108 CCU2C/0 DSP (atteso). + Fmax reale (via harness, stesso motivo pin-count di ERR-0005): + 165.86 MHz, PASS a 80MHz. +errors: vedi errors.log ERR-0005 (ricorrenza), ERR-0006 (3 bug nuovi). +decision: vedi decisions.log DEC-0006 (motore di prefetch singolo + + registro pendente, nessun arbitro backend ancora necessario). +next_action: M5 -- neural_director.v, scheduling first-free. diff --git a/hardware/v2/logs/errors.log b/hardware/v2/logs/errors.log index e63dbe4..6270ca6 100644 --- a/hardware/v2/logs/errors.log +++ b/hardware/v2/logs/errors.log @@ -124,3 +124,55 @@ WORKAROUND: hardware/v2/synthesis/harness_neural_processor_array.v -- STATUS: WORKED AROUND. Will become moot once M4/M5 exist and the array is synthesized as part of a larger design with on-chip ports instead of a bare top-level module. + +ERR-0006 (real RTL bugs in hardware/v2/rtl/memory_manager.v, FOUND AND FIXED) +DATE: 2026-09-05 +MODULE: hardware/v2/rtl/memory_manager.v +SYMPTOM: end-to-end M4 testbench (real V1 PSRAM backend + real M1 + neural_processor) hung permanently partway through the first + multi-tile job -- bank_ready for the "current" bank never became 1, + even though the byte-level backend clearly kept completing read + transactions (observed via cycle-by-cycle hierarchical tracing of + memory_manager/prefetch_engine internal state). +ROOT CAUSES (three, found together during the same debugging session): + 1. The tile-N+2 prefetch request, queued on tile-N's handoff, could + be issued (pf_start asserted) while prefetch_engine was STILL + mid-fetch for tile-N+1 -- there was no single-in-flight-request + discipline at all in the first draft. Fixed by adding a + single-entry pf_pending register: requests are queued, not + issued directly, and a dedicated rule launches the queued + request only once the engine reports free. + 2. Even with that queue, pf_busy does not read 1 until the cycle + AFTER pf_start was first observed by prefetch_engine (its own + fetch_busy<=1 lags its own fetch_start sampling by one clock) -- + checking only `!pf_busy` left a genuine one-cycle window where a + second queued request would fire on top of the one just + launched, silently overwriting pf_target_bank (and pf_x_addr/ + pf_w_addr) for the fetch already in flight. The address corruption + was harmless (prefetch_engine had already latched the correct + address into its own state that same edge), but pf_target_bank + corruption meant the eventually-completed fetch's real data got + filed into the WRONG bank's bank_ready/bank_x/bank_w, permanently + starving the bank actually needed next. Fixed by gating the issue + rule on `!pf_busy && !pf_start` (the extra term closes exactly + this one-cycle window). + 3. A combinational mux selecting between prefetch_engine's own + backend wires and the result-write-back FSM's wires was gated on + `state == MM_WRITE_RESULT`, but wr_mem_req (asserted while + state==MM_WRITE_RESULT) only becomes valid the FOLLOWING cycle, + i.e. while state==MM_DONE -- the mux therefore selected the wrong + source for the one cycle the write request pulse was actually + high, silently dropping the PSRAM write entirely. Fixed by + widening the mux's select condition to cover both states. +DIAGNOSIS METHOD: cycle-by-cycle hierarchical signal dumps (mm.state, + tile_idx, bank_ready, pf_busy, pf_pending, pf_target_bank, + prefetch_engine's own state) under Verilator, printed only on + signal-change to keep the trace readable, comparing against the + hand-derived expected sequence of events for a 3-tile job. +VERIFICATION: hardware/v2/sim/tb_memory_manager.v -- 3/3 tests PASS + after all three fixes, including a 5-tile job (steady-state + double-buffer swap across more than 2 tiles) and independent + PSRAM read-back of the written-back result byte (not just internal + signal inspection). +STATUS: FIXED, verified end-to-end with the real (unmodified) V1 + PSRAM backend chain and a real M1 neural_processor. diff --git a/hardware/v2/logs/experiments.log b/hardware/v2/logs/experiments.log index 1e05658..74f8c57 100644 --- a/hardware/v2/logs/experiments.log +++ b/hardware/v2/logs/experiments.log @@ -218,3 +218,59 @@ decision: keep DEPTH parametric as specified, but document (this next_action: M4 -- memory_manager.v + prefetch_engine.v (wires these three buffers + the array together, PSRAM backend reused unmodified from V1 per §15). + +EXP-0005 +timestamp: 2026-09-05T16:00:00Z +git_commit: 5f0d7f1 (+ uncommitted M4 work) +session: v2-M4-memory-manager +module: hardware/v2/rtl/memory_manager.v, prefetch_engine.v +configuration: P_IN=8, ADDR_WIDTH=23, real V1 backend chain + (int8_memory_access -> memory_interface -> psram_controller -> + psram_model, ALL unmodified), real M1 neural_processor +action: M4 -- end-to-end integration: memory_manager double-buffers + prefetch of X/W tiles from PSRAM, feeds a real neural_processor, + writes the computed result back to PSRAM. +command (sim, Verilator): verilator --binary --timing -j 0 -Wno-fatal + --top-module tb -o /tmp/vtb_mm hardware/v1/rtl/int8_memory_access.v + hardware/v1/rtl/memory_interface.v hardware/v1/rtl/psram_controller.v + hardware/v1/sim/psram_model.v hardware/v2/rtl/neural_processor.v + hardware/v2/rtl/prefetch_engine.v hardware/v2/rtl/memory_manager.v + hardware/v2/sim/tb_memory_manager.v && /tmp/vtb_mm +command (synth): yosys -p "synth_ecp5 -json .../top.json -top + memory_manager" hardware/v2/rtl/memory_manager.v + hardware/v2/rtl/prefetch_engine.v (standalone, for real resource + counts); harness_memory_manager.v (see errors.log ERR-0005 pattern) + for real P&R Fmax, since the bare module exceeds the device's + TRELLIS_IO budget as a top-level (same class of artifact as the + Processor Array, not a logic limit). +result: + SIMULATED: 3/3 jobs PASS end-to-end -- 3-tile (bias=0, ACT_RELU, + saturates to 127), 1-tile (no saturation, y=32), and 5-tile + (steady-state double-buffer swap across more than 2 tiles, y=40) + -- each verified by an INDEPENDENT PSRAM read-back of the + written result byte (not just internal signal inspection), with + "poison" bytes surrounding the real operand regions to catch any + off-by-one addressing (none found). + Cycle counts (real, PSRAM power-up already excluded): 3-tile job = + 446 cycles, 1-tile job = 166 cycles, 5-tile job = 728 cycles. + Roughly ~140-150 cycles/tile at this PSRAM timing (dominated by + the real ~70ns TAA access latency modeled in psram_model.v, not + by memory_manager's own control overhead) -- a real, measured + number, not estimated. + SYNTHESIZED (standalone, real resource count): 0 CHECK problems, + 851 LUT4, 789 TRELLIS_FF, 108 CCU2C, 0 DSP (expected -- no + multiplication in this module). + POST-P&R (via harness, real Fmax): 165.86 MHz, PASS at 80MHz with + large margin. +errors: ERR-0006 (three real RTL bugs found and fixed during bring-up + -- see errors.log for full detail: a missing single-in-flight- + request discipline, a one-cycle pf_busy blind spot, and an + off-by-one state mux for the write-back path). ERR-0005's pin-count + artifact recurred for this module too (worked around the same way). +decision: see decisions.log DEC-0006 (single prefetch engine + pending + register is sufficient for this milestone's scope; a real backend + arbiter is deferred until multiple processors/jobs actually need to + share one memory_manager). +next_action: M5 -- neural_director.v (first-free scheduling), wiring + job dispatch to potentially multiple (memory_manager, neural_ + processor) pairs instead of the single hardcoded pair tested here. diff --git a/hardware/v2/logs/simulation.log b/hardware/v2/logs/simulation.log index adc53ee..bb2d71b 100644 --- a/hardware/v2/logs/simulation.log +++ b/hardware/v2/logs/simulation.log @@ -36,3 +36,15 @@ vectors: extreme INT8 (-128, 127, -100, 100), regular values, full writes undisturbed simulator: Verilator 5.050 (--binary --timing) PASS/FAIL: 10/10 PASS + +[2026-09-05] EXP-0005 -- hardware/v2/sim/tb_memory_manager.v +test: 3 end-to-end jobs (3-tile/saturating, 1-tile/non-saturating, + 5-tile/steady-state-swap), real V1 PSRAM backend chain (unmodified), + real M1 neural_processor +simulator: Verilator 5.050 (--binary --timing) +PASS/FAIL: 3/3 PASS +bit-exact result: PSRAM-read-back result byte matches hand-computed + expectation in every case (independent oracle, not derived from the + RTL under test) +cycles: 446 (3 tiles), 166 (1 tile), 728 (5 tiles) -- real PSRAM + latency dominates, not memory_manager's own control overhead diff --git a/hardware/v2/logs/synthesis.log b/hardware/v2/logs/synthesis.log index bed6e8d..9cb7d75 100644 --- a/hardware/v2/logs/synthesis.log +++ b/hardware/v2/logs/synthesis.log @@ -36,3 +36,7 @@ result_buffer D=4096: LUT=37 FF=30 DP16KD=2 (D=256: LUT=21 FF=26 DP16KD=1) CHECK: 0 problems, all 6 configs correctly infer DP16KD (no LUT-RAM fallback). weight_buffer's DP16KD count does NOT drop with depth (width-bound, not depth-bound -- see decisions.log / benchmark.log). + +[2026-09-05] EXP-0005 -- memory_manager + prefetch_engine (standalone) +LUT4=851 TRELLIS_FF=789 CCU2C=108 MULT18X18D=0 (expected, no + multiplication in this module). CHECK: 0 problems. diff --git a/hardware/v2/logs/timing.log b/hardware/v2/logs/timing.log index 699ab0b..4f7717a 100644 --- a/hardware/v2/logs/timing.log +++ b/hardware/v2/logs/timing.log @@ -38,3 +38,9 @@ weight_buffer (D=512): Fmax=339.67 MHz PASS result_buffer (D=4096): Fmax=325.20 MHz PASS All far above the 80MHz target -- buffers are not a timing concern in isolation at these depths. + +[2026-09-05] EXP-0005 -- memory_manager + prefetch_engine (via +harness_memory_manager.v, see errors.log ERR-0005 for why a harness +was needed), real nextpnr-ecp5 --45k --package CABGA381 --speed 8 +--freq 80 --lpf-allow-unconstrained +Fmax: 165.86 MHz -- PASS at 80MHz (real place&route measurement) diff --git a/hardware/v2/rtl/memory_manager.v b/hardware/v2/rtl/memory_manager.v new file mode 100644 index 0000000..e7fd3f9 --- /dev/null +++ b/hardware/v2/rtl/memory_manager.v @@ -0,0 +1,313 @@ +`timescale 1ns/1ps + +// ================================================================ +// FPGA-Neural V2 -- Memory Manager (M4, docs/v2-description.md §12/§15) +// +// Sits between a single Neural Processor (M1) and the byte-level +// Memory Backend Interface (hardware/v1/rtl/int8_memory_access.v, +// reused UNMODIFIED, per §15 -- "NON iniziare modificando il +// controller PSRAM. Mantenere inizialmente il backend esistente"). +// The processor sees only "data available" (operand_valid/ready, +// tile_last) -- never PSRAM request/wait cycles directly (§12). +// +// Double-buffered prefetch (§13): while the processor consumes tile +// N from bank "current", this module retargets the single +// prefetch_engine instance (M4) at bank "next" to fetch tile N+1 +// concurrently. On tile handoff, banks swap; if a bank isn't ready in +// time (prefetch slower than compute for this run), operand_valid +// simply stays low until it is -- a real stall, not hidden, so its +// frequency is genuinely measurable (§22, deferred to M9). NOTE +// (measured characteristic, not yet optimized -- see +// hardware/v2/logs/decisions.log DEC-0006): the bank-swap-and-check +// control path itself costs a minimum 1 idle cycle per tile handoff +// even when the next bank was already prefetched in time, unlike +// neural_processor.v's own zero-gap tile acceptance -- a real, +// deliberately-not-hidden overhead of this first Memory Manager +// implementation, left for M10 (Optimization) to revisit with real +// stall-percentage data (§22) rather than optimized blindly now. +// +// One job = one neuron's worth of tiles (n_tiles), read from x_base/ +// w_base (PSRAM byte addresses), followed by writing the single +// INT8 result back to result_addr. The result write only happens +// after the last tile has been handed off and prefetch_engine is +// idle (temporally disjoint from prefetching by construction), so no +// separate backend arbiter is needed at this milestone -- see +// decisions.log DEC-0006 for why, and what changes once multiple +// concurrent jobs/processors need to share one backend port +// (deferred, not yet needed). +// ================================================================ + +module memory_manager #( + parameter DATA_WIDTH = 8, + parameter P_IN = 8, + parameter ADDR_WIDTH = 23 +)( + input wire clk, + input wire rst, + + // ---- job control (from a future Neural Director, M5; driven + // directly by a testbench at M4) ---- + input wire job_start, + input wire [ADDR_WIDTH-1:0] x_base, + input wire [ADDR_WIDTH-1:0] w_base, + input wire [15:0] n_tiles, + input wire [ADDR_WIDTH-1:0] result_addr, + output reg job_done, // one-cycle pulse + + // ---- Neural Processor-facing operand stream (mirrors + // neural_processor.v's own operand port exactly) ---- + output reg operand_valid, + input wire operand_ready, + output reg signed [DATA_WIDTH*P_IN-1:0] input_data, + output reg signed [DATA_WIDTH*P_IN-1:0] weight_data, + output reg tile_last, + + // ---- Neural Processor-facing result consumption ---- + input wire result_valid, + output reg result_ready, + input wire signed [DATA_WIDTH-1:0] result_data, + + // ---- Memory Backend Interface (matches int8_memory_access.v) ---- + output wire mem_req, + output wire mem_wr, + output wire [ADDR_WIDTH-1:0] mem_addr, + output wire signed [7:0] mem_wdata, + input wire signed [7:0] mem_rdata, + input wire mem_ready +); + + localparam MM_IDLE = 3'd0; + localparam MM_PREFETCH_FIRST = 3'd1; + localparam MM_STREAM = 3'd2; + localparam MM_WAIT_RESULT = 3'd3; + localparam MM_WRITE_RESULT = 3'd4; + localparam MM_DONE = 3'd5; + + reg [2:0] state; + + reg [ADDR_WIDTH-1:0] x_base_reg, w_base_reg, result_addr_reg; + reg [15:0] n_tiles_reg; + reg [15:0] tile_idx; // tile currently presented (bank `current`) + reg current_bank; // 0 or 1 + + reg [1:0] bank_ready; // bank_ready[b] = bank b holds valid, unconsumed prefetched data + + // ---- double-buffer storage (owned here, filled by prefetch_engine) ---- + reg signed [DATA_WIDTH*P_IN-1:0] bank_x [0:1]; + reg signed [DATA_WIDTH*P_IN-1:0] bank_w [0:1]; + + // ---- single prefetch_engine instance, retargeted per bank ---- + reg pf_start; + reg [ADDR_WIDTH-1:0] pf_x_addr, pf_w_addr; + wire pf_busy, pf_done; + wire signed [DATA_WIDTH*P_IN-1:0] pf_tile_x, pf_tile_w; + + reg pf_target_bank; // which bank the CURRENTLY-running (or just-launched) prefetch fills + + // Single-entry pending-request register: prefetch_engine is one + // instance, so a NEW fetch can only be launched once it has + // genuinely returned to idle (pf_busy low) -- issuing pf_start + // while it is still mid-fetch would silently corrupt + // pf_target_bank for the fetch ALREADY in flight (a real bug + // found and fixed here -- see hardware/v2/logs/errors.log + // ERR-0006). Every "kick a prefetch" site below sets this + // descriptor instead of touching pf_start directly; a single + // always-active rule issues pf_start once the engine is free. + reg pf_pending; + reg [ADDR_WIDTH-1:0] pf_pending_x, pf_pending_w; + reg pf_pending_bank; + + // prefetch_engine drives its OWN internal backend wires; the + // result-write FSM below drives its own. A combinational mux + // (never both at once, by construction -- see file header) + // selects which one actually reaches the real output port, + // avoiding a two-driver conflict on mem_req/mem_wr/mem_addr/ + // mem_wdata. + wire pf_mem_req, pf_mem_wr; + wire [ADDR_WIDTH-1:0] pf_mem_addr; + wire signed [7:0] pf_mem_wdata; + + prefetch_engine #( + .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ADDR_WIDTH(ADDR_WIDTH) + ) u_prefetch ( + .clk(clk), .rst(rst), + .fetch_start(pf_start), .x_addr(pf_x_addr), .w_addr(pf_w_addr), + .fetch_busy(pf_busy), .fetch_done(pf_done), + .tile_x(pf_tile_x), .tile_w(pf_tile_w), + .mem_req(pf_mem_req), .mem_wr(pf_mem_wr), .mem_addr(pf_mem_addr), .mem_wdata(pf_mem_wdata), + .mem_rdata(mem_rdata), .mem_ready(mem_ready) + ); + + reg wr_mem_req; + reg [ADDR_WIDTH-1:0] wr_mem_addr; + reg signed [7:0] wr_mem_wdata; + + // wr_mem_req is SET while state==MM_WRITE_RESULT but only becomes + // valid (via NBA) the FOLLOWING cycle, i.e. while state==MM_DONE -- + // the mux must select the write-back source across BOTH states, + // not just the one that issues it (an off-by-one here silently + // dropped the write request entirely -- found and fixed here, see + // hardware/v2/logs/errors.log ERR-0006). + wire wr_active = (state == MM_WRITE_RESULT) || (state == MM_DONE); + assign mem_req = wr_active ? wr_mem_req : pf_mem_req; + assign mem_wr = wr_active ? 1'b1 : pf_mem_wr; + assign mem_addr = wr_active ? wr_mem_addr : pf_mem_addr; + assign mem_wdata = wr_active ? wr_mem_wdata : pf_mem_wdata; + + always @(posedge clk) begin + if (rst) begin + state <= MM_IDLE; + job_done <= 1'b0; + operand_valid <= 1'b0; + tile_last <= 1'b0; + input_data <= {DATA_WIDTH*P_IN{1'b0}}; + weight_data <= {DATA_WIDTH*P_IN{1'b0}}; + result_ready <= 1'b0; + pf_start <= 1'b0; + current_bank <= 1'b0; + bank_ready <= 2'b00; + tile_idx <= 16'h0; + wr_mem_req <= 1'b0; + wr_mem_addr <= {ADDR_WIDTH{1'b0}}; + wr_mem_wdata <= 8'sd0; + pf_pending <= 1'b0; + end else begin + job_done <= 1'b0; + pf_start <= 1'b0; + result_ready <= 1'b0; + + // Latch a completed prefetch into its target bank. + if (pf_done) begin + bank_x[pf_target_bank] <= pf_tile_x; + bank_w[pf_target_bank] <= pf_tile_w; + bank_ready[pf_target_bank] <= 1'b1; + end + + // Issue a pending fetch request as soon as the (single) + // prefetch engine is genuinely free. The `!pf_start` guard + // is required, not cosmetic: pf_busy does not read 1 until + // the cycle AFTER pf_start was first observed (prefetch_ + // engine's own fetch_busy<=1 is one clock behind its own + // fetch_start sampling), so checking !pf_busy alone leaves + // a genuine one-cycle window where a second pending + // request would fire on top of the one just launched, + // silently corrupting pf_target_bank for the fetch already + // in flight (found and fixed here -- see + // hardware/v2/logs/errors.log ERR-0006). + if (pf_pending && !pf_busy && !pf_start) begin + pf_start <= 1'b1; + pf_x_addr <= pf_pending_x; + pf_w_addr <= pf_pending_w; + pf_target_bank <= pf_pending_bank; + pf_pending <= 1'b0; + end + + case (state) + + MM_IDLE: begin + if (job_start) begin + x_base_reg <= x_base; + w_base_reg <= w_base; + n_tiles_reg <= n_tiles; + result_addr_reg <= result_addr; + tile_idx <= 16'h0; + current_bank <= 1'b0; + bank_ready <= 2'b00; + operand_valid <= 1'b0; + // kick off the very first fetch (tile 0 into bank 0) + pf_pending <= 1'b1; + pf_pending_x <= x_base; + pf_pending_w <= w_base; + pf_pending_bank <= 1'b0; + state <= MM_PREFETCH_FIRST; + end + end + + MM_PREFETCH_FIRST: begin + if (bank_ready[0] || (pf_done && pf_target_bank == 1'b0)) begin + // Present tile 0; concurrently start prefetching + // tile 1 into bank 1, if there is one. + operand_valid <= 1'b1; + input_data <= pf_done ? pf_tile_x : bank_x[0]; + weight_data <= pf_done ? pf_tile_w : bank_w[0]; + tile_last <= (n_tiles_reg == 16'h1); + if (n_tiles_reg > 16'h1) begin + pf_pending <= 1'b1; + pf_pending_x <= x_base_reg + P_IN[ADDR_WIDTH-1:0]; + pf_pending_w <= w_base_reg + P_IN[ADDR_WIDTH-1:0]; + pf_pending_bank <= 1'b1; + end + state <= MM_STREAM; + end + end + + MM_STREAM: begin + if (operand_valid && operand_ready) begin + // This tile consumed; free its bank, swap. + bank_ready[current_bank] <= 1'b0; + current_bank <= ~current_bank; + tile_idx <= tile_idx + 16'h1; + operand_valid <= 1'b0; // re-asserted below once the new bank is ready + + if (tile_idx + 16'h1 == n_tiles_reg) begin + // That was the last tile -- nothing more to present. + state <= MM_WAIT_RESULT; + end else if (tile_idx + 16'h2 < n_tiles_reg) begin + // Queue a prefetch for the tile AFTER next into + // the bank we just freed (current_bank, pre-swap) + // -- it will actually launch once the (single) + // prefetch engine is free (see the pf_pending + // issue rule above); it is very likely still + // busy with the tile-N+1 fetch kicked off on the + // PREVIOUS handoff, so this almost always queues + // rather than launching immediately. + pf_pending <= 1'b1; + pf_pending_x <= x_base_reg + (tile_idx + 16'h2) * P_IN[ADDR_WIDTH-1:0]; + pf_pending_w <= w_base_reg + (tile_idx + 16'h2) * P_IN[ADDR_WIDTH-1:0]; + pf_pending_bank <= current_bank; // the one just freed + end + end else if (!operand_valid) begin + // Waiting for the new current bank to become ready + // (either just swapped, or a stall still in + // progress). + if (bank_ready[current_bank] && tile_idx < n_tiles_reg) begin + operand_valid <= 1'b1; + input_data <= bank_x[current_bank]; + weight_data <= bank_w[current_bank]; + tile_last <= (tile_idx == n_tiles_reg - 16'h1); + end + end + end + + MM_WAIT_RESULT: begin + result_ready <= 1'b1; + if (result_valid && result_ready) begin + wr_mem_wdata <= result_data; + state <= MM_WRITE_RESULT; + end + end + + MM_WRITE_RESULT: begin + // prefetch_engine is guaranteed idle here (no more + // tiles to fetch for this job), so driving the shared + // backend port directly is safe -- see file header. + wr_mem_req <= 1'b1; + wr_mem_addr <= result_addr_reg; + state <= MM_DONE; + end + + MM_DONE: begin + wr_mem_req <= 1'b0; + if (mem_ready) begin + job_done <= 1'b1; + state <= MM_IDLE; + end + end + + default: state <= MM_IDLE; + + endcase + end + end + +endmodule diff --git a/hardware/v2/rtl/prefetch_engine.v b/hardware/v2/rtl/prefetch_engine.v new file mode 100644 index 0000000..2ba1b9a --- /dev/null +++ b/hardware/v2/rtl/prefetch_engine.v @@ -0,0 +1,129 @@ +`timescale 1ns/1ps + +// ================================================================ +// FPGA-Neural V2 -- Prefetch Engine (M4, docs/v2-description.md §13) +// +// Fetches ONE tile (P_IN activation bytes + P_IN weight bytes) from +// the byte-level Memory Backend Interface into a pair of output +// registers, sequentially (2*P_IN single-byte transactions -- the +// same byte-at-a-time convention hardware/v1/rtl/neuron_memory.v +// already uses against the same backend, reused unmodified here). +// +// This module fetches exactly one tile per fetch_start pulse; the +// double-buffering strategy itself (§13: compute tile N while +// prefetching tile N+1, swap, repeat) is memory_manager.v's +// responsibility -- it retargets this single engine at whichever +// bank currently needs refilling, so no internal arbitration between +// multiple fetch engines sharing the backend port is ever needed. +// +// The backend port (mem_req/mem_wr/mem_addr/mem_wdata/mem_rdata/ +// mem_ready) matches hardware/v1/rtl/int8_memory_access.v's contract +// exactly -- this engine can sit directly on top of that unmodified +// V1 module (which itself sits on memory_interface.v -> +// psram_controller.v, also unmodified, per §15). +// ================================================================ + +module prefetch_engine #( + parameter DATA_WIDTH = 8, + parameter P_IN = 8, + parameter ADDR_WIDTH = 23 +)( + input wire clk, + input wire rst, + + input wire fetch_start, + input wire [ADDR_WIDTH-1:0] x_addr, // base addr of this tile's P_IN X bytes + input wire [ADDR_WIDTH-1:0] w_addr, // base addr of this tile's P_IN W bytes + output reg fetch_busy, + output reg fetch_done, // one-cycle pulse + output reg signed [DATA_WIDTH*P_IN-1:0] tile_x, + output reg signed [DATA_WIDTH*P_IN-1:0] tile_w, + + output reg mem_req, + output reg mem_wr, + output reg [ADDR_WIDTH-1:0] mem_addr, + output reg signed [7:0] mem_wdata, + input wire signed [7:0] mem_rdata, + input wire mem_ready +); + + localparam ST_IDLE = 2'd0; + localparam ST_READ_X = 2'd1; + localparam ST_READ_W = 2'd2; + localparam ST_DONE = 2'd3; + + reg [1:0] state; + reg [$clog2(P_IN+1)-1:0] byte_idx; + + always @(posedge clk) begin + if (rst) begin + state <= ST_IDLE; + byte_idx <= 0; + fetch_busy <= 1'b0; + fetch_done <= 1'b0; + mem_req <= 1'b0; + mem_wr <= 1'b0; + mem_addr <= {ADDR_WIDTH{1'b0}}; + mem_wdata <= 8'sd0; + end else begin + mem_req <= 1'b0; + fetch_done <= 1'b0; + + case (state) + + ST_IDLE: begin + if (fetch_start) begin + fetch_busy <= 1'b1; + byte_idx <= 0; + mem_req <= 1'b1; + mem_wr <= 1'b0; + mem_addr <= x_addr; + state <= ST_READ_X; + end + end + + ST_READ_X: begin + if (mem_ready) begin + tile_x[byte_idx*DATA_WIDTH +: DATA_WIDTH] <= mem_rdata; + if (byte_idx == P_IN[$clog2(P_IN+1)-1:0] - 1'b1) begin + byte_idx <= 0; + mem_req <= 1'b1; + mem_wr <= 1'b0; + mem_addr <= w_addr; + state <= ST_READ_W; + end else begin + byte_idx <= byte_idx + 1'b1; + mem_req <= 1'b1; + mem_wr <= 1'b0; + mem_addr <= x_addr + byte_idx + 1'b1; + end + end + end + + ST_READ_W: begin + if (mem_ready) begin + tile_w[byte_idx*DATA_WIDTH +: DATA_WIDTH] <= mem_rdata; + if (byte_idx == P_IN[$clog2(P_IN+1)-1:0] - 1'b1) begin + state <= ST_DONE; + end else begin + byte_idx <= byte_idx + 1'b1; + mem_req <= 1'b1; + mem_wr <= 1'b0; + mem_addr <= w_addr + byte_idx + 1'b1; + end + end + end + + ST_DONE: begin + fetch_busy <= 1'b0; + fetch_done <= 1'b1; + state <= ST_IDLE; + end + + default: state <= ST_IDLE; + + endcase + end + end + +endmodule diff --git a/hardware/v2/sim/tb_memory_manager.v b/hardware/v2/sim/tb_memory_manager.v new file mode 100644 index 0000000..785f1ae --- /dev/null +++ b/hardware/v2/sim/tb_memory_manager.v @@ -0,0 +1,287 @@ +`timescale 1ns/1ps + +// ============================================================ +// M4 testbench (docs/v2-description.md §12/§13/§15/§20): full +// end-to-end stack -- memory_manager.v + prefetch_engine.v (V2, M4) +// driving a REAL hardware/v2/rtl/neural_processor.v (M1) on one side, +// and the REAL, UNMODIFIED hardware/v1 PSRAM backend chain +// (int8_memory_access -> memory_interface -> psram_controller -> +// psram_model) on the other -- exactly the layering §15 mandates +// ("Memory Manager -> Memory Backend Interface -> PSRAM Controller"), +// with the backend reused byte-for-byte from the frozen V1 tree. +// +// Verified with Verilator (see decisions.log DEC-0004). +// +// Coverage: +// - end-to-end job: PSRAM pre-loaded with real X/W bytes at known +// addresses, memory_manager fetches them (double-buffered +// prefetch across multiple tiles), feeds neural_processor, and +// writes the computed result back to PSRAM -- read back +// independently afterward and checked against a hand-computed +// expectation (an oracle independent of the RTL under test). +// - multi-tile job (prefetch actually has to overlap tile N+1's +// fetch with tile N's compute, not just single-tile). +// - "poison" bytes surrounding the real operand region, to catch +// any off-by-one addressing error in prefetch_engine. +// ============================================================ + +module tb; + + localparam ADDR_WIDTH = 23; + localparam DATA_WIDTH = 8; + localparam P_IN = 8; + localparam ACC_WIDTH = 32; + localparam PSRAM_DATA_WIDTH = 16; + localparam CLK_PERIOD = 12.5; // 80 MHz, matches psram_controller's CLK_FREQ_MHZ + + reg clk, rst; + initial begin clk = 1'b0; forever #(CLK_PERIOD/2.0) clk = ~clk; end + + // ---- memory_manager <-> neural_processor ---- + reg job_start; + reg [ADDR_WIDTH-1:0] x_base, w_base, result_addr; + reg [15:0] n_tiles; + wire job_done; + + wire mm_operand_valid, mm_operand_ready; + wire signed [DATA_WIDTH*P_IN-1:0] mm_input_data, mm_weight_data; + wire mm_tile_last; + + wire mm_result_valid, mm_result_ready; + wire signed [DATA_WIDTH-1:0] mm_result_data; + + // ---- memory_manager <-> int8_memory_access (Memory Backend Interface) ---- + wire mem_req, mem_wr; + wire [ADDR_WIDTH-1:0] mem_addr; + wire signed [7:0] mem_wdata; + wire signed [7:0] mem_rdata; + wire mem_ready; + + memory_manager #( + .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ADDR_WIDTH(ADDR_WIDTH) + ) u_mm ( + .clk(clk), .rst(rst), + .job_start(job_start), .x_base(x_base), .w_base(w_base), + .n_tiles(n_tiles), .result_addr(result_addr), .job_done(job_done), + .operand_valid(mm_operand_valid), .operand_ready(mm_operand_ready), + .input_data(mm_input_data), .weight_data(mm_weight_data), .tile_last(mm_tile_last), + .result_valid(mm_result_valid), .result_ready(mm_result_ready), .result_data(mm_result_data), + .mem_req(mem_req), .mem_wr(mem_wr), .mem_addr(mem_addr), .mem_wdata(mem_wdata), + .mem_rdata(mem_rdata), .mem_ready(mem_ready) + ); + + // ---- real Neural Processor (M1), driven entirely by memory_manager ---- + reg job_valid_np; + wire job_ready_np; + wire result_valid_np; + wire signed [DATA_WIDTH-1:0] result_data_np; + wire [15:0] result_node_id_np; + wire [3:0] np_state; + wire np_error; + + neural_processor #( + .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ACC_WIDTH(ACC_WIDTH) + ) u_np ( + .clk(clk), .rst(rst), + .job_valid(job_valid_np), .job_ready(job_ready_np), + .job_node_id(16'h0), .job_bias(8'sd0), .job_activation(2'd1), // ACT_RELU + .operand_valid(mm_operand_valid), .operand_ready(mm_operand_ready), + .input_data(mm_input_data), .weight_data(mm_weight_data), .tile_last(mm_tile_last), + .result_valid(result_valid_np), .result_ready(mm_result_ready), + .result_data(result_data_np), .result_node_id(result_node_id_np), + .np_state(np_state), .np_error(np_error) + ); + assign mm_result_valid = result_valid_np; + assign mm_result_data = result_data_np; + + // job_valid_np must pulse once per memory_manager job, synchronized + // to job_start (both start a "job" at the same moment: memory_manager + // begins prefetching tile 0 while neural_processor waits in NP_IDLE + // until tile 0 actually arrives, exactly like any other operand + // producer feeding it). + always @(posedge clk) begin + if (rst) job_valid_np <= 1'b0; + else if (job_start) job_valid_np <= 1'b1; + else if (job_valid_np && job_ready_np) job_valid_np <= 1'b0; + end + + // ---- REAL, unmodified V1 backend chain ---- + wire if_mem_req, if_mem_wr; + wire [ADDR_WIDTH-1:0] if_mem_addr; + wire [PSRAM_DATA_WIDTH-1:0] if_mem_wdata; + wire if_mem_lb_n, if_mem_ub_n; + wire [PSRAM_DATA_WIDTH-1:0] if_mem_rdata; + wire if_mem_ready; + + int8_memory_access #(.ADDR_WIDTH(ADDR_WIDTH)) u_int8 ( + .clk(clk), .rst(rst), + .req(mem_req), .wr(mem_wr), .addr(mem_addr), .wdata(mem_wdata), + .rdata(mem_rdata), .ready(mem_ready), + .mem_req(if_mem_req), .mem_wr(if_mem_wr), .mem_addr(if_mem_addr), .mem_wdata(if_mem_wdata), + .mem_lb_n(if_mem_lb_n), .mem_ub_n(if_mem_ub_n), + .mem_rdata(if_mem_rdata), .mem_ready(if_mem_ready) + ); + + wire pc_mem_req, pc_mem_wr; + wire [ADDR_WIDTH-1:0] pc_mem_addr; + wire [PSRAM_DATA_WIDTH-1:0] pc_mem_wdata; + wire pc_mem_lb_n, pc_mem_ub_n; + wire [PSRAM_DATA_WIDTH-1:0] pc_mem_rdata; + wire pc_mem_ready; + + memory_interface #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(PSRAM_DATA_WIDTH)) u_memif ( + .clk(clk), .rst(rst), + .req(if_mem_req), .wr(if_mem_wr), .addr(if_mem_addr), .wdata(if_mem_wdata), + .lb_n(if_mem_lb_n), .ub_n(if_mem_ub_n), + .rdata(if_mem_rdata), .ready(if_mem_ready), + .mem_req(pc_mem_req), .mem_wr(pc_mem_wr), .mem_addr(pc_mem_addr), .mem_wdata(pc_mem_wdata), + .mem_lb_n(pc_mem_lb_n), .mem_ub_n(pc_mem_ub_n), + .mem_rdata(pc_mem_rdata), .mem_ready(pc_mem_ready) + ); + + wire [ADDR_WIDTH-1:0] psram_a; + wire [PSRAM_DATA_WIDTH-1:0] psram_dq; + wire psram_ce_n, psram_oe_n, psram_we_n, psram_lb_n, psram_ub_n, psram_zz_n; + + psram_controller #( + .ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(PSRAM_DATA_WIDTH), .CLK_FREQ_MHZ(80) + ) u_psram_ctrl ( + .clk(clk), .rst(rst), + .mem_req(pc_mem_req), .mem_wr(pc_mem_wr), .mem_addr(pc_mem_addr), .mem_wdata(pc_mem_wdata), + .mem_lb_n(pc_mem_lb_n), .mem_ub_n(pc_mem_ub_n), + .mem_rdata(pc_mem_rdata), .mem_ready(pc_mem_ready), + .psram_a(psram_a), .psram_dq(psram_dq), + .psram_ce_n(psram_ce_n), .psram_oe_n(psram_oe_n), .psram_we_n(psram_we_n), + .psram_lb_n(psram_lb_n), .psram_ub_n(psram_ub_n), .psram_zz_n(psram_zz_n) + ); + + psram_model #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(PSRAM_DATA_WIDTH), .DEPTH(16384)) u_psram ( + .clk(clk), .a(psram_a), .dq(psram_dq), + .ce_n(psram_ce_n), .oe_n(psram_oe_n), .we_n(psram_we_n), + .lb_n(psram_lb_n), .ub_n(psram_ub_n), .zz_n(psram_zz_n) + ); + + // ---- helper: poke one byte directly into psram_model's backing + // array (test setup only, bypasses the real write path -- same + // convention as hardware/v1/sim's own testbenches that pre-load + // psram_model for read-side tests). ---- + task automatic poke_byte(input [ADDR_WIDTH-1:0] byte_addr, input [7:0] val); + reg [ADDR_WIDTH-2:0] word_addr; + begin + word_addr = byte_addr[ADDR_WIDTH-1:1]; + if (byte_addr[0] == 1'b0) + u_psram.mem[word_addr][7:0] = val; + else + u_psram.mem[word_addr][15:8] = val; + end + endtask + + task automatic peek_byte(input [ADDR_WIDTH-1:0] byte_addr, output [7:0] val); + reg [ADDR_WIDTH-2:0] word_addr; + begin + word_addr = byte_addr[ADDR_WIDTH-1:1]; + val = (byte_addr[0] == 1'b0) ? u_psram.mem[word_addr][7:0] : u_psram.mem[word_addr][15:8]; + end + endtask + + integer errors, tests; + integer i; + + function automatic signed [7:0] expect_relu(input integer acc); + begin + if (acc <= 0) expect_relu = 0; + else if (acc > 127) expect_relu = 127; + else expect_relu = acc[7:0]; + end + endfunction + + task automatic run_job( + input [ADDR_WIDTH-1:0] xb, input [ADDR_WIDTH-1:0] wb, + input [15:0] nt, input [ADDR_WIDTH-1:0] resaddr, + input signed [7:0] exp_y + ); + integer wd; + reg [7:0] rb; + begin + @(posedge clk); + tests = tests + 1; + x_base = xb; w_base = wb; n_tiles = nt; result_addr = resaddr; + job_start = 1'b1; + @(posedge clk); + job_start = 1'b0; + wd = 0; + while (!job_done && wd < 2000) begin + @(posedge clk); + wd = wd + 1; + end + if (!job_done) begin + $display("FAIL job xb=%0d: no job_done within watchdog (%0d cycles)", xb, wd); + errors = errors + 1; + end else begin + peek_byte(resaddr, rb); + if (rb !== exp_y[7:0]) begin + $display("FAIL job xb=%0d: PSRAM result byte=%0d expected=%0d (%0d cycles)", xb, $signed(rb), exp_y, wd); + errors = errors + 1; + end else begin + $display("PASS job xb=%0d: PSRAM result byte=%0d correct, %0d cycles, n_tiles=%0d", xb, $signed(rb), wd, nt); + end + end + end + endtask + + initial begin + errors = 0; tests = 0; + rst = 1; job_start = 0; x_base = 0; w_base = 0; n_tiles = 0; result_addr = 0; + repeat(5) @(posedge clk); + rst = 0; + + // Wait for the real PSRAM controller's power-up sequence + // (~150us @ 80MHz) before issuing any request -- same + // requirement/convention documented in + // hardware/v1/docs/FPGA-NeuralNetwork-Engine.md's + // WRITE_RAM/READ_RAM backpressure warning. + wait (u_psram_ctrl.state == u_psram_ctrl.STATE_IDLE); + @(posedge clk); + + // ---- pre-load PSRAM: X at 0x1000, W at 0x2000, 3 tiles + // (24 inputs), with "poison" bytes immediately before/after + // the real region to catch any off-by-one in prefetch_engine's + // addressing. ---- + for (i = -4; i < 24+4; i = i + 1) begin + poke_byte(23'h1000 + i, 8'sd99); // poison + poke_byte(23'h2000 + i, 8'sd99); // poison + end + for (i = 0; i < 24; i = i + 1) begin + poke_byte(23'h1000 + i, 8'sd2); // X = 2 + poke_byte(23'h2000 + i, 8'sd3); // W = 3 + end + // acc = 24 * 2 * 3 = 144 -> ACT_RELU saturates to 127 + run_job(23'h1000, 23'h2000, 16'd3, 23'h3000, expect_relu(144)); + + // ---- second job: 1 tile (8 inputs), smaller, no saturation ---- + for (i = 0; i < 8; i = i + 1) begin + poke_byte(23'h4000 + i, 8'sd1); // X = 1 + poke_byte(23'h5000 + i, 8'sd4); // W = 4 + end + // acc = 8*1*4 = 32 + run_job(23'h4000, 23'h5000, 16'd1, 23'h3001, expect_relu(32)); + + // ---- third job: 5 tiles (40 inputs), exercises the + // steady-state double-buffer swap across more than 2 tiles. ---- + for (i = 0; i < 40; i = i + 1) begin + poke_byte(23'h6000 + i, 8'sd1); // X = 1 + poke_byte(23'h7000 + i, 8'sd1); // W = 1 + end + // acc = 40*1*1 = 40 + run_job(23'h6000, 23'h7000, 16'd5, 23'h3002, expect_relu(40)); + + $display("========================================"); + if (errors == 0) + $display("ALL %0d TESTS PASSED (memory_manager + prefetch_engine, real V1 PSRAM backend, real neural_processor)", tests); + else + $display("FAILED: %0d/%0d test(s) had errors -- see messages above", errors, tests); + $display("========================================"); + $finish; + end + +endmodule diff --git a/hardware/v2/synthesis/harness_memory_manager.v b/hardware/v2/synthesis/harness_memory_manager.v new file mode 100644 index 0000000..8ebd579 --- /dev/null +++ b/hardware/v2/synthesis/harness_memory_manager.v @@ -0,0 +1,71 @@ +// ================================================================ +// SYNTHESIS-ONLY TIMING HARNESS -- NOT a functional deliverable. +// Same rationale/pattern as harness_neural_processor_array.v (see its +// header and hardware/v2/logs/errors.log ERR-0005): memory_manager's +// wide ports (input_data/weight_data alone, 64 bits) exceed the +// LFE5U-45F's TRELLIS_IO budget as a bare top-level module. Drives +// them from an internal LFSR and reduces outputs to a small +// checksum, keeping only clk/rst/seed/checksum as real pins, to get +// a representative Fmax for memory_manager's own logic/routing. +// ================================================================ + +module harness_memory_manager #( + parameter DATA_WIDTH = 8, + parameter P_IN = 8, + parameter ADDR_WIDTH = 23 +)( + input wire clk, + input wire rst, + input wire [7:0] seed, + output wire [7:0] checksum +); + + reg [31:0] lfsr; + always @(posedge clk) begin + if (rst) lfsr <= {24'h0, seed} | 32'h1; + else lfsr <= {lfsr[30:0], lfsr[31] ^ lfsr[21] ^ lfsr[1] ^ lfsr[0]}; + end + + wire job_start = lfsr[0]; + wire [ADDR_WIDTH-1:0] x_base = lfsr[ADDR_WIDTH-1:0]; + wire [ADDR_WIDTH-1:0] w_base = {lfsr[7:0], lfsr[ADDR_WIDTH-9:0]}; + wire [15:0] n_tiles = lfsr[15:0]; + wire [ADDR_WIDTH-1:0] result_addr = {lfsr[3:0], lfsr[ADDR_WIDTH-5:0]}; + wire operand_ready = lfsr[2]; + wire result_valid = lfsr[3]; + wire signed [DATA_WIDTH-1:0] result_data = lfsr[7:0]; + wire signed [7:0] mem_rdata = lfsr[15:8]; + wire mem_ready = lfsr[4]; + + wire job_done; + wire operand_valid; + wire signed [DATA_WIDTH*P_IN-1:0] input_data, weight_data; + wire tile_last; + wire result_ready; + wire mem_req, mem_wr; + wire [ADDR_WIDTH-1:0] mem_addr; + wire signed [7:0] mem_wdata; + + memory_manager #( + .DATA_WIDTH(DATA_WIDTH), .P_IN(P_IN), .ADDR_WIDTH(ADDR_WIDTH) + ) dut ( + .clk(clk), .rst(rst), + .job_start(job_start), .x_base(x_base), .w_base(w_base), + .n_tiles(n_tiles), .result_addr(result_addr), .job_done(job_done), + .operand_valid(operand_valid), .operand_ready(operand_ready), + .input_data(input_data), .weight_data(weight_data), .tile_last(tile_last), + .result_valid(result_valid), .result_ready(result_ready), .result_data(result_data), + .mem_req(mem_req), .mem_wr(mem_wr), .mem_addr(mem_addr), .mem_wdata(mem_wdata), + .mem_rdata(mem_rdata), .mem_ready(mem_ready) + ); + + reg [7:0] chk; + always @(posedge clk) begin + if (rst) chk <= 8'h0; + else chk <= chk ^ input_data[7:0] ^ weight_data[7:0] ^ {7'h0, job_done} + ^ {6'h0, tile_last, result_ready} ^ mem_addr[7:0] + ^ {7'h0, mem_req} ^ {7'h0, mem_wr} ^ mem_wdata; + end + assign checksum = chk; + +endmodule diff --git a/hardware/v2/synthesis/harness_memory_manager/nextpnr.log b/hardware/v2/synthesis/harness_memory_manager/nextpnr.log new file mode 100644 index 0000000..156ba97 --- /dev/null +++ b/hardware/v2/synthesis/harness_memory_manager/nextpnr.log @@ -0,0 +1,302 @@ + + +Info: Logic utilisation before packing: +Info: Total LUT4s: 349/43848 0% +Info: logic LUTs: 257/43848 0% +Info: carry LUTs: 92/43848 0% +Info: RAM LUTs: 0/ 5481 0% +Info: RAMW LUTs: 0/10962 0% + +Info: Total DFFs: 203/43848 0% + +Info: Packing IOs.. +Info: Packing constants.. +Info: Packing carries... +Info: Packing LUTs... +Info: Packing LUT5-7s... +Info: Packing FFs... +Info: 72 FFs paired with LUTs. +Info: Generating derived timing constraints... +Info: Promoting globals... +Info: promoting clock net clk$TRELLIS_IO_IN to global network +Info: Checksum: 0x6e129573 + +Info: Device utilisation: +Info: TRELLIS_IO: 18/ 245 7% +Info: DCCA: 1/ 56 1% +Info: DP16KD: 0/ 108 0% +Info: MULT18X18D: 0/ 72 0% +Info: ALU54B: 0/ 36 0% +Info: EHXPLLL: 0/ 4 0% +Info: EXTREFB: 0/ 2 0% +Info: DCUA: 0/ 2 0% +Info: PCSCLKDIV: 0/ 2 0% +Info: IOLOGIC: 0/ 160 0% +Info: SIOLOGIC: 0/ 85 0% +Info: GSR: 0/ 1 0% +Info: JTAGG: 0/ 1 0% +Info: OSCG: 0/ 1 0% +Info: SEDGA: 0/ 1 0% +Info: DTR: 0/ 1 0% +Info: USRMCLK: 0/ 1 0% +Info: CLKDIVF: 0/ 4 0% +Info: ECLKSYNCB: 0/ 10 0% +Info: DLLDELD: 0/ 8 0% +Info: DDRDLL: 0/ 4 0% +Info: DQSBUFM: 0/ 10 0% +Info: TRELLIS_ECLKBUF: 0/ 8 0% +Info: ECLKBRIDGECS: 0/ 2 0% +Info: DCSC: 0/ 2 0% +Info: TRELLIS_FF: 203/ 43848 0% +Info: TRELLIS_COMB: 383/ 43848 0% +Info: TRELLIS_RAMW: 0/ 5481 0% + +Info: Placed 0 cells based on constraints. +Info: Creating initial analytic placement for 333 cells, random placement wirelen = 28028. +Info: at initial placer iter 0, wirelen = 1283 +Info: at initial placer iter 1, wirelen = 1162 +Info: at initial placer iter 2, wirelen = 1104 +Info: at initial placer iter 3, wirelen = 1098 +Info: Running main analytical placer, max placement attempts per cell = 45753. +Info: at iteration #1, type ALL: wirelen solved = 1068, spread = 2127, legal = 2276; time = 0.01s +Info: at iteration #2, type ALL: wirelen solved = 1116, spread = 2137, legal = 2271; time = 0.01s +Info: at iteration #3, type ALL: wirelen solved = 1148, spread = 1979, legal = 2159; time = 0.00s +Info: at iteration #4, type ALL: wirelen solved = 1209, spread = 1880, legal = 2056; time = 0.00s +Info: at iteration #5, type ALL: wirelen solved = 1233, spread = 1999, legal = 2152; time = 0.00s +Info: at iteration #6, type ALL: wirelen solved = 1282, spread = 1933, legal = 2171; time = 0.00s +Info: at iteration #7, type ALL: wirelen solved = 1355, spread = 1921, legal = 2143; time = 0.00s +Info: at iteration #8, type ALL: wirelen solved = 1411, spread = 1875, legal = 2071; time = 0.00s +Info: at iteration #9, type ALL: wirelen solved = 1399, spread = 1911, legal = 2120; time = 0.00s +Info: HeAP Placer Time: 0.07s +Info: of which solving equations: 0.04s +Info: of which spreading cells: 0.01s +Info: of which strict legalisation: 0.00s + +Info: Running simulated annealing placer for refinement. +Info: at iteration #1: temp = 0.000000, timing cost = 91, wirelen = 2056 +Info: at iteration #5: temp = 0.000000, timing cost = 72, wirelen = 1619 +Info: at iteration #10: temp = 0.000000, timing cost = 93, wirelen = 1531 +Info: at iteration #15: temp = 0.000000, timing cost = 90, wirelen = 1514 +Info: at iteration #15: temp = 0.000000, timing cost = 89, wirelen = 1514 +Info: SA placement time 0.09s + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 164.28 MHz (PASS at 80.00 MHz) + +Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.99 ns +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 4.67 ns + +Info: Slack histogram: +Info: legend: * represents 1 endpoint(s) +Info: + represents [1,1) endpoint(s) +Info: [ 6413, 6680) |********* +Info: [ 6680, 6947) |***** +Info: [ 6947, 7214) |**** +Info: [ 7214, 7481) |******** +Info: [ 7481, 7748) |*** +Info: [ 7748, 8015) | +Info: [ 8015, 8282) |** +Info: [ 8282, 8549) |******** +Info: [ 8549, 8816) |******* +Info: [ 8816, 9083) |************* +Info: [ 9083, 9350) |*************************************** +Info: [ 9350, 9617) |**************************** +Info: [ 9617, 9884) |********************* +Info: [ 9884, 10151) |******************************* +Info: [ 10151, 10418) |************************** +Info: [ 10418, 10685) |******************************** +Info: [ 10685, 10952) |********** +Info: [ 10952, 11219) |******************* +Info: [ 11219, 11486) |********************************************* +Info: [ 11486, 11753) |*************************************** +Info: Checksum: 0x691562ea +Info: Routing globals... +Info: routing clock net $glbnet$clk$TRELLIS_IO_IN using global 0 + +Info: Routing.. +Info: Setting up routing queue. +Info: Routing 1629 arcs. +Info: | (re-)routed arcs | delta | remaining| time spent | +Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| +Info: 1000 | 209 742 | 209 742 | 884| 0.08 0.08| +Info: 2000 | 361 1528 | 152 786 | 65| 0.13 0.21| +Info: 2066 | 363 1587 | 2 59 | 0| 0.01 0.22| +Info: Routing complete. +Info: Router1 time 0.22s +Info: Checksum: 0x5e42e5ef + +Info: Critical path report for clock '$glbnet$clk$TRELLIS_IO_IN' (posedge -> posedge): +Info: type curr total name +Info: clk-to-q 0.40 0.40 Source dut.tile_idx_TRELLIS_FF_Q_2.Q +Info: routing 0.93 1.32 Net dut.tile_idx[3] (31,5) -> (32,2) +Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.B +Info: Defined in: +Info: hardware/v2/rtl/memory_manager.v:90.26-90.34 +Info: logic 0.35 1.68 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 1.68 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (32,2) -> (32,2) +Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 1.68 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 1.68 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (32,2) -> (32,2) +Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: hardware/v2/rtl/memory_manager.v:255.38-255.54 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 1.73 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 1.73 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (32,2) -> (32,2) +Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 1.73 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 1.73 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (32,2) -> (33,2) +Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: hardware/v2/rtl/memory_manager.v:255.38-255.54 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 1.79 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 1.79 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (33,2) -> (33,2) +Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 1.79 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 1.79 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT_CIN (33,2) -> (33,2) +Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: hardware/v2/rtl/memory_manager.v:255.38-255.54 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 1.84 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 1.84 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_FCI_INT (33,2) -> (33,2) +Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 1.84 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 1.84 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT_CIN (33,2) -> (33,2) +Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: hardware/v2/rtl/memory_manager.v:255.38-255.54 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 1.90 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 1.90 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_FCI_INT (33,2) -> (33,2) +Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 1.90 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 1.90 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_CIN (33,2) -> (33,2) +Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1$CCU2_COMB0.FCI +Info: Defined in: +Info: hardware/v2/rtl/memory_manager.v:255.38-255.54 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.33 2.23 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1$CCU2_COMB0.F +Info: routing 1.01 3.24 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_A0_CCU2C_S1_S0 (33,2) -> (34,3) +Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.A +Info: logic 0.35 3.60 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_CIN_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 3.60 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT_CIN (34,3) -> (35,3) +Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT$CCU2_COMB0.FCI +Info: Defined in: +Info: hardware/v2/rtl/memory_manager.v:255.38-255.68 +Info: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v:74.7-80.4 +Info: /opt/homebrew/bin/../share/yosys/lattice/ccu2c_sim.vh:9.9-9.13 +Info: logic 0.06 3.65 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT$CCU2_COMB0.FCO +Info: routing 0.00 3.65 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT$CCU2_FCI_INT (35,3) -> (35,3) +Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT$CCU2_COMB1.FCI +Info: logic 0.00 3.65 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z_CCU2C_COUT$CCU2_COMB1.FCO +Info: routing 0.00 3.65 Net $nextpnr_CCU2C_5$CIN (35,3) -> (35,3) +Info: Sink $nextpnr_CCU2C_5$CCU2_COMB0.FCI +Info: logic 0.33 3.98 Source $nextpnr_CCU2C_5$CCU2_COMB0.F +Info: routing 0.71 4.69 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z[2] (35,3) -> (35,4) +Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.C +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 4.87 Source dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F +Info: routing 0.00 4.87 Net dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT (35,4) -> (35,4) +Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1 +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.30-157.32 +Info: logic 0.13 5.00 Source dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX +Info: routing 0.00 5.00 Net dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D0_L6MUX21_Z_D1 (35,4) -> (35,4) +Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.54-157.56 +Info: logic 0.18 5.18 Source dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.00 5.18 Net dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D0 (35,4) -> (35,4) +Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXA +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.66-157.68 +Info: logic 0.18 5.36 Source dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.67 6.03 Net dut.pf_pending_x_TRELLIS_FF_Q_CE (35,4) -> (35,7) +Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_1.CE +Info: setup 0.00 6.03 Source dut.pf_pending_x_TRELLIS_FF_Q_1.CE +Info: 2.71 ns logic, 3.32 ns routing + +Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk$TRELLIS_IO_IN': +Info: type curr total name +Info: source 0.00 0.00 Source rst$tr_io.O +Info: routing 1.39 1.39 Net rst$TRELLIS_IO_IN (38,0) -> (35,7) +Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_C_LUT4_Z.B +Info: Defined in: +Info: hardware/v2/synthesis/harness_memory_manager.v:18.17-18.20 +Info: logic 0.18 1.57 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_C_LUT4_Z.F +Info: routing 0.92 2.49 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C[2] (35,7) -> (36,4) +Info: Sink dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A.C +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 2.67 Source dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A.F +Info: routing 0.49 3.16 Net dut.operand_valid_TRELLIS_FF_Q_CE_LUT4_Z_C_LUT4_A_Z[3] (36,4) -> (35,4) +Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.D +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: logic 0.18 3.34 Source dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F +Info: routing 0.00 3.34 Net dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT (35,4) -> (35,4) +Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1 +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.46-157.48 +Info: logic 0.13 3.47 Source dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX +Info: routing 0.00 3.47 Net dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D1 (35,4) -> (35,4) +Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.62-157.64 +Info: logic 0.18 3.65 Source dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.00 3.65 Net dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1 (35,4) -> (35,4) +Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:157.70-157.72 +Info: logic 0.18 3.83 Source dut.pf_pending_x_TRELLIS_FF_Q_CE_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX +Info: routing 0.67 4.50 Net dut.pf_pending_x_TRELLIS_FF_Q_CE (35,4) -> (35,7) +Info: Sink dut.pf_pending_x_TRELLIS_FF_Q_1.CE +Info: setup 0.00 4.50 Source dut.pf_pending_x_TRELLIS_FF_Q_1.CE +Info: 1.03 ns logic, 3.47 ns routing + +Info: Critical path report for cross-domain path 'posedge $glbnet$clk$TRELLIS_IO_IN' -> '': +Info: type curr total name +Info: clk-to-q 0.40 0.40 Source chk_TRELLIS_FF_Q_2.Q +Info: routing 2.91 3.30 Net checksum[2]$TRELLIS_IO_OUT (38,8) -> (90,11) +Info: Sink checksum[2]$tr_io.I +Info: Defined in: +Info: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v:108.23-108.24 +Info: 0.40 ns logic, 2.91 ns routing + +Info: Max frequency for clock '$glbnet$clk$TRELLIS_IO_IN': 165.86 MHz (PASS at 80.00 MHz) + +Info: Max delay -> posedge $glbnet$clk$TRELLIS_IO_IN: 4.50 ns +Info: Max delay posedge $glbnet$clk$TRELLIS_IO_IN -> : 3.30 ns + +Info: Slack histogram: +Info: legend: * represents 1 endpoint(s) +Info: + represents [1,1) endpoint(s) +Info: [ 6471, 6738) |******* +Info: [ 6738, 7005) |** +Info: [ 7005, 7272) |** +Info: [ 7272, 7539) |* +Info: [ 7539, 7806) |* +Info: [ 7806, 8073) |*** +Info: [ 8073, 8340) |************* +Info: [ 8340, 8607) |*** +Info: [ 8607, 8874) |**** +Info: [ 8874, 9141) |************* +Info: [ 9141, 9408) |********************************************** +Info: [ 9408, 9675) |*********************************** +Info: [ 9675, 9942) |************************** +Info: [ 9942, 10209) |****************************** +Info: [ 10209, 10476) |**************************** +Info: [ 10476, 10743) |**************** +Info: [ 10743, 11010) |************** +Info: [ 11010, 11277) |********************* +Info: [ 11277, 11544) |********************************************** +Info: [ 11544, 11811) |************************************** + +Info: Program finished normally. diff --git a/hardware/v2/synthesis/harness_memory_manager/top.config b/hardware/v2/synthesis/harness_memory_manager/top.config new file mode 100644 index 0000000..ec5b51b --- /dev/null +++ b/hardware/v2/synthesis/harness_memory_manager/top.config @@ -0,0 +1,8279 @@ +.device LFE5U-45F + +.comment Part: LFE5U-45F-8CABGA381 + +.tile CIB_R10C13:CIB_EBR +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 + +.tile CIB_R10C19:CIB_EBR +arc: E3_H06E0003 W3_H06E0303 +arc: E3_H06E0203 W3_H06E0103 + +.tile CIB_R10C1:CIB_LR_S +arc: E3_H06E0003 V01N0001 +arc: E3_H06E0303 S3_V06N0303 + +.tile CIB_R10C25:CIB_EBR +arc: E3_H06E0103 W3_H06E0003 +arc: E3_H06E0203 W3_H06E0203 + +.tile CIB_R10C30:CIB_EBR +arc: N1_V02N0401 E1_H01W0000 + +.tile CIB_R10C31:CIB_EBR +arc: E3_H06E0303 W3_H06E0203 +arc: H01W0000 W3_H06E0103 + +.tile CIB_R10C33:CIB_EBR +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 E1_H02W0601 + +.tile CIB_R10C35:CIB_EBR +arc: N1_V02N0601 E1_H02W0601 +arc: W1_H02W0601 V02N0601 + +.tile CIB_R10C37:CIB_EBR +arc: W1_H02W0601 W3_H06E0303 + +.tile CIB_R10C3:PVT_COUNT2 +unknown: F2B0 +unknown: F3B0 +unknown: F5B0 +unknown: F11B0 +unknown: F13B0 + +.tile CIB_R10C7:CIB_EBR +arc: E3_H06E0003 W3_H06E0003 +arc: E3_H06E0303 W3_H06E0303 + +.tile CIB_R11C1:CIB_LR +arc: E3_H06E0303 JQ5 +arc: N1_V01N0001 JF5 +arc: S1_V02S0501 E1_H02W0501 +arc: S1_V02S0701 N1_V02S0601 + +.tile CIB_R11C89:CIB_LR +arc: S1_V02S0701 N1_V02S0601 +arc: W3_H06W0303 JQ5 + +.tile CIB_R13C1:CIB_LR +arc: JA0 N1_V02S0701 +arc: JA3 N1_V02S0501 +enum: CIB.JB3MUX 0 +enum: CIB.JB0MUX 0 + +.tile CIB_R13C89:CIB_LR +arc: JA0 N1_V02S0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R14C1:CIB_LR +arc: N3_V06N0303 JF5 +arc: S1_V02S0701 E1_H02W0701 + +.tile CIB_R16C1:CIB_LR +arc: JA0 N1_V02S0701 +arc: N3_V06N0303 JQ5 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C31:CIB +arc: JA0 V02N0701 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C32:CIB +arc: S3_V06S0003 E3_H06W0003 + +.tile CIB_R1C33:CIB +arc: V01S0000 S3_V06N0103 + +.tile CIB_R1C34:CIB +arc: S1_V02S0201 H06W0103 +arc: S3_V06S0103 H06W0103 + +.tile CIB_R1C36:CIB +arc: E1_H02E0001 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 + +.tile CIB_R1C37:CIB +arc: E3_H06E0303 S3_V06N0303 +arc: JA0 V01N0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0103 E1_H01W0100 +arc: W3_H06W0103 E1_H01W0100 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C38:CIB +arc: E1_H02E0401 E3_H06W0203 +arc: H01W0100 JQ0 +arc: S1_V02S0001 W1_H02E0001 +arc: V01S0000 S3_V06N0103 +arc: W3_H06W0003 JQ0 + +.tile CIB_R1C39:CIB +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0601 H06W0303 + +.tile CIB_R1C40:CIB +arc: S1_V02S0401 W1_H02E0401 + +.tile CIB_R1C42:CIB +arc: W3_H06W0003 JQ0 +arc: W3_H06W0303 E1_H01W0100 + +.tile CIB_R1C43:CIB +arc: E3_H06E0303 W3_H06E0303 +arc: H01W0100 JQ0 + +.tile CIB_R1C44:CIB +arc: H00L0000 V02N0201 +arc: JA0 H00L0000 +arc: W3_H06W0203 E1_H01W0000 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C45:CIB +arc: H01W0000 JQ0 + +.tile CIB_R1C46:CIB +arc: E1_H02E0701 V02N0701 + +.tile CIB_R1C48:CIB +arc: JA0 W1_H02E0701 +arc: JD7 E1_H01W0100 +enum: CIB.JB0MUX 0 + +.tile CIB_R1C49:CIB +arc: H01W0100 W3_H06E0303 + +.tile CIB_R5C1:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R5C89:CIB_PLL1 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C3:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R70C42:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C43:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C44:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C45:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C46:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C47:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C48:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C49:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C50:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C51:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C52:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C53:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R70C69:VCIB_DCU0 +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C6:CIB_EFB0 +enum: CIB.JB3MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C70:VCIB_DCUA +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C71:VCIB_DCUB +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C72:VCIB_DCUC +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C73:VCIB_DCUD +enum: CIB.JA1MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C74:VCIB_DCUF +enum: CIB.JA1MUX 0 +enum: CIB.JA3MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC2MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C75:VCIB_DCU3 +enum: CIB.JA5MUX 0 +enum: CIB.JA7MUX 0 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JC0MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC6MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C76:VCIB_DCU2 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C77:VCIB_DCUG +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C78:VCIB_DCUH +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C79:VCIB_DCUI +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB7MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD6MUX 0 + +.tile CIB_R70C7:CIB_EFB1 +enum: CIB.JA3MUX 0 +enum: CIB.JA4MUX 0 +enum: CIB.JA5MUX 0 +enum: CIB.JA6MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB4MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JB6MUX 0 +enum: CIB.JC3MUX 0 +enum: CIB.JC4MUX 0 +enum: CIB.JC5MUX 0 +enum: CIB.JD3MUX 0 +enum: CIB.JD4MUX 0 +enum: CIB.JD5MUX 0 + +.tile CIB_R70C80:VCIB_DCU1 +enum: CIB.JB1MUX 0 +enum: CIB.JB3MUX 0 +enum: CIB.JB5MUX 0 +enum: CIB.JD0MUX 0 +enum: CIB.JD2MUX 0 + +.tile CIB_R70C87:CIB_PLL3 +enum: CIB.JA3MUX 0 +enum: CIB.JB3MUX 0 + +.tile CIB_R8C1:CIB_LR +arc: E3_H06E0303 S3_V06N0303 + +.tile CIB_R9C1:CIB_LR +arc: S1_V02S0601 E3_H06W0303 + +.tile CIB_R9C89:CIB_LR +arc: S1_V02S0601 H06E0303 + +.tile MIB_R0C31:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C37:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C38:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C3:BANKREF0 +enum: BANK.VCCIO 3V3 + +.tile MIB_R0C40:TMID_0 +arc: G_TDCC0CLKI G_JTRQPCLKCIB1 + +.tile MIB_R0C42:PIOT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R0C43:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C44:PIOT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C45:PIOT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R0C48:PIOT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R0C87:BANKREF1 +enum: BANK.VCCIO 3V3 + +.tile MIB_R10C0:BANKREF7 +enum: BANK.VCCIO 3V3 + +.tile MIB_R10C30:EBR_SPINE_UL0 +arc: G_VPTX0000 G_HPRX0000 + +.tile MIB_R10C40:CMUX_UL_0 +arc: G_DCS0CLK0 G_VPFN0000 +arc: G_ULPCLK0 G_VPFS0000 + +.tile MIB_R10C41:CMUX_UR_0 +arc: G_DCS0CLK1 G_VPFN0000 +arc: G_URPCLK0 G_VPFS0000 + +.tile MIB_R10C90:BANKREF2 +enum: BANK.VCCIO 3V3 + +.tile MIB_R11C0:PICL0 +arc: JDIA JPADDIA_PIO +arc: JDIB JPADDIB_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R11C90:PICR0 +arc: JDIB JPADDIB_PIO +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R12C0:PICL1 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R12C90:PICR1 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 +enum: PIOB.HYSTERESIS ON + +.tile MIB_R13C0:PICL2 +enum: PIOD.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R13C90:PICR2 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R14C0:PICL0 +arc: JDIA JPADDIA_PIO +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R15C0:PICL1_DQS0 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOD.HYSTERESIS ON +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON + +.tile MIB_R16C0:PICL2_DQS1 +enum: PIOD.BASE_TYPE INPUT_LVCMOS33 +enum: PIOC.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C31:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C37:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C38:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C42:PICT0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C43:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C44:PICT0 +enum: PIOA.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R1C45:PICT1 +enum: PIOB.BASE_TYPE INPUT_LVCMOS33 + +.tile MIB_R1C48:PICT1 +enum: PIOB.BASE_TYPE OUTPUT_LVCMOS33 + +.tile MIB_R58C40:CMUX_LL_0 +arc: G_DCS1CLK0 G_VPFN0000 +arc: G_LLPCLK0 G_VPFS0000 + +.tile MIB_R58C41:CMUX_LR_0 +arc: G_DCS1CLK1 G_VPFN0000 +arc: G_LRPCLK0 G_VPFS0000 + +.tile MIB_R71C4:EFB0_PICB0 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.BASE_TYPE INPUT_LVCMOS33 +enum: PIOA.HYSTERESIS ON +unknown: F54B1 +unknown: F56B1 +unknown: F82B1 +unknown: F94B1 + +.tile R11C13:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R11C19:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R11C25:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R11C31:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R11C35:PLC2 +arc: N1_V02N0601 E1_H02W0601 + +.tile R11C37:PLC2 +arc: E1_H02E0601 N3_V06S0303 +arc: N1_V02N0401 W3_H06E0203 +arc: N1_V02N0701 N3_V06S0203 +arc: W1_H02W0601 N3_V06S0303 + +.tile R11C38:PLC2 +arc: N1_V02N0601 H02E0601 + +.tile R11C3:PLC2 +arc: W1_H02W0501 V06S0303 + +.tile R11C41:PLC2 +arc: N1_V02N0601 E3_H06W0303 + +.tile R11C47:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R11C53:PLC2 +arc: W3_H06W0303 E3_H06W0203 + +.tile R11C59:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R11C65:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R11C71:PLC2 +arc: W3_H06W0003 E3_H06W0303 + +.tile R11C77:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R11C7:PLC2 +arc: E3_H06E0303 W3_H06E0303 + +.tile R11C83:PLC2 +arc: W3_H06W0303 E3_H06W0303 + +.tile R14C3:PLC2 +arc: W1_H02W0701 N3_V06S0203 + +.tile R2C30:PLC2 +arc: E1_H02E0001 V06N0003 +arc: E1_H02E0501 E3_H06W0303 +arc: S3_V06S0303 E3_H06W0303 + +.tile R2C31:PLC2 +arc: E1_H02E0101 V06N0103 +arc: N1_V02N0701 S1_V02N0601 +arc: A0 H02W0701 +arc: A1 H02W0701 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0101 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0401 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: F0 F5A_SLICE +arc: M0 E1_H02W0601 +arc: S1_V02S0001 F0 +word: SLICEA.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 1100101011111111 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R2C32:PLC2 +arc: E1_H02E0101 V06N0103 +arc: E3_H06E0303 S3_V06N0303 +arc: V00T0000 V02N0401 +arc: W1_H02W0701 E1_H02W0601 +arc: A0 W1_H02E0501 +arc: A3 V01N0101 +arc: A5 V02N0301 +arc: B2 V01N0001 +arc: B4 H02E0101 +arc: B6 V00T0000 +arc: B7 S1_V02N0701 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: E1_H02E0401 F4 +arc: E1_H02E0501 F5 +arc: E1_H02E0701 F7 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: V01S0100 F4 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 + +.tile R2C33:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0601 H01E0001 +arc: S1_V02S0001 E3_H06W0003 +arc: S1_V02S0101 H01E0101 +arc: S3_V06S0003 E3_H06W0003 +arc: V00B0000 S1_V02N0001 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E1_H01W0000 +arc: A0 H02W0501 +arc: A1 S1_V02N0501 +arc: A2 H02W0701 +arc: A4 V00B0000 +arc: B3 S1_V02N0101 +arc: B5 V02N0701 +arc: B6 H02W0101 +arc: B7 H02E0101 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F0 +arc: E1_H02E0101 F1 +arc: E1_H02E0701 F7 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: S1_V02S0301 F3 +arc: S1_V02S0501 F5 +arc: V01S0000 F6 +arc: V01S0100 F2 +word: SLICEA.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R2C34:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 W1_H02E0401 +arc: H00R0000 H02W0601 +arc: H00R0100 E1_H02W0501 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H01E0101 +arc: S1_V02S0701 W1_H02E0701 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0701 V06N0203 +arc: A6 S1_V02N0101 +arc: B0 E1_H02W0101 +arc: B4 V02N0701 +arc: C4 Q4 +arc: C6 Q6 +arc: CE1 H00R0000 +arc: CE2 V02N0601 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D4 H02E0001 +arc: D6 V00B0000 +arc: E1_H01E0101 F0 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 Q2 +arc: M2 V00B0000 +arc: M6 V00B0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V00B0000 Q4 +arc: W1_H02W0601 Q6 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICED.K0.INIT 1111101001010000 +word: SLICEC.K0.INIT 1111000011001100 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R2C35:PLC2 +arc: E1_H02E0001 V02N0001 +arc: E1_H02E0101 S3_V06N0103 +arc: E1_H02E0401 S3_V06N0203 +arc: E1_H02E0701 S1_V02N0701 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 W1_H02E0601 +arc: S1_V02S0201 V01N0001 +arc: S1_V02S0501 H01E0101 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 W1_H02E0701 +arc: V00T0000 H02E0001 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0601 +arc: A0 H02W0701 +arc: A2 S1_V02N0701 +arc: A3 S1_V02N0501 +arc: A4 V02N0101 +arc: A5 H02E0501 +arc: A6 E1_H02W0501 +arc: B2 H02E0301 +arc: B3 H00L0000 +arc: B4 H00R0000 +arc: B5 V02N0701 +arc: B6 V00T0000 +arc: E1_H01E0001 F3 +arc: E1_H02E0501 F5 +arc: E1_H02E0601 F6 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: S1_V02S0401 F4 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEC.K0.INIT 0110011001101010 +word: SLICEC.K1.INIT 0110011001101100 +word: SLICED.K0.INIT 0110011001101010 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R2C36:PLC2 +arc: E1_H02E0301 V02S0301 +arc: H00L0100 V02N0301 +arc: H00R0000 H02E0401 +arc: H00R0100 H02E0701 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0101 H02E0101 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0501 H02E0501 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 H02E0601 +arc: V00B0100 H02W0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0701 E1_H01W0100 +arc: W3_H06W0303 E1_H01W0100 +arc: A2 F5 +arc: A5 Q5 +arc: A6 V02S0301 +arc: A7 V02S0301 +arc: B2 H02W0301 +arc: B3 H01W0100 +arc: B6 E1_H02W0301 +arc: B7 E1_H02W0101 +arc: C2 H00L0000 +arc: C3 E1_H02W0601 +arc: C5 E1_H02W0601 +arc: C6 V02N0201 +arc: C7 E1_H02W0401 +arc: CE2 H00R0000 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D2 V01S0100 +arc: D3 V02N0001 +arc: D5 S1_V02N0401 +arc: D6 E1_H02W0201 +arc: D7 V02N0401 +arc: E3_H06E0103 Q2 +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F6 F5D_SLICE +arc: H00L0000 Q2 +arc: H01W0000 F6 +arc: H01W0100 Q7 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M5 H00L0100 +arc: M6 V00B0000 +arc: M7 H00R0100 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: V01S0100 F3 +word: SLICED.K0.INIT 1111000001000100 +word: SLICED.K1.INIT 1111111010101110 +word: SLICEB.K1.INIT 1100111111000000 +word: SLICEC.K1.INIT 0101111110100000 +word: SLICEB.K0.INIT 0110100110010110 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R2C37:PLC2 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 V06N0203 +arc: E1_H02E0501 E1_H01W0100 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 V02S0701 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 E1_H02W0501 +arc: V00B0000 V02N0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0301 V02N0301 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 S1_V02N0501 +arc: W1_H02W0601 V06N0303 +arc: W1_H02W0701 V02S0701 +arc: A0 H02W0701 +arc: B0 F3 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: C0 H00L0000 +arc: C2 N1_V01N0001 +arc: C3 E1_H01W0000 +arc: CE1 H00R0000 +arc: CE2 H00R0000 +arc: CE3 W1_H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 F2 +arc: D2 S1_V02N0001 +arc: D3 V00B0100 +arc: E1_H01E0001 Q3 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0000 Q0 +arc: H01W0100 F4 +arc: LSR0 V00T0100 +arc: LSR1 V00T0100 +arc: M3 H00R0100 +arc: M5 W1_H02E0001 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q6 +arc: N1_V01N0101 Q0 +arc: S1_V02S0601 F4 +arc: V00B0100 Q5 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEB.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 0011110011110000 +word: SLICEA.K0.INIT 0110100110010110 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R2C38:PLC2 +arc: E1_H02E0501 V06N0303 +arc: H00L0000 S1_V02N0001 +arc: H00L0100 S1_V02N0301 +arc: H00R0100 H02E0501 +arc: H01W0100 W3_H06E0303 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 V02N0001 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 V01N0101 +arc: A1 V01N0101 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: A4 F5 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 W1_H02E0301 +arc: B3 W1_H02E0301 +arc: B4 H00R0000 +arc: B5 V01S0000 +arc: B7 S1_V02N0701 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 E1_H01E0101 +arc: C5 H01E0001 +arc: C7 V02N0201 +arc: CE0 S1_V02N0201 +arc: CE1 S1_V02N0201 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V02N0201 +arc: D3 V02N0201 +arc: D4 S1_V02N0601 +arc: D5 H00R0100 +arc: D7 S1_V02N0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 Q6 +arc: E3_H06E0203 Q4 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M0 V00T0100 +arc: M1 H02W0001 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: M6 V00T0000 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: V00B0100 F7 +arc: V00T0000 F2 +arc: V01S0000 Q3 +arc: W1_H02W0701 Q7 +word: SLICEA.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 1100101011111111 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEB.K0.INIT 1000110010000000 +word: SLICEB.K1.INIT 1011111110110011 +word: SLICEC.K1.INIT 0011110011001100 +word: SLICEC.K0.INIT 0110100110010110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R2C39:PLC2 +arc: E1_H02E0301 W1_H02E0301 +arc: H00L0000 V02N0201 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 H02E0501 +arc: S1_V02S0601 W1_H02E0601 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0501 E1_H01W0100 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 W1_H02E0701 +arc: A2 H00L0100 +arc: A3 H00L0100 +arc: A7 V00T0100 +arc: B1 W1_H02E0301 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: C0 V02S0601 +arc: C1 E1_H01W0000 +arc: C2 W1_H02E0401 +arc: C3 W1_H02E0401 +arc: C7 V02N0201 +arc: CE1 H00R0100 +arc: CE2 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 V02S0001 +arc: D2 V01S0100 +arc: D3 V01S0100 +arc: D7 E1_H02W0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H01W0100 Q1 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: M5 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: S3_V06S0103 Q1 +arc: V00B0100 F7 +arc: V00T0100 Q3 +arc: V01S0100 Q5 +arc: W1_H02W0001 F2 +arc: W3_H06W0003 Q0 +word: SLICEA.K1.INIT 1111110000110000 +word: SLICEA.K0.INIT 1111010110100000 +word: SLICED.K1.INIT 1111000010101010 +word: SLICEB.K0.INIT 1100100000001000 +word: SLICEB.K1.INIT 1111101100111011 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R2C40:PLC2 +arc: B0 H02E0301 +arc: C0 V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: H01W0100 Q0 +arc: MUXCLK0 CLK0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R2C41:PLC2 +arc: W1_H02W0201 S1_V02N0201 + +.tile R2C42:PLC2 +arc: E1_H02E0201 W3_H06E0103 + +.tile R2C44:PLC2 +arc: E1_H02E0701 W3_H06E0203 +arc: N1_V02N0201 W1_H02E0201 + +.tile R2C46:PLC2 +arc: N1_V02N0701 W1_H02E0701 + +.tile R3C30:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 E3_H06W0003 +arc: E1_H02E0601 S1_V02N0601 +arc: E3_H06E0003 S3_V06N0003 +arc: S1_V02S0301 S3_V06N0003 + +.tile R3C31:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0701 S1_V02N0701 +arc: S1_V02S0601 E1_H01W0000 + +.tile R3C32:PLC2 +arc: E1_H02E0101 V02N0101 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0000 S1_V02N0601 +arc: S1_V02S0701 H02W0701 +arc: V00B0000 W1_H02E0601 +arc: V00T0000 W1_H02E0001 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 S1_V02N0101 +arc: B0 V00B0000 +arc: B2 E1_H01W0100 +arc: B3 E1_H01W0100 +arc: B5 W1_H02E0301 +arc: C0 S1_V02N0401 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0601 +arc: C5 E1_H02W0601 +arc: C6 V02N0201 +arc: CE0 H02E0101 +arc: CE2 V02N0601 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D1 H00R0000 +arc: D2 E1_H02W0201 +arc: D3 E1_H02W0001 +arc: D4 V00B0000 +arc: D5 E1_H02W0001 +arc: D6 V00B0000 +arc: E1_H01E0001 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q4 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q0 +arc: N1_V02N0301 Q1 +arc: N1_V02N0401 Q6 +arc: S1_V02S0101 Q1 +arc: S1_V02S0201 Q0 +arc: S1_V02S0401 Q6 +arc: S1_V02S0601 Q4 +arc: V00B0100 F5 +arc: V01S0000 Q1 +arc: V01S0100 Q6 +word: SLICEA.K1.INIT 1111000000000000 +word: SLICEC.K0.INIT 1010101000000000 +word: SLICEA.K0.INIT 1100000011000000 +word: SLICEC.K1.INIT 1100111111000000 +word: SLICEB.K0.INIT 1101000010000000 +word: SLICEB.K1.INIT 1101111110001111 +word: SLICED.K0.INIT 1111000000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R3C33:PLC2 +arc: E1_H02E0201 W1_H02E0701 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 N1_V01S0100 +arc: H00R0000 S1_V02N0401 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0201 H01E0001 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 V02N0201 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0701 V02N0701 +arc: A0 V02N0701 +arc: A2 V00T0000 +arc: A3 S1_V02N0701 +arc: A4 V02N0301 +arc: A5 H02E0701 +arc: A6 H02E0501 +arc: A7 V02S0101 +arc: B3 H02E0101 +arc: B4 H02E0301 +arc: B5 H02W0301 +arc: B6 V00B0000 +arc: B7 E1_H02W0101 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: H01W0100 Q0 +arc: M0 H02E0601 +arc: MUXCLK0 CLK0 +word: SLICED.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R3C34:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: H00L0000 H02E0201 +arc: H00R0000 H02E0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0601 E1_H02W0601 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0301 N1_V02S0201 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0601 H06W0303 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00B0100 H02W0701 +arc: V00T0000 E1_H02W0201 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 V06N0303 +arc: A0 V02S0701 +arc: A1 E1_H02W0501 +arc: A2 S1_V02N0701 +arc: A3 H02E0701 +arc: A4 V02N0301 +arc: A5 V00B0000 +arc: A6 H02E0501 +arc: A7 H00R0000 +arc: B0 H00R0100 +arc: B1 V02S0301 +arc: B2 V02S0101 +arc: B3 V01N0001 +arc: B4 H02E0301 +arc: B5 V00B0100 +arc: B6 E1_H02W0301 +arc: B7 V02N0701 +arc: CE0 V02N0201 +arc: CE1 H00L0000 +arc: CLK0 G_HPBX0000 +arc: M1 E1_H02W0001 +arc: M2 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0101 Q1 +arc: S3_V06S0103 Q1 +arc: V01S0000 Q1 +arc: W1_H02W0001 Q2 +arc: W1_H02W0201 Q2 +word: SLICED.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEA.K0.INIT 1001100110011010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R3C35:PLC2 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0701 V02N0701 +arc: H00R0000 V02S0601 +arc: H00R0100 E1_H02W0501 +arc: N1_V01N0001 S3_V06N0003 +arc: N1_V02N0001 S3_V06N0003 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0701 H02W0701 +arc: V00B0000 E1_H02W0401 +arc: V00T0000 V02S0401 +arc: V00T0100 H02W0101 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0701 E1_H01W0100 +arc: A0 V02S0701 +arc: A1 V02S0501 +arc: A4 N1_V01N0101 +arc: A5 N1_V01N0101 +arc: A6 S1_V02N0301 +arc: A7 V00T0100 +arc: B0 V02N0101 +arc: B1 V02N0301 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 H02W0101 +arc: B7 S1_V02N0701 +arc: C4 W1_H02E0601 +arc: C5 W1_H02E0601 +arc: C6 V02S0201 +arc: C7 E1_H02W0401 +arc: CE0 H00R0100 +arc: CE1 S1_V02N0201 +arc: CE2 S1_V02N0601 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D4 H02E0201 +arc: D5 H02E0201 +arc: D6 V00B0000 +arc: D7 H02E0001 +arc: E1_H01E0001 Q7 +arc: E1_H02E0601 F4 +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q0 +arc: H01W0100 F6 +arc: M0 V00B0100 +arc: M1 H00L0100 +arc: M2 E1_H02W0601 +arc: M3 H01W0100 +arc: M4 H02E0401 +arc: M5 H00R0000 +arc: M6 V00T0000 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q1 +arc: S1_V02S0001 F2 +arc: S1_V02S0201 F2 +arc: S3_V06S0003 Q0 +arc: S3_V06S0103 F2 +arc: V00B0100 Q5 +arc: V01S0000 F2 +arc: W1_H02W0001 Q2 +arc: W1_H02W0301 Q1 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1001100110011010 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEC.K0.INIT 1111000011100010 +word: SLICEC.K1.INIT 1111100010101010 +word: SLICED.K1.INIT 1111110111101100 +word: SLICED.K0.INIT 1101110000010000 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R3C36:PLC2 +arc: E1_H02E0001 S3_V06N0003 +arc: E3_H06E0003 W3_H06E0003 +arc: H00L0000 W1_H02E0201 +arc: H00L0100 V02S0301 +arc: H00R0000 H02E0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 V01N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W3_H06E0003 +arc: N1_V02N0401 E1_H01W0000 +arc: V00B0000 V02S0001 +arc: V00B0100 N1_V02S0301 +arc: V00T0100 V02S0501 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 S1_V02N0301 +arc: W1_H02W0501 V06N0303 +arc: A0 S1_V02N0501 +arc: A1 H00L0100 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 V02S0301 +arc: A6 V02S0301 +arc: A7 V02S0301 +arc: B1 H02W0101 +arc: B2 N1_V02S0301 +arc: B3 N1_V02S0301 +arc: B4 H02W0101 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0101 +arc: C0 S1_V02N0401 +arc: C1 H00L0000 +arc: C2 V02S0401 +arc: C3 V02S0401 +arc: C4 H02E0401 +arc: C6 V00B0100 +arc: C7 V00B0100 +arc: CE0 V02N0201 +arc: CE2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 H00R0000 +arc: D2 E1_H02W0001 +arc: D3 E1_H02W0001 +arc: D4 W1_H02E0201 +arc: D6 E1_H01W0100 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F6 +arc: E1_H02E0101 F1 +arc: E1_H02E0601 F4 +arc: E1_H02E0701 Q5 +arc: E3_H06E0103 F1 +arc: E3_H06E0203 F4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 F2 +arc: H01W0100 Q4 +arc: M2 V00T0100 +arc: M4 E1_H02W0401 +arc: M5 H00R0100 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: S1_V02S0501 Q5 +arc: S1_V02S0601 F4 +arc: S3_V06S0103 F1 +arc: S3_V06S0203 F4 +arc: V01S0000 F1 +arc: V01S0100 Q4 +arc: W1_H02W0201 Q0 +arc: W1_H02W0401 Q4 +arc: W1_H02W0601 F4 +arc: W1_H02W0701 Q5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0203 Q4 +arc: W3_H06W0303 Q5 +word: SLICEB.K0.INIT 1010101000110000 +word: SLICEB.K1.INIT 1110111011111100 +word: SLICED.K0.INIT 1100111000000010 +word: SLICED.K1.INIT 1111111011110010 +word: SLICEA.K0.INIT 1111101000001010 +word: SLICEC.K0.INIT 0010000000110000 +word: SLICEA.K1.INIT 0000101100000000 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R3C37:PLC2 +arc: E1_H02E0601 E1_H01W0000 +arc: H00R0000 W1_H02E0601 +arc: N1_V02N0001 S1_V02N0501 +arc: S1_V02S0001 H02E0001 +arc: S3_V06S0003 N1_V02S0301 +arc: V00B0100 N1_V02S0301 +arc: V00T0000 V02S0601 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 V06N0103 +arc: W1_H02W0501 V06N0303 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0303 V06N0303 +arc: A2 W1_H02E0701 +arc: A5 H02E0701 +arc: B0 V00T0000 +arc: B3 V02N0101 +arc: B4 S1_V02N0501 +arc: B6 V02N0501 +arc: CE1 V02N0201 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: H01W0100 F3 +arc: LSR0 V00B0100 +arc: LSR1 V00T0100 +arc: M3 H02W0201 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V02N0301 Q3 +arc: V01S0000 Q7 +arc: W1_H02W0401 F4 +arc: W1_H02W0701 F5 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1100110011000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R3C38:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0501 S1_V02N0501 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 V02S0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0201 H02W0201 +arc: S1_V02S0201 E1_H01W0000 +arc: S1_V02S0401 E1_H01W0000 +arc: S1_V02S0601 W1_H02E0601 +arc: V00B0100 H02W0501 +arc: V00T0100 V02N0701 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0401 S1_V02N0401 +arc: A2 E1_H01E0001 +arc: A3 E1_H01E0001 +arc: A5 V02N0101 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: B4 H02W0101 +arc: C2 H02E0601 +arc: C3 H00L0000 +arc: C4 Q4 +arc: C5 H02W0601 +arc: CE0 H00R0000 +arc: CE1 H00R0100 +arc: CE2 S1_V02N0601 +arc: CE3 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D2 N1_V02S0001 +arc: D3 V01S0100 +arc: D4 V02N0401 +arc: D5 H00L0100 +arc: E1_H01E0001 Q6 +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H00L0100 Q3 +arc: H01W0000 Q4 +arc: M0 V00T0100 +arc: M2 V00B0000 +arc: M3 E1_H02W0201 +arc: M4 V00B0100 +arc: M6 V00B0100 +arc: M7 E1_H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: N1_V02N0701 F5 +arc: V00B0000 F4 +arc: V01S0100 Q4 +arc: W1_H02W0201 F2 +word: SLICEC.K1.INIT 1111010110100000 +word: SLICEA.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 0000000000001110 +word: SLICEC.K0.INIT 1100110011110000 +word: SLICEB.K0.INIT 1011100000000000 +word: SLICEB.K1.INIT 1011111110001111 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R3C39:PLC2 +arc: H00L0000 S1_V02N0001 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0001 H06E0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0701 H06E0203 +arc: V00B0100 V02N0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 S1_V02N0701 +arc: A1 H02E0501 +arc: B0 S1_V02N0101 +arc: B1 Q1 +arc: C0 H00L0000 +arc: CE0 H02E0101 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 S1_V02N0201 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: H01W0000 Q1 +arc: M2 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: N1_V02N0201 Q0 +arc: S1_V02S0301 Q1 +arc: W1_H02W0201 Q2 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEA.K1.INIT 1100110010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R3C40:PLC2 +arc: N1_V02N0001 H02W0001 +arc: W1_H02W0201 V02N0201 + +.tile R3C41:PLC2 +arc: W1_H02W0001 S3_V06N0003 + +.tile R4C30:PLC2 +arc: E1_H02E0301 V02S0301 + +.tile R4C31:PLC2 +arc: E1_H02E0001 S1_V02N0001 +arc: E1_H02E0301 V01N0101 +arc: H00L0000 N1_V02S0001 +arc: H00R0100 V02N0501 +arc: N1_V02N0301 H02W0301 +arc: S1_V02S0301 H02W0301 +arc: A1 H00L0100 +arc: A2 V00B0000 +arc: A3 V00B0000 +arc: B1 V02N0301 +arc: B2 H01W0100 +arc: B3 Q3 +arc: C1 V02N0601 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: CE0 E1_H02W0101 +arc: CE1 S1_V02N0201 +arc: CLK0 G_HPBX0000 +arc: D1 H02W0001 +arc: D2 V02N0001 +arc: D3 V02N0001 +arc: D4 V02S0601 +arc: E1_H01E0101 F4 +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q3 +arc: LSR0 H02W0301 +arc: LSR1 H02W0301 +arc: M1 H00R0100 +arc: M2 V00T0100 +arc: M3 H00L0000 +arc: M6 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0601 Q6 +arc: V00B0000 Q6 +arc: V00T0000 F2 +arc: V00T0100 F1 +word: SLICEC.K0.INIT 0000000011111111 +word: SLICEA.K1.INIT 0110111101100000 +word: SLICEB.K1.INIT 1001011001101001 +word: SLICEB.K0.INIT 0110100110010110 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C32:PLC2 +arc: E1_H02E0601 W1_H02E0301 +arc: E1_H02E0701 E3_H06W0203 +arc: E3_H06E0303 H01E0101 +arc: H00L0000 E1_H02W0201 +arc: H00L0100 S1_V02N0101 +arc: H00R0000 V02S0601 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 V01N0001 +arc: N1_V02N0601 S1_V02N0601 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0701 E1_H01W0100 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 V02S0201 +arc: V00T0000 S1_V02N0401 +arc: W1_H02W0001 S1_V02N0001 +arc: W1_H02W0301 V06S0003 +arc: A0 V02S0701 +arc: A3 V02N0501 +arc: A4 V00B0000 +arc: A5 V02N0301 +arc: A6 E1_H01W0000 +arc: A7 N1_V01S0100 +arc: B2 H02E0301 +arc: B3 H00R0000 +arc: B4 S1_V02N0501 +arc: B5 H00L0000 +arc: B6 N1_V01S0000 +arc: B7 V02N0701 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: H01W0000 Q7 +arc: LSR1 V00T0000 +arc: M7 H02W0201 +arc: MUXCLK3 CLK0 +arc: MUXLSR3 LSR1 +word: SLICEA.K0.INIT 0000000000001010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011100 +word: SLICEC.K0.INIT 1001100110011010 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011100 +word: SLICED.K1.INIT 1001100110011010 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C33:PLC2 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 V01N0001 +arc: E1_H02E0501 V01N0101 +arc: E1_H02E0701 S1_V02N0701 +arc: H00R0000 V02N0601 +arc: N1_V02N0001 H06W0003 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0701 S1_V02N0601 +arc: S1_V02S0101 H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0501 H06W0303 +arc: S1_V02S0701 H06W0203 +arc: V00B0000 N1_V02S0001 +arc: V00T0000 E1_H02W0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02S0201 +arc: A0 V02S0501 +arc: A1 S1_V02N0501 +arc: A2 E1_H02W0701 +arc: A3 H02W0501 +arc: A4 E1_H01W0000 +arc: A5 E1_H02W0501 +arc: A6 H00R0000 +arc: A7 H02E0701 +arc: B0 V00T0000 +arc: B1 V02N0301 +arc: B2 E1_H02W0101 +arc: B3 E1_H01W0100 +arc: B4 H02W0101 +arc: B5 V02S0701 +arc: B6 V02N0501 +arc: B7 H02W0301 +arc: CE1 V02N0201 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 Q2 +arc: E1_H02E0001 Q2 +arc: H01W0000 Q2 +arc: H01W0100 Q2 +arc: M2 V00B0000 +arc: MUXCLK1 CLK0 +arc: N1_V02N0201 Q2 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1001100110011100 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 1001100110011100 +word: SLICEB.K1.INIT 1001100110011010 +word: SLICEC.K0.INIT 1001100110011100 +word: SLICEC.K1.INIT 1001100110011010 +word: SLICED.K0.INIT 1001100110011010 +word: SLICED.K1.INIT 1001100110011100 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R4C34:PLC2 +arc: E1_H02E0201 V06S0103 +arc: H00L0000 V02S0001 +arc: H00L0100 V02S0101 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0701 W1_H02E0701 +arc: S1_V02S0401 H01E0001 +arc: V00B0000 V02N0201 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0501 V01N0101 +arc: A0 V02N0501 +arc: A1 H00R0000 +arc: A4 V00B0000 +arc: A5 V00B0000 +arc: A6 H02E0701 +arc: A7 H02E0701 +arc: B0 E1_H02W0301 +arc: B1 V02N0301 +arc: B4 S1_V02N0501 +arc: B5 S1_V02N0501 +arc: B6 N1_V01S0000 +arc: B7 H02E0101 +arc: C4 V00T0100 +arc: C5 V00T0100 +arc: C6 V00T0100 +arc: C7 V02N0201 +arc: CE0 S1_V02N0201 +arc: CE1 S1_V02N0201 +arc: CE2 V02S0601 +arc: CE3 V02S0601 +arc: CLK0 G_HPBX0000 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 V00B0000 +arc: D7 H00L0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q0 +arc: E1_H02E0101 Q3 +arc: E1_H02E0301 Q3 +arc: E1_H02E0401 F4 +arc: E1_H02E0601 F6 +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F5D_SLICE +arc: H00R0100 Q7 +arc: H01W0000 Q3 +arc: H01W0100 Q0 +arc: M0 V00T0000 +arc: M2 W1_H02E0601 +arc: M3 H02W0201 +arc: M4 V00B0100 +arc: M5 H00L0000 +arc: M6 V00B0100 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0301 Q3 +arc: S1_V02S0001 Q0 +arc: S1_V02S0201 Q2 +arc: S1_V02S0501 Q5 +arc: S1_V02S0701 Q7 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q2 +word: SLICEC.K0.INIT 1100110111001000 +word: SLICEC.K1.INIT 1111110110001000 +word: SLICED.K0.INIT 1010101010101100 +word: SLICED.K1.INIT 1110111110100000 +word: SLICEA.K0.INIT 1001100110011010 +word: SLICEA.K1.INIT 1001100110011100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 + +.tile R4C35:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0101 W1_H02E0001 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V06N0003 +arc: E1_H02E0501 V06N0303 +arc: E1_H02E0601 V06N0303 +arc: E1_H02E0701 H01E0101 +arc: E3_H06E0003 H01E0001 +arc: H00L0000 S1_V02N0201 +arc: H00R0000 E1_H02W0601 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 H06W0103 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0201 H06W0103 +arc: S1_V02S0301 H02E0301 +arc: S1_V02S0401 H06W0203 +arc: V00B0100 E1_H02W0501 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0701 V01N0101 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02W0501 +arc: A1 H02W0701 +arc: A2 H02W0701 +arc: A3 H02W0701 +arc: A4 E1_H02W0501 +arc: A5 H02W0501 +arc: A6 E1_H02W0501 +arc: A7 E1_H02W0501 +arc: B0 E1_H02W0301 +arc: B1 V02N0301 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B4 V02N0701 +arc: B5 N1_V01S0000 +arc: B6 V02N0701 +arc: B7 V02N0701 +arc: C0 S1_V02N0601 +arc: C2 S1_V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V02S0001 +arc: C5 V00B0100 +arc: C6 V02S0201 +arc: C7 V02S0001 +arc: CE3 H00L0100 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V00B0100 +arc: D2 V02S0201 +arc: D3 N1_V01S0000 +arc: D4 H00R0100 +arc: D5 H02W0001 +arc: D6 H00R0100 +arc: D7 H00R0100 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F3 +arc: H01W0000 Q7 +arc: M0 V00T0100 +arc: M1 H00L0000 +arc: M2 V00T0100 +arc: M3 E1_H02W0201 +arc: M4 V00T0100 +arc: M5 H00L0000 +arc: M6 V00T0100 +arc: M7 H00R0000 +arc: MUXCLK3 CLK0 +arc: S1_V02S0101 F3 +arc: V01S0000 F3 +word: SLICEA.K0.INIT 0000001000100010 +word: SLICEA.K1.INIT 0000000000100010 +word: SLICEB.K0.INIT 0000001000100010 +word: SLICEB.K1.INIT 0000001000100010 +word: SLICEC.K0.INIT 0001010100000000 +word: SLICEC.K1.INIT 0000001000001010 +word: SLICED.K0.INIT 0001010100000000 +word: SLICED.K1.INIT 0001010100000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C36:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0301 W1_H02E0201 +arc: E1_H02E0501 V02S0501 +arc: E1_H02E0701 W1_H02E0601 +arc: E3_H06E0003 V06N0003 +arc: H00L0100 V02N0101 +arc: H00R0000 W1_H02E0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0301 +arc: V00B0000 E1_H02W0601 +arc: V00B0100 S1_V02N0101 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0001 V06N0003 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0601 E1_H02W0301 +arc: W3_H06W0303 E1_H01W0100 +arc: A3 F5 +arc: A4 S1_V02N0101 +arc: A5 V00B0000 +arc: A6 N1_V01S0100 +arc: A7 E1_H02W0501 +arc: B1 S1_V02N0101 +arc: B2 S1_V02N0101 +arc: B5 H02E0301 +arc: B6 W1_H02E0101 +arc: B7 E1_H02W0101 +arc: C0 V02N0601 +arc: C3 S1_V02N0601 +arc: C4 V02N0001 +arc: C5 H02W0401 +arc: C7 V02N0201 +arc: CE0 H00L0100 +arc: CE1 H00L0100 +arc: CE2 H00L0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 H02E0201 +arc: D2 H02E0001 +arc: D3 E1_H02W0001 +arc: D5 S1_V02N0401 +arc: D6 E1_H02W0201 +arc: D7 W1_H02E0001 +arc: E1_H01E0101 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q4 +arc: H01W0100 Q0 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 Q7 +arc: N1_V02N0001 Q2 +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F6 +arc: S1_V02S0501 F7 +arc: V01S0000 Q2 +arc: W1_H02W0101 Q1 +arc: W1_H02W0201 Q2 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F5 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q1 +arc: W3_H06W0203 Q4 +word: SLICEC.K0.INIT 1010000010100000 +word: SLICEB.K0.INIT 1100110000000000 +word: SLICEA.K1.INIT 1100110000000000 +word: SLICEA.K0.INIT 1111000000000000 +word: SLICEC.K1.INIT 1100000011001000 +word: SLICED.K0.INIT 0000000000010001 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEB.K1.INIT 0000000000001010 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R4C37:PLC2 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0601 V02N0601 +arc: H00L0100 V02N0301 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0501 S1_V02N0501 +arc: N1_V02N0601 W1_H02E0601 +arc: S1_V02S0101 H01E0101 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0401 E1_H01W0000 +arc: V00B0100 H02E0501 +arc: V00T0000 V02N0601 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 V01N0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 V06N0203 +arc: W1_H02W0501 V01N0101 +arc: W1_H02W0701 V02N0701 +arc: A4 W1_H02E0701 +arc: A5 W1_H02E0701 +arc: B7 V00B0000 +arc: C0 V02N0601 +arc: C4 V02S0001 +arc: C5 V02N0001 +arc: C7 V00T0100 +arc: CE0 H00L0100 +arc: CE1 H00R0000 +arc: CE2 E1_H02W0101 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D7 S1_V02N0601 +arc: E1_H01E0001 F7 +arc: F0 F0_SLICE +arc: F4 F5C_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q5 +arc: H01W0100 Q0 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M3 H00R0100 +arc: M4 V00T0000 +arc: M5 E1_H02W0001 +arc: M6 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: V00B0000 Q6 +arc: V00T0100 Q3 +arc: W1_H02W0001 Q0 +arc: W1_H02W0601 F4 +word: SLICEC.K0.INIT 0101010111110000 +word: SLICEC.K1.INIT 0101111101011010 +word: SLICED.K1.INIT 1100110011110000 +word: SLICEA.K0.INIT 1111000000000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C38:PLC2 +arc: H00L0000 V02S0201 +arc: H00R0000 V02N0601 +arc: H00R0100 H02W0501 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0001 H06E0003 +arc: V00B0000 H02W0601 +arc: V00T0100 V02N0501 +arc: W1_H02W0001 V02N0001 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02N0701 +arc: A1 V02N0701 +arc: A5 S1_V02N0101 +arc: B0 V00B0000 +arc: B1 V00B0000 +arc: B4 V01S0000 +arc: C0 H02E0601 +arc: C1 H02E0601 +arc: C4 V02N0201 +arc: C5 E1_H01E0101 +arc: CE0 H00R0000 +arc: CE1 H02E0101 +arc: CE2 V02S0601 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V01S0100 +arc: D1 V01S0100 +arc: D4 H02W0201 +arc: D5 V02S0401 +arc: E1_H01E0101 Q1 +arc: E1_H02E0401 Q4 +arc: F0 F5A_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q2 +arc: M0 V00B0100 +arc: M1 H00L0000 +arc: M2 V00T0100 +arc: M3 H00R0100 +arc: M7 E1_H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V02N0001 F0 +arc: V00B0100 F5 +arc: V01S0000 Q4 +arc: V01S0100 Q1 +arc: W1_H02W0101 Q3 +arc: W1_H02W0201 Q2 +arc: W1_H02W0301 Q3 +arc: W1_H02W0501 Q7 +arc: W3_H06W0003 Q3 +arc: W3_H06W0103 Q2 +arc: W3_H06W0203 Q7 +word: SLICEC.K1.INIT 1111101001010000 +word: SLICEA.K0.INIT 1101000010000000 +word: SLICEA.K1.INIT 1101111110001111 +word: SLICEC.K0.INIT 1100110011110000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C39:PLC2 +arc: H00L0000 V02N0001 +arc: H00R0000 H02E0401 +arc: H00R0100 V02S0701 +arc: N1_V02N0301 H06E0003 +arc: V00B0100 V02S0301 +arc: W1_H02W0001 V01N0001 +arc: W1_H02W0101 S1_V02N0101 +arc: W1_H02W0201 V02N0201 +arc: W1_H02W0501 V01N0101 +arc: A0 E1_H01E0001 +arc: A1 V02N0501 +arc: B1 Q1 +arc: B2 V02N0301 +arc: C0 H00L0000 +arc: C2 V02N0401 +arc: CE0 H00R0100 +arc: CE1 V02S0201 +arc: CE2 V02N0601 +arc: CE3 N1_V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0201 +arc: D1 V02N0201 +arc: D2 Q2 +arc: E1_H01E0001 Q0 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: H01W0100 Q1 +arc: M5 H00R0000 +arc: M6 V00B0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q0 +arc: N1_V01N0101 Q2 +arc: N1_V02N0101 Q1 +arc: S1_V02S0501 Q7 +arc: V01S0000 Q5 +arc: V01S0100 Q5 +arc: W1_H02W0601 Q6 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEA.K0.INIT 1010101011110000 +word: SLICEA.K1.INIT 1100110010101010 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.C1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 1 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R4C40:PLC2 +arc: N1_V02N0201 H01E0001 +arc: W1_H02W0201 V02N0201 + +.tile R4C41:PLC2 +arc: N1_V02N0201 S1_V02N0201 + +.tile R5C30:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: E1_H02E0501 V06S0303 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0601 S1_V02N0301 +arc: N3_V06N0003 S1_V02N0301 + +.tile R5C31:PLC2 +arc: N1_V02N0001 E3_H06W0003 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E3_H06W0203 +arc: V00B0100 V02S0301 +arc: V00T0100 H02E0301 +arc: A0 E1_H01E0001 +arc: B2 H02E0301 +arc: C2 E1_H01W0000 +arc: CE0 E1_H02W0101 +arc: CE1 E1_H02W0101 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: E1_H01E0001 Q0 +arc: E1_H01E0101 Q2 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: LSR0 V00B0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 Q0 +arc: N3_V06N0103 Q2 +word: SLICEB.K0.INIT 1100000011000000 +word: SLICEA.K0.INIT 0101010100000000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C32:PLC2 +arc: E1_H02E0301 S1_V02N0301 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 V02N0701 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0701 H06W0203 +arc: N3_V06N0103 E3_H06W0103 +arc: S1_V02S0501 E1_H01W0100 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 S1_V02N0301 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0601 V06N0303 +arc: A0 W1_H02E0501 +arc: A2 H01E0001 +arc: A3 V00T0000 +arc: A4 V00B0000 +arc: A6 N1_V02S0101 +arc: A7 H00R0000 +arc: B5 H01E0101 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0000 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 F5 +arc: E3_H06E0203 F7 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F5 +arc: H01W0100 Q3 +arc: LSR1 V00B0100 +arc: M3 E1_H02W0201 +arc: MUXCLK1 CLK0 +arc: MUXLSR1 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V02N0101 F3 +arc: N1_V02N0401 F4 +arc: N1_V02N0601 F6 +arc: S1_V02S0301 F3 +arc: S1_V02S0401 F4 +arc: V01S0000 F6 +arc: V01S0100 F4 +word: SLICED.K1.INIT 1010101010100000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1100110011000000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1010101010100000 +word: SLICEB.K0.INIT 0110011001101100 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001010 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C33:PLC2 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0401 V02N0401 +arc: H00R0000 H02W0601 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 E1_H01W0000 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0301 N1_V02S0301 +arc: W1_H02W0101 E1_H02W0001 +arc: A0 V02S0701 +arc: A2 V02S0501 +arc: A4 V02S0101 +arc: A5 V02S0301 +arc: A6 E1_H01W0000 +arc: B1 E1_H01W0100 +arc: B3 H00R0000 +arc: B7 H02W0101 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F6 +arc: E1_H02E0001 F0 +arc: E1_H02E0201 F2 +arc: E1_H02E0301 F1 +arc: E1_H02E0601 F4 +arc: E1_H02E0701 F5 +arc: E3_H06E0003 F0 +arc: E3_H06E0103 F2 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q7 +arc: M7 H02W0201 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F4 +arc: N1_V01N0101 F7 +arc: N1_V02N0701 Q7 +arc: S1_V02S0201 F2 +arc: S1_V02S0701 F7 +arc: V01S0000 F6 +arc: V01S0100 Q7 +arc: W1_H02W0501 Q7 +word: SLICED.K1.INIT 1100110011000000 +word: SLICED.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 1010101010100000 +word: SLICEB.K1.INIT 1100110011000000 +word: SLICEB.K0.INIT 1010101010100000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 1010101010100000 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C34:PLC2 +arc: E1_H02E0001 W1_H02E0501 +arc: E1_H02E0401 W1_H02E0401 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 H01E0101 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0701 +arc: N1_V02N0301 E1_H02W0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H02W0601 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0003 H06E0003 +arc: S1_V02S0101 E1_H01W0100 +arc: S1_V02S0301 N1_V02S0301 +arc: S1_V02S0401 H02W0401 +arc: S1_V02S0601 E1_H02W0601 +arc: V00B0000 V02S0001 +arc: V00B0100 N1_V02S0301 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0201 S1_V02N0201 +arc: A7 H02E0701 +arc: B0 E1_H02W0101 +arc: B1 E1_H02W0301 +arc: B5 H02E0301 +arc: B6 H01E0101 +arc: B7 V00B0000 +arc: C4 H01E0001 +arc: C7 H01E0001 +arc: CE2 H02W0101 +arc: CE3 H02W0101 +arc: CLK0 G_HPBX0000 +arc: D4 H00R0100 +arc: D5 H00R0100 +arc: D6 H00R0100 +arc: D7 N1_V02S0401 +arc: E1_H01E0001 F0 +arc: E1_H01E0101 F7 +arc: E1_H02E0201 F0 +arc: E1_H02E0301 F1 +arc: E3_H06E0103 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q6 +arc: H01W0100 Q5 +arc: LSR0 W1_H02E0301 +arc: LSR1 V00B0100 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q4 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 Q5 +arc: W1_H02W0601 Q4 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1100110011000000 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICED.K0.INIT 1100110000000000 +word: SLICEC.K1.INIT 1100110000000000 +word: SLICED.K1.INIT 1000001001000001 +word: SLICEC.K0.INIT 1111000000000000 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C35:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 S1_V02N0401 +arc: E1_H02E0501 H01E0101 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0000 V02N0001 +arc: H00L0100 E1_H02W0301 +arc: H00R0000 H02W0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 N1_V01S0000 +arc: N1_V02N0301 S1_V02N0301 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0601 N1_V01S0000 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0001 H01E0001 +arc: S1_V02S0501 H06W0303 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0101 E1_H02W0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W1_H02W0601 E1_H02W0601 +arc: W1_H02W0701 S1_V02N0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 E1_H01E0001 +arc: A1 H02E0501 +arc: A7 H02W0501 +arc: B0 V02S0301 +arc: B1 H01W0100 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B7 W1_H02E0101 +arc: C0 N1_V01N0001 +arc: C1 V02N0401 +arc: C2 N1_V01N0001 +arc: C3 N1_V01N0001 +arc: C7 H02E0401 +arc: CE1 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0201 +arc: D1 W1_H02E0201 +arc: D2 W1_H02E0201 +arc: D3 W1_H02E0201 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 Q7 +arc: E1_H01E0101 Q7 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0100 Q3 +arc: M0 W1_H02E0601 +arc: M1 H00R0100 +arc: M2 W1_H02E0601 +arc: M3 H00L0100 +arc: M4 W1_H02E0401 +arc: M5 H00L0000 +arc: M6 W1_H02E0401 +arc: M7 E1_H02W0201 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q3 +arc: N1_V02N0501 F5 +arc: S1_V02S0101 F1 +arc: S1_V02S0701 F5 +arc: V01S0000 Q7 +arc: V01S0100 Q3 +arc: W1_H02W0501 Q7 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 1010001001010001 +word: SLICEA.K0.INIT 0010001000000010 +word: SLICEA.K1.INIT 1010000000100000 +word: SLICEB.K0.INIT 0011001100000011 +word: SLICEB.K1.INIT 1100110000001100 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 + +.tile R5C36:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 V01N0101 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0000 S1_V02N0001 +arc: H00R0000 H02E0601 +arc: H00R0100 V02N0501 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 H02W0101 +arc: N1_V02N0201 H01E0001 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 S1_V02N0101 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06E0303 +arc: S1_V02S0001 N1_V02S0501 +arc: S1_V02S0701 N1_V02S0601 +arc: S3_V06S0003 E1_H01W0000 +arc: V00B0000 E1_H02W0401 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 S1_V02N0401 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 E1_H02W0601 +arc: W3_H06W0003 E1_H01W0000 +arc: A0 V02N0701 +arc: A1 V02N0701 +arc: A2 V02N0701 +arc: A3 V02N0701 +arc: B0 H01W0100 +arc: B1 H01W0100 +arc: B2 H01W0100 +arc: B3 H01W0100 +arc: C0 W1_H02E0601 +arc: C1 W1_H02E0601 +arc: C2 W1_H02E0601 +arc: C3 W1_H02E0601 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 W1_H02E0001 +arc: D2 W1_H02E0001 +arc: D3 W1_H02E0001 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q7 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F3 FXB_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H01W0000 Q7 +arc: H01W0100 Q7 +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: M2 V00B0100 +arc: M3 H00R0100 +arc: M4 E1_H02W0401 +arc: M5 H00R0000 +arc: M6 E1_H02W0401 +arc: M7 H02E0201 +arc: MUXCLK3 CLK0 +arc: V01S0000 Q7 +word: SLICEA.K0.INIT 0010000000000010 +word: SLICEA.K1.INIT 1000000000001000 +word: SLICEB.K0.INIT 0001000000000001 +word: SLICEB.K1.INIT 0100000000000100 +word: SLICEC.K0.INIT 0000000000000000 +word: SLICEC.K1.INIT 0000000000000000 +word: SLICED.K0.INIT 0000000000000000 +word: SLICED.K1.INIT 0000000000000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 + +.tile R5C37:PLC2 +arc: E1_H01E0001 W3_H06E0003 +arc: E1_H02E0101 V01N0101 +arc: E1_H02E0201 S1_V02N0201 +arc: H00L0100 E1_H02W0101 +arc: N1_V02N0001 W3_H06E0003 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0301 V01N0101 +arc: N1_V02N0401 W1_H02E0401 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 S1_V02N0601 +arc: S1_V02S0301 H02E0301 +arc: S3_V06S0203 E1_H01W0000 +arc: V00B0000 S1_V02N0201 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0201 E1_H02W0701 +arc: W1_H02W0501 V01N0101 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0203 E1_H01W0000 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H01E0001 +arc: A1 E1_H01E0001 +arc: A3 W1_H02E0701 +arc: A4 S1_V02N0301 +arc: A5 S1_V02N0301 +arc: A6 V02N0301 +arc: A7 W1_H02E0501 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 S1_V02N0301 +arc: B3 S1_V02N0301 +arc: B5 H02W0101 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 H02E0401 +arc: C3 H02E0401 +arc: C4 V01N0101 +arc: C5 E1_H02W0601 +arc: C6 S1_V02N0201 +arc: C7 H01E0001 +arc: CE1 V02N0201 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 W1_H02E0001 +arc: D3 V02N0001 +arc: D4 V02N0401 +arc: D6 V01N0001 +arc: D7 F0 +arc: E1_H01E0101 Q4 +arc: E1_H02E0501 F5 +arc: E3_H06E0203 Q7 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 F2 +arc: H00R0000 Q6 +arc: H01W0000 Q4 +arc: H01W0100 Q6 +arc: LSR1 V00B0000 +arc: M0 H02E0601 +arc: M1 H00L0100 +arc: M2 V00B0100 +arc: M3 H00L0000 +arc: M6 V00T0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F5 +arc: N1_V02N0701 Q7 +arc: N3_V06N0203 Q4 +arc: N3_V06N0303 F6 +arc: S1_V02S0101 Q1 +arc: S1_V02S0401 Q4 +arc: S1_V02S0501 F5 +arc: S1_V02S0601 F6 +arc: S1_V02S0701 F7 +arc: S3_V06S0303 F6 +arc: V00B0100 F7 +arc: V00T0100 Q1 +arc: V01S0000 F7 +arc: W1_H02W0301 Q1 +arc: W1_H02W0401 F6 +arc: W1_H02W0601 Q6 +arc: W3_H06W0003 Q3 +word: SLICED.K1.INIT 1010000000000000 +word: SLICEC.K1.INIT 0010101000101010 +word: SLICEB.K0.INIT 0011000000110000 +word: SLICEB.K1.INIT 1011100000110000 +word: SLICED.K0.INIT 0000101000000000 +word: SLICEC.K0.INIT 0000111110100000 +word: SLICEA.K0.INIT 0000010100000001 +word: SLICEA.K1.INIT 0101000000010000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.D1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R5C38:PLC2 +arc: E1_H02E0101 H01E0101 +arc: E1_H02E0601 N1_V01S0000 +arc: H00L0000 E1_H02W0001 +arc: H00R0100 V02N0701 +arc: N1_V02N0001 S1_V02N0001 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0501 H02E0501 +arc: V00B0100 V02N0101 +arc: V00T0000 H02E0201 +arc: V00T0100 H02E0101 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0401 W3_H06E0203 +arc: W1_H02W0701 W3_H06E0203 +arc: W3_H06W0303 E1_H01W0100 +arc: A5 V02N0101 +arc: A6 V02N0101 +arc: B0 S1_V02N0301 +arc: B2 S1_V02N0301 +arc: B4 V01S0000 +arc: B5 V02N0501 +arc: C4 V00B0100 +arc: C5 V02N0001 +arc: C6 V00T0000 +arc: CE0 H02E0101 +arc: CE1 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: D2 W1_H02E0201 +arc: D4 H00R0100 +arc: D5 V02N0401 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F6 +arc: E1_H02E0501 Q7 +arc: E1_H02E0701 Q7 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: H00R0000 F4 +arc: H01W0000 F6 +arc: H01W0100 Q2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M4 V00T0100 +arc: M5 H00R0000 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR1 +arc: N1_V02N0501 Q7 +arc: N1_V02N0601 F6 +arc: N3_V06N0003 Q0 +arc: N3_V06N0303 F6 +arc: S1_V02S0601 F6 +arc: V01S0000 Q5 +arc: V01S0100 F6 +arc: W1_H02W0001 Q2 +arc: W1_H02W0201 Q0 +arc: W1_H02W0601 F6 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 1100110000000000 +word: SLICED.K0.INIT 0000000000001010 +word: SLICEC.K0.INIT 1111110011001100 +word: SLICEC.K1.INIT 1111100000000000 +word: SLICEB.K0.INIT 1100110000000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C39:PLC2 +arc: H00R0100 H02E0701 +arc: N1_V02N0101 S1_V02N0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 S1_V02N0201 +arc: N1_V02N0501 H02E0501 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: V00T0000 W1_H02E0201 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0201 W3_H06E0103 +arc: W1_H02W0601 S1_V02N0601 +arc: A0 V02S0501 +arc: A1 V02S0501 +arc: B0 H02E0101 +arc: B1 H02E0101 +arc: B3 E1_H02W0101 +arc: C0 N1_V01S0100 +arc: C1 N1_V01S0100 +arc: C3 H02E0601 +arc: CLK0 G_HPBX0000 +arc: D0 S1_V02N0001 +arc: D1 S1_V02N0001 +arc: D3 N1_V01S0000 +arc: E1_H01E0001 Q2 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q4 +arc: H01W0100 Q7 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M0 V00T0100 +arc: M2 V00B0100 +arc: M4 E1_H02W0401 +arc: M5 H00R0100 +arc: M7 H00R0000 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F0 +arc: N1_V01N0101 Q5 +arc: N1_V02N0001 Q2 +arc: N1_V02N0401 Q4 +arc: S1_V02S0701 Q5 +arc: V00B0100 Q7 +arc: V00T0100 F3 +arc: V01S0100 Q5 +arc: W1_H02W0701 Q7 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICEA.K0.INIT 1011100000000000 +word: SLICEA.K1.INIT 1011100011111111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R5C40:PLC2 +arc: N1_V02N0201 H01E0001 +arc: S1_V02S0401 H06E0203 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 W3_H06E0103 + +.tile R5C41:PLC2 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0401 E1_H02W0401 + +.tile R5C43:PLC2 +arc: W1_H02W0401 W3_H06E0203 + +.tile R6C31:PLC2 +arc: E1_H02E0301 V02N0301 +arc: E1_H02E0501 V01N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: S1_V02S0101 E1_H01W0100 +arc: V00B0000 S1_V02N0001 +arc: V00B0100 V02N0301 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: A2 V02N0501 +arc: A3 V00T0000 +arc: A4 S1_V02N0301 +arc: B0 V00T0000 +arc: B1 V00T0000 +arc: B2 E1_H02W0101 +arc: B4 V00B0100 +arc: C0 V02N0601 +arc: C1 V02N0601 +arc: C2 H00L0100 +arc: C3 E1_H02W0601 +arc: C4 Q4 +arc: CLK0 G_HPBX0000 +arc: D0 H02W0001 +arc: D1 H02W0001 +arc: D2 H02W0201 +arc: D3 S1_V02N0001 +arc: D4 V00B0000 +arc: E1_H02E0201 Q2 +arc: E3_H06E0103 Q2 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H00L0100 F3 +arc: M0 E1_H02W0601 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: N1_V02N0001 Q2 +arc: S1_V02S0201 F0 +arc: S1_V02S0401 Q4 +arc: S3_V06S0203 Q4 +arc: V00T0000 Q2 +arc: V01S0100 Q2 +word: SLICEA.K0.INIT 1010101110101000 +word: SLICEA.K1.INIT 1110111110100000 +word: SLICEB.K1.INIT 0000101010101010 +word: SLICEB.K0.INIT 0000000011111000 +word: SLICEC.K0.INIT 0010001000110010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R6C32:PLC2 +arc: E1_H02E0001 V01N0001 +arc: E1_H02E0701 E1_H01W0100 +arc: H00R0100 V02N0501 +arc: H01W0000 E3_H06W0103 +arc: N1_V02N0101 E3_H06W0103 +arc: N1_V02N0401 V01N0001 +arc: N1_V02N0501 E1_H01W0100 +arc: N1_V02N0601 H06W0303 +arc: N1_V02N0701 S1_V02N0701 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0401 H06W0203 +arc: S1_V02S0601 V01N0001 +arc: V00T0000 H02W0201 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 V01N0001 +arc: A1 N1_V02S0701 +arc: A4 V02S0301 +arc: A5 N1_V01N0101 +arc: B0 H02W0301 +arc: B1 E1_H01W0100 +arc: B4 V02S0501 +arc: B5 V00B0100 +arc: C0 F6 +arc: C1 N1_V01S0100 +arc: C3 F6 +arc: C4 V00T0000 +arc: C5 V02N0001 +arc: C6 E1_H02W0601 +arc: CE0 H00R0100 +arc: CE1 H00R0100 +arc: CE2 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02N0001 +arc: D1 N1_V01S0000 +arc: D2 V00T0100 +arc: D3 V01S0100 +arc: D4 V02S0401 +arc: D5 V00B0000 +arc: D6 H02E0201 +arc: E1_H01E0001 F4 +arc: E1_H01E0101 F1 +arc: E1_H02E0401 F6 +arc: E1_H02E0501 Q5 +arc: E3_H06E0303 F6 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H01W0100 F6 +arc: LSR0 E1_H02W0301 +arc: LSR1 H02E0301 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0101 Q3 +arc: N1_V02N0001 Q0 +arc: S1_V02S0201 Q2 +arc: V00B0000 F6 +arc: V00B0100 Q5 +arc: V00T0100 F3 +arc: V01S0000 Q5 +arc: V01S0100 Q3 +word: SLICEC.K0.INIT 1001000010011001 +word: SLICEC.K1.INIT 0000000001101100 +word: SLICEB.K1.INIT 0000000000001111 +word: SLICEA.K1.INIT 1010001011110011 +word: SLICEA.K0.INIT 1100110011000011 +word: SLICEB.K0.INIT 0000000011111111 +word: SLICED.K0.INIT 0000000000001111 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 + +.tile R6C33:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0301 N1_V01S0100 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0601 E1_H01W0000 +arc: E1_H02E0701 V02S0701 +arc: E3_H06E0303 H01E0101 +arc: H00R0000 V02N0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0101 S1_V02N0001 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 E3_H06W0103 +arc: S1_V02S0201 W1_H02E0201 +arc: S1_V02S0601 H06W0303 +arc: V00B0000 V02N0201 +arc: V00T0000 H02W0001 +arc: W1_H02W0101 E1_H02W0001 +arc: W1_H02W0301 E1_H01W0100 +arc: W1_H02W0601 V02N0601 +arc: A2 W1_H02E0501 +arc: A3 V00T0000 +arc: A4 H02W0701 +arc: A5 H02W0501 +arc: A6 V02S0301 +arc: B0 S1_V02N0101 +arc: B2 E1_H01W0100 +arc: B3 H00R0100 +arc: B4 S1_V02N0701 +arc: B7 H02W0101 +arc: CE0 H00R0000 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 F4 +arc: E1_H02E0101 F3 +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0100 Q0 +arc: M0 V00B0000 +arc: MUXCLK0 CLK0 +arc: N1_V02N0201 Q0 +arc: N1_V02N0701 F7 +arc: N3_V06N0303 F6 +arc: V01S0100 Q0 +arc: W1_H02W0201 Q0 +arc: W1_H02W0701 F5 +word: SLICED.K0.INIT 1010101010100000 +word: SLICEC.K1.INIT 1010101010100000 +word: SLICEC.K0.INIT 0110011001101100 +word: SLICEB.K1.INIT 0110011001101100 +word: SLICEB.K0.INIT 0110011001101010 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +word: SLICED.K1.INIT 1100110011000000 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C34:PLC2 +arc: E1_H02E0201 E1_H01W0000 +arc: E1_H02E0301 V02S0301 +arc: E1_H02E0501 W1_H02E0401 +arc: E1_H02E0701 V06S0203 +arc: E3_H06E0203 W1_H02E0701 +arc: H00R0100 H02W0701 +arc: N1_V02N0101 E1_H01W0100 +arc: N1_V02N0201 H06W0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0001 H06W0003 +arc: S1_V02S0201 H06E0103 +arc: S1_V02S0301 E1_H01W0100 +arc: S1_V02S0601 H06W0303 +arc: V00B0000 V02N0001 +arc: W1_H02W0101 V06S0103 +arc: W1_H02W0301 V02S0301 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0601 V01N0001 +arc: W1_H02W0701 N1_V02S0701 +arc: A4 W1_H02E0701 +arc: A5 V02N0301 +arc: A6 H02E0501 +arc: A7 V02S0101 +arc: B0 H02W0301 +arc: B4 H02E0301 +arc: B5 V02N0501 +arc: B6 E1_H02W0301 +arc: C4 N1_V02S0201 +arc: C5 S1_V02N0001 +arc: C6 V02N0201 +arc: CE0 H00R0100 +arc: CE3 H02W0101 +arc: CLK0 G_HPBX0000 +arc: D4 N1_V02S0401 +arc: D5 W1_H02E0001 +arc: D6 V02N0401 +arc: D7 H02E0201 +arc: E1_H01E0001 F7 +arc: E1_H02E0001 F0 +arc: E1_H02E0401 F4 +arc: E1_H02E0601 F4 +arc: E3_H06E0303 Q5 +arc: F0 F0_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 Q6 +arc: H01W0000 Q0 +arc: H01W0100 Q1 +arc: M0 V00B0000 +arc: M1 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: V01S0000 Q5 +arc: V01S0100 Q5 +arc: W1_H02W0001 Q0 +word: SLICED.K1.INIT 0101010100000000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICED.K0.INIT 1010101010111000 +word: SLICEC.K0.INIT 0000000000000001 +word: SLICEA.K0.INIT 1100110011000000 +word: SLICEC.K1.INIT 0000000010000000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 1 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ + +.tile R6C35:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0201 V06S0103 +arc: E1_H02E0401 V01N0001 +arc: E1_H02E0501 N1_V01S0100 +arc: E1_H02E0701 V02S0701 +arc: H00L0000 N1_V02S0201 +arc: H00R0100 W1_H02E0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0401 N1_V01S0000 +arc: N1_V02N0601 H02W0601 +arc: S1_V02S0201 H02W0201 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0601 H06E0303 +arc: S1_V02S0701 V01N0101 +arc: V00B0100 V02S0101 +arc: W1_H02W0101 N1_V02S0101 +arc: W1_H02W0301 V06S0003 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 E1_H02W0501 +arc: A3 F7 +arc: A4 H02E0701 +arc: A5 H02E0701 +arc: A6 H02E0501 +arc: B0 S1_V02N0301 +arc: B3 H00R0100 +arc: B4 E1_H02W0101 +arc: B5 E1_H02W0101 +arc: B6 W1_H02E0101 +arc: B7 N1_V01S0000 +arc: C0 H00L0100 +arc: C1 H00L0000 +arc: C3 N1_V02S0401 +arc: C4 V02N0001 +arc: C5 V02N0001 +arc: C6 W1_H02E0601 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 V02S0001 +arc: D3 V00T0100 +arc: D4 H02E0001 +arc: D5 H02E0001 +arc: D7 W1_H02E0001 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 F0 +arc: E1_H02E0001 F2 +arc: E1_H02E0301 Q1 +arc: E1_H02E0601 Q6 +arc: E3_H06E0103 Q1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q3 +arc: H00R0000 F4 +arc: H01W0000 Q3 +arc: H01W0100 Q1 +arc: LSR0 H02E0301 +arc: LSR1 H02E0301 +arc: M1 H02W0001 +arc: M2 V00B0100 +arc: M3 E1_H02W0201 +arc: M4 W1_H02E0401 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V02N0201 F2 +arc: S1_V02S0001 Q0 +arc: V00T0100 F1 +arc: V01S0000 F2 +arc: V01S0100 Q1 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 0000000000110000 +word: SLICEC.K0.INIT 1111111000000010 +word: SLICEC.K1.INIT 1111101010001010 +word: SLICED.K0.INIT 1110010011100100 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEB.K1.INIT 0000000001000001 +word: SLICEA.K1.INIT 0000111100000000 +word: SLICED.K1.INIT 0000000011001100 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R6C36:PLC2 +arc: E1_H02E0101 V06S0103 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0301 H01E0101 +arc: E1_H02E0401 V06S0203 +arc: E1_H02E0501 N1_V02S0501 +arc: E1_H02E0601 W1_H02E0601 +arc: H00L0000 E1_H02W0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 H06E0303 +arc: N1_V02N0601 V01N0001 +arc: N1_V02N0701 H02W0701 +arc: N3_V06N0303 E1_H01W0100 +arc: S1_V02S0201 E1_H02W0201 +arc: S1_V02S0601 H02E0601 +arc: V00B0000 H02W0401 +arc: V00B0100 N1_V02S0101 +arc: V00T0000 H02E0001 +arc: W1_H02W0001 E1_H02W0501 +arc: W1_H02W0201 V06S0103 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0601 V01N0001 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 F5 +arc: A1 H02E0701 +arc: A2 F5 +arc: A3 F5 +arc: A4 V02N0301 +arc: A6 F7 +arc: A7 H02E0501 +arc: B1 H00R0100 +arc: B5 H00L0000 +arc: B6 N1_V02S0501 +arc: B7 N1_V01S0000 +arc: C0 E1_H01W0000 +arc: C1 E1_H01W0000 +arc: C2 E1_H01W0000 +arc: C3 E1_H01W0000 +arc: C4 E1_H02W0601 +arc: C5 V01N0101 +arc: C6 W1_H02E0401 +arc: C7 V02S0001 +arc: CE2 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D1 H02E0201 +arc: D2 H02E0201 +arc: D3 H02E0201 +arc: D4 V00B0000 +arc: D5 V02N0601 +arc: D6 N1_V02S0401 +arc: D7 E1_H01W0100 +arc: E1_H01E0001 F1 +arc: E1_H01E0101 F7 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0100 F5 +arc: LSR0 V00B0100 +arc: M0 H01E0001 +arc: M1 H02W0001 +arc: M2 V00T0000 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR0 +arc: N1_V01N0001 F6 +arc: N1_V01N0101 Q4 +arc: N1_V02N0401 F6 +arc: S1_V02S0701 F5 +arc: V01S0100 F5 +word: SLICED.K0.INIT 1000000000000000 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICED.K1.INIT 0000000000000001 +word: SLICEC.K0.INIT 1111101011110000 +word: SLICEA.K0.INIT 0000111110101111 +word: SLICEA.K1.INIT 0000111101001111 +word: SLICEB.K0.INIT 0000111110101111 +word: SLICEB.K1.INIT 0000111110101111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.B1MUX 1 + +.tile R6C37:PLC2 +arc: E1_H02E0201 V02N0201 +arc: E1_H02E0601 W1_H02E0301 +arc: H00L0100 V02S0301 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0101 V01N0101 +arc: N1_V02N0201 E1_H01W0000 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 E1_H02W0401 +arc: N1_V02N0601 S1_V02N0301 +arc: N1_V02N0701 E1_H01W0100 +arc: N3_V06N0103 W3_H06E0103 +arc: S1_V02S0301 W1_H02E0301 +arc: S1_V02S0401 H02E0401 +arc: S1_V02S0601 E1_H01W0000 +arc: S1_V02S0701 H06E0203 +arc: V00B0000 W1_H02E0401 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0201 H01E0001 +arc: W1_H02W0301 V01N0101 +arc: W1_H02W0401 E1_H02W0401 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0103 V01N0101 +arc: W3_H06W0303 E1_H01W0100 +arc: A0 E1_H02W0701 +arc: A3 H02E0501 +arc: A4 V00B0000 +arc: A5 E1_H02W0701 +arc: A7 V00T0100 +arc: B0 H02E0301 +arc: B3 N1_V02S0101 +arc: B4 V00B0100 +arc: B5 V02S0501 +arc: B6 H02E0301 +arc: B7 W1_H02E0301 +arc: C0 W1_H02E0401 +arc: C3 H00R0100 +arc: C4 V02N0001 +arc: C5 W1_H02E0401 +arc: C6 V02N0201 +arc: C7 H02W0401 +arc: CE0 H00R0000 +arc: CE3 H02W0101 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0201 +arc: D2 V00B0100 +arc: D3 H01E0101 +arc: D4 V01N0001 +arc: D5 V02N0601 +arc: D7 V02N0401 +arc: E1_H01E0001 F7 +arc: E1_H01E0101 Q1 +arc: E1_H02E0401 F4 +arc: E1_H02E0701 F5 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00R0000 F6 +arc: H00R0100 F7 +arc: H01W0000 F0 +arc: H01W0100 Q7 +arc: M0 V00T0000 +arc: M1 H00L0100 +arc: M2 H02E0601 +arc: M7 E1_H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q1 +arc: N1_V01N0101 F5 +arc: N1_V02N0501 Q7 +arc: N3_V06N0303 F6 +arc: V00B0100 F7 +arc: V00T0000 F2 +arc: V00T0100 Q1 +arc: V01S0000 F7 +arc: W1_H02W0501 F5 +arc: W1_H02W0601 F6 +arc: W1_H02W0701 Q7 +word: SLICEB.K0.INIT 1111111100000000 +word: SLICEB.K1.INIT 0111000011110000 +word: SLICED.K0.INIT 0000110000001100 +word: SLICEC.K0.INIT 1111010111000100 +word: SLICED.K1.INIT 1111010000000000 +word: SLICEC.K1.INIT 0010001100100000 +word: SLICEA.K1.INIT 0000000000000000 +word: SLICEA.K0.INIT 0100110001011111 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ + +.tile R6C38:PLC2 +arc: E1_H02E0101 W1_H02E0101 +arc: E1_H02E0401 W1_H02E0401 +arc: H00R0000 H02E0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 N1_V01S0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0501 H01E0101 +arc: N1_V02N0601 H01E0001 +arc: N1_V02N0701 H01E0101 +arc: S1_V02S0001 E1_H01W0000 +arc: S1_V02S0101 H06E0103 +arc: S1_V02S0301 V01N0101 +arc: S1_V02S0701 N1_V01S0100 +arc: V00B0100 V02N0301 +arc: V00T0000 H02E0201 +arc: V00T0100 V02S0501 +arc: W1_H02W0101 V02N0101 +arc: W1_H02W0501 E1_H02W0501 +arc: W1_H02W0601 V01N0001 +arc: A0 F5 +arc: A2 F7 +arc: A3 F7 +arc: A5 V00B0000 +arc: A6 H02E0701 +arc: B0 V01N0001 +arc: B1 V00B0000 +arc: B2 V01N0001 +arc: B3 V02N0301 +arc: B5 N1_V01S0000 +arc: B6 F1 +arc: B7 F1 +arc: C0 H00L0000 +arc: C1 H02E0601 +arc: C3 H00L0000 +arc: C4 V00B0100 +arc: C5 N1_V02S0001 +arc: C6 V00B0100 +arc: C7 V02N0201 +arc: CE0 H00R0000 +arc: CE2 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H01E0101 +arc: D2 V00B0100 +arc: D3 V02N0201 +arc: D4 H02W0001 +arc: D5 H02W0001 +arc: D6 V02N0401 +arc: E1_H01E0001 Q4 +arc: E1_H01E0101 F2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H00L0000 Q0 +arc: H01W0000 F2 +arc: H01W0100 F2 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 N1_V01N0001 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 Q0 +arc: N1_V02N0201 F2 +arc: N1_V02N0401 F4 +arc: S1_V02S0201 F2 +arc: V00B0000 Q6 +arc: V01S0000 Q4 +arc: V01S0100 F7 +arc: W1_H02W0001 Q0 +arc: W1_H02W0201 F2 +arc: W1_H02W0401 Q6 +arc: W3_H06W0103 F2 +word: SLICEB.K0.INIT 0000000001000100 +word: SLICEB.K1.INIT 0001010100000100 +word: SLICEC.K0.INIT 0000000011110000 +word: SLICEA.K1.INIT 0011001100000011 +word: SLICEA.K0.INIT 1111111011001100 +word: SLICEC.K1.INIT 0000110000001010 +word: SLICED.K1.INIT 1100000011000000 +word: SLICED.K0.INIT 0011000100010001 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 1 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C39:PLC2 +arc: E1_H02E0101 V02N0101 +arc: N1_V02N0101 H01E0101 +arc: W1_H02W0001 H01E0001 +arc: W1_H02W0201 S1_V02N0201 +arc: W1_H02W0401 H01E0001 +arc: W1_H02W0701 V01N0101 +arc: B0 V02N0101 +arc: B2 V02N0101 +arc: C0 H02W0401 +arc: C2 N1_V01S0100 +arc: CE0 H02E0101 +arc: CE1 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D2 Q2 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: H01W0000 Q0 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: S1_V02S0001 Q0 +arc: S3_V06S0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEA.K0.INIT 1111110000110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R6C40:PLC2 +arc: H00R0000 W1_H02E0401 +arc: W1_H02W0401 V02S0401 +arc: W1_H02W0501 W3_H06E0303 +arc: B2 H02E0101 +arc: C2 V02S0401 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D2 Q2 +arc: F2 F2_SLICE +arc: MUXCLK1 CLK0 +arc: V01S0000 Q2 +word: SLICEB.K0.INIT 1111110000110000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 + +.tile R6C41:PLC2 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 + +.tile R7C30:PLC2 +arc: N1_V02N0301 E3_H06W0003 +arc: S1_V02S0301 E1_H02W0301 +arc: S1_V02S0601 H06W0303 + +.tile R7C31:PLC2 +arc: H00L0000 V02S0201 +arc: H00L0100 V02N0301 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0301 H02W0301 +arc: N1_V02N0501 E1_H02W0501 +arc: N1_V02N0601 H06W0303 +arc: V00B0000 V02N0001 +arc: V00B0100 V02S0101 +arc: A1 H00R0000 +arc: B1 V00B0000 +arc: B3 E1_H02W0101 +arc: B4 V02N0501 +arc: C0 V02S0401 +arc: C1 N1_V01S0100 +arc: C2 E1_H01W0000 +arc: C3 H02W0601 +arc: C4 Q4 +arc: CE0 H02W0101 +arc: CE1 H00R0100 +arc: CE2 H00L0100 +arc: CE3 H00R0100 +arc: CLK0 G_HPBX0000 +arc: D1 E1_H02W0201 +arc: D2 V00B0100 +arc: D3 V00B0100 +arc: D4 H01W0000 +arc: E1_H01E0101 Q2 +arc: E1_H02E0001 Q2 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: H01W0000 Q7 +arc: LSR1 H02W0301 +arc: M4 H02W0401 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q2 +arc: S1_V02S0101 F3 +arc: S1_V02S0401 F4 +arc: V01S0000 F1 +arc: V01S0100 Q0 +word: SLICEA.K0.INIT 0000111100001111 +word: SLICEB.K0.INIT 0000000011110000 +word: SLICEC.K0.INIT 1111001111000000 +word: SLICEB.K1.INIT 1111001111110000 +word: SLICEA.K1.INIT 1100010011000000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ + +.tile R7C32:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0301 N3_V06S0003 +arc: E1_H02E0601 N1_V01S0000 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02E0001 +arc: N1_V02N0301 N3_V06S0003 +arc: N1_V02N0501 H06W0303 +arc: N1_V02N0601 H06W0303 +arc: S1_V02S0001 N3_V06S0003 +arc: S1_V02S0301 H02W0301 +arc: V00B0000 V02N0001 +arc: V00T0000 V02S0601 +arc: W1_H02W0101 V01N0101 +arc: W1_H02W0301 N3_V06S0003 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0601 V02S0601 +arc: A5 N1_V01S0100 +arc: B0 V00B0000 +arc: B6 H01E0101 +arc: B7 N1_V01S0000 +arc: CE0 V02N0201 +arc: CLK0 G_HPBX0000 +arc: F6 F6_SLICE +arc: H01W0000 F6 +arc: LSR0 V00T0000 +arc: M0 H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +arc: V01S0000 Q0 +word: SLICED.K1.INIT 0011001100110000 +word: SLICED.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 0101010101010000 +word: SLICEC.K0.INIT 1111111111110000 +word: SLICEB.K1.INIT 1111111111110000 +word: SLICEB.K0.INIT 1111111111110000 +word: SLICEA.K1.INIT 1111111111111111 +word: SLICEA.K0.INIT 0000000000001100 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_1 NO +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 +enum: SLICED.D1MUX 1 +enum: SLICED.MODE CCU2 +enum: SLICED.CCU2.INJECT1_0 NO +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.D0MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_1 NO +enum: SLICEC.B1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEC.D1MUX 1 +enum: SLICEC.MODE CCU2 +enum: SLICEC.CCU2.INJECT1_0 NO +enum: SLICEC.A0MUX 1 +enum: SLICEC.B0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.D0MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 YES +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C33:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: E1_H02E0101 N1_V01S0100 +arc: E1_H02E0201 S1_V02N0201 +arc: E1_H02E0401 V01N0001 +arc: H00R0000 E1_H02W0601 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0401 H06W0203 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 N1_V02S0001 +arc: S1_V02S0301 H06W0003 +arc: S1_V02S0701 E1_H02W0701 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0301 E3_H06W0003 +arc: W1_H02W0501 E1_H01W0100 +arc: W1_H02W0601 V02S0601 +arc: W1_H02W0701 E1_H02W0601 +arc: W3_H06W0303 E1_H01W0100 +arc: A4 E1_H01W0000 +arc: A6 F5 +arc: B0 V00B0000 +arc: B4 V01S0000 +arc: B5 H02E0101 +arc: C4 V02S0201 +arc: C5 H02E0601 +arc: CE2 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D4 H00R0100 +arc: D5 W1_H02E0001 +arc: D6 V00B0000 +arc: E1_H01E0101 F6 +arc: E1_H02E0301 F1 +arc: E1_H02E0601 F6 +arc: E3_H06E0103 F1 +arc: F1 F1_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F6 F6_SLICE +arc: H00R0100 F5 +arc: LSR1 H02E0301 +arc: MUXCLK2 CLK0 +arc: MUXLSR2 LSR1 +arc: N1_V01N0001 F6 +arc: N1_V02N0601 F6 +arc: N3_V06N0103 F1 +arc: V00B0000 Q4 +arc: V01S0000 Q4 +arc: V01S0100 Q4 +arc: W1_H02W0401 F6 +word: SLICEB.K1.INIT 0000000000001110 +word: SLICEB.K0.INIT 0000000000000000 +word: SLICEA.K1.INIT 1111111111110000 +word: SLICEA.K0.INIT 0011001100110000 +word: SLICEC.K1.INIT 1100000000000000 +word: SLICED.K0.INIT 0000000010101010 +word: SLICEC.K0.INIT 0010001011001000 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_1 NO +enum: SLICEB.A1MUX 1 +enum: SLICEB.B1MUX 1 +enum: SLICEB.C1MUX 1 +enum: SLICEB.D1MUX 1 +enum: SLICEB.MODE CCU2 +enum: SLICEB.CCU2.INJECT1_0 NO +enum: SLICEB.A0MUX 1 +enum: SLICEB.B0MUX 1 +enum: SLICEB.C0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_1 NO +enum: SLICEA.A1MUX 1 +enum: SLICEA.B1MUX 1 +enum: SLICEA.C1MUX 1 +enum: SLICEA.D1MUX 1 +enum: SLICEA.MODE CCU2 +enum: SLICEA.CCU2.INJECT1_0 NO +enum: SLICEA.A0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C34:PLC2 +arc: E1_H02E0001 N1_V01S0000 +arc: H00L0000 H02W0201 +arc: H00R0000 N1_V02S0401 +arc: H00R0100 E1_H02W0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0401 H06W0203 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 N1_V01S0000 +arc: S1_V02S0701 H02W0701 +arc: V00T0000 H02E0001 +arc: A1 E1_H01E0001 +arc: A2 H02W0501 +arc: A4 N1_V01S0100 +arc: A6 V00T0100 +arc: A7 Q7 +arc: B1 W1_H02E0301 +arc: B2 H02E0301 +arc: B3 V02S0301 +arc: B4 W1_H02E0301 +arc: B6 E1_H02W0101 +arc: B7 E1_H02W0301 +arc: C0 N1_V01N0001 +arc: C1 H02E0401 +arc: C3 H00L0000 +arc: C4 Q4 +arc: C6 V00B0100 +arc: C7 V00T0000 +arc: CE0 H00R0000 +arc: CE1 H00R0100 +arc: CE3 N1_V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 W1_H02E0001 +arc: D1 V02S0201 +arc: D2 Q2 +arc: D3 V01S0100 +arc: D4 H02W0001 +arc: D6 H02E0001 +arc: D7 H00L0100 +arc: E1_H01E0001 Q5 +arc: E1_H01E0101 Q4 +arc: E1_H02E0601 Q4 +arc: E1_H02E0701 Q5 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 Q1 +arc: H01W0000 Q5 +arc: H01W0100 Q4 +arc: M0 H02E0601 +arc: M1 H00L0000 +arc: M5 V01S0000 +arc: M6 N1_V01N0101 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q5 +arc: N1_V01N0101 F3 +arc: N1_V02N0501 Q5 +arc: N1_V02N0701 Q5 +arc: S1_V02S0001 Q2 +arc: S1_V02S0401 Q4 +arc: S1_V02S0601 F6 +arc: V00B0100 Q7 +arc: V00T0100 Q1 +arc: V01S0000 F0 +arc: V01S0100 Q7 +arc: W3_H06W0303 Q5 +word: SLICEA.K1.INIT 0011001000000010 +word: SLICEA.K0.INIT 0000000011110000 +word: SLICEB.K1.INIT 1111001111000000 +word: SLICED.K0.INIT 1000100011000000 +word: SLICED.K1.INIT 1111101100111011 +word: SLICEB.K0.INIT 1110111000100010 +word: SLICEC.K0.INIT 1110111011111110 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ + +.tile R7C35:PLC2 +arc: E1_H02E0201 W1_H02E0201 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V01S0000 +arc: E1_H02E0701 N1_V02S0701 +arc: H00L0000 V02S0001 +arc: H00L0100 H02W0101 +arc: H00R0000 V02S0401 +arc: H00R0100 H02E0701 +arc: N1_V02N0001 H01E0001 +arc: N1_V02N0201 S1_V02N0201 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0701 E1_H01W0100 +arc: S1_V02S0101 E1_H02W0101 +arc: S1_V02S0401 E1_H02W0401 +arc: S1_V02S0501 N1_V01S0100 +arc: S1_V02S0701 E1_H01W0100 +arc: V00T0100 N1_V02S0501 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 E1_H02W0201 +arc: W1_H02W0501 N1_V02S0501 +arc: W1_H02W0701 N1_V01S0100 +arc: A0 V02S0701 +arc: A2 H00L0100 +arc: A6 F7 +arc: A7 H00L0000 +arc: B0 W1_H02E0301 +arc: B1 E1_H02W0101 +arc: B2 W1_H02E0101 +arc: B3 E1_H02W0101 +arc: B4 F3 +arc: B7 H01E0101 +arc: C1 H02E0601 +arc: C2 E1_H02W0601 +arc: C3 N1_V01N0001 +arc: C4 V02N0001 +arc: C6 W1_H02E0601 +arc: C7 V02N0001 +arc: CE0 V02S0201 +arc: CE1 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H02E0001 +arc: D2 W1_H02E0201 +arc: D3 E1_H02W0001 +arc: D4 V02N0401 +arc: D6 H00R0100 +arc: D7 V02S0601 +arc: E1_H01E0001 Q4 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: M7 E1_H01W0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q4 +arc: N1_V01N0101 Q0 +arc: N1_V02N0101 F1 +arc: N1_V02N0401 F6 +arc: N1_V02N0601 F6 +arc: N3_V06N0003 F3 +arc: N3_V06N0303 F6 +arc: S1_V02S0001 Q0 +arc: V01S0000 Q7 +arc: V01S0100 Q7 +arc: W1_H02W0601 F6 +arc: W3_H06W0303 F6 +word: SLICEB.K0.INIT 1100110111001000 +word: SLICEA.K0.INIT 1011101110001000 +word: SLICEA.K1.INIT 0000000000000011 +word: SLICEB.K1.INIT 0011001100000011 +word: SLICEC.K0.INIT 1111001100110011 +word: SLICED.K0.INIT 0000101010101010 +word: SLICED.K1.INIT 1000100010110000 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 1 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C36:PLC2 +arc: E1_H02E0001 H01E0001 +arc: E1_H02E0101 S1_V02N0101 +arc: E1_H02E0401 H01E0001 +arc: H00R0100 H02W0701 +arc: N1_V02N0001 E1_H01W0000 +arc: N1_V02N0101 H06E0103 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0001 W1_H02E0001 +arc: S1_V02S0101 H02W0101 +arc: V00B0100 H02E0701 +arc: V00T0100 V02S0701 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A0 H02W0501 +arc: A1 H02W0501 +arc: A2 H02W0501 +arc: A3 H02W0501 +arc: A5 H02E0701 +arc: B0 H02W0101 +arc: B1 H02W0101 +arc: B2 H02W0101 +arc: B3 H02W0101 +arc: B4 H02W0101 +arc: B5 V02S0701 +arc: B6 H02W0101 +arc: B7 H02W0101 +arc: C1 N1_V01S0100 +arc: C5 S1_V02N0001 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 V00B0100 +arc: D2 V00T0100 +arc: D3 V00T0100 +arc: D4 V02N0601 +arc: D5 V02N0401 +arc: D6 V02N0401 +arc: D7 V02N0601 +arc: E1_H01E0001 Q3 +arc: E1_H02E0301 Q3 +arc: E3_H06E0003 Q3 +arc: F0 F5A_SLICE +arc: F1 FXA_SLICE +arc: F2 F5B_SLICE +arc: F4 F5C_SLICE +arc: F5 FXC_SLICE +arc: F6 F5D_SLICE +arc: H00L0100 F1 +arc: H01W0000 F5 +arc: H01W0100 Q3 +arc: M0 H02E0601 +arc: M1 H00R0100 +arc: M2 H02E0601 +arc: M3 H00L0100 +arc: M4 H02E0401 +arc: M5 H00R0100 +arc: M6 H02E0401 +arc: MUXCLK1 CLK0 +arc: N1_V01N0001 Q3 +arc: N1_V01N0101 Q3 +arc: N1_V02N0301 Q3 +arc: N3_V06N0003 Q3 +arc: V01S0000 Q3 +arc: W1_H02W0101 Q3 +arc: W1_H02W0301 Q3 +arc: W3_H06W0003 Q3 +word: SLICEA.K0.INIT 0011001100010001 +word: SLICEA.K1.INIT 0001000100110001 +word: SLICEB.K0.INIT 0011001100010001 +word: SLICEB.K1.INIT 0011001100010001 +word: SLICEC.K0.INIT 0011001100000000 +word: SLICEC.K1.INIT 0000111100001000 +word: SLICED.K0.INIT 0011001100000000 +word: SLICED.K1.INIT 0011001100000000 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.C0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEC.C0MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.C0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.A1MUX 1 +enum: SLICED.C1MUX 1 + +.tile R7C37:PLC2 +arc: E1_H02E0101 N3_V06S0103 +arc: E1_H02E0401 N1_V02S0401 +arc: H00L0100 N1_V02S0101 +arc: H00R0000 V02S0401 +arc: H00R0100 N1_V02S0501 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0301 H02E0301 +arc: N1_V02N0401 E1_H01W0000 +arc: N1_V02N0601 H01E0001 +arc: N3_V06N0303 S1_V02N0501 +arc: S1_V02S0101 N3_V06S0103 +arc: S1_V02S0201 W1_H02E0201 +arc: V00B0100 E1_H02W0701 +arc: W1_H02W0001 E1_H02W0001 +arc: W1_H02W0101 N3_V06S0103 +arc: W1_H02W0401 N1_V02S0401 +arc: W1_H02W0601 E1_H01W0000 +arc: W1_H02W0701 N1_V02S0701 +arc: W3_H06W0203 E1_H01W0000 +arc: A3 E1_H01E0001 +arc: A7 E1_H01W0000 +arc: B0 E1_H02W0101 +arc: B1 V02N0101 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: B5 N1_V01S0000 +arc: C0 H00L0100 +arc: C1 H02E0401 +arc: C2 H00L0100 +arc: C7 H01E0001 +arc: CE0 H02E0101 +arc: CE1 H00R0000 +arc: CE3 N1_V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: D1 E1_H02W0001 +arc: D2 Q2 +arc: D3 V00B0100 +arc: D5 H00R0100 +arc: D7 H02E0001 +arc: E1_H01E0001 Q3 +arc: E1_H01E0101 F1 +arc: F0 F0_SLICE +arc: F1 F1_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H01W0000 F1 +arc: M7 H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 F7 +arc: N1_V01N0101 F1 +arc: N3_V06N0203 F7 +arc: S1_V02S0301 Q3 +arc: S1_V02S0501 Q7 +arc: S1_V02S0701 Q7 +arc: V01S0000 Q2 +arc: V01S0100 Q3 +arc: W1_H02W0201 Q0 +arc: W1_H02W0501 F5 +word: SLICEA.K0.INIT 1111110000110000 +word: SLICEC.K1.INIT 0000000000110011 +word: SLICEA.K1.INIT 0011000000000000 +word: SLICEB.K0.INIT 1111110000110000 +word: SLICEB.K1.INIT 1011101110001000 +word: SLICED.K1.INIT 0101010101010000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.C1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.A1MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.C1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 1 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C38:PLC2 +arc: H00L0000 V02S0001 +arc: H00R0100 V02S0701 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 W1_H02E0301 +arc: N1_V02N0401 N1_V01S0000 +arc: S1_V02S0301 W1_H02E0301 +arc: V00T0100 W1_H02E0301 +arc: W1_H02W0201 H01E0001 +arc: A0 H00R0000 +arc: A1 E1_H01E0001 +arc: A4 V02S0101 +arc: B0 H01W0100 +arc: B1 W1_H02E0301 +arc: B2 H02E0101 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C2 N1_V01S0100 +arc: C4 Q4 +arc: CE0 H00R0100 +arc: CE2 N1_V02S0601 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V00T0100 +arc: D1 H00R0000 +arc: D2 H01E0101 +arc: D4 E1_H02W0201 +arc: E1_H01E0001 Q6 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F4 F4_SLICE +arc: H00R0000 Q4 +arc: H01W0000 Q2 +arc: H01W0100 Q6 +arc: M0 V00B0000 +arc: M1 H00L0000 +arc: M4 E1_H02W0401 +arc: M6 E1_H02W0401 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q2 +arc: N1_V01N0101 F0 +arc: N1_V02N0001 Q2 +arc: N1_V02N0201 Q2 +arc: N3_V06N0103 Q2 +arc: V00B0000 F4 +arc: V01S0000 Q1 +arc: V01S0100 Q1 +word: SLICEC.K0.INIT 1111101001010000 +word: SLICEA.K0.INIT 1100101000000000 +word: SLICEA.K1.INIT 1011111110110011 +word: SLICEB.K0.INIT 1111111100110000 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C39:PLC2 +arc: N1_V02N0001 H06E0003 +arc: N1_V02N0101 W3_H06E0103 +arc: N1_V02N0201 W3_H06E0103 +arc: N1_V02N0601 S1_V02N0301 +arc: S1_V02S0101 W1_H02E0101 +arc: V00B0100 V02N0101 +arc: V00T0000 V02N0401 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0101 W3_H06E0103 +arc: W1_H02W0701 N1_V02S0701 +arc: A0 V02N0501 +arc: B0 V00B0000 +arc: C0 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H01E0101 Q1 +arc: F0 F0_SLICE +arc: H00L0000 Q2 +arc: H00L0100 Q3 +arc: H00R0000 Q6 +arc: H00R0100 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M1 H00L0100 +arc: M2 V00T0000 +arc: M3 H00R0100 +arc: M4 E1_H01E0101 +arc: M5 V01S0000 +arc: M6 V00T0100 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0101 Q0 +arc: S1_V02S0001 Q0 +arc: S1_V02S0401 Q4 +arc: V00B0000 Q4 +arc: V01S0000 Q7 +arc: W1_H02W0001 Q0 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0110100110010110 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET SET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R7C40:PLC2 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0401 N1_V01S0000 + +.tile R8C12:PLC2 +arc: W3_H06W0103 E3_H06W0003 +arc: W3_H06W0203 E3_H06W0103 + +.tile R8C13:PLC2 +arc: E3_H06E0103 W3_H06E0003 + +.tile R8C18:PLC2 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 + +.tile R8C19:PLC2 +arc: E3_H06E0103 W3_H06E0103 + +.tile R8C24:PLC2 +arc: W3_H06W0003 E3_H06W0003 +arc: W3_H06W0103 E3_H06W0103 + +.tile R8C25:PLC2 +arc: E3_H06E0203 W3_H06E0103 + +.tile R8C28:PLC2 +arc: E1_H02E0501 E3_H06W0303 + +.tile R8C30:PLC2 +arc: E1_H02E0401 E3_H06W0203 +arc: E1_H02E0601 V02S0601 +arc: V00B0100 V02S0301 +arc: A0 W1_H02E0501 +arc: B0 E1_H02W0101 +arc: C0 E1_H02W0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 Q2 +arc: F0 F0_SLICE +arc: LSR0 V00B0100 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXLSR0 LSR0 +arc: MUXLSR1 LSR0 +arc: W3_H06W0003 Q0 +arc: W3_H06W0103 Q2 +word: SLICEA.K0.INIT 0110100110010110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C31:PLC2 +arc: E1_H02E0401 N1_V02S0401 +arc: E1_H02E0701 W3_H06E0203 +arc: N1_V02N0001 E1_H02W0001 +arc: N1_V02N0301 H06W0003 +arc: N1_V02N0501 H02W0501 +arc: S1_V02S0701 H02W0701 +arc: V00B0100 V02S0101 +arc: V00T0000 E1_H02W0201 +arc: A2 V00T0000 +arc: A3 V00T0000 +arc: A4 N1_V01S0100 +arc: B0 H02W0301 +arc: B2 E1_H02W0101 +arc: B3 E1_H02W0101 +arc: C0 H02E0601 +arc: C2 F4 +arc: C3 F4 +arc: C4 E1_H01E0101 +arc: CLK0 G_HPBX0000 +arc: D0 N1_V01S0000 +arc: D2 H02E0001 +arc: D3 H02E0201 +arc: D4 E1_H01W0100 +arc: E1_H01E0001 F2 +arc: E1_H01E0101 Q0 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: LSR0 V00B0100 +arc: M2 E1_H02W0601 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR0 +word: SLICEC.K0.INIT 1010101000001111 +word: SLICEA.K0.INIT 1111111111000000 +word: SLICEB.K0.INIT 1001011001101001 +word: SLICEB.K1.INIT 0110100110010110 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ + +.tile R8C32:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0101 N1_V02S0101 +arc: H00L0000 H02W0001 +arc: H00R0000 E1_H02W0401 +arc: N1_V02N0201 E1_H02W0201 +arc: N1_V02N0701 H06W0203 +arc: S1_V02S0001 H02W0001 +arc: S1_V02S0601 N1_V02S0601 +arc: V00B0000 N1_V02S0201 +arc: V00B0100 V02S0301 +arc: V00T0000 N1_V02S0601 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0301 N1_V02S0301 +arc: W1_H02W0601 H01E0001 +arc: A2 F5 +arc: A3 V00B0000 +arc: A4 F5 +arc: A7 F5 +arc: B2 V01N0001 +arc: B3 V02N0301 +arc: B4 N1_V01S0000 +arc: B7 E1_H02W0301 +arc: C2 W1_H02E0401 +arc: C3 N1_V01N0001 +arc: C5 H02E0401 +arc: CE0 H00R0000 +arc: CE1 E1_H02W0101 +arc: CE3 E1_H02W0101 +arc: CLK0 G_HPBX0000 +arc: D2 Q2 +arc: D3 F2 +arc: D4 N1_V02S0401 +arc: D5 E1_H02W0001 +arc: D7 H00R0100 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 F0 +arc: E3_H06E0303 F5 +arc: F0 F0_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: F7 F7_SLICE +arc: H00R0100 Q7 +arc: H01W0100 F5 +arc: LSR0 V00T0000 +arc: LSR1 V00T0000 +arc: M2 V00B0100 +arc: M7 H00L0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR3 LSR0 +arc: N1_V01N0001 F5 +arc: N1_V01N0101 F5 +arc: N1_V02N0001 F0 +arc: N3_V06N0303 F5 +arc: V01S0100 Q0 +arc: W1_H02W0401 F4 +arc: W1_H02W0501 F5 +arc: W1_H02W0701 F7 +word: SLICEB.K1.INIT 0011010111001010 +word: SLICEC.K1.INIT 1111111111110000 +word: SLICEA.K0.INIT 1111111111111111 +word: SLICED.K1.INIT 0110011011001100 +word: SLICEC.K0.INIT 1101110110001000 +word: SLICEB.K0.INIT 1001011000111100 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEC.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.C1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ + +.tile R8C33:PLC2 +arc: E1_H02E0001 N3_V06S0003 +arc: E1_H02E0101 N1_V02S0101 +arc: E1_H02E0401 W1_H02E0401 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 V02S0701 +arc: N1_V01N0001 N3_V06S0003 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 H01E0101 +arc: N1_V02N0301 H01E0101 +arc: N1_V02N0701 N1_V01S0100 +arc: S1_V02S0001 E1_H02W0001 +arc: S1_V02S0401 N1_V02S0101 +arc: S1_V02S0701 W1_H02E0701 +arc: V00B0100 E1_H02W0701 +arc: V00T0000 H02E0001 +arc: V00T0100 V02S0701 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0601 H01E0001 +arc: A0 E1_H02W0501 +arc: A1 E1_H02W0701 +arc: A2 V01N0101 +arc: A3 V01N0101 +arc: A6 N1_V02S0101 +arc: B0 V02S0301 +arc: B1 V02S0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 H00R0000 +arc: C0 S1_V02N0401 +arc: C1 S1_V02N0401 +arc: C2 E1_H02W0401 +arc: C3 E1_H02W0401 +arc: C4 V00T0100 +arc: C6 V00B0100 +arc: CE2 H02E0101 +arc: CE3 H02E0101 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D1 V02S0001 +arc: D2 V02S0001 +arc: D3 V02S0001 +arc: D4 E1_H02W0001 +arc: D6 H00R0100 +arc: E1_H01E0001 F6 +arc: E1_H01E0101 F2 +arc: F0 F5A_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: H00L0000 F0 +arc: H01W0100 Q7 +arc: LSR0 V00T0000 +arc: M0 H02W0601 +arc: M2 V00B0000 +arc: M4 E1_H01E0101 +arc: M7 H00L0000 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR2 LSR0 +arc: MUXLSR3 LSR0 +arc: V00B0000 F4 +arc: V01S0100 Q4 +word: SLICED.K0.INIT 1010101011110000 +word: SLICEA.K0.INIT 1100000010001000 +word: SLICEA.K1.INIT 1111001110111011 +word: SLICEC.K0.INIT 1111110000001100 +word: SLICEB.K0.INIT 1000100011000000 +word: SLICEB.K1.INIT 1011101111110011 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.B0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.A0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C34:PLC2 +arc: E1_H02E0001 V02S0001 +arc: E1_H02E0201 V02S0201 +arc: E1_H02E0401 V02S0401 +arc: H00L0000 N1_V02S0001 +arc: H00R0000 V02S0601 +arc: H00R0100 V02S0701 +arc: N1_V02N0001 H02E0001 +arc: V00B0100 V02S0101 +arc: V00T0000 W1_H02E0001 +arc: W1_H02W0001 E1_H01W0000 +arc: W1_H02W0101 E1_H01W0100 +arc: W1_H02W0201 E1_H01W0000 +arc: W1_H02W0401 E1_H01W0000 +arc: W1_H02W0601 H01E0001 +arc: W3_H06W0003 E1_H01W0000 +arc: W3_H06W0303 E1_H02W0501 +arc: A0 E1_H02W0701 +arc: A1 E1_H02W0701 +arc: B0 H02W0301 +arc: B1 H02W0301 +arc: B6 E1_H02W0101 +arc: C0 E1_H02W0401 +arc: C1 E1_H02W0601 +arc: C6 V02S0001 +arc: CE0 H00L0000 +arc: CE2 N1_V02S0601 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0001 +arc: D1 E1_H02W0001 +arc: D6 H00R0100 +arc: E1_H02E0301 Q3 +arc: F0 F5A_SLICE +arc: F6 F6_SLICE +arc: H01W0000 Q3 +arc: H01W0100 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00T0000 +arc: M0 V00B0000 +arc: M1 V01S0100 +arc: M3 H02W0201 +arc: M5 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR0 +arc: MUXLSR2 LSR1 +arc: V00B0000 F6 +arc: V01S0100 F0 +arc: W1_H02W0301 Q1 +word: SLICED.K0.INIT 1111000011001100 +word: SLICEA.K0.INIT 1100000010100000 +word: SLICEA.K1.INIT 1100111110101111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C35:PLC2 +arc: H00L0000 N1_V02S0001 +arc: H00L0100 W1_H02E0101 +arc: H00R0000 E1_H02W0401 +arc: H00R0100 E1_H02W0501 +arc: N1_V02N0001 W1_H02E0001 +arc: N1_V02N0301 E1_H01W0100 +arc: N1_V02N0401 W1_H02E0401 +arc: S1_V02S0001 W1_H02E0001 +arc: V00T0000 H02E0001 +arc: V00T0100 N1_V02S0701 +arc: W1_H02W0001 V02S0001 +arc: W1_H02W0201 N1_V01S0000 +arc: A0 V02S0701 +arc: A1 V02S0701 +arc: A4 N1_V01S0100 +arc: A7 H00L0000 +arc: B0 V01N0001 +arc: B1 V01N0001 +arc: B2 V02S0101 +arc: B3 H02E0301 +arc: B4 H02E0301 +arc: B6 V02S0501 +arc: C0 V02S0401 +arc: C1 V02S0401 +arc: C2 F4 +arc: C3 N1_V01S0100 +arc: C4 V02N0001 +arc: C6 V00B0100 +arc: C7 H02E0401 +arc: CE0 H00R0100 +arc: CE2 H00R0000 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 V00B0100 +arc: D1 V00B0100 +arc: D3 V02N0001 +arc: D6 E1_H02W0001 +arc: D7 H02E0201 +arc: E1_H01E0001 F3 +arc: E1_H01E0101 Q6 +arc: E1_H02E0001 Q2 +arc: E1_H02E0201 F0 +arc: E1_H02E0401 F4 +arc: E1_H02E0501 F7 +arc: E1_H02E0601 F4 +arc: F0 F5A_SLICE +arc: F2 F2_SLICE +arc: F3 F3_SLICE +arc: F4 F4_SLICE +arc: F6 F6_SLICE +arc: F7 F7_SLICE +arc: H01W0000 Q2 +arc: H01W0100 F4 +arc: M0 V00B0000 +arc: M1 H02E0001 +arc: M4 V00T0100 +arc: M5 H00L0100 +arc: M6 V00T0000 +arc: M7 E1_H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N3_V06N0103 Q2 +arc: N3_V06N0203 F4 +arc: V00B0000 F6 +arc: V00B0100 Q7 +arc: W1_H02W0301 Q1 +arc: W1_H02W0401 Q4 +arc: W1_H02W0501 Q5 +arc: W1_H02W0701 Q5 +arc: W3_H06W0203 F4 +word: SLICED.K1.INIT 1010111110100000 +word: SLICEA.K0.INIT 1000101010000000 +word: SLICEA.K1.INIT 1101111111010101 +word: SLICEB.K0.INIT 0011000000110000 +word: SLICEB.K1.INIT 0011000011110000 +word: SLICEC.K0.INIT 1000000010000000 +word: SLICED.K0.INIT 1111110000110000 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.A0MUX 1 +enum: SLICEB.D0MUX 1 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 1 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.A1MUX 1 +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.D0MUX 1 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C36:PLC2 +arc: E1_H02E0001 V06S0003 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 N1_V01S0000 +arc: E1_H02E0601 N1_V02S0601 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 H02W0301 +arc: H00R0000 H02E0401 +arc: H00R0100 H02E0501 +arc: N1_V02N0401 H01E0001 +arc: N1_V02N0601 H01E0001 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 V06S0003 +arc: W1_H02W0101 H01E0101 +arc: W1_H02W0401 N1_V01S0000 +arc: W1_H02W0601 N1_V01S0000 +arc: W1_H02W0701 H01E0101 +arc: A5 Q5 +arc: C5 E1_H02W0601 +arc: CE0 H00R0100 +arc: CE2 H00R0000 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: D5 E1_H01W0100 +arc: F0 F0_SLICE +arc: F5 F5_SLICE +arc: H01W0100 Q0 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M5 H00L0100 +arc: M7 H02E0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: W1_H02W0501 F5 +arc: W3_H06W0203 Q7 +word: SLICEA.K0.INIT 0000000011111111 +word: SLICEC.K1.INIT 0101111110100000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.B0MUX 1 +enum: SLICEA.C0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.B1MUX 1 + +.tile R8C37:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0601 V06S0303 +arc: E1_H02E0701 E1_H01W0100 +arc: H00L0000 W1_H02E0001 +arc: H00R0000 W1_H02E0601 +arc: H00R0100 N1_V02S0701 +arc: N1_V02N0101 H02E0101 +arc: N1_V02N0301 E1_H01W0100 +arc: S1_V02S0201 N1_V01S0000 +arc: V00B0000 V02S0201 +arc: V00B0100 V02S0101 +arc: W1_H02W0001 N1_V01S0000 +arc: W1_H02W0201 N1_V01S0000 +arc: W1_H02W0301 E1_H02W0201 +arc: W1_H02W0401 V06S0203 +arc: W1_H02W0501 V06S0303 +arc: A0 V02S0701 +arc: A1 V02S0501 +arc: A3 V01N0101 +arc: A7 H02W0501 +arc: B0 V02N0301 +arc: B1 V02N0101 +arc: B3 N1_V02S0301 +arc: C0 H02E0401 +arc: C1 H02E0401 +arc: C3 N1_V01S0100 +arc: C7 H02E0601 +arc: CE0 H00L0000 +arc: CE2 N1_V02S0601 +arc: CE3 H00R0000 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: D1 H02E0001 +arc: D7 H00L0100 +arc: E1_H01E0101 F7 +arc: E1_H02E0401 Q6 +arc: F0 F5A_SLICE +arc: F3 F3_SLICE +arc: F7 F7_SLICE +arc: H00L0100 Q1 +arc: H01W0100 Q4 +arc: LSR1 V00B0100 +arc: M0 V00T0100 +arc: M1 H00R0100 +arc: M4 V00T0000 +arc: M6 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR1 +arc: V00T0000 F0 +arc: V00T0100 F3 +word: SLICEB.K1.INIT 1110001011100010 +word: SLICEA.K0.INIT 1010000011000000 +word: SLICEA.K1.INIT 1010111111001111 +word: SLICED.K1.INIT 1111101001010000 +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICEB.D1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_1 _NONE_ +enum: SLICED.B1MUX 1 + +.tile R8C38:PLC2 +arc: H00L0000 N1_V02S0201 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 H02E0701 +arc: H01W0100 W3_H06E0303 +arc: N1_V02N0601 H02E0601 +arc: V00T0100 H02E0101 +arc: W1_H02W0501 W3_H06E0303 +arc: W1_H02W0601 W3_H06E0303 +arc: A0 F5 +arc: A2 V02N0501 +arc: A3 V02N0701 +arc: A4 N1_V02S0101 +arc: B0 V02N0301 +arc: B2 V02S0301 +arc: B3 V02S0301 +arc: B4 N1_V01S0000 +arc: B5 V00B0100 +arc: C0 N1_V01N0001 +arc: C2 N1_V01S0100 +arc: C3 N1_V01S0100 +arc: C5 H02E0401 +arc: CE3 H00L0000 +arc: CLK0 G_HPBX0000 +arc: D0 H01E0101 +arc: D2 W1_H02E0001 +arc: D3 W1_H02E0001 +arc: D4 H02W0001 +arc: D5 H00R0100 +arc: F0 F0_SLICE +arc: F2 F5B_SLICE +arc: F4 F4_SLICE +arc: F5 F5_SLICE +arc: LSR1 V00T0100 +arc: M2 V00B0000 +arc: M6 V00T0000 +arc: M7 H00L0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR3 LSR1 +arc: N1_V01N0001 Q6 +arc: V00B0000 F4 +arc: V00B0100 Q7 +arc: V00T0000 F2 +arc: V01S0100 Q0 +word: SLICEC.K1.INIT 0011110011001100 +word: SLICEA.K0.INIT 0110100110010110 +word: SLICEC.K0.INIT 1110111001000100 +word: SLICEB.K0.INIT 1000100011000000 +word: SLICEB.K1.INIT 1011101111110011 +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_1 _NONE_ +enum: SLICEC.A1MUX 1 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.MODE LOGIC +enum: SLICEC.CCU2.INJECT1_0 _NONE_ +enum: SLICEC.C0MUX 1 +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_0 _NONE_ +enum: SLICEB.MODE LOGIC +enum: SLICEB.CCU2.INJECT1_1 _NONE_ +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C39:PLC2 +arc: E1_H02E0101 V02S0101 +arc: E1_H02E0401 W1_H02E0101 +arc: H00L0100 H02W0101 +arc: N1_V02N0101 W1_H02E0101 +arc: N1_V02N0201 N3_V06S0103 +arc: N1_V02N0501 V01N0101 +arc: V00B0100 V02S0101 +arc: V00T0000 V02S0401 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0201 N3_V06S0103 +arc: CLK0 G_HPBX0000 +arc: E1_H01E0101 Q2 +arc: E1_H02E0501 Q7 +arc: H00R0000 Q6 +arc: H00R0100 Q5 +arc: LSR0 V00B0100 +arc: LSR1 V00B0100 +arc: M0 V00T0000 +arc: M2 V00T0100 +arc: M3 H00R0100 +arc: M4 E1_H01E0101 +arc: M5 H00L0100 +arc: M6 N1_V01N0101 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK1 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR1 LSR1 +arc: MUXLSR2 LSR1 +arc: MUXLSR3 LSR0 +arc: N1_V01N0101 Q0 +arc: N1_V02N0401 Q4 +arc: V00T0100 Q3 +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG0.SD 0 +enum: SLICEB.REG0.REGSET RESET +enum: SLICEB.REG0.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG0.SD 0 +enum: SLICED.REG0.REGSET RESET +enum: SLICED.REG0.LSRMODE LSR +enum: SLICED.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C3:PLC2 +arc: S3_V06S0203 H06W0203 +arc: S3_V06S0303 H06W0303 + +.tile R8C40:PLC2 +arc: H00R0100 H02E0501 +arc: V00B0000 H02E0401 +arc: V00T0100 H02E0101 +arc: CLK0 G_HPBX0000 +arc: LSR0 V00B0000 +arc: LSR1 V00T0100 +arc: M1 V01S0100 +arc: M5 H00R0100 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXLSR0 LSR1 +arc: MUXLSR2 LSR0 +arc: V01S0100 Q5 +arc: W1_H02W0101 Q1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG1.SD 0 +enum: SLICEA.REG1.REGSET RESET +enum: SLICEA.REG1.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG1.SD 0 +enum: SLICEC.REG1.REGSET RESET +enum: SLICEC.REG1.LSRMODE LSR +enum: SLICEC.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R8C6:PLC2 +arc: W3_H06W0203 E3_H06W0103 +arc: W3_H06W0303 E3_H06W0203 + +.tile R8C7:PLC2 +arc: E3_H06E0003 W3_H06E0303 + +.tile R9C13:PLC2 +arc: W3_H06W0203 E3_H06W0103 + +.tile R9C19:PLC2 +arc: W3_H06W0103 E3_H06W0103 + +.tile R9C25:PLC2 +arc: W3_H06W0103 E3_H06W0003 + +.tile R9C30:PLC2 +arc: B0 N1_V02S0301 +arc: C0 V02N0401 +arc: CLK0 G_HPBX0000 +arc: D0 E1_H02W0201 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: MUXCLK0 CLK0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C31:PLC2 +arc: E1_H02E0401 V06S0203 +arc: V00T0000 H02W0001 +arc: A0 V02S0701 +arc: B0 E1_H02W0101 +arc: C0 N1_V02S0401 +arc: CLK0 G_HPBX0000 +arc: D0 Q0 +arc: F0 F0_SLICE +arc: LSR1 V00T0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: W3_H06W0003 Q0 +word: SLICEA.K0.INIT 0110100110010110 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C32:PLC2 +arc: E1_H02E0001 N1_V02S0001 +arc: N1_V02N0301 N1_V01S0100 +arc: V00B0000 V02S0001 +arc: W1_H02W0001 N1_V02S0001 +arc: W1_H02W0201 E1_H01W0000 +arc: C6 H02E0401 +arc: CLK0 G_HPBX0000 +arc: D6 V02S0601 +arc: E1_H01E0101 F6 +arc: F6 F6_SLICE +arc: LSR1 H02W0501 +arc: M0 V00B0000 +arc: MUXCLK0 CLK0 +arc: MUXLSR0 LSR1 +arc: N1_V01N0001 Q0 +word: SLICED.K0.INIT 1111111100001111 +enum: SLICED.MODE LOGIC +enum: SLICED.CCU2.INJECT1_0 _NONE_ +enum: SLICED.A0MUX 1 +enum: SLICED.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 0 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C33:PLC2 +arc: E1_H01E0001 E3_H06W0003 +arc: H00R0000 V02S0401 +arc: H00R0100 V02S0701 +arc: V00B0000 V02S0001 +arc: W1_H02W0101 N1_V01S0100 +arc: W1_H02W0501 H01E0101 +arc: A0 E1_H01E0001 +arc: C0 H00R0100 +arc: CE2 V02N0601 +arc: CE3 V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 H02E0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: M4 V00B0000 +arc: M7 H00R0000 +arc: MUXCLK0 CLK0 +arc: MUXCLK2 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0101 Q4 +arc: N1_V02N0201 Q0 +arc: V01S0000 Q7 +word: SLICEA.K0.INIT 1111000010101010 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.B0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICEC.GSR DISABLED +enum: SLICEC.REG0.SD 0 +enum: SLICEC.REG0.REGSET RESET +enum: SLICEC.REG0.LSRMODE LSR +enum: SLICEC.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C34:PLC2 +arc: E1_H02E0101 N1_V02S0101 +arc: N1_V02N0201 H01E0001 +arc: N3_V06N0003 E1_H01W0000 + +.tile R9C35:PLC2 +arc: N1_V02N0001 H02W0001 +arc: B0 H02E0101 +arc: C0 V02N0601 +arc: CE3 S1_V02N0601 +arc: CLK0 G_HPBX0000 +arc: D0 V02S0001 +arc: E3_H06E0003 Q0 +arc: F0 F0_SLICE +arc: H01W0000 Q0 +arc: M7 E1_H02W0201 +arc: MUXCLK0 CLK0 +arc: MUXCLK3 CLK0 +arc: N1_V01N0001 Q7 +arc: N1_V02N0201 Q0 +arc: N3_V06N0003 Q0 +word: SLICEA.K0.INIT 1111001111000000 +enum: SLICEA.MODE LOGIC +enum: SLICEA.CCU2.INJECT1_0 _NONE_ +enum: SLICEA.A0MUX 1 +enum: SLICEA.GSR DISABLED +enum: SLICEA.REG0.SD 1 +enum: SLICEA.REG0.REGSET RESET +enum: SLICEA.REG0.LSRMODE LSR +enum: SLICEA.CEMUX 1 +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK +enum: SLICED.GSR DISABLED +enum: SLICED.REG1.SD 0 +enum: SLICED.REG1.REGSET RESET +enum: SLICED.REG1.LSRMODE LSR +enum: SLICED.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C36:PLC2 +arc: N1_V02N0001 H02W0001 +arc: N1_V02N0101 N3_V06S0103 +arc: N1_V02N0301 H06E0003 +arc: N3_V06N0003 W3_H06E0003 +arc: W1_H02W0001 W3_H06E0003 + +.tile R9C37:PLC2 +arc: H00L0100 N1_V02S0301 +arc: H00R0100 S1_V02N0701 +arc: N1_V02N0501 S1_V02N0401 +arc: W1_H02W0001 N3_V06S0003 +arc: W1_H02W0201 V02S0201 +arc: CE1 H00R0100 +arc: CLK0 G_HPBX0000 +arc: M3 H00L0100 +arc: MUXCLK1 CLK0 +arc: N1_V01N0101 Q3 +arc: N1_V02N0101 Q3 +arc: N1_V02N0301 Q3 +enum: SLICEB.GSR DISABLED +enum: SLICEB.REG1.SD 0 +enum: SLICEB.REG1.REGSET RESET +enum: SLICEB.REG1.LSRMODE LSR +enum: SLICEB.CEMUX CE +enum: LSR0.SRMODE LSR_OVER_CE +enum: LSR0.LSRMUX LSR +enum: LSR1.SRMODE LSR_OVER_CE +enum: LSR1.LSRMUX LSR +enum: CLK0.CLKMUX CLK + +.tile R9C38:PLC2 +arc: E3_H06E0303 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"CH0_FF_TXI_CLK": { + "direction": "input", + "bits": [ 14 ] + }, + "CH1_FF_TXI_CLK": { + "direction": "input", + "bits": [ 15 ] + }, + "CH0_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 16 ] + }, + "CH1_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 17 ] + }, + "CH0_FF_TX_D_0": { + "direction": "input", + "bits": [ 18 ] + }, + "CH1_FF_TX_D_0": { + "direction": "input", + "bits": [ 19 ] + }, + "CH0_FF_TX_D_1": { + "direction": "input", + "bits": [ 20 ] + }, + "CH1_FF_TX_D_1": { + "direction": "input", + "bits": [ 21 ] + }, + "CH0_FF_TX_D_2": { + "direction": "input", + "bits": [ 22 ] + }, + "CH1_FF_TX_D_2": { + "direction": "input", + "bits": [ 23 ] + }, + "CH0_FF_TX_D_3": { + "direction": "input", + "bits": [ 24 ] + }, + "CH1_FF_TX_D_3": { + "direction": "input", + "bits": [ 25 ] + }, + "CH0_FF_TX_D_4": { + "direction": "input", + "bits": [ 26 ] + }, + "CH1_FF_TX_D_4": { + "direction": "input", + "bits": [ 27 ] + }, + "CH0_FF_TX_D_5": { + "direction": "input", + "bits": [ 28 ] + }, + "CH1_FF_TX_D_5": { + "direction": "input", + "bits": [ 29 ] + }, + "CH0_FF_TX_D_6": { + "direction": "input", + "bits": [ 30 ] + }, + "CH1_FF_TX_D_6": { + "direction": "input", + "bits": [ 31 ] + }, + "CH0_FF_TX_D_7": { + "direction": "input", + "bits": [ 32 ] + }, + "CH1_FF_TX_D_7": { + "direction": "input", + "bits": [ 33 ] + }, + "CH0_FF_TX_D_8": { + "direction": "input", + "bits": [ 34 ] + }, + "CH1_FF_TX_D_8": { + "direction": "input", + "bits": [ 35 ] + }, + "CH0_FF_TX_D_9": { + "direction": "input", + "bits": [ 36 ] + }, + "CH1_FF_TX_D_9": { + "direction": "input", + "bits": [ 37 ] + }, + "CH0_FF_TX_D_10": { + "direction": "input", + "bits": [ 38 ] + }, + "CH1_FF_TX_D_10": { + "direction": "input", + "bits": [ 39 ] + }, + "CH0_FF_TX_D_11": { + "direction": "input", + "bits": [ 40 ] + }, + "CH1_FF_TX_D_11": { + "direction": "input", + "bits": [ 41 ] + }, + "CH0_FF_TX_D_12": { + "direction": "input", + "bits": [ 42 ] + }, + "CH1_FF_TX_D_12": { + "direction": "input", + "bits": [ 43 ] + }, + "CH0_FF_TX_D_13": { + "direction": "input", + "bits": [ 44 ] + }, + "CH1_FF_TX_D_13": { + "direction": "input", + "bits": [ 45 ] + }, + "CH0_FF_TX_D_14": { + "direction": "input", + "bits": [ 46 ] + }, + "CH1_FF_TX_D_14": { + "direction": "input", + "bits": [ 47 ] + }, + "CH0_FF_TX_D_15": { + "direction": "input", + "bits": [ 48 ] + }, + "CH1_FF_TX_D_15": { + "direction": "input", + "bits": [ 49 ] + }, + "CH0_FF_TX_D_16": { + "direction": "input", + "bits": [ 50 ] + }, + "CH1_FF_TX_D_16": { + "direction": "input", + "bits": [ 51 ] + }, + "CH0_FF_TX_D_17": { + "direction": "input", + "bits": [ 52 ] + }, + "CH1_FF_TX_D_17": { + "direction": "input", + "bits": [ 53 ] + }, + "CH0_FF_TX_D_18": { + "direction": "input", + "bits": [ 54 ] + }, + "CH1_FF_TX_D_18": { + "direction": "input", + "bits": [ 55 ] + }, + "CH0_FF_TX_D_19": { + "direction": "input", + "bits": [ 56 ] + }, + "CH1_FF_TX_D_19": { + "direction": "input", + "bits": [ 57 ] + }, + "CH0_FF_TX_D_20": { + "direction": "input", + "bits": [ 58 ] + }, + "CH1_FF_TX_D_20": { + "direction": "input", + "bits": [ 59 ] + }, + "CH0_FF_TX_D_21": { + "direction": "input", + "bits": [ 60 ] + }, + "CH1_FF_TX_D_21": { + "direction": "input", + "bits": [ 61 ] + }, + "CH0_FF_TX_D_22": { + "direction": "input", + "bits": [ 62 ] + }, + "CH1_FF_TX_D_22": { + "direction": "input", + "bits": [ 63 ] + }, + "CH0_FF_TX_D_23": { + "direction": "input", + "bits": [ 64 ] + }, + "CH1_FF_TX_D_23": { + "direction": "input", + "bits": [ 65 ] + }, + "CH0_FFC_EI_EN": { + "direction": "input", + "bits": [ 66 ] + }, + "CH1_FFC_EI_EN": { + "direction": "input", + "bits": [ 67 ] + }, + "CH0_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 68 ] + }, + "CH1_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 69 ] + }, + "CH0_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 70 ] + }, + "CH1_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 71 ] + }, + "CH0_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 72 ] + }, + "CH1_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 73 ] + }, + "CH0_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 74 ] + }, + "CH1_FFC_ENABLE_CGALIGN": { + "direction": "input", + "bits": [ 75 ] + }, + "CH0_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 76 ] + }, + "CH1_FFC_SIGNAL_DETECT": { + "direction": "input", + "bits": [ 77 ] + }, + "CH0_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 78 ] + }, + "CH1_FFC_FB_LOOPBACK": { + "direction": "input", + "bits": [ 79 ] + }, + "CH0_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 80 ] + }, + "CH1_FFC_SB_PFIFO_LP": { + "direction": "input", + "bits": [ 81 ] + }, + "CH0_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 82 ] + }, + "CH1_FFC_PFIFO_CLR": { + "direction": "input", + "bits": [ 83 ] + }, + "CH0_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 84 ] + }, + "CH1_FFC_RATE_MODE_RX": { + "direction": "input", + "bits": [ 85 ] + }, + "CH0_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 86 ] + }, + "CH1_FFC_RATE_MODE_TX": { + "direction": "input", + "bits": [ 87 ] + }, + "CH0_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 88 ] + }, + "CH1_FFC_DIV11_MODE_RX": { + "direction": "input", + "bits": [ 89 ] + }, + "CH0_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 90 ] + }, + "CH1_FFC_RX_GEAR_MODE": { + "direction": "input", + "bits": [ 91 ] + }, + "CH0_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 92 ] + }, + "CH1_FFC_TX_GEAR_MODE": { + "direction": "input", + "bits": [ 93 ] + }, + "CH0_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 94 ] + }, + "CH1_FFC_DIV11_MODE_TX": { + "direction": "input", + "bits": [ 95 ] + }, + "CH0_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 96 ] + }, + "CH1_FFC_LDR_CORE2TX_EN": { + "direction": "input", + "bits": [ 97 ] + }, + "CH0_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 98 ] + }, + "CH1_FFC_LANE_TX_RST": { + "direction": "input", + "bits": [ 99 ] + }, + "CH0_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 100 ] + }, + "CH1_FFC_LANE_RX_RST": { + "direction": "input", + "bits": [ 101 ] + }, + "CH0_FFC_RRST": { + "direction": "input", + "bits": [ 102 ] + }, + "CH1_FFC_RRST": { + "direction": "input", + "bits": [ 103 ] + }, + "CH0_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 104 ] + }, + "CH1_FFC_TXPWDNB": { + "direction": "input", + "bits": [ 105 ] + }, + "CH0_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 106 ] + }, + "CH1_FFC_RXPWDNB": { + "direction": "input", + "bits": [ 107 ] + }, + "CH0_LDR_CORE2TX": { + "direction": "input", + "bits": [ 108 ] + }, + "CH1_LDR_CORE2TX": { + "direction": "input", + "bits": [ 109 ] + }, + "D_SCIWDATA0": { + "direction": "input", + "bits": [ 110 ] + }, + "D_SCIWDATA1": { + "direction": "input", + "bits": [ 111 ] + }, + "D_SCIWDATA2": { + "direction": "input", + "bits": [ 112 ] + }, + "D_SCIWDATA3": { + "direction": "input", + "bits": [ 113 ] + }, + "D_SCIWDATA4": { + "direction": "input", + "bits": [ 114 ] + }, + "D_SCIWDATA5": { + "direction": "input", + "bits": [ 115 ] + }, + "D_SCIWDATA6": { + "direction": "input", + "bits": [ 116 ] + }, + "D_SCIWDATA7": { + "direction": "input", + "bits": [ 117 ] + }, + "D_SCIADDR0": { + "direction": "input", + "bits": [ 118 ] + }, + "D_SCIADDR1": { + "direction": "input", + "bits": [ 119 ] + }, + "D_SCIADDR2": { + "direction": "input", + "bits": [ 120 ] + }, + "D_SCIADDR3": { + "direction": "input", + "bits": [ 121 ] + }, + "D_SCIADDR4": { + "direction": "input", + "bits": [ 122 ] + }, + "D_SCIADDR5": { + "direction": "input", + "bits": [ 123 ] + }, + "D_SCIENAUX": { + "direction": "input", + "bits": [ 124 ] + }, + "D_SCISELAUX": { + "direction": "input", + "bits": [ 125 ] + }, + "CH0_SCIEN": { + "direction": "input", + "bits": [ 126 ] + }, + "CH1_SCIEN": { + "direction": "input", + "bits": [ 127 ] + }, + "CH0_SCISEL": { + "direction": "input", + "bits": [ 128 ] + }, + "CH1_SCISEL": { + "direction": "input", + "bits": [ 129 ] + }, + "D_SCIRD": { + "direction": "input", + "bits": [ 130 ] + }, + "D_SCIWSTN": { + "direction": "input", + "bits": [ 131 ] + }, + "D_CYAWSTN": { + "direction": "input", + "bits": [ 132 ] + }, + "D_FFC_SYNC_TOGGLE": { + "direction": "input", + "bits": [ 133 ] + }, + "D_FFC_DUAL_RST": { + "direction": "input", + "bits": [ 134 ] + }, + "D_FFC_MACRO_RST": { + "direction": "input", + "bits": [ 135 ] + }, + "D_FFC_MACROPDB": { + "direction": "input", + "bits": [ 136 ] + }, + "D_FFC_TRST": { + "direction": "input", + "bits": [ 137 ] + }, + "CH0_FFC_CDR_EN_BITSLIP": { + "direction": "input", + "bits": [ 138 ] + }, + "CH1_FFC_CDR_EN_BITSLIP": { + "direction": "input", + "bits": [ 139 ] + }, + "D_SCAN_ENABLE": { + "direction": "input", + "bits": [ 140 ] + }, + "D_SCAN_IN_0": { + "direction": "input", + "bits": [ 141 ] + }, + "D_SCAN_IN_1": { + "direction": "input", + "bits": [ 142 ] + }, + "D_SCAN_IN_2": { + "direction": "input", + "bits": [ 143 ] + }, + "D_SCAN_IN_3": { + "direction": "input", + "bits": [ 144 ] + }, + "D_SCAN_IN_4": { + "direction": "input", + "bits": [ 145 ] + }, + "D_SCAN_IN_5": { + "direction": "input", + "bits": [ 146 ] + }, + "D_SCAN_IN_6": { + "direction": "input", + "bits": [ 147 ] + }, + "D_SCAN_IN_7": { + "direction": "input", + "bits": [ 148 ] + }, + "D_SCAN_MODE": { + "direction": "input", + "bits": [ 149 ] + }, + "D_SCAN_RESET": { + "direction": "input", + "bits": [ 150 ] + }, + "D_CIN0": { + "direction": "input", + "bits": [ 151 ] + }, + "D_CIN1": { + "direction": "input", + "bits": [ 152 ] + }, + "D_CIN2": { + "direction": "input", + "bits": [ 153 ] + }, + "D_CIN3": { + "direction": "input", + "bits": [ 154 ] + }, + "D_CIN4": { + "direction": "input", + "bits": [ 155 ] + }, + "D_CIN5": { + "direction": "input", + "bits": [ 156 ] + }, + "D_CIN6": { + "direction": "input", + "bits": [ 157 ] + }, + "D_CIN7": { + "direction": "input", + "bits": [ 158 ] + }, + "D_CIN8": { + "direction": "input", + "bits": [ 159 ] + }, + "D_CIN9": { + "direction": "input", + "bits": [ 160 ] + }, + "D_CIN10": { + "direction": "input", + "bits": [ 161 ] + }, + "D_CIN11": { + "direction": "input", + "bits": [ 162 ] + }, + "CH0_HDOUTP": { + "direction": "output", + "bits": [ 163 ] + }, + "CH1_HDOUTP": { + "direction": "output", + "bits": [ 164 ] + }, + "CH0_HDOUTN": { + "direction": "output", + "bits": [ 165 ] + }, + "CH1_HDOUTN": { + "direction": "output", + "bits": [ 166 ] + }, + "D_TXBIT_CLKP_TO_ND": { + "direction": "output", + "bits": [ 167 ] + }, + "D_TXBIT_CLKN_TO_ND": { + "direction": "output", + "bits": [ 168 ] + }, + "D_SYNC_PULSE2ND": { + "direction": "output", + "bits": [ 169 ] + }, + "D_TXPLL_LOL_TO_ND": { + "direction": "output", + "bits": [ 170 ] + }, + "CH0_FF_RX_F_CLK": { + "direction": "output", + "bits": [ 171 ] + }, + "CH1_FF_RX_F_CLK": { + "direction": "output", + "bits": [ 172 ] + }, + "CH0_FF_RX_H_CLK": { + "direction": "output", + "bits": [ 173 ] + }, + "CH1_FF_RX_H_CLK": { + "direction": "output", + "bits": [ 174 ] + }, + "CH0_FF_TX_F_CLK": { + "direction": "output", + "bits": [ 175 ] + }, + "CH1_FF_TX_F_CLK": { + "direction": "output", + "bits": [ 176 ] + }, + "CH0_FF_TX_H_CLK": { + "direction": "output", + "bits": [ 177 ] + }, + "CH1_FF_TX_H_CLK": { + "direction": "output", + "bits": [ 178 ] + }, + "CH0_FF_RX_PCLK": { + "direction": "output", + "bits": [ 179 ] + }, + "CH1_FF_RX_PCLK": { + "direction": "output", + "bits": [ 180 ] + }, + "CH0_FF_TX_PCLK": { + "direction": "output", + "bits": [ 181 ] + }, + "CH1_FF_TX_PCLK": { + "direction": "output", + "bits": [ 182 ] + }, + "CH0_FF_RX_D_0": { + "direction": "output", + "bits": [ 183 ] + }, + "CH1_FF_RX_D_0": { + "direction": "output", + "bits": [ 184 ] + }, + "CH0_FF_RX_D_1": { + "direction": "output", + "bits": [ 185 ] + }, + "CH1_FF_RX_D_1": { + "direction": "output", + "bits": [ 186 ] + }, + "CH0_FF_RX_D_2": { + "direction": "output", + "bits": [ 187 ] + }, + "CH1_FF_RX_D_2": { + "direction": "output", + "bits": [ 188 ] + }, + "CH0_FF_RX_D_3": { + "direction": "output", + "bits": [ 189 ] + }, + "CH1_FF_RX_D_3": { + "direction": "output", + "bits": [ 190 ] + }, + "CH0_FF_RX_D_4": { + "direction": "output", + "bits": [ 191 ] + }, + "CH1_FF_RX_D_4": { + "direction": "output", + "bits": [ 192 ] + }, + "CH0_FF_RX_D_5": { + "direction": "output", + "bits": [ 193 ] + }, + "CH1_FF_RX_D_5": { + "direction": "output", + "bits": [ 194 ] + }, + "CH0_FF_RX_D_6": { + "direction": "output", + "bits": [ 195 ] + }, + "CH1_FF_RX_D_6": { + "direction": "output", + "bits": [ 196 ] + }, + "CH0_FF_RX_D_7": { + "direction": "output", + "bits": [ 197 ] + }, + "CH1_FF_RX_D_7": { + "direction": "output", + "bits": [ 198 ] + }, + "CH0_FF_RX_D_8": { + "direction": "output", + "bits": [ 199 ] + }, + "CH1_FF_RX_D_8": { + "direction": "output", + "bits": [ 200 ] + }, + "CH0_FF_RX_D_9": { + "direction": "output", + "bits": [ 201 ] + }, + "CH1_FF_RX_D_9": { + "direction": "output", + "bits": [ 202 ] + }, + "CH0_FF_RX_D_10": { + "direction": "output", + "bits": [ 203 ] + }, + "CH1_FF_RX_D_10": { + "direction": "output", + "bits": [ 204 ] + }, + "CH0_FF_RX_D_11": { + "direction": "output", + "bits": [ 205 ] + }, + "CH1_FF_RX_D_11": { + "direction": "output", + "bits": [ 206 ] + }, + "CH0_FF_RX_D_12": { + "direction": "output", + "bits": [ 207 ] + }, + "CH1_FF_RX_D_12": { + "direction": "output", + "bits": [ 208 ] + }, + "CH0_FF_RX_D_13": { + "direction": "output", + "bits": [ 209 ] + }, + "CH1_FF_RX_D_13": { + "direction": "output", + "bits": [ 210 ] + }, + "CH0_FF_RX_D_14": { + "direction": "output", + "bits": [ 211 ] + }, + "CH1_FF_RX_D_14": { + "direction": "output", + "bits": [ 212 ] + }, + "CH0_FF_RX_D_15": { + "direction": "output", + "bits": [ 213 ] + }, + "CH1_FF_RX_D_15": { + "direction": "output", + "bits": [ 214 ] + }, + "CH0_FF_RX_D_16": { + "direction": "output", + "bits": [ 215 ] + }, + "CH1_FF_RX_D_16": { + "direction": "output", + "bits": [ 216 ] + }, + "CH0_FF_RX_D_17": { + "direction": "output", + "bits": [ 217 ] + }, + "CH1_FF_RX_D_17": { + "direction": "output", + "bits": [ 218 ] + }, + "CH0_FF_RX_D_18": { + "direction": "output", + "bits": [ 219 ] + }, + "CH1_FF_RX_D_18": { + "direction": "output", + "bits": [ 220 ] + }, + "CH0_FF_RX_D_19": { + "direction": "output", + "bits": [ 221 ] + }, + "CH1_FF_RX_D_19": { + "direction": "output", + "bits": [ 222 ] + }, + "CH0_FF_RX_D_20": { + "direction": "output", + "bits": [ 223 ] + }, + "CH1_FF_RX_D_20": { + "direction": "output", + "bits": [ 224 ] + }, + "CH0_FF_RX_D_21": { + "direction": "output", + "bits": [ 225 ] + }, + "CH1_FF_RX_D_21": { + "direction": "output", + "bits": [ 226 ] + }, + "CH0_FF_RX_D_22": { + "direction": "output", + "bits": [ 227 ] + }, + "CH1_FF_RX_D_22": { + "direction": "output", + "bits": [ 228 ] + }, + "CH0_FF_RX_D_23": { + "direction": "output", + "bits": [ 229 ] + }, + "CH1_FF_RX_D_23": { + "direction": "output", + "bits": [ 230 ] + }, + "CH0_FFS_PCIE_DONE": { + "direction": "output", + "bits": [ 231 ] + }, + "CH1_FFS_PCIE_DONE": { + "direction": "output", + "bits": [ 232 ] + }, + "CH0_FFS_PCIE_CON": { + "direction": "output", + "bits": [ 233 ] + }, + "CH1_FFS_PCIE_CON": { + "direction": "output", + "bits": [ 234 ] + }, + "CH0_FFS_RLOS": { + "direction": "output", + "bits": [ 235 ] + }, + "CH1_FFS_RLOS": { + "direction": "output", + "bits": [ 236 ] + }, + "CH0_FFS_LS_SYNC_STATUS": { + "direction": "output", + "bits": [ 237 ] + }, + "CH1_FFS_LS_SYNC_STATUS": { + "direction": "output", + "bits": [ 238 ] + }, + "CH0_FFS_CC_UNDERRUN": { + "direction": "output", + "bits": [ 239 ] + }, + "CH1_FFS_CC_UNDERRUN": { + "direction": "output", + "bits": [ 240 ] + }, + "CH0_FFS_CC_OVERRUN": { + "direction": "output", + "bits": [ 241 ] + }, + "CH1_FFS_CC_OVERRUN": { + "direction": "output", + "bits": [ 242 ] + }, + "CH0_FFS_RXFBFIFO_ERROR": { + "direction": "output", + "bits": [ 243 ] + }, + "CH1_FFS_RXFBFIFO_ERROR": { + "direction": "output", + "bits": [ 244 ] + }, + "CH0_FFS_TXFBFIFO_ERROR": { + "direction": "output", + "bits": [ 245 ] + }, + "CH1_FFS_TXFBFIFO_ERROR": { + "direction": "output", + "bits": [ 246 ] + }, + "CH0_FFS_RLOL": { + "direction": "output", + "bits": [ 247 ] + }, + "CH1_FFS_RLOL": { + "direction": "output", + "bits": [ 248 ] + }, + "CH0_FFS_SKP_ADDED": { + "direction": "output", + "bits": [ 249 ] + }, + "CH1_FFS_SKP_ADDED": { + "direction": "output", + "bits": [ 250 ] + }, + "CH0_FFS_SKP_DELETED": { + "direction": "output", + "bits": [ 251 ] + }, + "CH1_FFS_SKP_DELETED": { + "direction": "output", + "bits": [ 252 ] + }, + "CH0_LDR_RX2CORE": { + "direction": "output", + "bits": [ 253 ] + }, + "CH1_LDR_RX2CORE": { + "direction": "output", + "bits": [ 254 ] + }, + "D_SCIRDATA0": { + "direction": "output", + "bits": [ 255 ] + }, + "D_SCIRDATA1": { + "direction": "output", + "bits": [ 256 ] + }, + "D_SCIRDATA2": { + "direction": "output", + "bits": [ 257 ] + }, + "D_SCIRDATA3": { + "direction": "output", + "bits": [ 258 ] + }, + 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a/hardware/v2/synthesis/harness_memory_manager/yosys.log b/hardware/v2/synthesis/harness_memory_manager/yosys.log new file mode 100644 index 0000000..f3f96ae --- /dev/null +++ b/hardware/v2/synthesis/harness_memory_manager/yosys.log @@ -0,0 +1,2554 @@ + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2026 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) + +-- Parsing `hardware/v2/rtl/memory_manager.v' using frontend ` -vlog2k' -- + +1. Executing Verilog-2005 frontend: hardware/v2/rtl/memory_manager.v +Parsing Verilog input from `hardware/v2/rtl/memory_manager.v' to AST representation. +Storing AST representation for module `$abstract\memory_manager'. +Successfully finished Verilog frontend. + +-- Parsing `hardware/v2/rtl/prefetch_engine.v' using frontend ` -vlog2k' -- + +2. Executing Verilog-2005 frontend: hardware/v2/rtl/prefetch_engine.v +Parsing Verilog input from `hardware/v2/rtl/prefetch_engine.v' to AST representation. +Storing AST representation for module `$abstract\prefetch_engine'. +Successfully finished Verilog frontend. + +-- Parsing `hardware/v2/synthesis/harness_memory_manager.v' using frontend ` -vlog2k' -- + +3. Executing Verilog-2005 frontend: hardware/v2/synthesis/harness_memory_manager.v +Parsing Verilog input from `hardware/v2/synthesis/harness_memory_manager.v' to AST representation. +Storing AST representation for module `$abstract\harness_memory_manager'. +Successfully finished Verilog frontend. + +-- Running command `synth_ecp5 -json hardware/v2/synthesis/harness_memory_manager/top.json -top harness_memory_manager' -- + +4. Executing SYNTH_LATTICE pass. + +4.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Generating RTLIL representation for module `\L6MUX21'. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Generating RTLIL representation for module `\PFUMX'. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Generating RTLIL representation for module `\DPR16X4C'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\TRELLIS_FF'. +Generating RTLIL representation for module `\TRELLIS_IO'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\TRELLIS_COMB'. +Generating RTLIL representation for module `\VLO'. +Generating RTLIL representation for module `\VHI'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `\CCU2C'. +Generating RTLIL representation for module `\DP16KD'. +Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. +Generating RTLIL representation for module `\FD1P3AX'. +Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. +Generating RTLIL representation for module `\FD1P3AY'. +Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. +Generating RTLIL representation for module `\FD1P3BX'. +Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. +Generating RTLIL representation for module `\FD1P3DX'. +Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. +Generating RTLIL representation for module `\FD1P3IX'. +Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. +Generating RTLIL representation for module `\FD1P3JX'. +Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. +Generating RTLIL representation for module `\FD1S3AX'. +Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. +Generating RTLIL representation for module `\FD1S3AY'. +Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. +Generating RTLIL representation for module `\FD1S3BX'. +Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. +Generating RTLIL representation for module `\FD1S3DX'. +Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. +Generating RTLIL representation for module `\FD1S3IX'. +Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. +Generating RTLIL representation for module `\FD1S3JX'. +Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. +Generating RTLIL representation for module `\IFS1P3BX'. +Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. +Generating RTLIL representation for module `\IFS1P3DX'. +Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. +Generating RTLIL representation for module `\IFS1P3IX'. +Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. +Generating RTLIL representation for module `\IFS1P3JX'. +Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. +Generating RTLIL representation for module `\OFS1P3BX'. +Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. +Generating RTLIL representation for module `\OFS1P3DX'. +Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. +Generating RTLIL representation for module `\OFS1P3IX'. +Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. +Generating RTLIL representation for module `\OFS1P3JX'. +Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. +Generating RTLIL representation for module `\IB'. +Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. +Generating RTLIL representation for module `\IBPU'. +Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. +Generating RTLIL representation for module `\IBPD'. +Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. +Generating RTLIL representation for module `\OB'. +Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. +Generating RTLIL representation for module `\OBZ'. +Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. +Generating RTLIL representation for module `\OBZPU'. +Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. +Generating RTLIL representation for module `\OBZPD'. +Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. +Generating RTLIL representation for module `\OBCO'. +Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. +Generating RTLIL representation for module `\BB'. +Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. +Generating RTLIL representation for module `\BBPU'. +Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. +Generating RTLIL representation for module `\BBPD'. +Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. +Generating RTLIL representation for module `\ILVDS'. +Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +4.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. +Generating RTLIL representation for module `\GSR'. +Generating RTLIL representation for module `\PUR'. +Generating RTLIL representation for module `\SGSR'. +Generating RTLIL representation for module `\PDPW16KD'. +Generating RTLIL representation for module `\MULT18X18D'. +Generating RTLIL representation for module `\ALU54B'. +Generating RTLIL representation for module `\CLKDIVF'. +Generating RTLIL representation for module `\PCSCLKDIV'. +Generating RTLIL representation for module `\DCSC'. +Generating RTLIL representation for module `\DCCA'. +Generating RTLIL representation for module `\ECLKSYNCB'. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Generating RTLIL representation for module `\DELAYF'. +Generating RTLIL representation for module `\DELAYG'. +Generating RTLIL representation for module `\USRMCLK'. +Generating RTLIL representation for module `\DQSBUFM'. +Generating RTLIL representation for module `\DDRDLLA'. +Generating RTLIL representation for module `\DLLDELD'. +Generating RTLIL representation for module `\IDDRX1F'. +Generating RTLIL representation for module `\IDDRX2F'. +Generating RTLIL representation for module `\IDDR71B'. +Generating RTLIL representation for module `\IDDRX2DQA'. +Generating RTLIL representation for module `\ODDRX1F'. +Generating RTLIL representation for module `\ODDRX2F'. +Generating RTLIL representation for module `\ODDR71B'. +Generating RTLIL representation for module `\OSHX2A'. +Generating RTLIL representation for module `\TSHX2DQA'. +Generating RTLIL representation for module `\TSHX2DQSA'. +Generating RTLIL representation for module `\ODDRX2DQA'. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Generating RTLIL representation for module `\EHXPLLL'. +Generating RTLIL representation for module `\DTR'. +Generating RTLIL representation for module `\OSCG'. +Generating RTLIL representation for module `\EXTREFB'. +Generating RTLIL representation for module `\JTAGG'. +Generating RTLIL representation for module `\DCUA'. +Successfully finished Verilog frontend. + +4.3. Executing HIERARCHY pass (managing design hierarchy). + +4.4. Executing AST frontend in derive mode using pre-parsed AST for module `\harness_memory_manager'. +Generating RTLIL representation for module `\harness_memory_manager'. + +4.4.1. Analyzing design hierarchy.. +Top module: \harness_memory_manager +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 + +4.4.2. Executing AST frontend in derive mode using pre-parsed AST for module `\memory_manager'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 +Generating RTLIL representation for module `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager'. + +4.4.3. Analyzing design hierarchy.. +Top module: \harness_memory_manager +Used module: $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 + +4.4.4. Executing AST frontend in derive mode using pre-parsed AST for module `\prefetch_engine'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 +Generating RTLIL representation for module `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine'. + +4.4.5. Analyzing design hierarchy.. +Top module: \harness_memory_manager +Used module: $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager +Used module: $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine + +4.4.6. Analyzing design hierarchy.. +Top module: \harness_memory_manager +Used module: $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager +Used module: $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine +Removing unused module `$abstract\harness_memory_manager'. +Removing unused module `$abstract\prefetch_engine'. +Removing unused module `$abstract\memory_manager'. +Removed 3 unused modules. + +4.5. Executing PROC pass (convert processes to netlists). + +4.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +4.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed 1 dead cases from process $proc$hardware/v2/rtl/prefetch_engine.v:58$339 in module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine. +Marked 6 switch rules as full_case in process $proc$hardware/v2/rtl/prefetch_engine.v:58$339 in module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine. +Marked 6 switch rules as full_case in process $proc$hardware/v2/rtl/memory_manager.v:157$252 in module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager. +Marked 1 switch rules as full_case in process $proc$hardware/v2/synthesis/harness_memory_manager.v:63$231 in module harness_memory_manager. +Marked 1 switch rules as full_case in process $proc$hardware/v2/synthesis/harness_memory_manager.v:24$226 in module harness_memory_manager. +Removed a total of 1 dead cases. + +4.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 7 redundant assignments. +Promoted 16 assignments to connections. + +4.5.4. Executing PROC_INIT pass (extract init attributes). + +4.5.5. Executing PROC_ARST pass (detect async resets in processes). + +4.5.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +4.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'. + 1/20: $3$lookahead\tile_w$338[63:0]$368 + 2/20: $3$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:105$336[31:0]$367 + 3/20: $3$lookahead\tile_x$337[63:0]$353 + 4/20: $3$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:87$335[31:0]$352 + 5/20: $2$lookahead\tile_w$338[63:0]$351 + 6/20: $2$lookahead\tile_x$337[63:0]$350 + 7/20: $2$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:105$336[31:0]$349 + 8/20: $2$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:87$335[31:0]$348 + 9/20: $0\mem_req[0:0] + 10/20: $0\fetch_done[0:0] + 11/20: $1$lookahead\tile_w$338[63:0]$347 + 12/20: $1$lookahead\tile_x$337[63:0]$346 + 13/20: $1$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:105$336[31:0]$345 + 14/20: $1$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:87$335[31:0]$344 + 15/20: $0\byte_idx[3:0] + 16/20: $0\fetch_busy[0:0] + 17/20: $0\state[1:0] + 18/20: $0\mem_wdata[7:0] + 19/20: $0\mem_addr[22:0] + 20/20: $0\mem_wr[0:0] +Creating decoders for process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + 1/46: $5$lookahead\bank_ready$251[1:0]$306 + 2/46: $3$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:247$241[0:0]$305 + 3/46: $4$lookahead\bank_ready$251[1:0]$292 + 4/46: $3$lookahead\bank_ready$251[1:0]$291 + 5/46: $2$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:247$241[0:0]$290 + 6/46: $2$lookahead\bank_ready$251[1:0]$278 + 7/46: $2$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:183$240[0:0]$271 + 8/46: $2$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$277 + 9/46: $2$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_DATA[63:0]$276 + 10/46: $2$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_ADDR[0:0]$275 + 11/46: $2$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$274 + 12/46: $2$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_DATA[63:0]$273 + 13/46: $2$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_ADDR[0:0]$272 + 14/46: $1$lookahead\bank_ready$251[1:0]$270 + 15/46: $0\pf_start[0:0] + 16/46: $0\result_ready[0:0] + 17/46: $0\job_done[0:0] + 18/46: $1$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$269 + 19/46: $1$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_DATA[63:0]$268 + 20/46: $1$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_ADDR[0:0]$267 + 21/46: $1$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$266 + 22/46: $1$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_DATA[63:0]$265 + 23/46: $1$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_ADDR[0:0]$264 + 24/46: $1$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:247$241[0:0]$263 + 25/46: $1$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:183$240[0:0]$262 + 26/46: $0\wr_mem_wdata[7:0] + 27/46: $0\wr_mem_addr[22:0] + 28/46: $0\wr_mem_req[0:0] + 29/46: $0\pf_pending_bank[0:0] + 30/46: $0\pf_pending_w[22:0] + 31/46: $0\pf_pending_x[22:0] + 32/46: $0\pf_pending[0:0] + 33/46: $0\pf_target_bank[0:0] + 34/46: $0\pf_w_addr[22:0] + 35/46: $0\pf_x_addr[22:0] + 36/46: $0\current_bank[0:0] + 37/46: $0\tile_idx[15:0] + 38/46: $0\n_tiles_reg[15:0] + 39/46: $0\result_addr_reg[22:0] + 40/46: $0\w_base_reg[22:0] + 41/46: $0\x_base_reg[22:0] + 42/46: $0\state[2:0] + 43/46: $0\tile_last[0:0] + 44/46: $0\weight_data[63:0] + 45/46: $0\input_data[63:0] + 46/46: $0\operand_valid[0:0] +Creating decoders for process `\harness_memory_manager.$proc$hardware/v2/synthesis/harness_memory_manager.v:63$231'. + 1/1: $0\chk[7:0] +Creating decoders for process `\harness_memory_manager.$proc$hardware/v2/synthesis/harness_memory_manager.v:24$226'. + 1/1: $0\lfsr[31:0] + +4.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +4.5.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_req' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'. + created $dff cell `$procdff$1086' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_wr' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'. + created $dff cell `$procdff$1087' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_addr' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'. + created $dff cell `$procdff$1088' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_wdata' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'. + created $dff cell `$procdff$1089' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\state' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'. + created $dff cell `$procdff$1090' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\fetch_busy' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'. + created $dff cell `$procdff$1091' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\fetch_done' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'. + created $dff cell `$procdff$1092' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\tile_x' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'. + created $dff cell `$procdff$1093' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\tile_w' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'. + created $dff cell `$procdff$1094' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\byte_idx' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'. + created $dff cell `$procdff$1095' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:87$335' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'. + created $dff cell `$procdff$1096' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:105$336' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'. + created $dff cell `$procdff$1097' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$lookahead\tile_x$337' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'. + created $dff cell `$procdff$1098' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$lookahead\tile_w$338' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'. + created $dff cell `$procdff$1099' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\job_done' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1100' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\operand_valid' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1101' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\input_data' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1102' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\weight_data' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1103' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\tile_last' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1104' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\result_ready' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1105' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\state' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1106' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\x_base_reg' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1107' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\w_base_reg' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1108' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\result_addr_reg' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1109' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\n_tiles_reg' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1110' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\tile_idx' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1111' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\current_bank' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1112' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\bank_ready' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1113' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\pf_start' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1114' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\pf_x_addr' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1115' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\pf_w_addr' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1116' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\pf_target_bank' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1117' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\pf_pending' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1118' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\pf_pending_x' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1119' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\pf_pending_w' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1120' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\pf_pending_bank' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1121' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\wr_mem_req' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1122' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\wr_mem_addr' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1123' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.\wr_mem_wdata' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1124' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:183$240' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1125' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:247$241' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1126' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_ADDR' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1127' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_DATA' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1128' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1129' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_ADDR' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1130' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_DATA' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1131' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1132' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$lookahead\bank_ready$251' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. + created $dff cell `$procdff$1133' with positive edge clock. +Creating register for signal `\harness_memory_manager.\chk' using process `\harness_memory_manager.$proc$hardware/v2/synthesis/harness_memory_manager.v:63$231'. + created $dff cell `$procdff$1134' with positive edge clock. +Creating register for signal `\harness_memory_manager.\lfsr' using process `\harness_memory_manager.$proc$hardware/v2/synthesis/harness_memory_manager.v:24$226'. + created $dff cell `$procdff$1135' with positive edge clock. + +4.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +4.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 7 empty switches in `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'. +Removing empty process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$339'. +Found and cleaned up 14 empty switches in `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. +Removing empty process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$252'. +Found and cleaned up 1 empty switch in `\harness_memory_manager.$proc$hardware/v2/synthesis/harness_memory_manager.v:63$231'. +Removing empty process `harness_memory_manager.$proc$hardware/v2/synthesis/harness_memory_manager.v:63$231'. +Found and cleaned up 1 empty switch in `\harness_memory_manager.$proc$hardware/v2/synthesis/harness_memory_manager.v:24$226'. +Removing empty process `harness_memory_manager.$proc$hardware/v2/synthesis/harness_memory_manager.v:24$226'. +Cleaned up 23 empty switches. + +4.5.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine. + +Optimizing module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager. + +Optimizing module harness_memory_manager. + + +4.6. Executing CHECK pass (checking for obvious problems). +Checking module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine... +Checking module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager... +Checking module harness_memory_manager... +Found and reported 0 problems. + +4.7. Executing FLATTEN pass (flatten design). +Deleting now unused module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine. +Deleting now unused module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\memory_manager. + + +4.8. Executing TRIBUF pass. + +4.9. Executing DEMINOUT pass (demote inout ports to input or output). + +4.10. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + + +4.11. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. +Removed 47 unused cells and 312 unused wires. + + +4.12. Executing CHECK pass (checking for obvious problems). +Checking module harness_memory_manager... +Found and reported 0 problems. + +4.13. Executing OPT pass (performing simple optimizations). + +4.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + +4.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 391 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 316 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 313 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 312 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. + +Removed a total of 79 cells. + +4.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Replacing known input bits on port B of cell $flatten\dut.$procmux$811: { \lfsr [7:0] \lfsr [14:0] } -> { \lfsr [7:1] 1'1 \lfsr [14:1] 1'1 } + Replacing known input bits on port B of cell $flatten\dut.$procmux$837: \lfsr [22:0] -> { \lfsr [22:1] 1'1 } + Replacing known input bits on port B of cell $flatten\dut.$procmux$925: \lfsr [15:0] -> { \lfsr [15:1] 1'1 } + Replacing known input bits on port B of cell $flatten\dut.$procmux$939: { \lfsr [3:0] \lfsr [18:0] } -> { \lfsr [3:1] 1'1 \lfsr [18:1] 1'1 } + Replacing known input bits on port B of cell $flatten\dut.$procmux$953: { \lfsr [7:0] \lfsr [14:0] } -> { \lfsr [7:1] 1'1 \lfsr [14:1] 1'1 } + Replacing known input bits on port B of cell $flatten\dut.$procmux$967: \lfsr [22:0] -> { \lfsr [22:1] 1'1 } + Replacing known input bits on port B of cell $flatten\dut.$procmux$1063: \dut.operand_valid -> 1'1 + Replacing known input bits on port A of cell $flatten\dut.$procmux$1061: \dut.operand_valid -> 1'0 + Analyzing evaluation results. + dead port 2/2 on $mux $flatten\dut.$procmux$595. + dead port 1/2 on $mux $flatten\dut.$procmux$598. + dead port 2/2 on $mux $flatten\dut.$procmux$621. + dead port 1/2 on $mux $flatten\dut.$procmux$624. + dead port 1/2 on $mux $flatten\dut.$procmux$634. + dead port 1/2 on $mux $flatten\dut.$procmux$661. + dead port 1/2 on $mux $flatten\dut.$procmux$667. + dead port 1/2 on $mux $flatten\dut.$procmux$673. + dead port 1/2 on $mux $flatten\dut.$procmux$679. + dead port 1/2 on $mux $flatten\dut.$procmux$685. + dead port 1/2 on $mux $flatten\dut.$procmux$691. + dead port 1/2 on $mux $flatten\dut.\u_prefetch.$procmux$434. + dead port 1/2 on $mux $flatten\dut.\u_prefetch.$procmux$426. + dead port 1/2 on $mux $flatten\dut.\u_prefetch.$procmux$408. + dead port 2/2 on $mux $flatten\dut.\u_prefetch.$procmux$405. + dead port 1/2 on $mux $flatten\dut.\u_prefetch.$procmux$389. + dead port 2/2 on $mux $flatten\dut.\u_prefetch.$procmux$386. +Removed 17 multiplexer ports. + + +4.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_memory_manager. + Consolidated identical input bits for $mux cell $flatten\dut.$procmux$658: + Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$procmux$658_Y + New ports: A=1'0, B=1'1, Y=$flatten\dut.$procmux$658_Y [0] + New connections: $flatten\dut.$procmux$658_Y [63:1] = { $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] $flatten\dut.$procmux$658_Y [0] } + Consolidated identical input bits for $mux cell $flatten\dut.$procmux$676: + Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$flatten\dut.$procmux$676_Y + New ports: A=1'0, B=1'1, Y=$flatten\dut.$procmux$676_Y [0] + New connections: $flatten\dut.$procmux$676_Y [63:1] = { $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] $flatten\dut.$procmux$676_Y [0] } + New ctrl vector for $pmux cell $flatten\dut.\u_prefetch.$procmux$428: { $auto$opt_reduce.cc:137:opt_pmux$1141 $flatten\dut.\u_prefetch.$procmux$581_CMP } + New ctrl vector for $pmux cell $flatten\dut.\u_prefetch.$procmux$420: { $auto$opt_reduce.cc:137:opt_pmux$1143 $flatten\dut.\u_prefetch.$procmux$575_CMP } + Optimizing cells in module \harness_memory_manager. + Consolidated identical input bits for $mux cell $flatten\dut.$procmux$718: + Old ports: A=$flatten\dut.$2$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$277, B=64'0000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 + New ports: A=$flatten\dut.$procmux$658_Y [0], B=1'0, Y=$flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] + New connections: $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [63:1] = { $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] $flatten\dut.$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$243_EN[63:0]$260 [0] } + Consolidated identical input bits for $mux cell $flatten\dut.$procmux$727: + Old ports: A=$flatten\dut.$2$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$274, B=64'0000000000000000000000000000000000000000000000000000000000000000, Y=$flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 + New ports: A=$flatten\dut.$procmux$676_Y [0], B=1'0, Y=$flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] + New connections: $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [63:1] = { $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] $flatten\dut.$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$242_EN[63:0]$257 [0] } + Optimizing cells in module \harness_memory_manager. +Performed a total of 6 changes. + +4.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 297 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 294 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 292 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. + +Removed a total of 5 cells. + +4.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. +Removed 0 unused cells and 101 unused wires. + + +4.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + +4.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +4.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_memory_manager. +Performed a total of 0 changes. + +4.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 292 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Removed a total of 0 cells. + +4.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +4.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. + +4.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + +4.13.16. Finished fast OPT passes. (There is nothing left to do.) + +4.14. Executing FSM pass (extract and optimize FSM). + +4.14.1. Executing FSM_DETECT pass (finding FSMs in design). +Found FSM state register harness_memory_manager.dut.state. +Found FSM state register harness_memory_manager.dut.u_prefetch.state. +Not marking harness_memory_manager.dut.u_prefetch.mem_wdata as FSM state register: + Users of register don't seem to benefit from recoding. + +4.14.2. Executing FSM_EXTRACT pass (extracting FSM from design). +Extracting FSM `\dut.state' from module `\harness_memory_manager'. + found $dff cell for state register: $flatten\dut.$procdff$1106 + root of input selection tree: $flatten\dut.$0\state[2:0] + found reset state: 3'000 (guessed from mux tree) + found ctrl input: \rst + found ctrl input: $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:151$245_Y + found ctrl input: $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:151$244_Y + found ctrl input: $flatten\dut.$procmux$705_CMP + found ctrl input: $flatten\dut.$procmux$1012_CMP + found ctrl input: $flatten\dut.$procmux$1015_CMP + found ctrl input: $flatten\dut.$procmux$1076_CMP + found state code: 3'000 + found ctrl input: \lfsr [4] + found state code: 3'101 + found ctrl input: $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:284$334_Y + found state code: 3'100 + found ctrl input: $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:245$304_Y + found ctrl input: $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:252$317_Y + found state code: 3'011 + found ctrl input: $flatten\dut.$logic_or$hardware/v2/rtl/memory_manager.v:227$295_Y + found state code: 3'010 + found ctrl input: \lfsr [0] + found state code: 3'001 + found ctrl output: $flatten\dut.$procmux$1015_CMP + found ctrl output: $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:151$244_Y + found ctrl output: $flatten\dut.$procmux$705_CMP + found ctrl output: $flatten\dut.$procmux$1076_CMP + found ctrl output: $flatten\dut.$procmux$1012_CMP + found ctrl output: $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:151$245_Y + ctrl inputs: { $flatten\dut.$logic_or$hardware/v2/rtl/memory_manager.v:227$295_Y $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:245$304_Y $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:252$317_Y $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:284$334_Y \lfsr [4] \lfsr [0] \rst } + ctrl outputs: { $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:151$244_Y $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:151$245_Y $flatten\dut.$0\state[2:0] $flatten\dut.$procmux$705_CMP $flatten\dut.$procmux$1012_CMP $flatten\dut.$procmux$1015_CMP $flatten\dut.$procmux$1076_CMP } + transition: 3'000 7'-----00 -> 3'000 9'000000001 + transition: 3'000 7'-----10 -> 3'001 9'000010001 + transition: 3'000 7'------1 -> 3'000 9'000000001 + transition: 3'100 7'------0 -> 3'101 9'101010000 + transition: 3'100 7'------1 -> 3'000 9'100000000 + transition: 3'010 7'-0----0 -> 3'010 9'000100100 + transition: 3'010 7'-10---0 -> 3'010 9'000100100 + transition: 3'010 7'-11---0 -> 3'011 9'000110100 + transition: 3'010 7'------1 -> 3'000 9'000000100 + transition: 3'001 7'0-----0 -> 3'001 9'000010010 + transition: 3'001 7'1-----0 -> 3'010 9'000100010 + transition: 3'001 7'------1 -> 3'000 9'000000010 + transition: 3'101 7'----0-0 -> 3'101 9'011010000 + transition: 3'101 7'----1-0 -> 3'000 9'010000000 + transition: 3'101 7'------1 -> 3'000 9'010000000 + transition: 3'011 7'---0--0 -> 3'011 9'000111000 + transition: 3'011 7'---1--0 -> 3'100 9'001001000 + transition: 3'011 7'------1 -> 3'000 9'000001000 +Extracting FSM `\dut.u_prefetch.state' from module `\harness_memory_manager'. + found $dff cell for state register: $flatten\dut.\u_prefetch.$procdff$1090 + root of input selection tree: $flatten\dut.\u_prefetch.$0\state[1:0] + found reset state: 2'00 (guessed from mux tree) + found ctrl input: \rst + found ctrl input: $flatten\dut.\u_prefetch.$procmux$421_CMP + found ctrl input: $flatten\dut.\u_prefetch.$procmux$387_CMP + found ctrl input: $flatten\dut.\u_prefetch.$procmux$406_CMP + found ctrl input: $flatten\dut.\u_prefetch.$procmux$424_CMP + found state code: 2'00 + found ctrl input: \lfsr [4] + found ctrl input: $flatten\dut.\u_prefetch.$eq$hardware/v2/rtl/prefetch_engine.v:106$378_Y + found state code: 2'11 + found state code: 2'10 + found ctrl input: \dut.pf_start + found state code: 2'01 + found ctrl output: $flatten\dut.\u_prefetch.$procmux$421_CMP + found ctrl output: $flatten\dut.\u_prefetch.$procmux$387_CMP + found ctrl output: $flatten\dut.\u_prefetch.$procmux$406_CMP + found ctrl output: $flatten\dut.\u_prefetch.$procmux$424_CMP + ctrl inputs: { \dut.pf_start $flatten\dut.\u_prefetch.$eq$hardware/v2/rtl/prefetch_engine.v:106$378_Y \lfsr [4] \rst } + ctrl outputs: { $flatten\dut.\u_prefetch.$procmux$424_CMP $flatten\dut.\u_prefetch.$procmux$421_CMP $flatten\dut.\u_prefetch.$procmux$406_CMP $flatten\dut.\u_prefetch.$procmux$387_CMP $flatten\dut.\u_prefetch.$0\state[1:0] } + transition: 2'00 4'0--0 -> 2'00 6'100000 + transition: 2'00 4'1--0 -> 2'01 6'100001 + transition: 2'00 4'---1 -> 2'00 6'100000 + transition: 2'10 4'--00 -> 2'10 6'000110 + transition: 2'10 4'-010 -> 2'10 6'000110 + transition: 2'10 4'-110 -> 2'11 6'000111 + transition: 2'10 4'---1 -> 2'00 6'000100 + transition: 2'01 4'--00 -> 2'01 6'001001 + transition: 2'01 4'-010 -> 2'01 6'001001 + transition: 2'01 4'-110 -> 2'10 6'001010 + transition: 2'01 4'---1 -> 2'00 6'001000 + transition: 2'11 4'---0 -> 2'00 6'010000 + transition: 2'11 4'---1 -> 2'00 6'010000 + +4.14.3. Executing FSM_OPT pass (simple optimizations of FSMs). +Optimizing FSM `$fsm$\dut.u_prefetch.state$1152' from module `\harness_memory_manager'. + Merging pattern 4'---0 and 4'---1 from group (3 0 6'010000). + Merging pattern 4'---1 and 4'---0 from group (3 0 6'010000). +Optimizing FSM `$fsm$\dut.state$1144' from module `\harness_memory_manager'. + +4.14.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. +Removed 27 unused cells and 27 unused wires. + + +4.14.5. Executing FSM_OPT pass (simple optimizations of FSMs). +Optimizing FSM `$fsm$\dut.state$1144' from module `\harness_memory_manager'. + Removing unused output signal $flatten\dut.$0\state[2:0] [0]. + Removing unused output signal $flatten\dut.$0\state[2:0] [1]. + Removing unused output signal $flatten\dut.$0\state[2:0] [2]. +Optimizing FSM `$fsm$\dut.u_prefetch.state$1152' from module `\harness_memory_manager'. + Removing unused output signal $flatten\dut.\u_prefetch.$0\state[1:0] [0]. + Removing unused output signal $flatten\dut.\u_prefetch.$0\state[1:0] [1]. + +4.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). +Recoding FSM `$fsm$\dut.state$1144' from module `\harness_memory_manager' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 000 -> -----1 + 100 -> ----1- + 010 -> ---1-- + 001 -> --1--- + 101 -> -1---- + 011 -> 1----- +Recoding FSM `$fsm$\dut.u_prefetch.state$1152' from module `\harness_memory_manager' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 00 -> ---1 + 10 -> --1- + 01 -> -1-- + 11 -> 1--- + +4.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +FSM `$fsm$\dut.state$1144' from module `harness_memory_manager': +------------------------------------- + + Information on FSM $fsm$\dut.state$1144 (\dut.state): + + Number of input signals: 7 + Number of output signals: 6 + Number of state bits: 6 + + Input signals: + 0: \rst + 1: \lfsr [0] + 2: \lfsr [4] + 3: $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:284$334_Y + 4: $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:252$317_Y + 5: $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:245$304_Y + 6: $flatten\dut.$logic_or$hardware/v2/rtl/memory_manager.v:227$295_Y + + Output signals: + 0: $flatten\dut.$procmux$1076_CMP + 1: $flatten\dut.$procmux$1015_CMP + 2: $flatten\dut.$procmux$1012_CMP + 3: $flatten\dut.$procmux$705_CMP + 4: $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:151$245_Y + 5: $flatten\dut.$eq$hardware/v2/rtl/memory_manager.v:151$244_Y + + State encoding: + 0: 6'-----1 + 1: 6'----1- + 2: 6'---1-- + 3: 6'--1--- + 4: 6'-1---- + 5: 6'1----- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 7'-----00 -> 0 6'000001 + 1: 0 7'------1 -> 0 6'000001 + 2: 0 7'-----10 -> 3 6'000001 + 3: 1 7'------1 -> 0 6'100000 + 4: 1 7'------0 -> 4 6'100000 + 5: 2 7'------1 -> 0 6'000100 + 6: 2 7'-10---0 -> 2 6'000100 + 7: 2 7'-0----0 -> 2 6'000100 + 8: 2 7'-11---0 -> 5 6'000100 + 9: 3 7'------1 -> 0 6'000010 + 10: 3 7'1-----0 -> 2 6'000010 + 11: 3 7'0-----0 -> 3 6'000010 + 12: 4 7'----1-0 -> 0 6'010000 + 13: 4 7'------1 -> 0 6'010000 + 14: 4 7'----0-0 -> 4 6'010000 + 15: 5 7'------1 -> 0 6'001000 + 16: 5 7'---1--0 -> 1 6'001000 + 17: 5 7'---0--0 -> 5 6'001000 + +------------------------------------- + +FSM `$fsm$\dut.u_prefetch.state$1152' from module `harness_memory_manager': +------------------------------------- + + Information on FSM $fsm$\dut.u_prefetch.state$1152 (\dut.u_prefetch.state): + + Number of input signals: 4 + Number of output signals: 4 + Number of state bits: 4 + + Input signals: + 0: \rst + 1: \lfsr [4] + 2: $flatten\dut.\u_prefetch.$eq$hardware/v2/rtl/prefetch_engine.v:106$378_Y + 3: \dut.pf_start + + Output signals: + 0: $flatten\dut.\u_prefetch.$procmux$387_CMP + 1: $flatten\dut.\u_prefetch.$procmux$406_CMP + 2: $flatten\dut.\u_prefetch.$procmux$421_CMP + 3: $flatten\dut.\u_prefetch.$procmux$424_CMP + + State encoding: + 0: 4'---1 + 1: 4'--1- + 2: 4'-1-- + 3: 4'1--- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 4'0--0 -> 0 4'1000 + 1: 0 4'---1 -> 0 4'1000 + 2: 0 4'1--0 -> 2 4'1000 + 3: 1 4'---1 -> 0 4'0001 + 4: 1 4'--00 -> 1 4'0001 + 5: 1 4'-010 -> 1 4'0001 + 6: 1 4'-110 -> 3 4'0001 + 7: 2 4'---1 -> 0 4'0010 + 8: 2 4'-110 -> 1 4'0010 + 9: 2 4'--00 -> 2 4'0010 + 10: 2 4'-010 -> 2 4'0010 + 11: 3 4'---- -> 0 4'0100 + +------------------------------------- + +4.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic). +Mapping FSM `$fsm$\dut.state$1144' from module `\harness_memory_manager'. +Mapping FSM `$fsm$\dut.u_prefetch.state$1152' from module `\harness_memory_manager'. + +4.15. Executing OPT pass (performing simple optimizations). + +4.15.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + + +4.15.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 315 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 311 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. + +Removed a total of 4 cells. + +4.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_memory_manager. +Performed a total of 0 changes. + +4.15.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 311 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Removed a total of 0 cells. + +4.15.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $procdff$1135 ($dff) from module harness_memory_manager (D = { \lfsr [30:7] $xor$hardware/v2/synthesis/harness_memory_manager.v:26$230_Y }, Q = { \lfsr [31:8] \lfsr [0] }, rval = 25'0000000000000000000000001). +Adding SRST signal on $procdff$1134 ($dff) from module harness_memory_manager (D = $xor$hardware/v2/synthesis/harness_memory_manager.v:65$239_Y, Q = \chk, rval = 8'00000000). +Adding SRST signal on $flatten\dut.\u_prefetch.$procdff$1086 ($dff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$459_Y, Q = \dut.u_prefetch.mem_req, rval = 1'0). +Adding SRST signal on $flatten\dut.\u_prefetch.$procdff$1087 ($dff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$574_Y, Q = \dut.u_prefetch.mem_wr, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$1262 ($sdff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$574_Y, Q = \dut.u_prefetch.mem_wr). +Adding SRST signal on $flatten\dut.\u_prefetch.$procdff$1088 ($dff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$552_Y, Q = \dut.u_prefetch.mem_addr, rval = 23'00000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$1276 ($sdff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$552_Y, Q = \dut.u_prefetch.mem_addr). +Adding EN signal on $flatten\dut.\u_prefetch.$procdff$1089 ($dff) from module harness_memory_manager (D = 8'00000000, Q = \dut.u_prefetch.mem_wdata). +Adding SRST signal on $flatten\dut.\u_prefetch.$procdff$1091 ($dff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$512_Y, Q = \dut.u_prefetch.fetch_busy, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$1291 ($sdff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$512_Y, Q = \dut.u_prefetch.fetch_busy). +Adding SRST signal on $flatten\dut.\u_prefetch.$procdff$1092 ($dff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$473_Y, Q = \dut.u_prefetch.fetch_done, rval = 1'0). +Adding EN signal on $flatten\dut.\u_prefetch.$procdff$1093 ($dff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$2$lookahead\tile_x$337[63:0]$350, Q = \dut.u_prefetch.tile_x). +Adding EN signal on $flatten\dut.\u_prefetch.$procdff$1094 ($dff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$2$lookahead\tile_w$338[63:0]$351, Q = \dut.u_prefetch.tile_w). +Adding SRST signal on $flatten\dut.\u_prefetch.$procdff$1095 ($dff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$497_Y, Q = \dut.u_prefetch.byte_idx, rval = 4'0000). +Adding EN signal on $auto$ff.cc:337:slice$1318 ($sdff) from module harness_memory_manager (D = $flatten\dut.\u_prefetch.$procmux$497_Y, Q = \dut.u_prefetch.byte_idx). +Adding SRST signal on $flatten\dut.$procdff$1124 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$746_Y, Q = \dut.wr_mem_wdata, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$1332 ($sdff) from module harness_memory_manager (D = \lfsr [7:0], Q = \dut.wr_mem_wdata). +Adding SRST signal on $flatten\dut.$procdff$1123 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$753_Y, Q = \dut.wr_mem_addr, rval = 23'00000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$1336 ($sdff) from module harness_memory_manager (D = \dut.result_addr_reg, Q = \dut.wr_mem_addr). +Adding SRST signal on $flatten\dut.$procdff$1122 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$759_Y, Q = \dut.wr_mem_req, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$1338 ($sdff) from module harness_memory_manager (D = $flatten\dut.$procmux$759_Y, Q = \dut.wr_mem_req). +Adding EN signal on $flatten\dut.$procdff$1121 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$777_Y, Q = \dut.pf_pending_bank). +Adding EN signal on $flatten\dut.$procdff$1120 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$803_Y, Q = \dut.pf_pending_w). +Adding EN signal on $flatten\dut.$procdff$1119 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$829_Y, Q = \dut.pf_pending_x). +Adding SRST signal on $flatten\dut.$procdff$1118 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$857_Y, Q = \dut.pf_pending, rval = 1'0). +Adding EN signal on $flatten\dut.$procdff$1117 ($dff) from module harness_memory_manager (D = \dut.pf_pending_bank, Q = \dut.pf_target_bank). +Adding EN signal on $flatten\dut.$procdff$1116 ($dff) from module harness_memory_manager (D = \dut.pf_pending_w, Q = \dut.pf_w_addr). +Adding EN signal on $flatten\dut.$procdff$1115 ($dff) from module harness_memory_manager (D = \dut.pf_pending_x, Q = \dut.pf_x_addr). +Adding SRST signal on $flatten\dut.$procdff$1114 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$696_Y, Q = \dut.pf_start, rval = 1'0). +Adding SRST signal on $flatten\dut.$procdff$1113 ($dff) from module harness_memory_manager (D = $flatten\dut.$3$lookahead\bank_ready$251[1:0]$291, Q = \dut.bank_ready, rval = 2'00). +Adding SRST signal on $flatten\dut.$procdff$1112 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$893_Y, Q = \dut.current_bank, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$1417 ($sdff) from module harness_memory_manager (D = $flatten\dut.$procmux$893_Y, Q = \dut.current_bank). +Adding SRST signal on $flatten\dut.$procdff$1111 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$909_Y, Q = \dut.tile_idx, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$1427 ($sdff) from module harness_memory_manager (D = $flatten\dut.$procmux$909_Y, Q = \dut.tile_idx). +Adding EN signal on $flatten\dut.$procdff$1110 ($dff) from module harness_memory_manager (D = { \lfsr [15:1] 1'1 }, Q = \dut.n_tiles_reg). +Adding EN signal on $flatten\dut.$procdff$1109 ($dff) from module harness_memory_manager (D = { \lfsr [3:1] 1'1 \lfsr [18:1] 1'1 }, Q = \dut.result_addr_reg). +Adding EN signal on $flatten\dut.$procdff$1108 ($dff) from module harness_memory_manager (D = { \lfsr [7:1] 1'1 \lfsr [14:1] 1'1 }, Q = \dut.w_base_reg). +Adding EN signal on $flatten\dut.$procdff$1107 ($dff) from module harness_memory_manager (D = { \lfsr [22:1] 1'1 }, Q = \dut.x_base_reg). +Adding SRST signal on $flatten\dut.$procdff$1105 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$704_Y, Q = \dut.result_ready, rval = 1'0). +Adding SRST signal on $flatten\dut.$procdff$1104 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$1011_Y, Q = \dut.tile_last, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$1458 ($sdff) from module harness_memory_manager (D = $flatten\dut.$procmux$1011_Y, Q = \dut.tile_last). +Adding SRST signal on $flatten\dut.$procdff$1103 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$1030_Y, Q = \dut.weight_data, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$1472 ($sdff) from module harness_memory_manager (D = $flatten\dut.$procmux$1030_Y, Q = \dut.weight_data). +Adding SRST signal on $flatten\dut.$procdff$1102 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$1049_Y, Q = \dut.input_data, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$1486 ($sdff) from module harness_memory_manager (D = $flatten\dut.$procmux$1049_Y, Q = \dut.input_data). +Adding SRST signal on $flatten\dut.$procdff$1101 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$1068_Y, Q = \dut.operand_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$1500 ($sdff) from module harness_memory_manager (D = $flatten\dut.$procmux$1068_Y, Q = \dut.operand_valid). +Adding SRST signal on $flatten\dut.$procdff$1100 ($dff) from module harness_memory_manager (D = $flatten\dut.$procmux$710_Y, Q = \dut.job_done, rval = 1'0). +Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$1452 ($dffe) from module harness_memory_manager. +Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$1447 ($dffe) from module harness_memory_manager. +Setting constant 1-bit at position 15 on $auto$ff.cc:337:slice$1447 ($dffe) from module harness_memory_manager. +Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$1442 ($dffe) from module harness_memory_manager. +Setting constant 1-bit at position 19 on $auto$ff.cc:337:slice$1442 ($dffe) from module harness_memory_manager. +Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$1437 ($dffe) from module harness_memory_manager. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$1290 ($dffe) from module harness_memory_manager. +Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$1290 ($dffe) from module harness_memory_manager. +Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$1290 ($dffe) from module harness_memory_manager. +Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$1290 ($dffe) from module harness_memory_manager. +Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$1290 ($dffe) from module harness_memory_manager. +Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$1290 ($dffe) from module harness_memory_manager. +Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$1290 ($dffe) from module harness_memory_manager. +Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$1290 ($dffe) from module harness_memory_manager. + +4.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. +Removed 49 unused cells and 71 unused wires. + + +4.15.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + + +4.15.9. Rerunning OPT passes. (Maybe there is more to do..) + +4.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_memory_manager. + New ctrl vector for $pmux cell $flatten\dut.\u_prefetch.$procmux$428: \dut.u_prefetch.state [2] + New ctrl vector for $pmux cell $flatten\dut.\u_prefetch.$procmux$420: \dut.u_prefetch.state [1] + Optimizing cells in module \harness_memory_manager. +Performed a total of 2 changes. + +4.15.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 366 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 306 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 294 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. + +Removed a total of 72 cells. + +4.15.13. Executing OPT_DFF pass (perform DFF optimizations). + +4.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. +Removed 0 unused cells and 72 unused wires. + + +4.15.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + +4.15.16. Rerunning OPT passes. (Maybe there is more to do..) + +4.15.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.15.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_memory_manager. +Performed a total of 0 changes. + +4.15.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 294 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Removed a total of 0 cells. + +4.15.20. Executing OPT_DFF pass (perform DFF optimizations). + +4.15.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. + +4.15.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + +4.15.23. Finished fast OPT passes. (There is nothing left to do.) + +4.16. Executing WREDUCE pass (reducing word size of cells). +Removed top 31 address bits (of 32) from memory read port harness_memory_manager.$flatten\dut.$memrd$\bank_w$hardware/v2/rtl/memory_manager.v:232$298 (dut.bank_w). +Removed top 31 address bits (of 32) from memory read port harness_memory_manager.$flatten\dut.$memrd$\bank_x$hardware/v2/rtl/memory_manager.v:231$296 (dut.bank_x). +Removed top 56 bits (of 64) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1487 ($sdffe). +Removed top 56 bits (of 64) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1473 ($sdffe). +Removed top 1 bits (of 2) from port B of cell harness_memory_manager.$auto$opt_dff.cc:320:make_patterns_logic$1327 ($ne). +Removed top 1 bits (of 3) from port B of cell harness_memory_manager.$auto$fsm_map.cc:77:implement_pattern_cache$1246 ($eq). +Removed top 7 bits (of 8) from port B of cell harness_memory_manager.$xor$hardware/v2/synthesis/harness_memory_manager.v:65$234 ($xor). +Removed top 6 bits (of 8) from port B of cell harness_memory_manager.$xor$hardware/v2/synthesis/harness_memory_manager.v:65$235 ($xor). +Removed top 7 bits (of 8) from port B of cell harness_memory_manager.$xor$hardware/v2/synthesis/harness_memory_manager.v:65$237 ($xor). +Removed top 7 bits (of 8) from port B of cell harness_memory_manager.$xor$hardware/v2/synthesis/harness_memory_manager.v:65$238 ($xor). +Removed top 24 bits (of 32) from mux cell harness_memory_manager.$procmux$1084 ($mux). +Removed top 25 bits (of 33) from port A of cell harness_memory_manager.$flatten\dut.\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$375 ($neg). +Converting cell harness_memory_manager.$flatten\dut.\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$375 ($neg) from signed to unsigned. +Removed top 1 bits (of 8) from port A of cell harness_memory_manager.$flatten\dut.\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$375 ($neg). +Removed top 1 bits (of 4) from port B of cell harness_memory_manager.$flatten\dut.\u_prefetch.$eq$hardware/v2/rtl/prefetch_engine.v:106$378 ($eq). +Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1049 ($pmux). +Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1047 ($mux). +Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1044 ($mux). +Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1042 ($mux). +Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1030 ($pmux). +Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1028 ($mux). +Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1025 ($mux). +Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1023 ($mux). +Removed top 15 bits (of 16) from port B of cell harness_memory_manager.$flatten\dut.$sub$hardware/v2/rtl/memory_manager.v:277$332 ($sub). +Removed top 14 bits (of 16) from port B of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$323 ($add). +Removed top 6 bits (of 23) from port Y of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$323 ($add). +Removed top 3 bits (of 23) from port B of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:265$322 ($add). +Removed top 14 bits (of 16) from port B of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:255$318 ($add). +Removed top 15 bits (of 16) from port B of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:252$316 ($add). +Converting cell harness_memory_manager.$flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:247$311 ($neg) from signed to unsigned. +Removed top 1 bits (of 2) from port A of cell harness_memory_manager.$flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:247$311 ($neg). +Removed top 19 bits (of 23) from port B of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:237$303 ($add). +Removed top 19 bits (of 23) from port B of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:236$302 ($add). +Removed top 15 bits (of 16) from port B of cell harness_memory_manager.$flatten\dut.$gt$hardware/v2/rtl/memory_manager.v:234$301 ($gt). +Converting cell harness_memory_manager.$flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:183$283 ($neg) from signed to unsigned. +Removed top 1 bits (of 2) from port A of cell harness_memory_manager.$flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:183$283 ($neg). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$ternary$hardware/v2/rtl/memory_manager.v:154$249 ($mux). +Removed top 15 bits (of 23) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1337 ($sdffe). +Removed top 15 bits (of 23) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1277 ($sdffe). +Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1051 ($mux). +Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$procmux$1032 ($mux). +Removed top 14 bits (of 21) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1517 ($dffe). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$552 ($pmux). +Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$ternary$hardware/v2/rtl/memory_manager.v:232$299 ($mux). +Removed top 56 bits (of 64) from mux cell harness_memory_manager.$flatten\dut.$ternary$hardware/v2/rtl/memory_manager.v:231$297 ($mux). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$550 ($mux). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$558 ($mux). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$561 ($mux). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$548 ($mux). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$556 ($mux). +Removed top 15 bits (of 23) from port Y of cell harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$366 ($add). +Removed top 15 bits (of 23) from port A of cell harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$366 ($add). +Removed top 15 bits (of 23) from port Y of cell harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$381 ($add). +Removed top 15 bits (of 23) from port A of cell harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$381 ($add). +Removed top 15 bits (of 23) from port Y of cell harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$365 ($add). +Removed top 15 bits (of 23) from port A of cell harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$365 ($add). +Removed top 15 bits (of 23) from port Y of cell harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$380 ($add). +Removed top 15 bits (of 23) from port A of cell harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$380 ($add). +Removed top 15 bits (of 23) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1410 ($dffe). +Removed top 15 bits (of 23) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1405 ($dffe). +Removed top 15 bits (of 23) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1380 ($dffe). +Removed top 15 bits (of 23) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1361 ($dffe). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$829 ($pmux). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$803 ($pmux). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$837 ($mux). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$833 ($mux). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$827 ($mux). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$811 ($mux). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$807 ($mux). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$801 ($mux). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$831 ($mux). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$825 ($mux). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$805 ($mux). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$799 ($mux). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$822 ($mux). +Removed top 15 bits (of 23) from mux cell harness_memory_manager.$flatten\dut.$procmux$796 ($mux). +Removed top 15 bits (of 23) from port Y of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:237$303 ($add). +Removed top 15 bits (of 23) from port A of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:237$303 ($add). +Removed top 15 bits (of 23) from port Y of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:236$302 ($add). +Removed top 15 bits (of 23) from port A of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:236$302 ($add). +Removed top 3 bits (of 23) from port B of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$325 ($add). +Removed top 15 bits (of 23) from port Y of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$325 ($add). +Removed top 15 bits (of 23) from port A of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$325 ($add). +Removed top 12 bits (of 20) from port B of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$325 ($add). +Removed top 15 bits (of 23) from port Y of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:265$322 ($add). +Removed top 15 bits (of 23) from port A of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:265$322 ($add). +Removed top 12 bits (of 20) from port B of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:265$322 ($add). +Removed top 14 bits (of 21) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1516 ($dffe). +Removed top 15 bits (of 22) from FF cell harness_memory_manager.$auto$ff.cc:337:slice$1515 ($dffe). +Removed top 12 bits (of 17) from port Y of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$323 ($add). +Removed top 11 bits (of 16) from port A of cell harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$323 ($add). +Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$ternary$hardware/v2/rtl/memory_manager.v:231$297_Y. +Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1023_Y. +Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1025_Y. +Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1028_Y. +Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1030_Y. +Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1032_Y. +Removed top 18 bits (of 23) from wire harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:265$320_Y. +Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1042_Y. +Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1044_Y. +Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1047_Y. +Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1049_Y. +Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$procmux$1051_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:265$322_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$325_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$561_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$558_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$556_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$552_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$550_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$procmux$548_Y. +Removed top 56 bits (of 64) from wire harness_memory_manager.$flatten\dut.$ternary$hardware/v2/rtl/memory_manager.v:232$299_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$796_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$799_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$801_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$803_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$805_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$807_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$811_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$837_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$833_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$831_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$829_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$827_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$825_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$381_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$380_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:237$303_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$366_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$365_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$procmux$822_Y. +Removed top 15 bits (of 23) from wire harness_memory_manager.$flatten\dut.$add$hardware/v2/rtl/memory_manager.v:236$302_Y. +Removed top 24 bits (of 32) from wire harness_memory_manager.$0\lfsr[31:0]. +Removed top 15 bits (of 23) from wire harness_memory_manager.mem_addr. +Removed top 56 bits (of 64) from wire harness_memory_manager.weight_data. +Removed top 56 bits (of 64) from wire harness_memory_manager.input_data. + +4.17. Executing PEEPOPT pass (run peephole optimizers). + +4.18. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. +Removed 0 unused cells and 45 unused wires. + + +4.19. Executing SHARE pass (SAT-based resource sharing). +Found 2 cells in module harness_memory_manager that may be considered for resource sharing. + Analyzing resource sharing options for $flatten\dut.$memrd$\bank_w$hardware/v2/rtl/memory_manager.v:276$331 ($memrd): + Found 1 activation_patterns using ctrl signal { \dut.operand_valid \dut.state [2] $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:245$304_Y $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:273$329_Y }. + No candidates found. + Analyzing resource sharing options for $flatten\dut.$memrd$\bank_x$hardware/v2/rtl/memory_manager.v:275$330 ($memrd): + Found 1 activation_patterns using ctrl signal { \dut.operand_valid \dut.state [2] $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:245$304_Y $flatten\dut.$logic_and$hardware/v2/rtl/memory_manager.v:273$329_Y }. + No candidates found. + +4.20. Executing TECHMAP pass (map to technology primitives). + +4.20.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +4.20.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.21. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + +4.22. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. + +4.23. Executing TECHMAP pass (map to technology primitives). + +4.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +4.23.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.24. Executing TECHMAP pass (map to technology primitives). + +4.24.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. +Generating RTLIL representation for module `$__MUL18X18'. +Successfully finished Verilog frontend. + +4.24.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.25. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module harness_memory_manager: + creating $macc model for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$323 ($add). + creating $macc model for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:265$322 ($add). + creating $macc model for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:252$316 ($add). + creating $macc model for $flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:247$311 ($neg). + creating $macc model for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:237$303 ($add). + creating $macc model for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:236$302 ($add). + creating $macc model for $flatten\dut.$sub$hardware/v2/rtl/memory_manager.v:277$332 ($sub). + creating $macc model for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:255$318 ($add). + creating $macc model for $flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:183$283 ($neg). + creating $macc model for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$325 ($add). + creating $macc model for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$381 ($add). + creating $macc model for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$380 ($add). + creating $macc model for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:109$379 ($add). + creating $macc model for $flatten\dut.\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$375 ($neg). + creating $macc model for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$366 ($add). + creating $macc model for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$365 ($add). + merging $macc model for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$365 into $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$366. + merging $macc model for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$380 into $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$381. + creating $alu model for $macc $flatten\dut.\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$375. + creating $alu model for $macc $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:109$379. + creating $alu model for $macc $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$366. + creating $alu model for $macc $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$381. + creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$325. + creating $alu model for $macc $flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:183$283. + creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:255$318. + creating $alu model for $macc $flatten\dut.$sub$hardware/v2/rtl/memory_manager.v:277$332. + creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:236$302. + creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:237$303. + creating $alu model for $macc $flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:247$311. + creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:252$316. + creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:265$322. + creating $alu model for $macc $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$323. + creating $alu model for $flatten\dut.$lt$hardware/v2/rtl/memory_manager.v:255$319 ($lt): new $alu + creating $alu model for $flatten\dut.$gt$hardware/v2/rtl/memory_manager.v:234$301 ($gt): merged with $flatten\dut.$sub$hardware/v2/rtl/memory_manager.v:277$332. + creating $alu model for $flatten\dut.$lt$hardware/v2/rtl/memory_manager.v:273$328 ($lt): new $alu + creating $alu cell for $flatten\dut.$lt$hardware/v2/rtl/memory_manager.v:273$328: $auto$alumacc.cc:548:replace_alu$1567 + creating $alu cell for $flatten\dut.$lt$hardware/v2/rtl/memory_manager.v:255$319: $auto$alumacc.cc:548:replace_alu$1572 + creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$323: $auto$alumacc.cc:548:replace_alu$1577 + creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:265$322: $auto$alumacc.cc:548:replace_alu$1580 + creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:252$316: $auto$alumacc.cc:548:replace_alu$1583 + creating $alu cell for $flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:247$311: $auto$alumacc.cc:548:replace_alu$1586 + creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:237$303: $auto$alumacc.cc:548:replace_alu$1589 + creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:236$302: $auto$alumacc.cc:548:replace_alu$1592 + creating $alu cell for $flatten\dut.$sub$hardware/v2/rtl/memory_manager.v:277$332, $flatten\dut.$gt$hardware/v2/rtl/memory_manager.v:234$301: $auto$alumacc.cc:548:replace_alu$1595 + creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:255$318: $auto$alumacc.cc:548:replace_alu$1606 + creating $alu cell for $flatten\dut.$neg$hardware/v2/rtl/memory_manager.v:183$283: $auto$alumacc.cc:548:replace_alu$1609 + creating $alu cell for $flatten\dut.$add$hardware/v2/rtl/memory_manager.v:266$325: $auto$alumacc.cc:548:replace_alu$1612 + creating $alu cell for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$381: $auto$alumacc.cc:548:replace_alu$1615 + creating $alu cell for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$366: $auto$alumacc.cc:548:replace_alu$1618 + creating $alu cell for $flatten\dut.\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:109$379: $auto$alumacc.cc:548:replace_alu$1621 + creating $alu cell for $flatten\dut.\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$375: $auto$alumacc.cc:548:replace_alu$1624 + created 16 $alu and 0 $macc cells. + +4.26. Executing OPT pass (performing simple optimizations). + +4.26.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + + +4.26.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 299 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 297 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 295 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. + +Removed a total of 4 cells. + +4.26.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.26.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_memory_manager. +Performed a total of 0 changes. + +4.26.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 295 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 292 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 290 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 289 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 288 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 287 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 286 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 284 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. + +Removed a total of 11 cells. + +4.26.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.26.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. +Removed 1 unused cells and 21 unused wires. + + +4.26.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + +4.26.9. Rerunning OPT passes. (Maybe there is more to do..) + +4.26.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.26.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_memory_manager. +Performed a total of 0 changes. + +4.26.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 283 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Removed a total of 0 cells. + +4.26.13. Executing OPT_DFF pass (perform DFF optimizations). + +4.26.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. + +4.26.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + +4.26.16. Finished fast OPT passes. (There is nothing left to do.) + +4.27. Executing MEMORY pass. + +4.27.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +4.27.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +4.27.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing harness_memory_manager.dut.bank_x write port 0. + Analyzing harness_memory_manager.dut.bank_w write port 0. + +4.27.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +4.27.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Checking read port `\dut.bank_x'[0] in module `\harness_memory_manager': no output FF found. +Checking read port `\dut.bank_x'[1] in module `\harness_memory_manager': no output FF found. +Checking read port `\dut.bank_w'[0] in module `\harness_memory_manager': no output FF found. +Checking read port `\dut.bank_w'[1] in module `\harness_memory_manager': no output FF found. +Checking read port address `\dut.bank_x'[0] in module `\harness_memory_manager': no address FF found. +Checking read port address `\dut.bank_x'[1] in module `\harness_memory_manager': merged address FF to cell. +Checking read port address `\dut.bank_w'[0] in module `\harness_memory_manager': no address FF found. +Checking read port address `\dut.bank_w'[1] in module `\harness_memory_manager': merged address FF to cell. + +4.27.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. + +4.27.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). +Consolidating read ports of memory harness_memory_manager.dut.bank_x by address: +Consolidating read ports of memory harness_memory_manager.dut.bank_w by address: + +4.27.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +4.27.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. + +4.27.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +4.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. + +4.29. Executing MEMORY_LIBMAP pass (mapping memories to cells). +using FF mapping for memory harness_memory_manager.dut.bank_w +using FF mapping for memory harness_memory_manager.dut.bank_x + + +4.30. Executing TECHMAP pass (map to technology primitives). + +4.30.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. +Successfully finished Verilog frontend. + +4.30.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. +Generating RTLIL representation for module `$__DP16KD_'. +Generating RTLIL representation for module `$__PDPW16KD_'. +Successfully finished Verilog frontend. + +4.30.3. Continuing TECHMAP pass. +No more expansions possible. + + +4.31. Executing OPT pass (performing simple optimizations). + +4.31.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + + +4.31.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 223 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 222 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 221 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. + +Removed a total of 2 cells. + +4.31.3. Executing OPT_DFF pass (perform DFF optimizations). + +4.31.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. +Removed 0 unused cells and 71 unused wires. + + +4.31.5. Finished fast OPT passes. + +4.32. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). +Mapping memory \dut.bank_w in module \harness_memory_manager: + created 2 $dff cells and 0 static cells of width 64. +Extracted addr FF from read port 1 of harness_memory_manager.dut.bank_w: $\dut.bank_w$rdreg[1] + read interface: 1 $dff and 2 $mux cells. + write interface: 2 write mux blocks. +Mapping memory \dut.bank_x in module \harness_memory_manager: + created 2 $dff cells and 0 static cells of width 64. +Extracted addr FF from read port 1 of harness_memory_manager.dut.bank_x: $\dut.bank_x$rdreg[1] + read interface: 1 $dff and 2 $mux cells. + write interface: 2 write mux blocks. + +4.33. Executing OPT pass (performing simple optimizations). + +4.33.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + + +4.33.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 235 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 231 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. + +Removed a total of 4 cells. + +4.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_memory_manager. + Consolidated identical input bits for $pmux cell $flatten\dut.\u_prefetch.$procmux$574: + Old ports: A=1'0, B=2'00, Y=$flatten\dut.\u_prefetch.$procmux$574_Y + New connections: $flatten\dut.\u_prefetch.$procmux$574_Y = 1'0 + Consolidated identical input bits for $pmux cell $flatten\dut.$procmux$803: + Old ports: A={ \lfsr [7:1] 1'1 }, B={ $auto$wreduce.cc:514:run$1544 [7:3] \dut.x_base_reg [2:1] 1'1 $auto$wreduce.cc:514:run$1531 [7:3] \dut.x_base_reg [2:1] 1'1 }, Y=$auto$wreduce.cc:514:run$1543 [7:0] + New ports: A=\lfsr [7:1], B={ $auto$wreduce.cc:514:run$1544 [7:3] \dut.x_base_reg [2:1] $auto$wreduce.cc:514:run$1531 [7:3] \dut.x_base_reg [2:1] }, Y=$auto$wreduce.cc:514:run$1543 [7:1] + New connections: $auto$wreduce.cc:514:run$1543 [0] = 1'1 + Optimizing cells in module \harness_memory_manager. +Performed a total of 2 changes. + +4.33.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 230 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Removed a total of 0 cells. + +4.33.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $\dut.bank_x$rdreg[1] ($dff) from module harness_memory_manager (D = $auto$rtlil.cc:3402:Mux$1634, Q = $\dut.bank_x$rdreg[1]$q, rval = 1'0). + +4.33.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. +Removed 1 unused cells and 21 unused wires. + + +4.33.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + +4.33.9. Rerunning OPT passes. (Maybe there is more to do..) + +4.33.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.33.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_memory_manager. +Performed a total of 0 changes. + +4.33.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 229 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Removed a total of 0 cells. + +4.33.13. Executing OPT_DFF pass (perform DFF optimizations). +Adding EN signal on $memory\dut.bank_x[1]$1813 ($dff) from module harness_memory_manager (D = \dut.u_prefetch.tile_x, Q = \dut.bank_x[1]). +Adding EN signal on $memory\dut.bank_x[0]$1811 ($dff) from module harness_memory_manager (D = \dut.u_prefetch.tile_x, Q = \dut.bank_x[0]). +Adding EN signal on $memory\dut.bank_w[0]$1789 ($dff) from module harness_memory_manager (D = \dut.u_prefetch.tile_w, Q = \dut.bank_w[0]). +Adding EN signal on $memory\dut.bank_w[1]$1791 ($dff) from module harness_memory_manager (D = \dut.u_prefetch.tile_w, Q = \dut.bank_w[1]). +Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$1380 ($dffe) from module harness_memory_manager. +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$1263 ($sdffe) from module harness_memory_manager. + +4.33.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. +Removed 4 unused cells and 4 unused wires. + + +4.33.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + + +4.33.16. Rerunning OPT passes. (Maybe there is more to do..) + +4.33.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.33.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_memory_manager. +Performed a total of 0 changes. + +4.33.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 223 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Removed a total of 0 cells. + +4.33.20. Executing OPT_DFF pass (perform DFF optimizations). +Setting constant 1-bit at position 0 on $auto$ff.cc:337:slice$1410 ($dffe) from module harness_memory_manager. + +4.33.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. + +4.33.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + + +4.33.23. Rerunning OPT passes. (Maybe there is more to do..) + +4.33.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.33.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_memory_manager. +Performed a total of 0 changes. + +4.33.26. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 224 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Removed a total of 0 cells. + +4.33.27. Executing OPT_DFF pass (perform DFF optimizations). + +4.33.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. +Removed 1 unused cells and 1 unused wires. + + +4.33.29. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + +4.33.30. Rerunning OPT passes. (Maybe there is more to do..) + +4.33.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +4.33.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_memory_manager. +Performed a total of 0 changes. + +4.33.33. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 223 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Removed a total of 0 cells. + +4.33.34. Executing OPT_DFF pass (perform DFF optimizations). + +4.33.35. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. + +4.33.36. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + +4.33.37. Finished fast OPT passes. (There is nothing left to do.) + +4.34. Executing TECHMAP pass (map to technology primitives). + +4.34.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +4.34.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. +Generating RTLIL representation for module `\_80_ccu2c_alu'. +Successfully finished Verilog frontend. + +4.34.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $dffe. +Using extmapper simplemap for cells of type $sdff. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $mux. +Using template $paramod$3e2546d640bb80c4407ce51aec1dbdbdc5bff143\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. +Using template $paramod$08b2a3505d8f2cd2b03f068ccaf5ce95d4eb0556\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$9e8c19db10db5b8954224cafa0587db20bab09bd\_90_alu for cells of type $alu. +Using template $paramod$3b7577489eb4433b1d5620cab7f3794743dee5ea\_80_ccu2c_alu for cells of type $alu. +Using extmapper simplemap for cells of type $reduce_and. +Using template $paramod$672a140277c71df8314410f22acc08d55222c3c7\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$b18e16801adf491a64caa0542270798e5d4ac6b6\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_80_ccu2c_alu for cells of type $alu. +Using extmapper simplemap for cells of type $reduce_or. +Using extmapper simplemap for cells of type $sdffe. +Using extmapper simplemap for cells of type $ne. +Using extmapper simplemap for cells of type $reduce_bool. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $eq. +Using extmapper simplemap for cells of type $logic_not. +Using extmapper simplemap for cells of type $or. +Using template $paramod$constmap:27fc41eec160220305c22e2c40782fd680a452dd$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx for cells of type $shift. +Analyzing pattern of constant bits for this cell: +Creating constmapped module `$paramod$constmap:f559a679ff835ab881c809a3c11cd4b7ac7c221b$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx'. + +4.34.29. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:f559a679ff835ab881c809a3c11cd4b7ac7c221b$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$3312. + dead port 2/2 on $mux $procmux$3318. + dead port 2/2 on $mux $procmux$3324. + dead port 2/2 on $mux $procmux$3330. + dead port 2/2 on $mux $procmux$3336. + dead port 2/2 on $mux $procmux$3342. + dead port 2/2 on $mux $procmux$3348. +Removed 7 multiplexer ports. + + +4.34.30. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:f559a679ff835ab881c809a3c11cd4b7ac7c221b$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx. + +Removed 0 unused cells and 12 unused wires. +Using template $paramod$constmap:f559a679ff835ab881c809a3c11cd4b7ac7c221b$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx for cells of type $shift. +Using extmapper simplemap for cells of type $pmux. +Using extmapper simplemap for cells of type $logic_and. +Using template $paramod$constmap:de554f9cc18e049d5b7dc95f0bcf8e03e57019ff$paramod$1e265d9719406ee45a570be27d6567e3eeff81e5\_90_shift_shiftx for cells of type $shiftx. +Using template $paramod$constmap:d8aefc1ccc4cc8f7577de99159ea22c4a240a5fa$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx for cells of type $shift. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port A: 1'1 +Creating constmapped module `$paramod$constmap:dd82805e02d0c05f7629d78043ee7bd4bcc370d0$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx'. + +4.34.41. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:dd82805e02d0c05f7629d78043ee7bd4bcc370d0$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$4017. +Removed 1 multiplexer ports. + + +4.34.42. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:dd82805e02d0c05f7629d78043ee7bd4bcc370d0$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx. + +Removed 0 unused cells and 7 unused wires. +Using template $paramod$constmap:dd82805e02d0c05f7629d78043ee7bd4bcc370d0$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx for cells of type $shift. +Using extmapper simplemap for cells of type $logic_or. +Using extmapper simplemap for cells of type $pos. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. +No more expansions possible. + + +4.35. Executing OPT pass (performing simple optimizations). + +4.35.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + + +4.35.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 2705 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2576 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2554 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2541 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2532 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2531 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2530 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2529 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2528 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2527 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2526 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2525 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2524 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2523 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2522 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2521 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2520 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2519 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2518 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2517 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2516 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2515 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2514 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2513 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2512 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 2511 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. + +Removed a total of 194 cells. + +4.35.3. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $auto$ff.cc:337:slice$2888 ($_SDFF_PP0_) from module harness_memory_manager (D = $auto$simplemap.cc:189:logic_reduce$3659, Q = \dut.u_prefetch.mem_req, rval = 1'0). +Adding SRST signal on $auto$ff.cc:337:slice$2671 ($_DFFE_PP_) from module harness_memory_manager (D = $auto$simplemap.cc:189:logic_reduce$3887, Q = \dut.pf_pending_bank, rval = 1'0). + +4.35.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. +Removed 1402 unused cells and 838 unused wires. + + +4.35.5. Rerunning OPT passes. (Removed registers in this run.) + +4.35.6. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + + +4.35.7. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 1106 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Removed a total of 0 cells. + +4.35.8. Executing OPT_DFF pass (perform DFF optimizations). + +4.35.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. + +4.35.10. Finished fast OPT passes. + +4.36. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. + +4.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +4.38. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 1108 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Removed a total of 0 cells. + +4.39. Executing TECHMAP pass (map to technology primitives). + +4.39.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +4.39.2. Continuing TECHMAP pass. +Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. +Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. +Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. +Using template $_SDFF_PP1_ for cells of type $_SDFF_PP1_. +Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. +No more expansions possible. + + +4.40. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + + +4.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +4.42. Executing LATTICE_GSR pass (implement FF init values). +Handling GSR in harness_memory_manager. + +4.43. Executing ATTRMVCP pass (move or copy attributes). + +4.44. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. +Removed 0 unused cells and 1064 unused wires. + + +4.45. Executing CHECK pass (checking for obvious problems). +Checking module harness_memory_manager... +Found and reported 0 problems. + +4.46. Executing TECHMAP pass (map to technology primitives). + +4.46.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. +Generating RTLIL representation for module `$_DLATCH_N_'. +Generating RTLIL representation for module `$_DLATCH_P_'. +Successfully finished Verilog frontend. + +4.46.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.47. Executing ABC9 pass. + +4.47.1. Executing ABC9_OPS pass (helper functions for ABC9). + +4.47.2. Executing ABC9_OPS pass (helper functions for ABC9). + +4.47.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module harness_memory_manager. +Found 0 SCCs. + +4.47.4. Executing ABC9_OPS pass (helper functions for ABC9). + +4.47.5. Executing TECHMAP pass (map to technology primitives). + +4.47.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +4.47.5.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.47.6. Executing OPT pass (performing simple optimizations). + +4.47.6.1. Executing OPT_EXPR pass (perform const folding). + +4.47.6.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +4.47.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +4.47.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +4.47.6.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +4.47.6.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.47.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +4.47.6.8. Executing OPT_EXPR pass (perform const folding). + +4.47.6.9. Finished fast OPT passes. (There is nothing left to do.) + +4.47.7. Executing TECHMAP pass (map to technology primitives). + +4.47.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +4.47.7.2. Continuing TECHMAP pass. +No more expansions possible. + + +4.47.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +4.47.9. Executing ABC9_OPS pass (helper functions for ABC9). + + +4.47.10. Executing ABC9_OPS pass (helper functions for ABC9). + +4.47.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +4.47.12. Executing TECHMAP pass (map to technology primitives). + +4.47.12.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +4.47.12.2. Continuing TECHMAP pass. +Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. +Using extmapper simplemap for cells of type $or. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $xor. +Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. +Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. +Using extmapper simplemap for cells of type $mux. +No more expansions possible. + + +4.47.13. Executing OPT pass (performing simple optimizations). + +4.47.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + + +4.47.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 59 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Computing hashes of 57 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. + +Removed a total of 2 cells. + +4.47.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_memory_manager.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.47.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_memory_manager. +Performed a total of 0 changes. + +4.47.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 57 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Removed a total of 0 cells. + +4.47.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +4.47.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. +Removed 0 unused cells and 55 unused wires. + + +4.47.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + +4.47.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +4.47.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \harness_memory_manager.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +4.47.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \harness_memory_manager. +Performed a total of 0 changes. + +4.47.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\harness_memory_manager'. +Computing hashes of 57 cells of `\harness_memory_manager'. +Finding duplicate cells in `\harness_memory_manager'. +Removed a total of 0 cells. + +4.47.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +4.47.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \harness_memory_manager.. + +4.47.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module harness_memory_manager. + +4.47.13.16. Finished fast OPT passes. (There is nothing left to do.) + +4.47.14. Executing AIGMAP pass (map logic to AIG). +Module harness_memory_manager: replaced 18 cells with 120 new cells, skipped 39 cells. + replaced 3 cell types: + 14 $_MUX_ + 2 $_OR_ + 2 $_XOR_ + not replaced 3 cell types: + 4 $_AND_ + 4 $_NOT_ + 31 $specify2 + +4.47.15. Executing AIGMAP pass (map logic to AIG). +Module harness_memory_manager: replaced 623 cells with 3832 new cells, skipped 485 cells. + replaced 4 cell types: + 346 $_MUX_ + 1 $_ORNOT_ + 175 $_OR_ + 101 $_XOR_ + not replaced 5 cell types: + 143 $_AND_ + 78 $_NOT_ + 2 $scopeinfo + 203 TRELLIS_FF + 59 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C + +4.47.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +4.47.15.2. Executing ABC9_OPS pass (helper functions for ABC9). + +4.47.15.3. Executing XAIGER backend. + +Extracted 1660 AND gates and 4563 wires from module `harness_memory_manager' to a netlist network with 213 inputs and 195 outputs. + +4.47.15.4. Executing ABC9_EXE pass (technology mapping using ABC9). + +4.47.15.5. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ======== ABC command line "source /abc.script" +ABC: + read_lut /input.lut +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 213/ 195 and = 1241 lev = 40 (1.56) mem = 0.03 MB box = 59 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f -r +ABC: + &ps +ABC: /input : i/o = 213/ 195 and = 1071 lev = 35 (0.91) mem = 0.03 MB ch = 128 box = 46 bb = 0 +ABC: cst = 0 cls = 121 lit = 128 unused = 1173 proof = 0 +ABC: + &if -W 300 -v +ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no +ABC: Node = 1071. Ch = 121. Total mem = 0.33 MB. Peak cut mem = 0.05 MB. +ABC: P: Del = 2695.00. Ar = 421.0. Edge = 682. Cut = 10209. T = 0.00 sec +ABC: P: Del = 2695.00. Ar = 419.0. Edge = 682. Cut = 10160. T = 0.00 sec +ABC: P: Del = 2695.00. Ar = 276.0. Edge = 727. Cut = 12681. T = 0.00 sec +ABC: F: Del = 2694.00. Ar = 254.0. Edge = 706. Cut = 12158. T = 0.00 sec +ABC: A: Del = 2694.00. Ar = 253.0. Edge = 665. Cut = 11942. T = 0.00 sec +ABC: A: Del = 2694.00. Ar = 253.0. Edge = 665. Cut = 11972. T = 0.00 sec +ABC: Total time = 0.01 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: + &ps -l +ABC: /input : i/o = 213/ 195 and = 798 lev = 11 (0.73) mem = 0.02 MB box = 46 bb = 0 +ABC: Mapping (K=7) : lut = 188 edge = 665 lev = 4 (0.36) levB = 11 mem = 0.01 MB +ABC: LUT = 188 : 2=30 16.0 % 3=79 42.0 % 4=36 19.1 % 5=36 19.1 % 6=5 2.7 % 7=2 1.1 % Ave = 3.54 +ABC: + &write -n /output.aig +ABC: + &verify +ABC: Networks are equivalent. Time = 0.01 sec +ABC: + time +ABC: elapse: 0.06 seconds, total: 0.06 seconds + +4.47.15.6. Executing AIGER frontend. + +Removed 1366 unused cells and 2254 unused wires. + +4.47.15.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). +ABC RESULTS: $lut cells: 192 +ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 46 +ABC RESULTS: input signals: 29 +ABC RESULTS: output signals: 57 + +Removing temp directory. + +4.47.16. Executing TECHMAP pass (map to technology primitives). + +4.47.16.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +4.47.16.2. Continuing TECHMAP pass. +Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. +No more expansions possible. + +Removed 34 unused cells and 5237 unused wires. + +4.48. Executing TECHMAP pass (map to technology primitives). + +4.48.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `$lut'. +Successfully finished Verilog frontend. + +4.48.2. Continuing TECHMAP pass. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. +Using template $paramod$93ec78a4b6126ae3554c86addda654d541cb4719$lut for cells of type $lut. +Using template $paramod$77f0cd72667b23cc49e7a8bf984ad848b10003d7$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. +Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101100 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. +Using template $paramod$0939298d426d727b8afa3e9642d621400f6da76d$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111010 for cells of type $lut. +Using template $paramod$9c65fdfac74256c2eb67dd209b598e25d1f0a099$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101010 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. +Using template $paramod$9dd298ae76fb41ac94779a83c068607fbc09ce4f$lut for cells of type $lut. +Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. +Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4$lut for cells of type $lut. +Using template $paramod$e89ac58f360f774aaa6ec82384df6d4f7265bb69$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. +Using template $paramod$497f13c7e9d8874cb8b4b43fa26e853c983f9245$lut for cells of type $lut. +Using template $paramod$b5babc618720ace64bafddb303d6f59fd10af395$lut for cells of type $lut. +Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7$lut for cells of type $lut. +Using template $paramod$d88fd66b53df71bbe52e82830648a83e094f1df5$lut for cells of type $lut. +Using template $paramod$86d1a43c2f1d620ff2cef866448dd1258c868fad$lut for cells of type $lut. +Using template $paramod$9f86076d51df9a4da463f6218e6cd2ddba0c7c03$lut for cells of type $lut. +Using template $paramod$464d286cc302627c2e44b6c4a8450c9bebc28389$lut for cells of type $lut. +Using template $paramod$ef977315233b261d896c6dc860993180807776fe$lut for cells of type $lut. +Using template $paramod$9d68839eeea365341905043c456ff287bcaf2673$lut for cells of type $lut. +Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9$lut for cells of type $lut. +Using template $paramod$a2fe29d35d71ba7d334ca8c2b44396dd8da29e4d$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut. +Using template $paramod$6b7c9c56fc2a32a479d463d5f3b0d3f4673b67f1$lut for cells of type $lut. +Using template $paramod$d0f38a65bef8d9a879a1b1d9ea0674536118587c$lut for cells of type $lut. +Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101100 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001001 for cells of type $lut. +Using template $paramod$cba63f0d3ee9d49c25aa31a3006491d02c8ce45c$lut for cells of type $lut. +Using template $paramod$f5c97e291c8b48d9f1b4239d871ab7639e5a24ac$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. +Using template $paramod$87e4893c126e651fbcc858fe02419505665b5399$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011100 for cells of type $lut. +Using template $paramod$b27834385f52eaf4ed276ecbffb1b05d9c8a8b56$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. +Using template $paramod$5a203febca29678ab5583c0f96bc052b4d0c83a4$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut. +Using template $paramod$8dea978432b975a06d487b3763d4d556f8d362b4$lut for cells of type $lut. +Using template $paramod$6a34cd5b50e324824168b4186d0b04ba5e83b039$lut for cells of type $lut. +Using template $paramod$21a9cf1c7cffed4ea7970972274e8bcced7c7005$lut for cells of type $lut. +Using template $paramod$0c822c65361ce832091b6c90f1a02f1ee0b109d4$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. +Using template $paramod$fea512844f0598125018304dfe86621dbf348f27$lut for cells of type $lut. +Using template $paramod$3718b46f9fc8e7db62b1202aeaec21c3331ed565$lut for cells of type $lut. +Using template $paramod$4f09540800ac966d6e31a7ccf5f32a559a8ce57a$lut for cells of type $lut. +Using template $paramod$05d370b062891027af6b8f05be843bc31de021fe$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut. +Using template $paramod$d9f23974f72a3ab437d1a63d2f34fd3483a6f58d$lut for cells of type $lut. +Using template $paramod$68f172e97da51dd6c1b822ba5fb6b7d7637cc6ee$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. +Using template $paramod$643ce31b2f69d175e7b02dbd6812353f778f3a34$lut for cells of type $lut. +Using template $paramod$87dddaec08d92df4cf510a25382b68aa17e8b57e$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut. +Using template $paramod$aea49449ff8b0f1602874cfa6c3a753c41a1b4a8$lut for cells of type $lut. +Using template $paramod$8829675bb8c52553aed9f101ec0d5ef0c865e5c7$lut for cells of type $lut. +Using template $paramod$4133fe00eb18442862a284ccc67a95f8194d041c$lut for cells of type $lut. +Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8$lut for cells of type $lut. +Using template $paramod$b9d8b7e91a2c68da033af948ea0bd8bdebbaf6b2$lut for cells of type $lut. +Using template $paramod$2713208c8364adbd0af661a2a44fb5c0ddb61fdf$lut for cells of type $lut. +Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b$lut for cells of type $lut. +Using template $paramod$1b4942fad7257f60532954b1eb94a6b84f2e5ae3$lut for cells of type $lut. +Using template $paramod$a03ef989f8f4e1878ce2f5c4e0e3d2dfb54307ef$lut for cells of type $lut. +Using template $paramod$c231c665eed0e54f6cd365c2b07ecdea418a10e6$lut for cells of type $lut. +Using template $paramod$2d73cf21e7a3b53006ebbae47ecc48e73975ec46$lut for cells of type $lut. +Using template $paramod$d575d3554e876f643193272ee6813447059f103f$lut for cells of type $lut. +Using template $paramod$3575d59b4ef3f53a6d1fe17e5c5d02df47e8ec93$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. +No more expansions possible. + + +4.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). +Optimizing LUTs in harness_memory_manager. + Optimizing lut $abc$17166$lut$aiger$o528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$17166$lut$aiger$o488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$17166$lut$aiger$o455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$17187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $abc$17166$lut$aiger17165$550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$17166$lut$aiger17165$550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$17166$lut$aiger17165$497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) + Optimizing lut $abc$17166$lut$aiger17165$497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) + Optimizing lut $abc$17166$lut$aiger17165$519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$17166$lut$aiger$o472.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$17177.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$17177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$17187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$17166$lut$aiger17165$550.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$17186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$17187.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$17166$lut$aiger$o528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$17166$lut$aiger$o528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$17166$lut$aiger$o466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $abc$17166$lut$aiger$o488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$17166$lut$aiger$o488.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$17166$lut$aiger17165$497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$17166$lut$aiger17165$497.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$17166$lut$aiger17165$519.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$17166$lut$aiger17165$537.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $abc$17166$lut$aiger17165$527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$17166$lut$aiger17165$531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) + Optimizing lut $abc$17166$lut$aiger$o415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) +Removed 0 unused cells and 423 unused wires. + +4.50. Executing AUTONAME pass. +Renamed 913 objects in module harness_memory_manager. + + +4.51. Executing HIERARCHY pass (managing design hierarchy). +Attribute `top' found on module `harness_memory_manager'. Setting top module to harness_memory_manager. + +4.51.1. Analyzing design hierarchy.. +Top module: \harness_memory_manager + +4.51.2. Analyzing design hierarchy.. +Top module: \harness_memory_manager +Removed 0 unused modules. + +4.52. Printing statistics. + +=== harness_memory_manager === + + +----------Local Count, excluding submodules. + | + 435 wires + 2001 wire bits + 435 public wires + 2001 public wire bits + 4 ports + 18 port bits + 2 cells + 2 $scopeinfo + 571 submodules + 46 CCU2C + 11 L6MUX21 + 257 LUT4 + 54 PFUMX + 203 TRELLIS_FF + +=== design hierarchy === + + +----------Count including submodules. + | + 2 harness_memory_manager + + +----------Count including submodules. + | + 435 wires + 2001 wire bits + 435 public wires + 2001 public wire bits + 4 ports + 18 port bits + - memories + - memory bits + - processes + 2 cells + 2 $scopeinfo + 571 submodules + 46 CCU2C + 11 L6MUX21 + 257 LUT4 + 54 PFUMX + 203 TRELLIS_FF + +4.53. Executing CHECK pass (checking for obvious problems). +Checking module harness_memory_manager... +Found and reported 0 problems. + +4.54. Executing JSON backend. + +End of script. Logfile hash: 18af420c8c, time: 0.61s, user: 0.53s, system: 0.02s, MEM: 65.89 MB peak +Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) +Time spent: 29% 25x read_verilog (0 sec), 12% 1x abc9_exe (0 sec), ... diff --git a/hardware/v2/synthesis/memory_manager_p8/nextpnr.log b/hardware/v2/synthesis/memory_manager_p8/nextpnr.log new file mode 100644 index 0000000..abef4d2 --- /dev/null +++ b/hardware/v2/synthesis/memory_manager_p8/nextpnr.log @@ -0,0 +1,56 @@ + + +Info: Logic utilisation before packing: +Info: Total LUT4s: 1067/43848 2% +Info: logic LUTs: 851/43848 1% +Info: carry LUTs: 216/43848 0% +Info: RAM LUTs: 0/ 5481 0% +Info: RAMW LUTs: 0/10962 0% + +Info: Total DFFs: 789/43848 1% + +Info: Packing IOs.. +Info: Packing constants.. +Info: Packing carries... +Info: Packing LUTs... +Info: Packing LUT5-7s... +Info: Packing FFs... +Info: 167 FFs paired with LUTs. +Info: Generating derived timing constraints... +Info: Promoting globals... +Info: promoting clock net clk$TRELLIS_IO_IN to global network +Info: Checksum: 0x6e816bc9 + +Info: Device utilisation: +Info: TRELLIS_IO: 272/ 245 111% +Info: DCCA: 1/ 56 1% +Info: DP16KD: 0/ 108 0% +Info: MULT18X18D: 0/ 72 0% +Info: ALU54B: 0/ 36 0% +Info: EHXPLLL: 0/ 4 0% +Info: EXTREFB: 0/ 2 0% +Info: DCUA: 0/ 2 0% +Info: PCSCLKDIV: 0/ 2 0% +Info: IOLOGIC: 0/ 160 0% +Info: SIOLOGIC: 0/ 85 0% +Info: GSR: 0/ 1 0% +Info: JTAGG: 0/ 1 0% +Info: OSCG: 0/ 1 0% +Info: SEDGA: 0/ 1 0% +Info: DTR: 0/ 1 0% +Info: USRMCLK: 0/ 1 0% +Info: CLKDIVF: 0/ 4 0% +Info: ECLKSYNCB: 0/ 10 0% +Info: DLLDELD: 0/ 8 0% +Info: DDRDLL: 0/ 4 0% +Info: DQSBUFM: 0/ 10 0% +Info: TRELLIS_ECLKBUF: 0/ 8 0% +Info: ECLKBRIDGECS: 0/ 2 0% +Info: DCSC: 0/ 2 0% +Info: TRELLIS_FF: 789/ 43848 1% +Info: TRELLIS_COMB: 1117/ 43848 2% +Info: TRELLIS_RAMW: 0/ 5481 0% + +Info: Placed 0 cells based on constraints. +ERROR: Unable to place cell 'input_data[54]$tr_io', no BELs remaining to implement cell type 'TRELLIS_IO' +0 warnings, 1 error diff --git a/hardware/v2/synthesis/memory_manager_p8/top.json b/hardware/v2/synthesis/memory_manager_p8/top.json new file mode 100644 index 0000000..db7d2b8 --- /dev/null +++ b/hardware/v2/synthesis/memory_manager_p8/top.json @@ -0,0 +1,82873 @@ +{ + "creator": "Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101)", + "modules": { + "$__ABC9_DELAY": { + "attributes": { + "abc9_box_id": "00000000000000000000000000000011", + "blackbox": "00000000000000000000000000000001", + "abc9_box": "00000000000000000000000000000001", + "cells_not_processed": "00000000000000000000000000000001", + "src": "/opt/homebrew/bin/../share/yosys/abc9_model.v:2.1-7.10" + }, + "parameter_default_values": { + "DELAY": "00000000000000000000000000000000" + }, + "ports": { + "I": { + "direction": "input", + "bits": [ 2 ] + }, + "O": { + "direction": "output", + "bits": [ 3 ] + } + }, + "cells": { + "$specify$11299": { + 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"CH0_DCOFLTDAC": "DONTCARE", + "CH0_DCOFTNRG": "DONTCARE", + "CH0_DCOIOSTUNE": "DONTCARE", + "CH0_DCOITUNE": "DONTCARE", + "CH0_DCOITUNE4LSB": "DONTCARE", + "CH0_DCOIUPDNX2": "DONTCARE", + "CH0_DCONUOFLSB": "DONTCARE", + "CH0_DCOSCALEI": "DONTCARE", + "CH0_DCOSTARTVAL": "DONTCARE", + "CH0_DCOSTEP": "DONTCARE", + "CH0_DEC_BYPASS": "DONTCARE", + "CH0_ENABLE_CG_ALIGN": "DONTCARE", + "CH0_ENC_BYPASS": "DONTCARE", + "CH0_FF_RX_F_CLK_DIS": "DONTCARE", + "CH0_FF_RX_H_CLK_EN": "DONTCARE", + "CH0_FF_TX_F_CLK_DIS": "DONTCARE", + "CH0_FF_TX_H_CLK_EN": "DONTCARE", + "CH0_GE_AN_ENABLE": "DONTCARE", + "CH0_INVERT_RX": "DONTCARE", + "CH0_INVERT_TX": "DONTCARE", + "CH0_LDR_CORE2TX_SEL": "DONTCARE", + "CH0_LDR_RX2CORE_SEL": "DONTCARE", + "CH0_LEQ_OFFSET_SEL": "DONTCARE", + "CH0_LEQ_OFFSET_TRIM": "DONTCARE", + "CH0_LSM_DISABLE": "DONTCARE", + "CH0_MATCH_2_ENABLE": "DONTCARE", + "CH0_MATCH_4_ENABLE": "DONTCARE", + "CH0_MIN_IPG_CNT": "DONTCARE", + "CH0_PCIE_EI_EN": "DONTCARE", + "CH0_PCIE_MODE": "DONTCARE", + "CH0_PCS_DET_TIME_SEL": "DONTCARE", + "CH0_PDEN_SEL": "DONTCARE", + "CH0_PRBS_ENABLE": "DONTCARE", + "CH0_PRBS_LOCK": "DONTCARE", + "CH0_PRBS_SELECTION": "DONTCARE", + "CH0_PROTOCOL": "DONTCARE", + "CH0_RATE_MODE_RX": "DONTCARE", + "CH0_RATE_MODE_TX": "DONTCARE", + "CH0_RCV_DCC_EN": "DONTCARE", + "CH0_REG_BAND_OFFSET": "DONTCARE", + "CH0_REG_BAND_SEL": "DONTCARE", + "CH0_REG_IDAC_EN": "DONTCARE", + "CH0_REG_IDAC_SEL": "DONTCARE", + "CH0_REQ_EN": "DONTCARE", + "CH0_REQ_LVL_SET": "DONTCARE", + "CH0_RIO_MODE": "DONTCARE", + "CH0_RLOS_SEL": "DONTCARE", + "CH0_RPWDNB": "DONTCARE", + "CH0_RTERM_RX": "DONTCARE", + "CH0_RTERM_TX": "DONTCARE", + "CH0_RXIN_CM": "DONTCARE", + "CH0_RXTERM_CM": "DONTCARE", + "CH0_RX_DCO_CK_DIV": "DONTCARE", + "CH0_RX_DIV11_SEL": "DONTCARE", + "CH0_RX_GEAR_BYPASS": "DONTCARE", + "CH0_RX_GEAR_MODE": "DONTCARE", + "CH0_RX_LOS_CEQ": "DONTCARE", + "CH0_RX_LOS_EN": "DONTCARE", + "CH0_RX_LOS_HYST_EN": "DONTCARE", + "CH0_RX_LOS_LVL": "DONTCARE", + "CH0_RX_RATE_SEL": "DONTCARE", + "CH0_RX_SB_BYPASS": "DONTCARE", + "CH0_SB_BYPASS": "DONTCARE", + "CH0_SEL_SD_RX_CLK": "DONTCARE", + "CH0_TDRV_DAT_SEL": "DONTCARE", + "CH0_TDRV_POST_EN": "DONTCARE", + "CH0_TDRV_PRE_EN": "DONTCARE", + "CH0_TDRV_SLICE0_CUR": "DONTCARE", + "CH0_TDRV_SLICE0_SEL": "DONTCARE", + "CH0_TDRV_SLICE1_CUR": "DONTCARE", + "CH0_TDRV_SLICE1_SEL": "DONTCARE", + "CH0_TDRV_SLICE2_CUR": "DONTCARE", + "CH0_TDRV_SLICE2_SEL": "DONTCARE", + "CH0_TDRV_SLICE3_CUR": "DONTCARE", + "CH0_TDRV_SLICE3_SEL": "DONTCARE", + "CH0_TDRV_SLICE4_CUR": "DONTCARE", + "CH0_TDRV_SLICE4_SEL": "DONTCARE", + "CH0_TDRV_SLICE5_CUR": "DONTCARE", + "CH0_TDRV_SLICE5_SEL": "DONTCARE", + "CH0_TPWDNB": "DONTCARE", + "CH0_TXAMPLITUDE": "DONTCARE", + "CH0_TXDEPOST": "DONTCARE", + "CH0_TXDEPRE": "DONTCARE", + "CH0_TX_CM_SEL": "DONTCARE", + "CH0_TX_DIV11_SEL": "DONTCARE", + "CH0_TX_GEAR_BYPASS": "DONTCARE", + "CH0_TX_GEAR_MODE": "DONTCARE", + "CH0_TX_POST_SIGN": "DONTCARE", + "CH0_TX_PRE_SIGN": "DONTCARE", + "CH0_UC_MODE": "DONTCARE", + "CH0_UDF_COMMA_A": "DONTCARE", + "CH0_UDF_COMMA_B": "DONTCARE", + "CH0_UDF_COMMA_MASK": "DONTCARE", + "CH0_WA_BYPASS": "DONTCARE", + "CH0_WA_MODE": "DONTCARE", + "CH1_AUTO_CALIB_EN": "DONTCARE", + "CH1_AUTO_FACQ_EN": "DONTCARE", + "CH1_BAND_THRESHOLD": "DONTCARE", + "CH1_CALIB_CK_MODE": "DONTCARE", + "CH1_CC_MATCH_1": "DONTCARE", + "CH1_CC_MATCH_2": "DONTCARE", + "CH1_CC_MATCH_3": "DONTCARE", + "CH1_CC_MATCH_4": "DONTCARE", + "CH1_CDR_CNT4SEL": "DONTCARE", + "CH1_CDR_CNT8SEL": "DONTCARE", + "CH1_CDR_MAX_RATE": "DONTCARE", + "CH1_CTC_BYPASS": "DONTCARE", + "CH1_DCOATDCFG": "DONTCARE", + "CH1_DCOATDDLY": "DONTCARE", + "CH1_DCOBYPSATD": "DONTCARE", + "CH1_DCOCALDIV": "DONTCARE", + "CH1_DCOCTLGI": "DONTCARE", + "CH1_DCODISBDAVOID": "DONTCARE", + "CH1_DCOFLTDAC": "DONTCARE", + "CH1_DCOFTNRG": "DONTCARE", + "CH1_DCOIOSTUNE": "DONTCARE", + "CH1_DCOITUNE": "DONTCARE", + "CH1_DCOITUNE4LSB": "DONTCARE", + "CH1_DCOIUPDNX2": "DONTCARE", + "CH1_DCONUOFLSB": "DONTCARE", + "CH1_DCOSCALEI": "DONTCARE", + "CH1_DCOSTARTVAL": "DONTCARE", + "CH1_DCOSTEP": "DONTCARE", + "CH1_DEC_BYPASS": "DONTCARE", + "CH1_ENABLE_CG_ALIGN": "DONTCARE", + "CH1_ENC_BYPASS": "DONTCARE", + "CH1_FF_RX_F_CLK_DIS": "DONTCARE", + "CH1_FF_RX_H_CLK_EN": "DONTCARE", + "CH1_FF_TX_F_CLK_DIS": "DONTCARE", + "CH1_FF_TX_H_CLK_EN": "DONTCARE", + "CH1_GE_AN_ENABLE": "DONTCARE", + "CH1_INVERT_RX": "DONTCARE", + "CH1_INVERT_TX": "DONTCARE", + "CH1_LDR_CORE2TX_SEL": "DONTCARE", + "CH1_LDR_RX2CORE_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_SEL": "DONTCARE", + "CH1_LEQ_OFFSET_TRIM": "DONTCARE", + "CH1_LSM_DISABLE": "DONTCARE", + "CH1_MATCH_2_ENABLE": "DONTCARE", + "CH1_MATCH_4_ENABLE": "DONTCARE", + "CH1_MIN_IPG_CNT": "DONTCARE", + "CH1_PCIE_EI_EN": "DONTCARE", + "CH1_PCIE_MODE": "DONTCARE", + "CH1_PCS_DET_TIME_SEL": "DONTCARE", + "CH1_PDEN_SEL": "DONTCARE", + "CH1_PRBS_ENABLE": "DONTCARE", + "CH1_PRBS_LOCK": "DONTCARE", + "CH1_PRBS_SELECTION": "DONTCARE", + "CH1_PROTOCOL": "DONTCARE", + "CH1_RATE_MODE_RX": "DONTCARE", + "CH1_RATE_MODE_TX": "DONTCARE", + "CH1_RCV_DCC_EN": "DONTCARE", + "CH1_REG_BAND_OFFSET": "DONTCARE", + "CH1_REG_BAND_SEL": "DONTCARE", + "CH1_REG_IDAC_EN": "DONTCARE", + "CH1_REG_IDAC_SEL": "DONTCARE", + "CH1_REQ_EN": "DONTCARE", + "CH1_REQ_LVL_SET": "DONTCARE", + "CH1_RIO_MODE": "DONTCARE", + "CH1_RLOS_SEL": "DONTCARE", + "CH1_RPWDNB": "DONTCARE", + "CH1_RTERM_RX": "DONTCARE", + "CH1_RTERM_TX": "DONTCARE", + "CH1_RXIN_CM": "DONTCARE", + "CH1_RXTERM_CM": "DONTCARE", + "CH1_RX_DCO_CK_DIV": "DONTCARE", + "CH1_RX_DIV11_SEL": "DONTCARE", + "CH1_RX_GEAR_BYPASS": "DONTCARE", + "CH1_RX_GEAR_MODE": "DONTCARE", + "CH1_RX_LOS_CEQ": "DONTCARE", + "CH1_RX_LOS_EN": "DONTCARE", + "CH1_RX_LOS_HYST_EN": "DONTCARE", + "CH1_RX_LOS_LVL": "DONTCARE", + "CH1_RX_RATE_SEL": "DONTCARE", + "CH1_RX_SB_BYPASS": "DONTCARE", + "CH1_SB_BYPASS": "DONTCARE", + "CH1_SEL_SD_RX_CLK": "DONTCARE", + "CH1_TDRV_DAT_SEL": "DONTCARE", + "CH1_TDRV_POST_EN": "DONTCARE", + "CH1_TDRV_PRE_EN": "DONTCARE", + "CH1_TDRV_SLICE0_CUR": "DONTCARE", + "CH1_TDRV_SLICE0_SEL": "DONTCARE", + "CH1_TDRV_SLICE1_CUR": "DONTCARE", + "CH1_TDRV_SLICE1_SEL": "DONTCARE", + "CH1_TDRV_SLICE2_CUR": "DONTCARE", + "CH1_TDRV_SLICE2_SEL": "DONTCARE", + "CH1_TDRV_SLICE3_CUR": "DONTCARE", + "CH1_TDRV_SLICE3_SEL": "DONTCARE", + "CH1_TDRV_SLICE4_CUR": "DONTCARE", + "CH1_TDRV_SLICE4_SEL": "DONTCARE", + "CH1_TDRV_SLICE5_CUR": "DONTCARE", + "CH1_TDRV_SLICE5_SEL": "DONTCARE", + "CH1_TPWDNB": "DONTCARE", + "CH1_TXAMPLITUDE": "DONTCARE", + "CH1_TXDEPOST": "DONTCARE", + "CH1_TXDEPRE": "DONTCARE", + "CH1_TX_CM_SEL": "DONTCARE", + "CH1_TX_DIV11_SEL": "DONTCARE", + "CH1_TX_GEAR_BYPASS": "DONTCARE", + "CH1_TX_GEAR_MODE": "DONTCARE", + "CH1_TX_POST_SIGN": "DONTCARE", + "CH1_TX_PRE_SIGN": "DONTCARE", + "CH1_UC_MODE": "DONTCARE", + "CH1_UDF_COMMA_A": "DONTCARE", + "CH1_UDF_COMMA_B": "DONTCARE", + "CH1_UDF_COMMA_MASK": "DONTCARE", + "CH1_WA_BYPASS": "DONTCARE", + "CH1_WA_MODE": "DONTCARE", + "D_BITCLK_FROM_ND_EN": "DONTCARE", + "D_BITCLK_LOCAL_EN": "DONTCARE", + "D_BITCLK_ND_EN": "DONTCARE", + "D_BUS8BIT_SEL": "DONTCARE", + "D_CDR_LOL_SET": "DONTCARE", + "D_CMUSETBIASI": "DONTCARE", + "D_CMUSETI4CPP": "DONTCARE", + "D_CMUSETI4CPZ": "DONTCARE", + "D_CMUSETI4VCO": "DONTCARE", + "D_CMUSETICP4P": "DONTCARE", + "D_CMUSETICP4Z": "DONTCARE", + "D_CMUSETINITVCT": "DONTCARE", + "D_CMUSETISCL4VCO": "DONTCARE", + "D_CMUSETP1GM": "DONTCARE", + "D_CMUSETP2AGM": "DONTCARE", + "D_CMUSETZGM": "DONTCARE", + "D_DCO_CALIB_TIME_SEL": "DONTCARE", + "D_HIGH_MARK": "DONTCARE", + "D_IB_PWDNB": "DONTCARE", + "D_ISETLOS": "DONTCARE", + "D_LOW_MARK": "DONTCARE", + "D_MACROPDB": "DONTCARE", + "D_PD_ISET": "DONTCARE", + "D_PLL_LOL_SET": "DONTCARE", + "D_REFCK_MODE": "DONTCARE", + "D_REQ_ISET": "DONTCARE", + "D_RG_EN": "DONTCARE", + "D_RG_SET": "DONTCARE", + "D_SETICONST_AUX": "DONTCARE", + "D_SETICONST_CH": "DONTCARE", + "D_SETIRPOLY_AUX": "DONTCARE", + "D_SETIRPOLY_CH": "DONTCARE", + "D_SETPLLRC": "DONTCARE", + "D_SYNC_LOCAL_EN": "DONTCARE", + "D_SYNC_ND_EN": "DONTCARE", + "D_TXPLL_PWDNB": "DONTCARE", + "D_TX_MAX_RATE": "DONTCARE", + "D_TX_VCO_CK_DIV": "DONTCARE", + "D_XGE_MODE": "DONTCARE" + }, + "ports": { + "CH0_HDINP": { + "direction": "input", + "bits": [ 2 ] + }, + "CH1_HDINP": { + "direction": "input", + "bits": [ 3 ] + }, + "CH0_HDINN": { + "direction": "input", + "bits": [ 4 ] + }, + "CH1_HDINN": { + "direction": "input", + "bits": [ 5 ] + }, + "D_TXBIT_CLKP_FROM_ND": { + "direction": "input", + "bits": [ 6 ] + }, + "D_TXBIT_CLKN_FROM_ND": { + "direction": "input", + "bits": [ 7 ] + }, + "D_SYNC_ND": { + "direction": "input", + "bits": [ 8 ] + }, + "D_TXPLL_LOL_FROM_ND": { + "direction": "input", + "bits": [ 9 ] + }, + "CH0_RX_REFCLK": { + "direction": "input", + "bits": [ 10 ] + }, + "CH1_RX_REFCLK": { + "direction": "input", + "bits": [ 11 ] + }, + "CH0_FF_RXI_CLK": { + "direction": "input", + "bits": [ 12 ] + }, + "CH1_FF_RXI_CLK": { + "direction": "input", + "bits": [ 13 ] + }, + "CH0_FF_TXI_CLK": { + "direction": "input", + "bits": [ 14 ] + }, + "CH1_FF_TXI_CLK": { + "direction": "input", + "bits": [ 15 ] + }, + "CH0_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 16 ] + }, + "CH1_FF_EBRD_CLK": { + "direction": "input", + "bits": [ 17 ] + }, + "CH0_FF_TX_D_0": { + "direction": "input", + "bits": [ 18 ] + }, + "CH1_FF_TX_D_0": { + "direction": "input", + "bits": [ 19 ] + }, + "CH0_FF_TX_D_1": { + "direction": "input", + "bits": [ 20 ] + }, + "CH1_FF_TX_D_1": { + "direction": "input", + "bits": [ 21 ] + }, + "CH0_FF_TX_D_2": { + "direction": "input", + "bits": [ 22 ] + }, + "CH1_FF_TX_D_2": { + "direction": "input", + "bits": [ 23 ] + }, + "CH0_FF_TX_D_3": { + "direction": "input", + "bits": [ 24 ] + }, + "CH1_FF_TX_D_3": { + "direction": "input", + "bits": [ 25 ] + }, + "CH0_FF_TX_D_4": { + "direction": "input", + "bits": [ 26 ] + }, + "CH1_FF_TX_D_4": { + "direction": "input", + "bits": [ 27 ] + }, + "CH0_FF_TX_D_5": { + "direction": "input", + "bits": [ 28 ] + }, + "CH1_FF_TX_D_5": { + "direction": "input", + "bits": [ 29 ] + }, + "CH0_FF_TX_D_6": { + "direction": "input", + "bits": [ 30 ] + }, + "CH1_FF_TX_D_6": { + "direction": "input", + "bits": [ 31 ] + }, + "CH0_FF_TX_D_7": { + "direction": "input", + "bits": [ 32 ] + }, + "CH1_FF_TX_D_7": { + "direction": "input", + "bits": [ 33 ] + }, + "CH0_FF_TX_D_8": { + "direction": "input", + "bits": [ 34 ] + }, + "CH1_FF_TX_D_8": { + "direction": "input", + "bits": [ 35 ] + }, + "CH0_FF_TX_D_9": { + "direction": "input", + "bits": [ 36 ] + }, + "CH1_FF_TX_D_9": { + "direction": "input", + "bits": [ 37 ] + }, + "CH0_FF_TX_D_10": { + "direction": "input", + "bits": [ 38 ] + }, + "CH1_FF_TX_D_10": { + "direction": "input", + "bits": [ 39 ] + }, + "CH0_FF_TX_D_11": { + "direction": "input", + "bits": [ 40 ] + }, + "CH1_FF_TX_D_11": { + "direction": "input", + "bits": [ 41 ] + }, + "CH0_FF_TX_D_12": { + "direction": "input", + "bits": [ 42 ] + }, + "CH1_FF_TX_D_12": { + "direction": "input", + "bits": [ 43 ] + }, + "CH0_FF_TX_D_13": { + "direction": "input", + "bits": [ 44 ] + }, + "CH1_FF_TX_D_13": { + "direction": "input", + "bits": [ 45 ] + }, + "CH0_FF_TX_D_14": { + "direction": "input", + "bits": [ 46 ] + }, + "CH1_FF_TX_D_14": { + "direction": "input", + "bits": [ 47 ] + }, + "CH0_FF_TX_D_15": { + "direction": "input", + "bits": [ 48 ] + }, + "CH1_FF_TX_D_15": { + "direction": "input", + "bits": [ 49 ] + }, + "CH0_FF_TX_D_16": { + "direction": "input", + "bits": [ 50 ] + }, + "CH1_FF_TX_D_16": { + "direction": "input", + "bits": [ 51 ] + }, + "CH0_FF_TX_D_17": { + "direction": "input", + "bits": [ 52 ] + }, + "CH1_FF_TX_D_17": { + "direction": "input", + "bits": [ 53 ] + }, + "CH0_FF_TX_D_18": { + "direction": "input", + "bits": [ 54 ] + }, + "CH1_FF_TX_D_18": { + "direction": "input", + "bits": [ 55 ] + }, + "CH0_FF_TX_D_19": { + "direction": "input", + "bits": [ 56 ] + }, + "CH1_FF_TX_D_19": { + "direction": "input", + "bits": [ 57 ] + }, + "CH0_FF_TX_D_20": { + "direction": "input", + "bits": [ 58 ] + }, + "CH1_FF_TX_D_20": { + "direction": "input", + "bits": [ 59 ] + }, + "CH0_FF_TX_D_21": { + "direction": "input", + "bits": [ 60 ] + }, + "CH1_FF_TX_D_21": { + "direction": "input", + "bits": [ 61 ] + }, + "CH0_FF_TX_D_22": { + "direction": "input", + "bits": [ 62 ] + }, + "CH1_FF_TX_D_22": { + "direction": "input", + "bits": [ 63 ] + }, + "CH0_FF_TX_D_23": { + "direction": "input", + "bits": [ 64 ] + }, + "CH1_FF_TX_D_23": { + "direction": "input", + "bits": [ 65 ] + }, + "CH0_FFC_EI_EN": { + "direction": "input", + "bits": [ 66 ] + }, + "CH1_FFC_EI_EN": { + "direction": "input", + "bits": [ 67 ] + }, + "CH0_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 68 ] + }, + "CH1_FFC_PCIE_DET_EN": { + "direction": "input", + "bits": [ 69 ] + }, + "CH0_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 70 ] + }, + "CH1_FFC_PCIE_CT": { + "direction": "input", + "bits": [ 71 ] + }, + "CH0_FFC_SB_INV_RX": { + "direction": "input", + "bits": [ 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b/hardware/v2/synthesis/memory_manager_p8/yosys.log @@ -0,0 +1,2344 @@ + + /----------------------------------------------------------------------------\ + | yosys -- Yosys Open SYnthesis Suite | + | Copyright (C) 2012 - 2026 Claire Xenia Wolf | + | Distributed under an ISC-like license, type "license" to see terms | + \----------------------------------------------------------------------------/ + Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) + +-- Parsing `hardware/v2/rtl/memory_manager.v' using frontend ` -vlog2k' -- + +1. Executing Verilog-2005 frontend: hardware/v2/rtl/memory_manager.v +Parsing Verilog input from `hardware/v2/rtl/memory_manager.v' to AST representation. +Storing AST representation for module `$abstract\memory_manager'. +Successfully finished Verilog frontend. + +-- Parsing `hardware/v2/rtl/prefetch_engine.v' using frontend ` -vlog2k' -- + +2. Executing Verilog-2005 frontend: hardware/v2/rtl/prefetch_engine.v +Parsing Verilog input from `hardware/v2/rtl/prefetch_engine.v' to AST representation. +Storing AST representation for module `$abstract\prefetch_engine'. +Successfully finished Verilog frontend. + +-- Running command `synth_ecp5 -json hardware/v2/synthesis/memory_manager_p8/top.json -top memory_manager' -- + +3. Executing SYNTH_LATTICE pass. + +3.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_sim_ecp5.v' to AST representation. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\$__ABC9_LUT5'. +Generating RTLIL representation for module `\$__ABC9_LUT6'. +Generating RTLIL representation for module `\$__ABC9_LUT7'. +Generating RTLIL representation for module `\L6MUX21'. +Generating RTLIL representation for module `\TRELLIS_RAM16X2'. +Generating RTLIL representation for module `\PFUMX'. +Generating RTLIL representation for module `\TRELLIS_DPR16X4'. +Generating RTLIL representation for module `\DPR16X4C'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\TRELLIS_FF'. +Generating RTLIL representation for module `\TRELLIS_IO'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\TRELLIS_COMB'. +Generating RTLIL representation for module `\VLO'. +Generating RTLIL representation for module `\VHI'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `\CCU2C'. +Generating RTLIL representation for module `\DP16KD'. +Replacing existing blackbox module `\FD1P3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:2.1-2.261. +Generating RTLIL representation for module `\FD1P3AX'. +Replacing existing blackbox module `\FD1P3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:3.1-3.261. +Generating RTLIL representation for module `\FD1P3AY'. +Replacing existing blackbox module `\FD1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:4.1-4.261. +Generating RTLIL representation for module `\FD1P3BX'. +Replacing existing blackbox module `\FD1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:5.1-5.261. +Generating RTLIL representation for module `\FD1P3DX'. +Replacing existing blackbox module `\FD1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:6.1-6.261. +Generating RTLIL representation for module `\FD1P3IX'. +Replacing existing blackbox module `\FD1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:7.1-7.261. +Generating RTLIL representation for module `\FD1P3JX'. +Replacing existing blackbox module `\FD1S3AX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:8.1-8.261. +Generating RTLIL representation for module `\FD1S3AX'. +Replacing existing blackbox module `\FD1S3AY' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:9.1-9.261. +Generating RTLIL representation for module `\FD1S3AY'. +Replacing existing blackbox module `\FD1S3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:10.1-10.261. +Generating RTLIL representation for module `\FD1S3BX'. +Replacing existing blackbox module `\FD1S3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:11.1-11.261. +Generating RTLIL representation for module `\FD1S3DX'. +Replacing existing blackbox module `\FD1S3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:12.1-12.261. +Generating RTLIL representation for module `\FD1S3IX'. +Replacing existing blackbox module `\FD1S3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:13.1-13.261. +Generating RTLIL representation for module `\FD1S3JX'. +Replacing existing blackbox module `\IFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:26.1-26.301. +Generating RTLIL representation for module `\IFS1P3BX'. +Replacing existing blackbox module `\IFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:27.1-27.301. +Generating RTLIL representation for module `\IFS1P3DX'. +Replacing existing blackbox module `\IFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:28.1-28.301. +Generating RTLIL representation for module `\IFS1P3IX'. +Replacing existing blackbox module `\IFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:29.1-29.301. +Generating RTLIL representation for module `\IFS1P3JX'. +Replacing existing blackbox module `\OFS1P3BX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:31.1-31.302. +Generating RTLIL representation for module `\OFS1P3BX'. +Replacing existing blackbox module `\OFS1P3DX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:32.1-32.302. +Generating RTLIL representation for module `\OFS1P3DX'. +Replacing existing blackbox module `\OFS1P3IX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:33.1-33.302. +Generating RTLIL representation for module `\OFS1P3IX'. +Replacing existing blackbox module `\OFS1P3JX' at /opt/homebrew/bin/../share/yosys/lattice/cells_ff.vh:34.1-34.302. +Generating RTLIL representation for module `\OFS1P3JX'. +Replacing existing blackbox module `\IB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:2.1-2.157. +Generating RTLIL representation for module `\IB'. +Replacing existing blackbox module `\IBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:3.1-3.157. +Generating RTLIL representation for module `\IBPU'. +Replacing existing blackbox module `\IBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:4.1-4.157. +Generating RTLIL representation for module `\IBPD'. +Replacing existing blackbox module `\OB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:5.1-5.157. +Generating RTLIL representation for module `\OB'. +Replacing existing blackbox module `\OBZ' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:6.1-6.164. +Generating RTLIL representation for module `\OBZ'. +Replacing existing blackbox module `\OBZPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:7.1-7.164. +Generating RTLIL representation for module `\OBZPU'. +Replacing existing blackbox module `\OBZPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:8.1-8.164. +Generating RTLIL representation for module `\OBZPD'. +Replacing existing blackbox module `\OBCO' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:9.1-9.90. +Generating RTLIL representation for module `\OBCO'. +Replacing existing blackbox module `\BB' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:10.1-10.179. +Generating RTLIL representation for module `\BB'. +Replacing existing blackbox module `\BBPU' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:11.1-11.179. +Generating RTLIL representation for module `\BBPU'. +Replacing existing blackbox module `\BBPD' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:12.1-12.179. +Generating RTLIL representation for module `\BBPD'. +Replacing existing blackbox module `\ILVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:13.1-13.139. +Generating RTLIL representation for module `\ILVDS'. +Replacing existing blackbox module `\OLVDS' at /opt/homebrew/bin/../share/yosys/lattice/cells_io.vh:14.1-14.146. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +3.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_bb_ecp5.v' to AST representation. +Generating RTLIL representation for module `\GSR'. +Generating RTLIL representation for module `\PUR'. +Generating RTLIL representation for module `\SGSR'. +Generating RTLIL representation for module `\PDPW16KD'. +Generating RTLIL representation for module `\MULT18X18D'. +Generating RTLIL representation for module `\ALU54B'. +Generating RTLIL representation for module `\CLKDIVF'. +Generating RTLIL representation for module `\PCSCLKDIV'. +Generating RTLIL representation for module `\DCSC'. +Generating RTLIL representation for module `\DCCA'. +Generating RTLIL representation for module `\ECLKSYNCB'. +Generating RTLIL representation for module `\ECLKBRIDGECS'. +Generating RTLIL representation for module `\DELAYF'. +Generating RTLIL representation for module `\DELAYG'. +Generating RTLIL representation for module `\USRMCLK'. +Generating RTLIL representation for module `\DQSBUFM'. +Generating RTLIL representation for module `\DDRDLLA'. +Generating RTLIL representation for module `\DLLDELD'. +Generating RTLIL representation for module `\IDDRX1F'. +Generating RTLIL representation for module `\IDDRX2F'. +Generating RTLIL representation for module `\IDDR71B'. +Generating RTLIL representation for module `\IDDRX2DQA'. +Generating RTLIL representation for module `\ODDRX1F'. +Generating RTLIL representation for module `\ODDRX2F'. +Generating RTLIL representation for module `\ODDR71B'. +Generating RTLIL representation for module `\OSHX2A'. +Generating RTLIL representation for module `\TSHX2DQA'. +Generating RTLIL representation for module `\TSHX2DQSA'. +Generating RTLIL representation for module `\ODDRX2DQA'. +Generating RTLIL representation for module `\ODDRX2DQSB'. +Generating RTLIL representation for module `\EHXPLLL'. +Generating RTLIL representation for module `\DTR'. +Generating RTLIL representation for module `\OSCG'. +Generating RTLIL representation for module `\EXTREFB'. +Generating RTLIL representation for module `\JTAGG'. +Generating RTLIL representation for module `\DCUA'. +Successfully finished Verilog frontend. + +3.3. Executing HIERARCHY pass (managing design hierarchy). + +3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\memory_manager'. +Generating RTLIL representation for module `\memory_manager'. + +3.4.1. Analyzing design hierarchy.. +Top module: \memory_manager +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 + +3.4.2. Executing AST frontend in derive mode using pre-parsed AST for module `\prefetch_engine'. +Parameter \DATA_WIDTH = 8 +Parameter \P_IN = 8 +Parameter \ADDR_WIDTH = 23 +Generating RTLIL representation for module `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine'. + +3.4.3. Analyzing design hierarchy.. +Top module: \memory_manager +Used module: $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine + +3.4.4. Analyzing design hierarchy.. +Top module: \memory_manager +Used module: $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine +Removing unused module `$abstract\prefetch_engine'. +Removing unused module `$abstract\memory_manager'. +Removed 2 unused modules. + +3.5. Executing PROC pass (convert processes to netlists). + +3.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +3.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed 1 dead cases from process $proc$hardware/v2/rtl/prefetch_engine.v:58$325 in module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine. +Marked 6 switch rules as full_case in process $proc$hardware/v2/rtl/prefetch_engine.v:58$325 in module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine. +Marked 6 switch rules as full_case in process $proc$hardware/v2/rtl/memory_manager.v:157$238 in module memory_manager. +Removed a total of 1 dead cases. + +3.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 5 redundant assignments. +Promoted 16 assignments to connections. + +3.5.4. Executing PROC_INIT pass (extract init attributes). + +3.5.5. Executing PROC_ARST pass (detect async resets in processes). + +3.5.6. Executing PROC_ROM pass (convert switches to ROMs). +Converted 0 switches. + + +3.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'. + 1/20: $3$lookahead\tile_w$324[63:0]$354 + 2/20: $3$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:105$322[31:0]$353 + 3/20: $3$lookahead\tile_x$323[63:0]$339 + 4/20: $3$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:87$321[31:0]$338 + 5/20: $2$lookahead\tile_w$324[63:0]$337 + 6/20: $2$lookahead\tile_x$323[63:0]$336 + 7/20: $2$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:105$322[31:0]$335 + 8/20: $2$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:87$321[31:0]$334 + 9/20: $0\mem_req[0:0] + 10/20: $0\fetch_done[0:0] + 11/20: $1$lookahead\tile_w$324[63:0]$333 + 12/20: $1$lookahead\tile_x$323[63:0]$332 + 13/20: $1$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:105$322[31:0]$331 + 14/20: $1$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:87$321[31:0]$330 + 15/20: $0\byte_idx[3:0] + 16/20: $0\fetch_busy[0:0] + 17/20: $0\state[1:0] + 18/20: $0\mem_wdata[7:0] + 19/20: $0\mem_addr[22:0] + 20/20: $0\mem_wr[0:0] +Creating decoders for process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + 1/46: $5$lookahead\bank_ready$237[1:0]$292 + 2/46: $3$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:247$227[0:0]$291 + 3/46: $4$lookahead\bank_ready$237[1:0]$278 + 4/46: $3$lookahead\bank_ready$237[1:0]$277 + 5/46: $2$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:247$227[0:0]$276 + 6/46: $2$lookahead\bank_ready$237[1:0]$264 + 7/46: $2$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:183$226[0:0]$257 + 8/46: $2$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$263 + 9/46: $2$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_DATA[63:0]$262 + 10/46: $2$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_ADDR[0:0]$261 + 11/46: $2$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$260 + 12/46: $2$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_DATA[63:0]$259 + 13/46: $2$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_ADDR[0:0]$258 + 14/46: $1$lookahead\bank_ready$237[1:0]$256 + 15/46: $0\pf_start[0:0] + 16/46: $0\result_ready[0:0] + 17/46: $0\job_done[0:0] + 18/46: $1$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$255 + 19/46: $1$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_DATA[63:0]$254 + 20/46: $1$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_ADDR[0:0]$253 + 21/46: $1$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$252 + 22/46: $1$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_DATA[63:0]$251 + 23/46: $1$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_ADDR[0:0]$250 + 24/46: $1$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:247$227[0:0]$249 + 25/46: $1$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:183$226[0:0]$248 + 26/46: $0\wr_mem_wdata[7:0] + 27/46: $0\wr_mem_addr[22:0] + 28/46: $0\wr_mem_req[0:0] + 29/46: $0\pf_pending_bank[0:0] + 30/46: $0\pf_pending_w[22:0] + 31/46: $0\pf_pending_x[22:0] + 32/46: $0\pf_pending[0:0] + 33/46: $0\pf_target_bank[0:0] + 34/46: $0\pf_w_addr[22:0] + 35/46: $0\pf_x_addr[22:0] + 36/46: $0\current_bank[0:0] + 37/46: $0\tile_idx[15:0] + 38/46: $0\n_tiles_reg[15:0] + 39/46: $0\result_addr_reg[22:0] + 40/46: $0\w_base_reg[22:0] + 41/46: $0\x_base_reg[22:0] + 42/46: $0\state[2:0] + 43/46: $0\tile_last[0:0] + 44/46: $0\weight_data[63:0] + 45/46: $0\input_data[63:0] + 46/46: $0\operand_valid[0:0] + +3.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). + +3.5.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_req' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'. + created $dff cell `$procdff$1066' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_wr' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'. + created $dff cell `$procdff$1067' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_addr' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'. + created $dff cell `$procdff$1068' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\mem_wdata' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'. + created $dff cell `$procdff$1069' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\state' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'. + created $dff cell `$procdff$1070' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\fetch_busy' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'. + created $dff cell `$procdff$1071' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\fetch_done' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'. + created $dff cell `$procdff$1072' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\tile_x' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'. + created $dff cell `$procdff$1073' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\tile_w' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'. + created $dff cell `$procdff$1074' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.\byte_idx' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'. + created $dff cell `$procdff$1075' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:87$321' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'. + created $dff cell `$procdff$1076' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$bitselwrite$pos$hardware/v2/rtl/prefetch_engine.v:105$322' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'. + created $dff cell `$procdff$1077' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$lookahead\tile_x$323' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'. + created $dff cell `$procdff$1078' with positive edge clock. +Creating register for signal `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$lookahead\tile_w$324' using process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'. + created $dff cell `$procdff$1079' with positive edge clock. +Creating register for signal `\memory_manager.\job_done' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1080' with positive edge clock. +Creating register for signal `\memory_manager.\operand_valid' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1081' with positive edge clock. +Creating register for signal `\memory_manager.\input_data' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1082' with positive edge clock. +Creating register for signal `\memory_manager.\weight_data' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1083' with positive edge clock. +Creating register for signal `\memory_manager.\tile_last' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1084' with positive edge clock. +Creating register for signal `\memory_manager.\result_ready' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1085' with positive edge clock. +Creating register for signal `\memory_manager.\state' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1086' with positive edge clock. +Creating register for signal `\memory_manager.\x_base_reg' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1087' with positive edge clock. +Creating register for signal `\memory_manager.\w_base_reg' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1088' with positive edge clock. +Creating register for signal `\memory_manager.\result_addr_reg' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1089' with positive edge clock. +Creating register for signal `\memory_manager.\n_tiles_reg' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1090' with positive edge clock. +Creating register for signal `\memory_manager.\tile_idx' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1091' with positive edge clock. +Creating register for signal `\memory_manager.\current_bank' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1092' with positive edge clock. +Creating register for signal `\memory_manager.\bank_ready' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1093' with positive edge clock. +Creating register for signal `\memory_manager.\pf_start' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1094' with positive edge clock. +Creating register for signal `\memory_manager.\pf_x_addr' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1095' with positive edge clock. +Creating register for signal `\memory_manager.\pf_w_addr' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1096' with positive edge clock. +Creating register for signal `\memory_manager.\pf_target_bank' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1097' with positive edge clock. +Creating register for signal `\memory_manager.\pf_pending' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1098' with positive edge clock. +Creating register for signal `\memory_manager.\pf_pending_x' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1099' with positive edge clock. +Creating register for signal `\memory_manager.\pf_pending_w' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1100' with positive edge clock. +Creating register for signal `\memory_manager.\pf_pending_bank' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1101' with positive edge clock. +Creating register for signal `\memory_manager.\wr_mem_req' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1102' with positive edge clock. +Creating register for signal `\memory_manager.\wr_mem_addr' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1103' with positive edge clock. +Creating register for signal `\memory_manager.\wr_mem_wdata' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1104' with positive edge clock. +Creating register for signal `\memory_manager.$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:183$226' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1105' with positive edge clock. +Creating register for signal `\memory_manager.$bitselwrite$pos$hardware/v2/rtl/memory_manager.v:247$227' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1106' with positive edge clock. +Creating register for signal `\memory_manager.$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_ADDR' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1107' with positive edge clock. +Creating register for signal `\memory_manager.$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_DATA' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1108' with positive edge clock. +Creating register for signal `\memory_manager.$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1109' with positive edge clock. +Creating register for signal `\memory_manager.$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_ADDR' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1110' with positive edge clock. +Creating register for signal `\memory_manager.$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_DATA' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1111' with positive edge clock. +Creating register for signal `\memory_manager.$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1112' with positive edge clock. +Creating register for signal `\memory_manager.$lookahead\bank_ready$237' using process `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. + created $dff cell `$procdff$1113' with positive edge clock. + +3.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). + +3.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 7 empty switches in `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'. +Removing empty process `$paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine.$proc$hardware/v2/rtl/prefetch_engine.v:58$325'. +Found and cleaned up 14 empty switches in `\memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. +Removing empty process `memory_manager.$proc$hardware/v2/rtl/memory_manager.v:157$238'. +Cleaned up 21 empty switches. + +3.5.12. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine. + +Optimizing module memory_manager. + + +3.6. Executing CHECK pass (checking for obvious problems). +Checking module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine... +Checking module memory_manager... +Found and reported 0 problems. + +3.7. Executing FLATTEN pass (flatten design). +Deleting now unused module $paramod$4802f1ca3572ed92e504a0cda0b383b31954c659\prefetch_engine. + + +3.8. Executing TRIBUF pass. + +3.9. Executing DEMINOUT pass (demote inout ports to input or output). + +3.10. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + + +3.11. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. +Removed 47 unused cells and 307 unused wires. + + +3.12. Executing CHECK pass (checking for obvious problems). +Checking module memory_manager... +Found and reported 0 problems. + +3.13. Executing OPT pass (performing simple optimizations). + +3.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + +3.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 375 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 300 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 297 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 296 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. + +Removed a total of 79 cells. + +3.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Replacing known input bits on port B of cell $procmux$1049: \operand_valid -> 1'1 + Replacing known input bits on port A of cell $procmux$1047: \operand_valid -> 1'0 + Analyzing evaluation results. + dead port 1/2 on $mux $flatten\u_prefetch.$procmux$375. + dead port 2/2 on $mux $flatten\u_prefetch.$procmux$372. + dead port 1/2 on $mux $flatten\u_prefetch.$procmux$412. + dead port 1/2 on $mux $flatten\u_prefetch.$procmux$420. + dead port 1/2 on $mux $flatten\u_prefetch.$procmux$394. + dead port 2/2 on $mux $flatten\u_prefetch.$procmux$391. + dead port 1/2 on $mux $procmux$677. + dead port 1/2 on $mux $procmux$671. + dead port 1/2 on $mux $procmux$665. + dead port 1/2 on $mux $procmux$659. + dead port 1/2 on $mux $procmux$653. + dead port 1/2 on $mux $procmux$647. + dead port 1/2 on $mux $procmux$620. + dead port 1/2 on $mux $procmux$610. + dead port 2/2 on $mux $procmux$607. + dead port 1/2 on $mux $procmux$584. + dead port 2/2 on $mux $procmux$581. +Removed 17 multiplexer ports. + + +3.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memory_manager. + New ctrl vector for $pmux cell $flatten\u_prefetch.$procmux$414: { $auto$opt_reduce.cc:137:opt_pmux$1118 $flatten\u_prefetch.$procmux$409_CMP } + New ctrl vector for $pmux cell $flatten\u_prefetch.$procmux$406: { $auto$opt_reduce.cc:137:opt_pmux$1120 $flatten\u_prefetch.$procmux$408_CMP } + Consolidated identical input bits for $mux cell $procmux$662: + Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$procmux$662_Y + New ports: A=1'0, B=1'1, Y=$procmux$662_Y [0] + New connections: $procmux$662_Y [63:1] = { $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] $procmux$662_Y [0] } + Consolidated identical input bits for $mux cell $procmux$644: + Old ports: A=64'0000000000000000000000000000000000000000000000000000000000000000, B=64'1111111111111111111111111111111111111111111111111111111111111111, Y=$procmux$644_Y + New ports: A=1'0, B=1'1, Y=$procmux$644_Y [0] + New connections: $procmux$644_Y [63:1] = { $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] $procmux$644_Y [0] } + Optimizing cells in module \memory_manager. + Consolidated identical input bits for $mux cell $procmux$713: + Old ports: A=$2$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$260, B=64'0000000000000000000000000000000000000000000000000000000000000000, Y=$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 + New ports: A=$procmux$662_Y [0], B=1'0, Y=$0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] + New connections: $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [63:1] = { $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] $0$memwr$\bank_x$hardware/v2/rtl/memory_manager.v:181$228_EN[63:0]$243 [0] } + Consolidated identical input bits for $mux cell $procmux$704: + Old ports: A=$2$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$263, B=64'0000000000000000000000000000000000000000000000000000000000000000, Y=$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 + New ports: A=$procmux$644_Y [0], B=1'0, Y=$0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] + New connections: $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [63:1] = { $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] $0$memwr$\bank_w$hardware/v2/rtl/memory_manager.v:182$229_EN[63:0]$246 [0] } + Optimizing cells in module \memory_manager. +Performed a total of 6 changes. + +3.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 281 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 278 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 276 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. + +Removed a total of 5 cells. + +3.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. +Removed 0 unused cells and 101 unused wires. + + +3.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + +3.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memory_manager. +Performed a total of 0 changes. + +3.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 276 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Removed a total of 0 cells. + +3.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +3.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. + +3.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + +3.13.16. Finished fast OPT passes. (There is nothing left to do.) + +3.14. Executing FSM pass (extract and optimize FSM). + +3.14.1. Executing FSM_DETECT pass (finding FSMs in design). +Found FSM state register memory_manager.u_prefetch.state. +Not marking memory_manager.u_prefetch.mem_wdata as FSM state register: + Users of register don't seem to benefit from recoding. +Found FSM state register memory_manager.state. + +3.14.2. Executing FSM_EXTRACT pass (extracting FSM from design). +Extracting FSM `\u_prefetch.state' from module `\memory_manager'. + found $dff cell for state register: $flatten\u_prefetch.$procdff$1070 + root of input selection tree: $flatten\u_prefetch.$0\state[1:0] + found reset state: 2'00 (guessed from mux tree) + found ctrl input: \rst + found ctrl input: $flatten\u_prefetch.$procmux$407_CMP + found ctrl input: $flatten\u_prefetch.$procmux$373_CMP + found ctrl input: $flatten\u_prefetch.$procmux$392_CMP + found ctrl input: $flatten\u_prefetch.$procmux$410_CMP + found state code: 2'00 + found ctrl input: \mem_ready + found ctrl input: $flatten\u_prefetch.$eq$hardware/v2/rtl/prefetch_engine.v:106$364_Y + found state code: 2'11 + found state code: 2'10 + found ctrl input: \pf_start + found state code: 2'01 + found ctrl output: $flatten\u_prefetch.$procmux$410_CMP + found ctrl output: $flatten\u_prefetch.$procmux$392_CMP + found ctrl output: $flatten\u_prefetch.$procmux$373_CMP + found ctrl output: $flatten\u_prefetch.$procmux$407_CMP + ctrl inputs: { $flatten\u_prefetch.$eq$hardware/v2/rtl/prefetch_engine.v:106$364_Y \pf_start \mem_ready \rst } + ctrl outputs: { $flatten\u_prefetch.$0\state[1:0] $flatten\u_prefetch.$procmux$373_CMP $flatten\u_prefetch.$procmux$392_CMP $flatten\u_prefetch.$procmux$407_CMP $flatten\u_prefetch.$procmux$410_CMP } + transition: 2'00 4'-0-0 -> 2'00 6'000001 + transition: 2'00 4'-1-0 -> 2'01 6'010001 + transition: 2'00 4'---1 -> 2'00 6'000001 + transition: 2'10 4'--00 -> 2'10 6'101000 + transition: 2'10 4'0-10 -> 2'10 6'101000 + transition: 2'10 4'1-10 -> 2'11 6'111000 + transition: 2'10 4'---1 -> 2'00 6'001000 + transition: 2'01 4'--00 -> 2'01 6'010100 + transition: 2'01 4'0-10 -> 2'01 6'010100 + transition: 2'01 4'1-10 -> 2'10 6'100100 + transition: 2'01 4'---1 -> 2'00 6'000100 + transition: 2'11 4'---0 -> 2'00 6'000010 + transition: 2'11 4'---1 -> 2'00 6'000010 +Extracting FSM `\state' from module `\memory_manager'. + found $dff cell for state register: $procdff$1086 + root of input selection tree: $0\state[2:0] + found reset state: 3'000 (guessed from mux tree) + found ctrl input: \rst + found ctrl input: $eq$hardware/v2/rtl/memory_manager.v:151$231_Y + found ctrl input: $eq$hardware/v2/rtl/memory_manager.v:151$230_Y + found ctrl input: $procmux$691_CMP + found ctrl input: $procmux$1017_CMP + found ctrl input: $procmux$1001_CMP + found ctrl input: $procmux$1062_CMP + found state code: 3'000 + found ctrl input: \mem_ready + found state code: 3'101 + found ctrl input: $logic_and$hardware/v2/rtl/memory_manager.v:284$320_Y + found state code: 3'100 + found ctrl input: $logic_and$hardware/v2/rtl/memory_manager.v:245$290_Y + found ctrl input: $eq$hardware/v2/rtl/memory_manager.v:252$303_Y + found state code: 3'011 + found ctrl input: $logic_or$hardware/v2/rtl/memory_manager.v:227$281_Y + found state code: 3'010 + found ctrl input: \job_start + found state code: 3'001 + found ctrl output: $eq$hardware/v2/rtl/memory_manager.v:151$231_Y + found ctrl output: $eq$hardware/v2/rtl/memory_manager.v:151$230_Y + found ctrl output: $procmux$691_CMP + found ctrl output: $procmux$1017_CMP + found ctrl output: $procmux$1001_CMP + found ctrl output: $procmux$1062_CMP + ctrl inputs: { $logic_and$hardware/v2/rtl/memory_manager.v:284$320_Y $eq$hardware/v2/rtl/memory_manager.v:252$303_Y $logic_and$hardware/v2/rtl/memory_manager.v:245$290_Y $logic_or$hardware/v2/rtl/memory_manager.v:227$281_Y \mem_ready \job_start \rst } + ctrl outputs: { $procmux$1062_CMP $procmux$1017_CMP $procmux$1001_CMP $procmux$691_CMP $0\state[2:0] $eq$hardware/v2/rtl/memory_manager.v:151$231_Y $eq$hardware/v2/rtl/memory_manager.v:151$230_Y } + transition: 3'000 7'-----00 -> 3'000 9'100000000 + transition: 3'000 7'-----10 -> 3'001 9'100000100 + transition: 3'000 7'------1 -> 3'000 9'100000000 + transition: 3'100 7'------0 -> 3'101 9'000010101 + transition: 3'100 7'------1 -> 3'000 9'000000001 + transition: 3'010 7'--0---0 -> 3'010 9'010001000 + transition: 3'010 7'-01---0 -> 3'010 9'010001000 + transition: 3'010 7'-11---0 -> 3'011 9'010001100 + transition: 3'010 7'------1 -> 3'000 9'010000000 + transition: 3'001 7'---0--0 -> 3'001 9'001000100 + transition: 3'001 7'---1--0 -> 3'010 9'001001000 + transition: 3'001 7'------1 -> 3'000 9'001000000 + transition: 3'101 7'----0-0 -> 3'101 9'000010110 + transition: 3'101 7'----1-0 -> 3'000 9'000000010 + transition: 3'101 7'------1 -> 3'000 9'000000010 + transition: 3'011 7'0-----0 -> 3'011 9'000101100 + transition: 3'011 7'1-----0 -> 3'100 9'000110000 + transition: 3'011 7'------1 -> 3'000 9'000100000 + +3.14.3. Executing FSM_OPT pass (simple optimizations of FSMs). +Optimizing FSM `$fsm$\state$1127' from module `\memory_manager'. +Optimizing FSM `$fsm$\u_prefetch.state$1121' from module `\memory_manager'. + Merging pattern 4'---0 and 4'---1 from group (3 0 6'000010). + Merging pattern 4'---1 and 4'---0 from group (3 0 6'000010). + +3.14.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. +Removed 27 unused cells and 27 unused wires. + + +3.14.5. Executing FSM_OPT pass (simple optimizations of FSMs). +Optimizing FSM `$fsm$\u_prefetch.state$1121' from module `\memory_manager'. + Removing unused output signal $flatten\u_prefetch.$0\state[1:0] [0]. + Removing unused output signal $flatten\u_prefetch.$0\state[1:0] [1]. +Optimizing FSM `$fsm$\state$1127' from module `\memory_manager'. + Removing unused output signal $0\state[2:0] [0]. + Removing unused output signal $0\state[2:0] [1]. + Removing unused output signal $0\state[2:0] [2]. + +3.14.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). +Recoding FSM `$fsm$\u_prefetch.state$1121' from module `\memory_manager' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 00 -> ---1 + 10 -> --1- + 01 -> -1-- + 11 -> 1--- +Recoding FSM `$fsm$\state$1127' from module `\memory_manager' using `auto' encoding: + mapping auto encoding to `one-hot` for this FSM. + 000 -> -----1 + 100 -> ----1- + 010 -> ---1-- + 001 -> --1--- + 101 -> -1---- + 011 -> 1----- + +3.14.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +FSM `$fsm$\u_prefetch.state$1121' from module `memory_manager': +------------------------------------- + + Information on FSM $fsm$\u_prefetch.state$1121 (\u_prefetch.state): + + Number of input signals: 4 + Number of output signals: 4 + Number of state bits: 4 + + Input signals: + 0: \rst + 1: \mem_ready + 2: \pf_start + 3: $flatten\u_prefetch.$eq$hardware/v2/rtl/prefetch_engine.v:106$364_Y + + Output signals: + 0: $flatten\u_prefetch.$procmux$410_CMP + 1: $flatten\u_prefetch.$procmux$407_CMP + 2: $flatten\u_prefetch.$procmux$392_CMP + 3: $flatten\u_prefetch.$procmux$373_CMP + + State encoding: + 0: 4'---1 + 1: 4'--1- + 2: 4'-1-- + 3: 4'1--- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 4'-0-0 -> 0 4'0001 + 1: 0 4'---1 -> 0 4'0001 + 2: 0 4'-1-0 -> 2 4'0001 + 3: 1 4'---1 -> 0 4'1000 + 4: 1 4'--00 -> 1 4'1000 + 5: 1 4'0-10 -> 1 4'1000 + 6: 1 4'1-10 -> 3 4'1000 + 7: 2 4'---1 -> 0 4'0100 + 8: 2 4'1-10 -> 1 4'0100 + 9: 2 4'--00 -> 2 4'0100 + 10: 2 4'0-10 -> 2 4'0100 + 11: 3 4'---- -> 0 4'0010 + +------------------------------------- + +FSM `$fsm$\state$1127' from module `memory_manager': +------------------------------------- + + Information on FSM $fsm$\state$1127 (\state): + + Number of input signals: 7 + Number of output signals: 6 + Number of state bits: 6 + + Input signals: + 0: \rst + 1: \job_start + 2: \mem_ready + 3: $logic_or$hardware/v2/rtl/memory_manager.v:227$281_Y + 4: $logic_and$hardware/v2/rtl/memory_manager.v:245$290_Y + 5: $eq$hardware/v2/rtl/memory_manager.v:252$303_Y + 6: $logic_and$hardware/v2/rtl/memory_manager.v:284$320_Y + + Output signals: + 0: $eq$hardware/v2/rtl/memory_manager.v:151$230_Y + 1: $eq$hardware/v2/rtl/memory_manager.v:151$231_Y + 2: $procmux$691_CMP + 3: $procmux$1001_CMP + 4: $procmux$1017_CMP + 5: $procmux$1062_CMP + + State encoding: + 0: 6'-----1 + 1: 6'----1- + 2: 6'---1-- + 3: 6'--1--- + 4: 6'-1---- + 5: 6'1----- + + Transition Table (state_in, ctrl_in, state_out, ctrl_out): + 0: 0 7'-----00 -> 0 6'100000 + 1: 0 7'------1 -> 0 6'100000 + 2: 0 7'-----10 -> 3 6'100000 + 3: 1 7'------1 -> 0 6'000001 + 4: 1 7'------0 -> 4 6'000001 + 5: 2 7'------1 -> 0 6'010000 + 6: 2 7'--0---0 -> 2 6'010000 + 7: 2 7'-01---0 -> 2 6'010000 + 8: 2 7'-11---0 -> 5 6'010000 + 9: 3 7'------1 -> 0 6'001000 + 10: 3 7'---1--0 -> 2 6'001000 + 11: 3 7'---0--0 -> 3 6'001000 + 12: 4 7'----1-0 -> 0 6'000010 + 13: 4 7'------1 -> 0 6'000010 + 14: 4 7'----0-0 -> 4 6'000010 + 15: 5 7'------1 -> 0 6'000100 + 16: 5 7'1-----0 -> 1 6'000100 + 17: 5 7'0-----0 -> 5 6'000100 + +------------------------------------- + +3.14.8. Executing FSM_MAP pass (mapping FSMs to basic logic). +Mapping FSM `$fsm$\u_prefetch.state$1121' from module `\memory_manager'. +Mapping FSM `$fsm$\state$1127' from module `\memory_manager'. + +3.15. Executing OPT pass (performing simple optimizations). + +3.15.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + + +3.15.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 299 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 295 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. + +Removed a total of 4 cells. + +3.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memory_manager. +Performed a total of 0 changes. + +3.15.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 295 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Removed a total of 0 cells. + +3.15.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $procdff$1084 ($dff) from module memory_manager (D = $procmux$997_Y, Q = \tile_last, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$1235 ($sdff) from module memory_manager (D = $procmux$997_Y, Q = \tile_last). +Adding SRST signal on $flatten\u_prefetch.$procdff$1068 ($dff) from module memory_manager (D = $flatten\u_prefetch.$procmux$538_Y, Q = \u_prefetch.mem_addr, rval = 23'00000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$1249 ($sdff) from module memory_manager (D = $flatten\u_prefetch.$procmux$538_Y, Q = \u_prefetch.mem_addr). +Adding SRST signal on $procdff$1083 ($dff) from module memory_manager (D = $procmux$1016_Y, Q = \weight_data, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$1263 ($sdff) from module memory_manager (D = $procmux$1016_Y, Q = \weight_data). +Adding SRST signal on $flatten\u_prefetch.$procdff$1067 ($dff) from module memory_manager (D = $flatten\u_prefetch.$procmux$560_Y, Q = \u_prefetch.mem_wr, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$1277 ($sdff) from module memory_manager (D = $flatten\u_prefetch.$procmux$560_Y, Q = \u_prefetch.mem_wr). +Adding SRST signal on $procdff$1081 ($dff) from module memory_manager (D = $procmux$1054_Y, Q = \operand_valid, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$1291 ($sdff) from module memory_manager (D = $procmux$1054_Y, Q = \operand_valid). +Adding SRST signal on $flatten\u_prefetch.$procdff$1066 ($dff) from module memory_manager (D = $flatten\u_prefetch.$procmux$445_Y, Q = \u_prefetch.mem_req, rval = 1'0). +Adding EN signal on $flatten\u_prefetch.$procdff$1069 ($dff) from module memory_manager (D = 8'00000000, Q = \u_prefetch.mem_wdata). +Adding SRST signal on $flatten\u_prefetch.$procdff$1071 ($dff) from module memory_manager (D = $flatten\u_prefetch.$procmux$498_Y, Q = \u_prefetch.fetch_busy, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$1303 ($sdff) from module memory_manager (D = $flatten\u_prefetch.$procmux$498_Y, Q = \u_prefetch.fetch_busy). +Adding SRST signal on $procdff$1092 ($dff) from module memory_manager (D = $procmux$879_Y, Q = \current_bank, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$1311 ($sdff) from module memory_manager (D = $procmux$879_Y, Q = \current_bank). +Adding SRST signal on $procdff$1091 ($dff) from module memory_manager (D = $procmux$895_Y, Q = \tile_idx, rval = 16'0000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$1321 ($sdff) from module memory_manager (D = $procmux$895_Y, Q = \tile_idx). +Adding EN signal on $procdff$1090 ($dff) from module memory_manager (D = \n_tiles, Q = \n_tiles_reg). +Adding EN signal on $procdff$1089 ($dff) from module memory_manager (D = \result_addr, Q = \result_addr_reg). +Adding EN signal on $procdff$1088 ($dff) from module memory_manager (D = \w_base, Q = \w_base_reg). +Adding EN signal on $procdff$1087 ($dff) from module memory_manager (D = \x_base, Q = \x_base_reg). +Adding SRST signal on $procdff$1093 ($dff) from module memory_manager (D = $3$lookahead\bank_ready$237[1:0]$277, Q = \bank_ready, rval = 2'00). +Adding SRST signal on $procdff$1085 ($dff) from module memory_manager (D = $procmux$690_Y, Q = \result_ready, rval = 1'0). +Adding SRST signal on $procdff$1082 ($dff) from module memory_manager (D = $procmux$1035_Y, Q = \input_data, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$1353 ($sdff) from module memory_manager (D = $procmux$1035_Y, Q = \input_data). +Adding SRST signal on $flatten\u_prefetch.$procdff$1075 ($dff) from module memory_manager (D = $flatten\u_prefetch.$procmux$483_Y, Q = \u_prefetch.byte_idx, rval = 4'0000). +Adding EN signal on $auto$ff.cc:337:slice$1367 ($sdff) from module memory_manager (D = $flatten\u_prefetch.$procmux$483_Y, Q = \u_prefetch.byte_idx). +Adding SRST signal on $procdff$1104 ($dff) from module memory_manager (D = $procmux$732_Y, Q = \wr_mem_wdata, rval = 8'00000000). +Adding EN signal on $auto$ff.cc:337:slice$1381 ($sdff) from module memory_manager (D = \result_data, Q = \wr_mem_wdata). +Adding SRST signal on $procdff$1103 ($dff) from module memory_manager (D = $procmux$739_Y, Q = \wr_mem_addr, rval = 23'00000000000000000000000). +Adding EN signal on $auto$ff.cc:337:slice$1385 ($sdff) from module memory_manager (D = \result_addr_reg, Q = \wr_mem_addr). +Adding SRST signal on $procdff$1102 ($dff) from module memory_manager (D = $procmux$745_Y, Q = \wr_mem_req, rval = 1'0). +Adding EN signal on $auto$ff.cc:337:slice$1387 ($sdff) from module memory_manager (D = $procmux$745_Y, Q = \wr_mem_req). +Adding EN signal on $procdff$1101 ($dff) from module memory_manager (D = $procmux$763_Y, Q = \pf_pending_bank). +Adding EN signal on $procdff$1100 ($dff) from module memory_manager (D = $procmux$789_Y, Q = \pf_pending_w). +Adding EN signal on $procdff$1099 ($dff) from module memory_manager (D = $procmux$815_Y, Q = \pf_pending_x). +Adding SRST signal on $procdff$1098 ($dff) from module memory_manager (D = $procmux$843_Y, Q = \pf_pending, rval = 1'0). +Adding EN signal on $flatten\u_prefetch.$procdff$1074 ($dff) from module memory_manager (D = $flatten\u_prefetch.$2$lookahead\tile_w$324[63:0]$337, Q = \u_prefetch.tile_w). +Adding EN signal on $procdff$1097 ($dff) from module memory_manager (D = \pf_pending_bank, Q = \pf_target_bank). +Adding EN signal on $flatten\u_prefetch.$procdff$1073 ($dff) from module memory_manager (D = $flatten\u_prefetch.$2$lookahead\tile_x$323[63:0]$336, Q = \u_prefetch.tile_x). +Adding SRST signal on $flatten\u_prefetch.$procdff$1072 ($dff) from module memory_manager (D = $flatten\u_prefetch.$procmux$459_Y, Q = \u_prefetch.fetch_done, rval = 1'0). +Adding EN signal on $procdff$1096 ($dff) from module memory_manager (D = \pf_pending_w, Q = \pf_w_addr). +Adding EN signal on $procdff$1095 ($dff) from module memory_manager (D = \pf_pending_x, Q = \pf_x_addr). +Adding SRST signal on $procdff$1094 ($dff) from module memory_manager (D = $procmux$682_Y, Q = \pf_start, rval = 1'0). +Adding SRST signal on $procdff$1080 ($dff) from module memory_manager (D = $flatten\u_prefetch.$procmux$450_Y, Q = \job_done, rval = 1'0). +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$1302 ($dffe) from module memory_manager. +Setting constant 0-bit at position 1 on $auto$ff.cc:337:slice$1302 ($dffe) from module memory_manager. +Setting constant 0-bit at position 2 on $auto$ff.cc:337:slice$1302 ($dffe) from module memory_manager. +Setting constant 0-bit at position 3 on $auto$ff.cc:337:slice$1302 ($dffe) from module memory_manager. +Setting constant 0-bit at position 4 on $auto$ff.cc:337:slice$1302 ($dffe) from module memory_manager. +Setting constant 0-bit at position 5 on $auto$ff.cc:337:slice$1302 ($dffe) from module memory_manager. +Setting constant 0-bit at position 6 on $auto$ff.cc:337:slice$1302 ($dffe) from module memory_manager. +Setting constant 0-bit at position 7 on $auto$ff.cc:337:slice$1302 ($dffe) from module memory_manager. + +3.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. +Removed 48 unused cells and 70 unused wires. + + +3.15.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + + +3.15.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memory_manager. + New ctrl vector for $pmux cell $flatten\u_prefetch.$procmux$414: \u_prefetch.state [2] + New ctrl vector for $pmux cell $flatten\u_prefetch.$procmux$406: \u_prefetch.state [1] + Optimizing cells in module \memory_manager. +Performed a total of 2 changes. + +3.15.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 350 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 290 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 278 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. + +Removed a total of 72 cells. + +3.15.13. Executing OPT_DFF pass (perform DFF optimizations). + +3.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. +Removed 0 unused cells and 72 unused wires. + + +3.15.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + +3.15.16. Rerunning OPT passes. (Maybe there is more to do..) + +3.15.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.15.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memory_manager. +Performed a total of 0 changes. + +3.15.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 278 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Removed a total of 0 cells. + +3.15.20. Executing OPT_DFF pass (perform DFF optimizations). + +3.15.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. + +3.15.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + +3.15.23. Finished fast OPT passes. (There is nothing left to do.) + +3.16. Executing WREDUCE pass (reducing word size of cells). +Removed top 31 address bits (of 32) from memory read port memory_manager.$memrd$\bank_w$hardware/v2/rtl/memory_manager.v:232$284 (bank_w). +Removed top 31 address bits (of 32) from memory read port memory_manager.$memrd$\bank_x$hardware/v2/rtl/memory_manager.v:231$282 (bank_x). +Removed top 1 bits (of 2) from port B of cell memory_manager.$auto$opt_dff.cc:320:make_patterns_logic$1405 ($ne). +Removed top 1 bits (of 2) from port B of cell memory_manager.$auto$opt_dff.cc:320:make_patterns_logic$1401 ($ne). +Removed top 1 bits (of 2) from port B of cell memory_manager.$auto$opt_dff.cc:320:make_patterns_logic$1364 ($ne). +Removed top 1 bits (of 2) from port B of cell memory_manager.$auto$opt_dff.cc:320:make_patterns_logic$1362 ($ne). +Removed top 1 bits (of 2) from port B of cell memory_manager.$auto$opt_dff.cc:320:make_patterns_logic$1328 ($ne). +Removed top 1 bits (of 3) from port B of cell memory_manager.$auto$fsm_map.cc:77:implement_pattern_cache$1204 ($eq). +Removed top 1 bits (of 3) from port B of cell memory_manager.$auto$fsm_map.cc:77:implement_pattern_cache$1164 ($eq). +Converting cell memory_manager.$neg$hardware/v2/rtl/memory_manager.v:183$269 ($neg) from signed to unsigned. +Removed top 1 bits (of 2) from port A of cell memory_manager.$neg$hardware/v2/rtl/memory_manager.v:183$269 ($neg). +Removed top 15 bits (of 16) from port B of cell memory_manager.$eq$hardware/v2/rtl/memory_manager.v:233$286 ($eq). +Removed top 15 bits (of 16) from port B of cell memory_manager.$gt$hardware/v2/rtl/memory_manager.v:234$287 ($gt). +Removed top 19 bits (of 23) from port B of cell memory_manager.$add$hardware/v2/rtl/memory_manager.v:236$288 ($add). +Removed top 19 bits (of 23) from port B of cell memory_manager.$add$hardware/v2/rtl/memory_manager.v:237$289 ($add). +Converting cell memory_manager.$neg$hardware/v2/rtl/memory_manager.v:247$297 ($neg) from signed to unsigned. +Removed top 1 bits (of 2) from port A of cell memory_manager.$neg$hardware/v2/rtl/memory_manager.v:247$297 ($neg). +Removed top 15 bits (of 16) from port B of cell memory_manager.$add$hardware/v2/rtl/memory_manager.v:252$302 ($add). +Removed top 14 bits (of 16) from port B of cell memory_manager.$add$hardware/v2/rtl/memory_manager.v:255$304 ($add). +Removed top 14 bits (of 16) from port B of cell memory_manager.$add$hardware/v2/rtl/memory_manager.v:266$309 ($add). +Removed top 6 bits (of 23) from port Y of cell memory_manager.$add$hardware/v2/rtl/memory_manager.v:266$309 ($add). +Removed top 3 bits (of 23) from port B of cell memory_manager.$add$hardware/v2/rtl/memory_manager.v:266$311 ($add). +Removed top 15 bits (of 16) from port B of cell memory_manager.$sub$hardware/v2/rtl/memory_manager.v:277$318 ($sub). +Removed top 1 bits (of 4) from port B of cell memory_manager.$flatten\u_prefetch.$eq$hardware/v2/rtl/prefetch_engine.v:106$364 ($eq). +Removed top 25 bits (of 33) from port A of cell memory_manager.$flatten\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$361 ($neg). +Converting cell memory_manager.$flatten\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$361 ($neg) from signed to unsigned. +Removed top 1 bits (of 8) from port A of cell memory_manager.$flatten\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$361 ($neg). +Removed top 6 bits (of 23) from wire memory_manager.$add$hardware/v2/rtl/memory_manager.v:265$306_Y. + +3.17. Executing PEEPOPT pass (run peephole optimizers). + +3.18. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. +Removed 0 unused cells and 1 unused wires. + + +3.19. Executing SHARE pass (SAT-based resource sharing). +Found 2 cells in module memory_manager that may be considered for resource sharing. + Analyzing resource sharing options for $memrd$\bank_x$hardware/v2/rtl/memory_manager.v:275$316 ($memrd): + Found 1 activation_patterns using ctrl signal { $logic_and$hardware/v2/rtl/memory_manager.v:273$315_Y $logic_and$hardware/v2/rtl/memory_manager.v:245$290_Y \state [2] \operand_valid }. + No candidates found. + Analyzing resource sharing options for $memrd$\bank_w$hardware/v2/rtl/memory_manager.v:276$317 ($memrd): + Found 1 activation_patterns using ctrl signal { $logic_and$hardware/v2/rtl/memory_manager.v:273$315_Y $logic_and$hardware/v2/rtl/memory_manager.v:245$290_Y \state [2] \operand_valid }. + No candidates found. + +3.20. Executing TECHMAP pass (map to technology primitives). + +3.20.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/cmp2lut.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +3.20.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.21. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + +3.22. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. + +3.23. Executing TECHMAP pass (map to technology primitives). + +3.23.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/mul2dsp.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +3.23.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.24. Executing TECHMAP pass (map to technology primitives). + +3.24.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/dsp_map_18x18.v' to AST representation. +Generating RTLIL representation for module `$__MUL18X18'. +Successfully finished Verilog frontend. + +3.24.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.25. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module memory_manager: + creating $macc model for $flatten\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$361 ($neg). + creating $macc model for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$352 ($add). + creating $macc model for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$351 ($add). + creating $macc model for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$367 ($add). + creating $macc model for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$366 ($add). + creating $macc model for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:109$365 ($add). + creating $macc model for $sub$hardware/v2/rtl/memory_manager.v:277$318 ($sub). + creating $macc model for $add$hardware/v2/rtl/memory_manager.v:266$311 ($add). + creating $macc model for $add$hardware/v2/rtl/memory_manager.v:266$309 ($add). + creating $macc model for $add$hardware/v2/rtl/memory_manager.v:265$308 ($add). + creating $macc model for $add$hardware/v2/rtl/memory_manager.v:255$304 ($add). + creating $macc model for $add$hardware/v2/rtl/memory_manager.v:252$302 ($add). + creating $macc model for $neg$hardware/v2/rtl/memory_manager.v:247$297 ($neg). + creating $macc model for $add$hardware/v2/rtl/memory_manager.v:237$289 ($add). + creating $macc model for $add$hardware/v2/rtl/memory_manager.v:236$288 ($add). + creating $macc model for $neg$hardware/v2/rtl/memory_manager.v:183$269 ($neg). + merging $macc model for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$366 into $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$367. + merging $macc model for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$351 into $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$352. + creating $alu model for $macc $add$hardware/v2/rtl/memory_manager.v:237$289. + creating $alu model for $macc $neg$hardware/v2/rtl/memory_manager.v:247$297. + creating $alu model for $macc $add$hardware/v2/rtl/memory_manager.v:252$302. + creating $alu model for $macc $add$hardware/v2/rtl/memory_manager.v:255$304. + creating $alu model for $macc $add$hardware/v2/rtl/memory_manager.v:265$308. + creating $alu model for $macc $add$hardware/v2/rtl/memory_manager.v:266$309. + creating $alu model for $macc $add$hardware/v2/rtl/memory_manager.v:266$311. + creating $alu model for $macc $sub$hardware/v2/rtl/memory_manager.v:277$318. + creating $alu model for $macc $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:109$365. + creating $alu model for $macc $add$hardware/v2/rtl/memory_manager.v:236$288. + creating $alu model for $macc $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$367. + creating $alu model for $macc $neg$hardware/v2/rtl/memory_manager.v:183$269. + creating $alu model for $macc $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$352. + creating $alu model for $macc $flatten\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$361. + creating $alu model for $lt$hardware/v2/rtl/memory_manager.v:273$314 ($lt): new $alu + creating $alu model for $lt$hardware/v2/rtl/memory_manager.v:255$305 ($lt): new $alu + creating $alu model for $gt$hardware/v2/rtl/memory_manager.v:234$287 ($gt): merged with $sub$hardware/v2/rtl/memory_manager.v:277$318. + creating $alu model for $eq$hardware/v2/rtl/memory_manager.v:233$286 ($eq): merged with $sub$hardware/v2/rtl/memory_manager.v:277$318. + creating $alu cell for $lt$hardware/v2/rtl/memory_manager.v:255$305: $auto$alumacc.cc:548:replace_alu$1493 + creating $alu cell for $lt$hardware/v2/rtl/memory_manager.v:273$314: $auto$alumacc.cc:548:replace_alu$1498 + creating $alu cell for $flatten\u_prefetch.$neg$hardware/v2/rtl/prefetch_engine.v:105$361: $auto$alumacc.cc:548:replace_alu$1503 + creating $alu cell for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:98$352: $auto$alumacc.cc:548:replace_alu$1506 + creating $alu cell for $neg$hardware/v2/rtl/memory_manager.v:183$269: $auto$alumacc.cc:548:replace_alu$1509 + creating $alu cell for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:112$367: $auto$alumacc.cc:548:replace_alu$1512 + creating $alu cell for $add$hardware/v2/rtl/memory_manager.v:236$288: $auto$alumacc.cc:548:replace_alu$1515 + creating $alu cell for $flatten\u_prefetch.$add$hardware/v2/rtl/prefetch_engine.v:109$365: $auto$alumacc.cc:548:replace_alu$1518 + creating $alu cell for $sub$hardware/v2/rtl/memory_manager.v:277$318, $gt$hardware/v2/rtl/memory_manager.v:234$287, $eq$hardware/v2/rtl/memory_manager.v:233$286: $auto$alumacc.cc:548:replace_alu$1521 + creating $alu cell for $add$hardware/v2/rtl/memory_manager.v:266$311: $auto$alumacc.cc:548:replace_alu$1532 + creating $alu cell for $add$hardware/v2/rtl/memory_manager.v:265$308: $auto$alumacc.cc:548:replace_alu$1535 + creating $alu cell for $add$hardware/v2/rtl/memory_manager.v:266$309: $auto$alumacc.cc:548:replace_alu$1538 + creating $alu cell for $add$hardware/v2/rtl/memory_manager.v:255$304: $auto$alumacc.cc:548:replace_alu$1541 + creating $alu cell for $add$hardware/v2/rtl/memory_manager.v:252$302: $auto$alumacc.cc:548:replace_alu$1544 + creating $alu cell for $neg$hardware/v2/rtl/memory_manager.v:247$297: $auto$alumacc.cc:548:replace_alu$1547 + creating $alu cell for $add$hardware/v2/rtl/memory_manager.v:237$289: $auto$alumacc.cc:548:replace_alu$1550 + created 16 $alu and 0 $macc cells. + +3.26. Executing OPT pass (performing simple optimizations). + +3.26.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + + +3.26.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 282 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Removed a total of 0 cells. + +3.26.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.26.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memory_manager. +Performed a total of 0 changes. + +3.26.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 282 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Removed a total of 0 cells. + +3.26.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.26.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. +Removed 2 unused cells and 6 unused wires. + + +3.26.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + +3.26.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.26.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.26.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memory_manager. +Performed a total of 0 changes. + +3.26.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 280 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Removed a total of 0 cells. + +3.26.13. Executing OPT_DFF pass (perform DFF optimizations). + +3.26.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. + +3.26.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + +3.26.16. Finished fast OPT passes. (There is nothing left to do.) + +3.27. Executing MEMORY pass. + +3.27.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +3.27.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +Performed a total of 0 transformations. + +3.27.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing memory_manager.bank_w write port 0. + Analyzing memory_manager.bank_x write port 0. + +3.27.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). + +3.27.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Checking read port `\bank_w'[0] in module `\memory_manager': no output FF found. +Checking read port `\bank_w'[1] in module `\memory_manager': no output FF found. +Checking read port `\bank_x'[0] in module `\memory_manager': no output FF found. +Checking read port `\bank_x'[1] in module `\memory_manager': no output FF found. +Checking read port address `\bank_w'[0] in module `\memory_manager': no address FF found. +Checking read port address `\bank_w'[1] in module `\memory_manager': merged address FF to cell. +Checking read port address `\bank_x'[0] in module `\memory_manager': no address FF found. +Checking read port address `\bank_x'[1] in module `\memory_manager': merged address FF to cell. + +3.27.6. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. + +3.27.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). +Consolidating read ports of memory memory_manager.bank_w by address: +Consolidating read ports of memory memory_manager.bank_x by address: + +3.27.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +Performed a total of 0 transformations. + +3.27.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. + +3.27.10. Executing MEMORY_COLLECT pass (generating $mem cells). + +3.28. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. + +3.29. Executing MEMORY_LIBMAP pass (mapping memories to cells). +using FF mapping for memory memory_manager.bank_w +using FF mapping for memory memory_manager.bank_x + + +3.30. Executing TECHMAP pass (map to technology primitives). + +3.30.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/lutrams_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$__TRELLIS_DPR16X4_'. +Successfully finished Verilog frontend. + +3.30.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/brams_map_16kd.v' to AST representation. +Generating RTLIL representation for module `$__DP16KD_'. +Generating RTLIL representation for module `$__PDPW16KD_'. +Successfully finished Verilog frontend. + +3.30.3. Continuing TECHMAP pass. +No more expansions possible. + + +3.31. Executing OPT pass (performing simple optimizations). + +3.31.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + + +3.31.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 215 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 214 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 213 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. + +Removed a total of 2 cells. + +3.31.3. Executing OPT_DFF pass (perform DFF optimizations). + +3.31.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. +Removed 0 unused cells and 67 unused wires. + + +3.31.5. Finished fast OPT passes. + +3.32. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). +Mapping memory \bank_w in module \memory_manager: + created 2 $dff cells and 0 static cells of width 64. +Extracted addr FF from read port 1 of memory_manager.bank_w: $\bank_w$rdreg[1] + read interface: 1 $dff and 2 $mux cells. + write interface: 2 write mux blocks. +Mapping memory \bank_x in module \memory_manager: + created 2 $dff cells and 0 static cells of width 64. +Extracted addr FF from read port 1 of memory_manager.bank_x: $\bank_x$rdreg[1] + read interface: 1 $dff and 2 $mux cells. + write interface: 2 write mux blocks. + +3.33. Executing OPT pass (performing simple optimizations). + +3.33.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + + +3.33.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 228 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 224 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. + +Removed a total of 4 cells. + +3.33.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.33.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memory_manager. + Consolidated identical input bits for $pmux cell $flatten\u_prefetch.$procmux$560: + Old ports: A=1'0, B=2'00, Y=$flatten\u_prefetch.$procmux$560_Y + New connections: $flatten\u_prefetch.$procmux$560_Y = 1'0 + Optimizing cells in module \memory_manager. +Performed a total of 1 changes. + +3.33.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 223 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Removed a total of 0 cells. + +3.33.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $\bank_x$rdreg[1] ($dff) from module memory_manager (D = $auto$rtlil.cc:3402:Mux$1560, Q = $\bank_x$rdreg[1]$q, rval = 1'0). + +3.33.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. +Removed 1 unused cells and 21 unused wires. + + +3.33.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + +3.33.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.33.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.33.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memory_manager. +Performed a total of 0 changes. + +3.33.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 222 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Removed a total of 0 cells. + +3.33.13. Executing OPT_DFF pass (perform DFF optimizations). +Adding EN signal on $memory\bank_x[1]$1723 ($dff) from module memory_manager (D = \u_prefetch.tile_x, Q = \bank_x[1]). +Adding EN signal on $memory\bank_x[0]$1721 ($dff) from module memory_manager (D = \u_prefetch.tile_x, Q = \bank_x[0]). +Adding EN signal on $memory\bank_w[0]$1699 ($dff) from module memory_manager (D = \u_prefetch.tile_w, Q = \bank_w[0]). +Adding EN signal on $memory\bank_w[1]$1701 ($dff) from module memory_manager (D = \u_prefetch.tile_w, Q = \bank_w[1]). +Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$1278 ($sdffe) from module memory_manager. + +3.33.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. +Removed 4 unused cells and 4 unused wires. + + +3.33.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + + +3.33.16. Rerunning OPT passes. (Maybe there is more to do..) + +3.33.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memory_manager.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.33.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memory_manager. +Performed a total of 0 changes. + +3.33.19. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 216 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Removed a total of 0 cells. + +3.33.20. Executing OPT_DFF pass (perform DFF optimizations). + +3.33.21. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. + +3.33.22. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + +3.33.23. Finished fast OPT passes. (There is nothing left to do.) + +3.34. Executing TECHMAP pass (map to technology primitives). + +3.34.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +3.34.2. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/arith_map_ccu2c.v' to AST representation. +Generating RTLIL representation for module `\_80_ccu2c_alu'. +Successfully finished Verilog frontend. + +3.34.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $dffe. +Using extmapper simplemap for cells of type $sdff. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $mux. +Using template $paramod$ce0ec84be7047712840b0952f343ee9e63ef75d1\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$9e8c19db10db5b8954224cafa0587db20bab09bd\_90_alu for cells of type $alu. +Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$3b7577489eb4433b1d5620cab7f3794743dee5ea\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$6177de982a145c5b9397c76cce0d57e0a983739a\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$6fc37af1c109ae54e8aed83fcd995c12d378ce93\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$5a0392b4d8e708c73744507ba019664673a3d600\_80_ccu2c_alu for cells of type $alu. +Using extmapper simplemap for cells of type $or. +Using extmapper simplemap for cells of type $reduce_and. +Using template $paramod$a1665ef28c749ebcdbe9aecd466e644647b56463\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. +Using template $paramod$7945baf943a7eaf2bd95deee6e66976c53d43b8d\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$3e2546d640bb80c4407ce51aec1dbdbdc5bff143\_80_ccu2c_alu for cells of type $alu. +Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_80_ccu2c_alu for cells of type $alu. +Using extmapper simplemap for cells of type $reduce_or. +Using extmapper simplemap for cells of type $ne. +Using extmapper simplemap for cells of type $reduce_bool. +Using extmapper simplemap for cells of type $sdffe. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $logic_not. +Using extmapper simplemap for cells of type $eq. +Using extmapper simplemap for cells of type $dff. +Using extmapper simplemap for cells of type $logic_or. +Using template $paramod$constmap:dd82805e02d0c05f7629d78043ee7bd4bcc370d0$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx for cells of type $shift. +Using extmapper simplemap for cells of type $logic_and. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port A: 1'0 +Creating constmapped module `$paramod$constmap:d8aefc1ccc4cc8f7577de99159ea22c4a240a5fa$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx'. + +3.34.35. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:d8aefc1ccc4cc8f7577de99159ea22c4a240a5fa$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$3485. +Removed 1 multiplexer ports. + + +3.34.36. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:d8aefc1ccc4cc8f7577de99159ea22c4a240a5fa$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx. + +Removed 0 unused cells and 9 unused wires. +Using template $paramod$constmap:d8aefc1ccc4cc8f7577de99159ea22c4a240a5fa$paramod$5aa0fbdc3e385f336e95d2896ce5aed0c003c799\_90_shift_shiftx for cells of type $shift. +Using template $paramod$constmap:de554f9cc18e049d5b7dc95f0bcf8e03e57019ff$paramod$1e265d9719406ee45a570be27d6567e3eeff81e5\_90_shift_shiftx for cells of type $shiftx. +Using extmapper simplemap for cells of type $pmux. +Using template $paramod$constmap:f559a679ff835ab881c809a3c11cd4b7ac7c221b$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx for cells of type $shift. +Analyzing pattern of constant bits for this cell: + Constant input on bit 0 of port A: 1'1 + Constant input on bit 1 of port A: 1'1 + Constant input on bit 2 of port A: 1'1 + Constant input on bit 3 of port A: 1'1 + Constant input on bit 4 of port A: 1'1 + Constant input on bit 5 of port A: 1'1 + Constant input on bit 6 of port A: 1'1 + Constant input on bit 7 of port A: 1'1 +Creating constmapped module `$paramod$constmap:27fc41eec160220305c22e2c40782fd680a452dd$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx'. + +3.34.47. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module $paramod$constmap:27fc41eec160220305c22e2c40782fd680a452dd$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. + dead port 2/2 on $mux $procmux$4621. + dead port 2/2 on $mux $procmux$4627. + dead port 2/2 on $mux $procmux$4633. + dead port 2/2 on $mux $procmux$4639. + dead port 2/2 on $mux $procmux$4645. + dead port 2/2 on $mux $procmux$4651. + dead port 2/2 on $mux $procmux$4657. +Removed 7 multiplexer ports. + + +3.34.48. Executing OPT_EXPR pass (perform const folding). +Optimizing module $paramod$constmap:27fc41eec160220305c22e2c40782fd680a452dd$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx. + +Removed 0 unused cells and 12 unused wires. +Using template $paramod$constmap:27fc41eec160220305c22e2c40782fd680a452dd$paramod$409781814c91f00d9cc7cbbb6c4394c1e0dab276\_90_shift_shiftx for cells of type $shift. +Using extmapper simplemap for cells of type $xor. +Using extmapper simplemap for cells of type $pos. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. +Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa. +Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. +No more expansions possible. + + +3.35. Executing OPT pass (performing simple optimizations). + +3.35.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + + +3.35.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 3703 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3528 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3507 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3493 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3484 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3483 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3482 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3481 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3480 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3479 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3478 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3477 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3476 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3475 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3474 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3473 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3472 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3471 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3470 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3469 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3468 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3467 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3466 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3465 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3464 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 3463 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. + +Removed a total of 240 cells. + +3.35.3. Executing OPT_DFF pass (perform DFF optimizations). +Adding SRST signal on $auto$ff.cc:337:slice$3145 ($_SDFF_PP0_) from module memory_manager (D = $auto$simplemap.cc:189:logic_reduce$4509, Q = \u_prefetch.mem_req, rval = 1'0). +Adding SRST signal on $auto$ff.cc:337:slice$2847 ($_DFFE_PP_) from module memory_manager (D = $auto$simplemap.cc:189:logic_reduce$3768, Q = \pf_pending_bank, rval = 1'0). + +3.35.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. +Removed 555 unused cells and 1183 unused wires. + + +3.35.5. Rerunning OPT passes. (Removed registers in this run.) + +3.35.6. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + + +3.35.7. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 2904 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Removed a total of 0 cells. + +3.35.8. Executing OPT_DFF pass (perform DFF optimizations). + +3.35.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. + +3.35.10. Finished fast OPT passes. + +3.36. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. + +3.37. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). + +3.38. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 2906 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Removed a total of 0 cells. + +3.39. Executing TECHMAP pass (map to technology primitives). + +3.39.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Successfully finished Verilog frontend. + +3.39.2. Continuing TECHMAP pass. +Using template $_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. +Using template $_SDFF_PP0_ for cells of type $_SDFF_PP0_. +Using template $paramod$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. +Using template $paramod$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. +No more expansions possible. + + +3.40. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + +3.41. Executing SIMPLEMAP pass (map simple cells to gate primitives). + +3.42. Executing LATTICE_GSR pass (implement FF init values). +Handling GSR in memory_manager. + +3.43. Executing ATTRMVCP pass (move or copy attributes). + +3.44. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. +Removed 0 unused cells and 4143 unused wires. + + +3.45. Executing CHECK pass (checking for obvious problems). +Checking module memory_manager... +Found and reported 0 problems. + +3.46. Executing TECHMAP pass (map to technology primitives). + +3.46.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/latches_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/latches_map.v' to AST representation. +Generating RTLIL representation for module `$_DLATCH_N_'. +Generating RTLIL representation for module `$_DLATCH_P_'. +Successfully finished Verilog frontend. + +3.46.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.47. Executing ABC9 pass. + +3.47.1. Executing ABC9_OPS pass (helper functions for ABC9). + +3.47.2. Executing ABC9_OPS pass (helper functions for ABC9). + +3.47.3. Executing SCC pass (detecting logic loops). +Found 0 SCCs in module memory_manager. +Found 0 SCCs. + +3.47.4. Executing ABC9_OPS pass (helper functions for ABC9). + +3.47.5. Executing TECHMAP pass (map to technology primitives). + +3.47.5.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +3.47.5.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.47.6. Executing OPT pass (performing simple optimizations). + +3.47.6.1. Executing OPT_EXPR pass (perform const folding). + +3.47.6.2. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +3.47.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Removed 0 multiplexer ports. + +3.47.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +Performed a total of 0 changes. + +3.47.6.5. Executing OPT_MERGE pass (detect identical cells). +Removed a total of 0 cells. + +3.47.6.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.47.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). + +3.47.6.8. Executing OPT_EXPR pass (perform const folding). + +3.47.6.9. Finished fast OPT passes. (There is nothing left to do.) + +3.47.7. Executing TECHMAP pass (map to technology primitives). + +3.47.7.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_map.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_map.v' to AST representation. +Successfully finished Verilog frontend. + +3.47.7.2. Continuing TECHMAP pass. +No more expansions possible. + + +3.47.8. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_model.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_model.v' to AST representation. +Generating RTLIL representation for module `$__ABC9_DELAY'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. +Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. +Successfully finished Verilog frontend. + +3.47.9. Executing ABC9_OPS pass (helper functions for ABC9). + + +3.47.10. Executing ABC9_OPS pass (helper functions for ABC9). + +3.47.11. Executing ABC9_OPS pass (helper functions for ABC9). + + +3.47.12. Executing TECHMAP pass (map to technology primitives). + +3.47.12.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/techmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu_brent_kung'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `$__div_mod_u'. +Generating RTLIL representation for module `$__div_mod_trunc'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `$__div_mod_floor'. +Generating RTLIL representation for module `\_90_divfloor'. +Generating RTLIL representation for module `\_90_modfloor'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_demux'. +Generating RTLIL representation for module `\_90_lut'. +Generating RTLIL representation for module `$connect'. +Generating RTLIL representation for module `$input_port'. +Successfully finished Verilog frontend. + +3.47.12.2. Continuing TECHMAP pass. +Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. +Using extmapper simplemap for cells of type $or. +Using extmapper simplemap for cells of type $and. +Using extmapper simplemap for cells of type $not. +Using extmapper simplemap for cells of type $xor. +Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. +Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. +Using extmapper simplemap for cells of type $mux. +No more expansions possible. + + +3.47.13. Executing OPT pass (performing simple optimizations). + +3.47.13.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + + +3.47.13.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 59 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Computing hashes of 57 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. + +Removed a total of 2 cells. + +3.47.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memory_manager.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +3.47.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memory_manager. +Performed a total of 0 changes. + +3.47.13.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 57 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Removed a total of 0 cells. + +3.47.13.6. Executing OPT_DFF pass (perform DFF optimizations). + +3.47.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. +Removed 0 unused cells and 55 unused wires. + + +3.47.13.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + +3.47.13.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.47.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \memory_manager.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +3.47.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \memory_manager. +Performed a total of 0 changes. + +3.47.13.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\memory_manager'. +Computing hashes of 57 cells of `\memory_manager'. +Finding duplicate cells in `\memory_manager'. +Removed a total of 0 cells. + +3.47.13.13. Executing OPT_DFF pass (perform DFF optimizations). + +3.47.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \memory_manager.. + +3.47.13.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module memory_manager. + +3.47.13.16. Finished fast OPT passes. (There is nothing left to do.) + +3.47.14. Executing AIGMAP pass (map logic to AIG). +Module memory_manager: replaced 18 cells with 120 new cells, skipped 39 cells. + replaced 3 cell types: + 14 $_MUX_ + 2 $_OR_ + 2 $_XOR_ + not replaced 3 cell types: + 4 $_AND_ + 4 $_NOT_ + 31 $specify2 + +3.47.15. Executing AIGMAP pass (map logic to AIG). +Module memory_manager: replaced 1493 cells with 9466 new cells, skipped 1413 cells. + replaced 4 cell types: + 1105 $_MUX_ + 1 $_ORNOT_ + 327 $_OR_ + 60 $_XOR_ + not replaced 5 cell types: + 362 $_AND_ + 132 $_NOT_ + 1 $scopeinfo + 789 TRELLIS_FF + 129 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C + +3.47.15.1. Executing ABC9_OPS pass (helper functions for ABC9). + +3.47.15.2. Executing ABC9_OPS pass (helper functions for ABC9). + +3.47.15.3. Executing XAIGER backend. + +Extracted 4185 AND gates and 11738 wires from module `memory_manager' to a netlist network with 896 inputs and 750 outputs. + +3.47.15.4. Executing ABC9_EXE pass (technology mapping using ABC9). + +3.47.15.5. Executing ABC9. +Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 +ABC: ======== ABC command line "source /abc.script" +ABC: + read_lut /input.lut +ABC: + read_box /input.box +ABC: + &read /input.xaig +ABC: + &ps +ABC: /input : i/o = 896/ 750 and = 3196 lev = 40 (3.29) mem = 0.09 MB box = 129 bb = 0 +ABC: + &scorr +ABC: Warning: The network is combinational. +ABC: + &sweep +ABC: + &dc2 +ABC: + &dch -f -r +ABC: + &ps +ABC: /input : i/o = 896/ 750 and = 3447 lev = 24 (0.95) mem = 0.09 MB ch = 424 box = 108 bb = 0 +ABC: cst = 0 cls = 382 lit = 424 unused = 3861 proof = 0 +ABC: + &if -W 300 -v +ABC: K = 7. Memory (bytes): Truth = 0. Cut = 76. Obj = 156. Set = 780. CutMin = no +ABC: Node = 3447. Ch = 382. Total mem = 1.05 MB. Peak cut mem = 0.03 MB. +ABC: P: Del = 2687.00. Ar = 2021.0. Edge = 2622. Cut = 32074. T = 0.00 sec +ABC: P: Del = 2687.00. Ar = 2011.0. Edge = 2613. Cut = 32025. T = 0.00 sec +ABC: P: Del = 2687.00. Ar = 919.0. Edge = 2604. Cut = 34076. T = 0.00 sec +ABC: F: Del = 2680.00. Ar = 853.0. Edge = 2438. Cut = 33213. T = 0.00 sec +ABC: A: Del = 2680.00. Ar = 853.0. Edge = 2389. Cut = 32452. T = 0.00 sec +ABC: A: Del = 2680.00. Ar = 853.0. Edge = 2389. Cut = 32408. T = 0.00 sec +ABC: Total time = 0.02 sec +ABC: + &write -n /output.aig +ABC: + &mfs +ABC: + &ps -l +ABC: /input : i/o = 896/ 750 and = 2422 lev = 11 (0.93) mem = 0.07 MB box = 108 bb = 0 +ABC: Mapping (K=7) : lut = 622 edge = 2309 lev = 4 (0.52) levB = 14 mem = 0.03 MB +ABC: LUT = 622 : 2=40 6.4 % 3=317 51.0 % 4=53 8.5 % 5=207 33.3 % 6=4 0.6 % 7=1 0.2 % Ave = 3.71 +ABC: + &write -n /output.aig +ABC: + &verify +ABC: Networks are equivalent. Time = 0.03 sec +ABC: + time +ABC: elapse: 0.17 seconds, total: 0.17 seconds + +3.47.15.6. Executing AIGER frontend. + +Removed 4102 unused cells and 6711 unused wires. + +3.47.15.7. Executing ABC_OPS_REINTEGRATE pass (reintegrate ABC mapped design into module). +ABC RESULTS: $lut cells: 625 +ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 108 +ABC RESULTS: input signals: 38 +ABC RESULTS: output signals: 59 + +Removing temp directory. + +3.47.16. Executing TECHMAP pass (map to technology primitives). + +3.47.16.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/abc9_unmap.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/abc9_unmap.v' to AST representation. +Generating RTLIL representation for module `$__DFF_x__$abc9_flop'. +Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. +Successfully finished Verilog frontend. + +3.47.16.2. Continuing TECHMAP pass. +Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. +No more expansions possible. + +Removed 77 unused cells and 13057 unused wires. + +3.48. Executing TECHMAP pass (map to technology primitives). + +3.48.1. Executing Verilog-2005 frontend: /opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v +Parsing Verilog input from `/opt/homebrew/bin/../share/yosys/lattice/cells_map_trellis.v' to AST representation. +Generating RTLIL representation for module `$_DFF_N_'. +Generating RTLIL representation for module `$_DFF_P_'. +Generating RTLIL representation for module `$_DFFE_NN_'. +Generating RTLIL representation for module `$_DFFE_PN_'. +Generating RTLIL representation for module `$_DFFE_NP_'. +Generating RTLIL representation for module `$_DFFE_PP_'. +Generating RTLIL representation for module `$_DFF_NP0_'. +Generating RTLIL representation for module `$_DFF_NP1_'. +Generating RTLIL representation for module `$_DFF_PP0_'. +Generating RTLIL representation for module `$_DFF_PP1_'. +Generating RTLIL representation for module `$_SDFF_NP0_'. +Generating RTLIL representation for module `$_SDFF_NP1_'. +Generating RTLIL representation for module `$_SDFF_PP0_'. +Generating RTLIL representation for module `$_SDFF_PP1_'. +Generating RTLIL representation for module `$_DFFE_NP0P_'. +Generating RTLIL representation for module `$_DFFE_NP1P_'. +Generating RTLIL representation for module `$_DFFE_PP0P_'. +Generating RTLIL representation for module `$_DFFE_PP1P_'. +Generating RTLIL representation for module `$_DFFE_NP0N_'. +Generating RTLIL representation for module `$_DFFE_NP1N_'. +Generating RTLIL representation for module `$_DFFE_PP0N_'. +Generating RTLIL representation for module `$_DFFE_PP1N_'. +Generating RTLIL representation for module `$_SDFFE_NP0P_'. +Generating RTLIL representation for module `$_SDFFE_NP1P_'. +Generating RTLIL representation for module `$_SDFFE_PP0P_'. +Generating RTLIL representation for module `$_SDFFE_PP1P_'. +Generating RTLIL representation for module `$_SDFFE_NP0N_'. +Generating RTLIL representation for module `$_SDFFE_NP1N_'. +Generating RTLIL representation for module `$_SDFFE_PP0N_'. +Generating RTLIL representation for module `$_SDFFE_PP1N_'. +Generating RTLIL representation for module `$_ALDFF_NP_'. +Generating RTLIL representation for module `$_ALDFF_PP_'. +Generating RTLIL representation for module `$_ALDFFE_NPN_'. +Generating RTLIL representation for module `$_ALDFFE_NPP_'. +Generating RTLIL representation for module `$_ALDFFE_PPN_'. +Generating RTLIL representation for module `$_ALDFFE_PPP_'. +Generating RTLIL representation for module `\FD1P3AX'. +Generating RTLIL representation for module `\FD1P3AY'. +Generating RTLIL representation for module `\FD1P3BX'. +Generating RTLIL representation for module `\FD1P3DX'. +Generating RTLIL representation for module `\FD1P3IX'. +Generating RTLIL representation for module `\FD1P3JX'. +Generating RTLIL representation for module `\FD1S3AX'. +Generating RTLIL representation for module `\FD1S3AY'. +Generating RTLIL representation for module `\FD1S3BX'. +Generating RTLIL representation for module `\FD1S3DX'. +Generating RTLIL representation for module `\FD1S3IX'. +Generating RTLIL representation for module `\FD1S3JX'. +Generating RTLIL representation for module `\IFS1P3BX'. +Generating RTLIL representation for module `\IFS1P3DX'. +Generating RTLIL representation for module `\IFS1P3IX'. +Generating RTLIL representation for module `\IFS1P3JX'. +Generating RTLIL representation for module `\OFS1P3BX'. +Generating RTLIL representation for module `\OFS1P3DX'. +Generating RTLIL representation for module `\OFS1P3IX'. +Generating RTLIL representation for module `\OFS1P3JX'. +Generating RTLIL representation for module `\IB'. +Generating RTLIL representation for module `\IBPU'. +Generating RTLIL representation for module `\IBPD'. +Generating RTLIL representation for module `\OB'. +Generating RTLIL representation for module `\OBZ'. +Generating RTLIL representation for module `\OBZPU'. +Generating RTLIL representation for module `\OBZPD'. +Generating RTLIL representation for module `\OBCO'. +Generating RTLIL representation for module `\BB'. +Generating RTLIL representation for module `\BBPU'. +Generating RTLIL representation for module `\BBPD'. +Generating RTLIL representation for module `\ILVDS'. +Generating RTLIL representation for module `\OLVDS'. +Generating RTLIL representation for module `$lut'. +Successfully finished Verilog frontend. + +3.48.2. Continuing TECHMAP pass. +Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8$lut for cells of type $lut. +Using template $paramod$6e238df02989b317f10820a22773676e71120644$lut for cells of type $lut. +Using template $paramod$8adf7fbd410d2cc654c288d5be5f7508ee8809b0$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut. +Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4$lut for cells of type $lut. +Using template $paramod$b287726797d0722f64e731f1134f7c05af8f1578$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. +Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7$lut for cells of type $lut. +Using template $paramod$b5babc618720ace64bafddb303d6f59fd10af395$lut for cells of type $lut. +Using template $paramod$464d286cc302627c2e44b6c4a8450c9bebc28389$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. +Using template $paramod$86d1a43c2f1d620ff2cef866448dd1258c868fad$lut for cells of type $lut. +Using template $paramod$f12fe2ef5af134a926cc7292d32ee6988934ef95$lut for cells of type $lut. +Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624$lut for cells of type $lut. +Using template $paramod$ac977fdb827743bc5fe009760f4eb846eab5907d$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. +Using template $paramod$a34c3a113f6322a855b111888cced8dfe18cd967$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101100 for cells of type $lut. +Using template $paramod$ff315d5084ed3c80e34901fe05add0db5feb0b93$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. +Using template $paramod$a249737383b43f5fd82429cdb8b49973f28934bb$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101010 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut. +Using template $paramod$d7fff18f4a1584e5dce7e6dfbc06d7e09d60216e$lut for cells of type $lut. +Using template $paramod$720c7833e3169f9dadd6b9edcfecd044664bf968$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. +Using template $paramod$4abe3dc2dfc6ad230292110951d5330af081367b$lut for cells of type $lut. +Using template $paramod$98a845e3fcf8cfe488f4d5055f2cf6fcbfd5da81$lut for cells of type $lut. +Using template $paramod$4976b5f7a7b9f6e596e742c7d9dd919d8c62448f$lut for cells of type $lut. +Using template $paramod$2b26b4922e8ee12b5b5d0f35a909c50a2c48701c$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. +Using template $paramod$9664b2f5fd61944d7798b30cde43b99ccda87303$lut for cells of type $lut. +Using template $paramod$f81ecf3eb88491df8fecf1e071b57debc429282a$lut for cells of type $lut. +Using template $paramod$9c65fdfac74256c2eb67dd209b598e25d1f0a099$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. +Using template $paramod$c50474b30f5187625746303b03b42bd612263de0$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. +Using template $paramod$a5a9d48041af65bd5d7b6a1f6014e7ed22f6b87a$lut for cells of type $lut. +Using template $paramod$6ed7ed61521c2ee3ec4e86802248d93207c213e1$lut for cells of type $lut. +Using template $paramod$b27834385f52eaf4ed276ecbffb1b05d9c8a8b56$lut for cells of type $lut. +Using template $paramod$54feebfc143584f0d3dec83621f4f6627929f2a4$lut for cells of type $lut. +Using template $paramod$09d7ff7c3d1d9901344b01d38c40f254e5edc311$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. +Using template $paramod$4a0b7d2a2849f16773696ba19d68aee3da2f49f1$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011100 for cells of type $lut. +Using template $paramod$77f0cd72667b23cc49e7a8bf984ad848b10003d7$lut for cells of type $lut. +Using template $paramod$2349469c9d9d0a3245a5c6f030ac99add533eb96$lut for cells of type $lut. +Using template $paramod$55f6f9cee16c7757093cb8f1db45e773789af9a7$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. +Using template $paramod$4f09540800ac966d6e31a7ccf5f32a559a8ce57a$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. +Using template $paramod$0c822c65361ce832091b6c90f1a02f1ee0b109d4$lut for cells of type $lut. +Using template $paramod$5669c8db8e6f25f93d37029b0fad4d742a70b03a$lut for cells of type $lut. +Using template $paramod$ea2b11aca30aa162d3b93de07d97b9c1565643dd$lut for cells of type $lut. +Using template $paramod$3a16cdc423338332acc062d6121d7f50fc30fbe6$lut for cells of type $lut. +Using template $paramod$dbc9832e8c07df12a10ac142cba717a43c21c0ab$lut for cells of type $lut. +Using template $paramod$cf52221ef2d451442dd7d72d5c8ad598e89310e9$lut for cells of type $lut. +Using template $paramod$c231c665eed0e54f6cd365c2b07ecdea418a10e6$lut for cells of type $lut. +Using template $paramod$eab8c2e20ad6848564bec45c7148558972138f5b$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. +Using template $paramod$fea512844f0598125018304dfe86621dbf348f27$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. +Using template $paramod$f8a9198ede5f55f66707edafc5a980c0d1845964$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. +Using template $paramod$a4e96f70220c8c72bfba8aef01ed46347df8de63$lut for cells of type $lut. +Using template $paramod$183ec76ed3429a430a8be24b57f3de734985f568$lut for cells of type $lut. +Using template $paramod$d0f69fc2671bbe315699d75b65aae8328a796f77$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. +Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. +Using template $paramod$56e6d8a28a52006bb4e50e077743f0a2163235af$lut for cells of type $lut. +Using template $paramod$9f2673a51432cc74523a76959f201c232331430c$lut for cells of type $lut. +Using template $paramod$137d5d1409eb709bcd6ab98f2ead06fef72ee46f$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut. +Using template $paramod$8829675bb8c52553aed9f101ec0d5ef0c865e5c7$lut for cells of type $lut. +Using template $paramod$9dfe2a25d99d8640a9f67a2438aaca85b684d257$lut for cells of type $lut. +Using template $paramod$5a203febca29678ab5583c0f96bc052b4d0c83a4$lut for cells of type $lut. +Using template $paramod$4133fe00eb18442862a284ccc67a95f8194d041c$lut for cells of type $lut. +Using template $paramod$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. +No more expansions possible. + + +3.49. Executing OPT_LUT_INS pass (discard unused LUT inputs). +Optimizing LUTs in memory_manager. + Optimizing lut $abc$30601$lut$aiger$o1007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) + Optimizing lut $abc$30601$lut$aiger$o1096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) + Optimizing lut $abc$30601$lut$aiger$o1096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) + Optimizing lut $abc$30601$lut$aiger$o1036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) + Optimizing lut $abc$30601$lut$aiger30600$1372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) + Optimizing lut $abc$30601$lut$aiger30600$1372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) + Optimizing lut $abc$30601$lut$aiger30600$1372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) + Optimizing lut $abc$30601$lut$aiger30600$1372.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) + Optimizing lut $abc$30601$lut$aiger30600$1283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$30601$lut$aiger30600$1299.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30663.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$30601$lut$aiger$o983.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30624.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$30601$lut$aiger30600$1401.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$30601$lut$aiger30600$1392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30660.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$30601$lut$aiger$o998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30648.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$30601$lut$aiger$o1096.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30655.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$30601$lut$aiger$o1034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30665.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$30601$lut$aiger$o1036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $abc$30601$lut$aiger$o1036.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$30601$lut$aiger$o1043.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30666.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$30601$lut$aiger$o1047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30677.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) + Optimizing lut $abc$30601$lut$aiger30600$1253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $abc$30601$lut$aiger30600$1268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) + Optimizing lut $auto$abc_ops_reintegrate.cc:611:reintegrate$30679.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) +Removed 0 unused cells and 1350 unused wires. + +3.50. Executing AUTONAME pass. +Renamed 2900 objects in module memory_manager. + + +3.51. Executing HIERARCHY pass (managing design hierarchy). +Attribute `top' found on module `memory_manager'. Setting top module to memory_manager. + +3.51.1. Analyzing design hierarchy.. +Top module: \memory_manager + +3.51.2. Analyzing design hierarchy.. +Top module: \memory_manager +Removed 0 unused modules. + +3.52. Printing statistics. + +=== memory_manager === + + +----------Local Count, excluding submodules. + | + 997 wires + 3408 wire bits + 997 public wires + 3408 public wire bits + 22 ports + 272 port bits + 1 cells + 1 $scopeinfo + 1974 submodules + 108 CCU2C + 7 L6MUX21 + 851 LUT4 + 219 PFUMX + 789 TRELLIS_FF + +=== design hierarchy === + + +----------Count including submodules. + | + 1 memory_manager + + +----------Count including submodules. + | + 997 wires + 3408 wire bits + 997 public wires + 3408 public wire bits + 22 ports + 272 port bits + - memories + - memory bits + - processes + 1 cells + 1 $scopeinfo + 1974 submodules + 108 CCU2C + 7 L6MUX21 + 851 LUT4 + 219 PFUMX + 789 TRELLIS_FF + +3.53. Executing CHECK pass (checking for obvious problems). +Checking module memory_manager... +Found and reported 0 problems. + +3.54. Executing JSON backend. + +End of script. Logfile hash: bb7d874436, time: 0.82s, user: 0.63s, system: 0.03s, MEM: 76.50 MB peak +Yosys 0.68+post (git sha1 c12172fbae8af5e20f6fb52e3d4e92d56ed587b6, Release, AppleClang clang++ 21.0.0.21000101) +Time spent: 21% 23x read_verilog (0 sec), 21% 1x abc9_exe (0 sec), ...